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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
a1452a37 DW |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
5e81e88a | 28 | struct nand_flash_dev; |
1da177e4 | 29 | /* Scan and identify a NAND device */ |
a0491fc4 SAS |
30 | extern int nand_scan(struct mtd_info *mtd, int max_chips); |
31 | /* | |
32 | * Separate phases of nand_scan(), allowing board driver to intervene | |
33 | * and override command or ECC setup according to flash type. | |
34 | */ | |
5e81e88a DW |
35 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
36 | struct nand_flash_dev *table); | |
3b85c321 DW |
37 | extern int nand_scan_tail(struct mtd_info *mtd); |
38 | ||
1da177e4 | 39 | /* Free resources held by the NAND device */ |
a0491fc4 | 40 | extern void nand_release(struct mtd_info *mtd); |
1da177e4 | 41 | |
b77d95c7 DW |
42 | /* Internal helper for board drivers which need to override command function */ |
43 | extern void nand_wait_ready(struct mtd_info *mtd); | |
44 | ||
7d70f334 VS |
45 | /* locks all blockes present in the device */ |
46 | extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); | |
47 | ||
48 | /* unlocks specified locked blockes */ | |
49 | extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); | |
50 | ||
1da177e4 LT |
51 | /* The maximum number of NAND chips in an array */ |
52 | #define NAND_MAX_CHIPS 8 | |
53 | ||
a0491fc4 SAS |
54 | /* |
55 | * This constant declares the max. oobsize / page, which | |
1da177e4 LT |
56 | * is supported now. If you add a chip with bigger oobsize/page |
57 | * adjust this accordingly. | |
58 | */ | |
5c709ee9 BN |
59 | #define NAND_MAX_OOBSIZE 576 |
60 | #define NAND_MAX_PAGESIZE 8192 | |
1da177e4 LT |
61 | |
62 | /* | |
63 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
64 | * |
65 | * These are bits which can be or'ed to set/clear multiple | |
66 | * bits in one go. | |
67 | */ | |
1da177e4 | 68 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 69 | #define NAND_NCE 0x01 |
1da177e4 | 70 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 71 | #define NAND_CLE 0x02 |
1da177e4 | 72 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
73 | #define NAND_ALE 0x04 |
74 | ||
75 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
76 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
77 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
78 | |
79 | /* | |
80 | * Standard NAND flash commands | |
81 | */ | |
82 | #define NAND_CMD_READ0 0 | |
83 | #define NAND_CMD_READ1 1 | |
7bc3312b | 84 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
85 | #define NAND_CMD_PAGEPROG 0x10 |
86 | #define NAND_CMD_READOOB 0x50 | |
87 | #define NAND_CMD_ERASE1 0x60 | |
88 | #define NAND_CMD_STATUS 0x70 | |
89 | #define NAND_CMD_STATUS_MULTI 0x71 | |
90 | #define NAND_CMD_SEQIN 0x80 | |
7bc3312b | 91 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
92 | #define NAND_CMD_READID 0x90 |
93 | #define NAND_CMD_ERASE2 0xd0 | |
caa4b6f2 | 94 | #define NAND_CMD_PARAM 0xec |
1da177e4 LT |
95 | #define NAND_CMD_RESET 0xff |
96 | ||
7d70f334 VS |
97 | #define NAND_CMD_LOCK 0x2a |
98 | #define NAND_CMD_UNLOCK1 0x23 | |
99 | #define NAND_CMD_UNLOCK2 0x24 | |
100 | ||
1da177e4 LT |
101 | /* Extended commands for large page devices */ |
102 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 103 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
104 | #define NAND_CMD_CACHEDPROG 0x15 |
105 | ||
28a48de7 | 106 | /* Extended commands for AG-AND device */ |
61ecfa87 TG |
107 | /* |
108 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but | |
28a48de7 DM |
109 | * there is no way to distinguish that from NAND_CMD_READ0 |
110 | * until the remaining sequence of commands has been completed | |
111 | * so add a high order bit and mask it off in the command. | |
112 | */ | |
113 | #define NAND_CMD_DEPLETE1 0x100 | |
114 | #define NAND_CMD_DEPLETE2 0x38 | |
115 | #define NAND_CMD_STATUS_MULTI 0x71 | |
116 | #define NAND_CMD_STATUS_ERROR 0x72 | |
117 | /* multi-bank error status (banks 0-3) */ | |
118 | #define NAND_CMD_STATUS_ERROR0 0x73 | |
119 | #define NAND_CMD_STATUS_ERROR1 0x74 | |
120 | #define NAND_CMD_STATUS_ERROR2 0x75 | |
121 | #define NAND_CMD_STATUS_ERROR3 0x76 | |
122 | #define NAND_CMD_STATUS_RESET 0x7f | |
123 | #define NAND_CMD_STATUS_CLEAR 0xff | |
124 | ||
7abd3ef9 TG |
125 | #define NAND_CMD_NONE -1 |
126 | ||
1da177e4 LT |
127 | /* Status bits */ |
128 | #define NAND_STATUS_FAIL 0x01 | |
129 | #define NAND_STATUS_FAIL_N1 0x02 | |
130 | #define NAND_STATUS_TRUE_READY 0x20 | |
131 | #define NAND_STATUS_READY 0x40 | |
132 | #define NAND_STATUS_WP 0x80 | |
133 | ||
61ecfa87 | 134 | /* |
1da177e4 LT |
135 | * Constants for ECC_MODES |
136 | */ | |
6dfc6d25 TG |
137 | typedef enum { |
138 | NAND_ECC_NONE, | |
139 | NAND_ECC_SOFT, | |
140 | NAND_ECC_HW, | |
141 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 142 | NAND_ECC_HW_OOB_FIRST, |
6dfc6d25 | 143 | } nand_ecc_modes_t; |
1da177e4 LT |
144 | |
145 | /* | |
146 | * Constants for Hardware ECC | |
068e3c0a | 147 | */ |
1da177e4 LT |
148 | /* Reset Hardware ECC for read */ |
149 | #define NAND_ECC_READ 0 | |
150 | /* Reset Hardware ECC for write */ | |
151 | #define NAND_ECC_WRITE 1 | |
152 | /* Enable Hardware ECC before syndrom is read back from flash */ | |
153 | #define NAND_ECC_READSYN 2 | |
154 | ||
068e3c0a DM |
155 | /* Bit mask for flags passed to do_nand_read_ecc */ |
156 | #define NAND_GET_DEVICE 0x80 | |
157 | ||
158 | ||
a0491fc4 SAS |
159 | /* |
160 | * Option constants for bizarre disfunctionality and real | |
161 | * features. | |
162 | */ | |
1da177e4 LT |
163 | /* Chip can not auto increment pages */ |
164 | #define NAND_NO_AUTOINCR 0x00000001 | |
165 | /* Buswitdh is 16 bit */ | |
166 | #define NAND_BUSWIDTH_16 0x00000002 | |
167 | /* Device supports partial programming without padding */ | |
168 | #define NAND_NO_PADDING 0x00000004 | |
169 | /* Chip has cache program function */ | |
170 | #define NAND_CACHEPRG 0x00000008 | |
171 | /* Chip has copy back function */ | |
172 | #define NAND_COPYBACK 0x00000010 | |
a0491fc4 SAS |
173 | /* |
174 | * AND Chip which has 4 banks and a confusing page / block | |
175 | * assignment. See Renesas datasheet for further information. | |
176 | */ | |
1da177e4 | 177 | #define NAND_IS_AND 0x00000020 |
a0491fc4 SAS |
178 | /* |
179 | * Chip has a array of 4 pages which can be read without | |
180 | * additional ready /busy waits. | |
181 | */ | |
61ecfa87 | 182 | #define NAND_4PAGE_ARRAY 0x00000040 |
a0491fc4 SAS |
183 | /* |
184 | * Chip requires that BBT is periodically rewritten to prevent | |
28a48de7 | 185 | * bits from adjacent blocks from 'leaking' in altering data. |
a0491fc4 SAS |
186 | * This happens with the Renesas AG-AND chips, possibly others. |
187 | */ | |
28a48de7 | 188 | #define BBT_AUTO_REFRESH 0x00000080 |
a0491fc4 SAS |
189 | /* |
190 | * Chip does not require ready check on read. True | |
7a30601b | 191 | * for all large page devices, as they do not support |
a0491fc4 SAS |
192 | * autoincrement. |
193 | */ | |
7a30601b | 194 | #define NAND_NO_READRDY 0x00000100 |
29072b96 TG |
195 | /* Chip does not allow subpage writes */ |
196 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
197 | ||
93edbad6 ML |
198 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
199 | #define NAND_BROKEN_XD 0x00000400 | |
200 | ||
201 | /* Device behaves just like nand, but is readonly */ | |
202 | #define NAND_ROM 0x00000800 | |
203 | ||
1da177e4 LT |
204 | /* Options valid for Samsung large page devices */ |
205 | #define NAND_SAMSUNG_LP_OPTIONS \ | |
206 | (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) | |
207 | ||
208 | /* Macros to identify the above */ | |
209 | #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) | |
210 | #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) | |
211 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) | |
212 | #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) | |
96d8b647 AK |
213 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
214 | #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ | |
215 | && (chip->page_shift > 9)) | |
1da177e4 LT |
216 | |
217 | /* Mask to zero out the chip options, which come from the id table */ | |
218 | #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) | |
219 | ||
220 | /* Non chip related options */ | |
7cba7b14 SAS |
221 | /* |
222 | * Use a flash based bad block table. OOB identifier is saved in OOB area. | |
223 | * This option is passed to the default bad block table function. | |
224 | */ | |
1da177e4 | 225 | #define NAND_USE_FLASH_BBT 0x00010000 |
0040bf38 | 226 | /* This option skips the bbt scan during initialization. */ |
f75e5097 | 227 | #define NAND_SKIP_BBTSCAN 0x00020000 |
a0491fc4 SAS |
228 | /* |
229 | * This option is defined if the board driver allocates its own buffers | |
230 | * (e.g. because it needs them DMA-coherent). | |
231 | */ | |
4bf63fcb | 232 | #define NAND_OWN_BUFFERS 0x00040000 |
b1c6e6db BD |
233 | /* Chip may not exist, so silence any errors in scan */ |
234 | #define NAND_SCAN_SILENT_NODEV 0x00080000 | |
7cba7b14 SAS |
235 | /* |
236 | * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch | |
237 | * the OOB area. | |
238 | */ | |
239 | #define NAND_USE_FLASH_BBT_NO_OOB 0x00100000 | |
453281a9 SAS |
240 | /* Create an empty BBT with no vendor information if the BBT is available */ |
241 | #define NAND_CREATE_EMPTY_BBT 0x00200000 | |
b1c6e6db | 242 | |
1da177e4 | 243 | /* Options set by nand scan */ |
a36ed299 | 244 | /* Nand scan has allocated controller struct */ |
f75e5097 | 245 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 246 | |
29072b96 TG |
247 | /* Cell info constants */ |
248 | #define NAND_CI_CHIPNR_MSK 0x03 | |
249 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
1da177e4 | 250 | |
1da177e4 LT |
251 | /* Keep gcc happy */ |
252 | struct nand_chip; | |
253 | ||
d1e1f4e4 FF |
254 | struct nand_onfi_params { |
255 | /* rev info and features block */ | |
b46daf7e SAS |
256 | /* 'O' 'N' 'F' 'I' */ |
257 | u8 sig[4]; | |
258 | __le16 revision; | |
259 | __le16 features; | |
260 | __le16 opt_cmd; | |
261 | u8 reserved[22]; | |
d1e1f4e4 FF |
262 | |
263 | /* manufacturer information block */ | |
b46daf7e SAS |
264 | char manufacturer[12]; |
265 | char model[20]; | |
266 | u8 jedec_id; | |
267 | __le16 date_code; | |
268 | u8 reserved2[13]; | |
d1e1f4e4 FF |
269 | |
270 | /* memory organization block */ | |
b46daf7e SAS |
271 | __le32 byte_per_page; |
272 | __le16 spare_bytes_per_page; | |
273 | __le32 data_bytes_per_ppage; | |
274 | __le16 spare_bytes_per_ppage; | |
275 | __le32 pages_per_block; | |
276 | __le32 blocks_per_lun; | |
277 | u8 lun_count; | |
278 | u8 addr_cycles; | |
279 | u8 bits_per_cell; | |
280 | __le16 bb_per_lun; | |
281 | __le16 block_endurance; | |
282 | u8 guaranteed_good_blocks; | |
283 | __le16 guaranteed_block_endurance; | |
284 | u8 programs_per_page; | |
285 | u8 ppage_attr; | |
286 | u8 ecc_bits; | |
287 | u8 interleaved_bits; | |
288 | u8 interleaved_ops; | |
289 | u8 reserved3[13]; | |
d1e1f4e4 FF |
290 | |
291 | /* electrical parameter block */ | |
b46daf7e SAS |
292 | u8 io_pin_capacitance_max; |
293 | __le16 async_timing_mode; | |
294 | __le16 program_cache_timing_mode; | |
295 | __le16 t_prog; | |
296 | __le16 t_bers; | |
297 | __le16 t_r; | |
298 | __le16 t_ccs; | |
299 | __le16 src_sync_timing_mode; | |
300 | __le16 src_ssync_features; | |
301 | __le16 clk_pin_capacitance_typ; | |
302 | __le16 io_pin_capacitance_typ; | |
303 | __le16 input_pin_capacitance_typ; | |
304 | u8 input_pin_capacitance_max; | |
305 | u8 driver_strenght_support; | |
306 | __le16 t_int_r; | |
307 | __le16 t_ald; | |
308 | u8 reserved4[7]; | |
d1e1f4e4 FF |
309 | |
310 | /* vendor */ | |
b46daf7e | 311 | u8 reserved5[90]; |
d1e1f4e4 FF |
312 | |
313 | __le16 crc; | |
314 | } __attribute__((packed)); | |
315 | ||
316 | #define ONFI_CRC_BASE 0x4F4E | |
317 | ||
1da177e4 | 318 | /** |
844d3b42 | 319 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 320 | * @lock: protection lock |
1da177e4 | 321 | * @active: the mtd device which holds the controller currently |
a0491fc4 SAS |
322 | * @wq: wait queue to sleep on if a NAND operation is in |
323 | * progress used instead of the per chip wait queue | |
324 | * when a hw controller is available. | |
1da177e4 LT |
325 | */ |
326 | struct nand_hw_control { | |
b46daf7e | 327 | spinlock_t lock; |
1da177e4 | 328 | struct nand_chip *active; |
0dfc6246 | 329 | wait_queue_head_t wq; |
1da177e4 LT |
330 | }; |
331 | ||
6dfc6d25 TG |
332 | /** |
333 | * struct nand_ecc_ctrl - Control structure for ecc | |
334 | * @mode: ecc mode | |
335 | * @steps: number of ecc steps per page | |
336 | * @size: data bytes per ecc step | |
337 | * @bytes: ecc bytes per step | |
9577f44a TG |
338 | * @total: total number of ecc bytes per page |
339 | * @prepad: padding information for syndrome based ecc generators | |
340 | * @postpad: padding information for syndrome based ecc generators | |
844d3b42 | 341 | * @layout: ECC layout control struct pointer |
6dfc6d25 TG |
342 | * @hwctl: function to control hardware ecc generator. Must only |
343 | * be provided if an hardware ECC is available | |
344 | * @calculate: function for ecc calculation or readback from ecc hardware | |
345 | * @correct: function for ecc correction, matching to ecc generator (sw/hw) | |
956e944c DW |
346 | * @read_page_raw: function to read a raw page without ECC |
347 | * @write_page_raw: function to write a raw page without ECC | |
a0491fc4 SAS |
348 | * @read_page: function to read a page according to the ecc generator |
349 | * requirements. | |
17c1d2be | 350 | * @read_subpage: function to read parts of the page covered by ECC. |
a0491fc4 SAS |
351 | * @write_page: function to write a page according to the ecc generator |
352 | * requirements. | |
844d3b42 RD |
353 | * @read_oob: function to read chip OOB data |
354 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
355 | */ |
356 | struct nand_ecc_ctrl { | |
b46daf7e SAS |
357 | nand_ecc_modes_t mode; |
358 | int steps; | |
359 | int size; | |
360 | int bytes; | |
361 | int total; | |
362 | int prepad; | |
363 | int postpad; | |
5bd34c09 | 364 | struct nand_ecclayout *layout; |
b46daf7e SAS |
365 | void (*hwctl)(struct mtd_info *mtd, int mode); |
366 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
367 | uint8_t *ecc_code); | |
368 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
369 | uint8_t *calc_ecc); | |
370 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
371 | uint8_t *buf, int page); | |
372 | void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
373 | const uint8_t *buf); | |
374 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
375 | uint8_t *buf, int page); | |
376 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, | |
377 | uint32_t offs, uint32_t len, uint8_t *buf); | |
378 | void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
379 | const uint8_t *buf); | |
380 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page, | |
381 | int sndcmd); | |
382 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, | |
383 | int page); | |
f75e5097 TG |
384 | }; |
385 | ||
386 | /** | |
387 | * struct nand_buffers - buffer structure for read/write | |
388 | * @ecccalc: buffer for calculated ecc | |
389 | * @ecccode: buffer for ecc read from flash | |
f75e5097 | 390 | * @databuf: buffer for data - dynamically sized |
f75e5097 TG |
391 | * |
392 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
393 | * consecutive order. | |
394 | */ | |
395 | struct nand_buffers { | |
396 | uint8_t ecccalc[NAND_MAX_OOBSIZE]; | |
397 | uint8_t ecccode[NAND_MAX_OOBSIZE]; | |
7dcdcbef | 398 | uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
6dfc6d25 TG |
399 | }; |
400 | ||
1da177e4 LT |
401 | /** |
402 | * struct nand_chip - NAND Private Flash Chip Data | |
a0491fc4 SAS |
403 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
404 | * flash device | |
405 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
406 | * flash device. | |
1da177e4 | 407 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 408 | * @read_word: [REPLACEABLE] read one word from the chip |
1da177e4 LT |
409 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
410 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
a0491fc4 SAS |
411 | * @verify_buf: [REPLACEABLE] verify buffer contents against the chip |
412 | * data. | |
1da177e4 LT |
413 | * @select_chip: [REPLACEABLE] select chip nr |
414 | * @block_bad: [REPLACEABLE] check, if the block is bad | |
415 | * @block_markbad: [REPLACEABLE] mark the block bad | |
7abd3ef9 TG |
416 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling |
417 | * ALE/CLE/nCE. Also used to write command and address | |
12a40a57 HS |
418 | * @init_size: [BOARDSPECIFIC] hardwarespecific funtion for setting |
419 | * mtd->oobsize, mtd->writesize and so on. | |
420 | * @id_data contains the 8 bytes values of NAND_CMD_READID. | |
421 | * Return with the bus width. | |
a0491fc4 SAS |
422 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing |
423 | * device ready/busy line. If set to NULL no access to | |
424 | * ready/busy is available and the ready/busy information | |
425 | * is read from the chip status register. | |
426 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
427 | * commands to the chip. | |
428 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
429 | * ready. | |
6dfc6d25 | 430 | * @ecc: [BOARDSPECIFIC] ecc control ctructure |
844d3b42 RD |
431 | * @buffers: buffer structure for read/write |
432 | * @hwcontrol: platform-specific hardware control structure | |
433 | * @ops: oob operation operands | |
a0491fc4 SAS |
434 | * @erase_cmd: [INTERN] erase command write function, selectable due |
435 | * to AND support. | |
1da177e4 | 436 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
a0491fc4 SAS |
437 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering |
438 | * data from array to read regs (tR). | |
2c0a2bed | 439 | * @state: [INTERN] the current state of the NAND device |
844d3b42 | 440 | * @oob_poi: poison value buffer |
a0491fc4 SAS |
441 | * @page_shift: [INTERN] number of address bits in a page (column |
442 | * address bits). | |
1da177e4 LT |
443 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
444 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
445 | * @chip_shift: [INTERN] number of address bits in one chip | |
a0491fc4 SAS |
446 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
447 | * be set to inform nand_scan about special functionality. | |
448 | * See the defines for further explanation. | |
449 | * @badblockpos: [INTERN] position of the bad block marker in the oob | |
450 | * area. | |
552a8278 | 451 | * @cellinfo: [INTERN] MLC/multichip data from chip ident |
1da177e4 LT |
452 | * @numchips: [INTERN] number of physical chips |
453 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
454 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
a0491fc4 SAS |
455 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
456 | * data_buf. | |
29072b96 | 457 | * @subpagesize: [INTERN] holds the subpagesize |
a0491fc4 SAS |
458 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
459 | * non 0 if ONFI supported. | |
460 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is | |
461 | * supported, 0 otherwise. | |
5bd34c09 | 462 | * @ecclayout: [REPLACEABLE] the default ecc placement scheme |
1da177e4 | 463 | * @bbt: [INTERN] bad block table pointer |
a0491fc4 SAS |
464 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
465 | * lookup. | |
1da177e4 | 466 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
a0491fc4 SAS |
467 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
468 | * bad block scan. | |
469 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
470 | * structure which is shared among multiple independend | |
471 | * devices. | |
1da177e4 | 472 | * @priv: [OPTIONAL] pointer to private chip date |
a0491fc4 SAS |
473 | * @errstat: [OPTIONAL] hardware specific function to perform |
474 | * additional error status checks (determine if errors are | |
475 | * correctable). | |
351edd24 | 476 | * @write_page: [REPLACEABLE] High-level page write function |
1da177e4 | 477 | */ |
61ecfa87 | 478 | |
1da177e4 | 479 | struct nand_chip { |
b46daf7e SAS |
480 | void __iomem *IO_ADDR_R; |
481 | void __iomem *IO_ADDR_W; | |
482 | ||
483 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
484 | u16 (*read_word)(struct mtd_info *mtd); | |
485 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
486 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
487 | int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
488 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
489 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
490 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
491 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
492 | int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, | |
493 | u8 *id_data); | |
494 | int (*dev_ready)(struct mtd_info *mtd); | |
495 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
496 | int page_addr); | |
497 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
498 | void (*erase_cmd)(struct mtd_info *mtd, int page); | |
499 | int (*scan_bbt)(struct mtd_info *mtd); | |
500 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, | |
501 | int status, int page); | |
502 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
503 | const uint8_t *buf, int page, int cached, int raw); | |
504 | ||
505 | int chip_delay; | |
506 | unsigned int options; | |
507 | ||
508 | int page_shift; | |
509 | int phys_erase_shift; | |
510 | int bbt_erase_shift; | |
511 | int chip_shift; | |
512 | int numchips; | |
513 | uint64_t chipsize; | |
514 | int pagemask; | |
515 | int pagebuf; | |
516 | int subpagesize; | |
517 | uint8_t cellinfo; | |
518 | int badblockpos; | |
519 | int badblockbits; | |
520 | ||
521 | int onfi_version; | |
d1e1f4e4 FF |
522 | struct nand_onfi_params onfi_params; |
523 | ||
b46daf7e | 524 | flstate_t state; |
f75e5097 | 525 | |
b46daf7e SAS |
526 | uint8_t *oob_poi; |
527 | struct nand_hw_control *controller; | |
528 | struct nand_ecclayout *ecclayout; | |
f75e5097 TG |
529 | |
530 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 531 | struct nand_buffers *buffers; |
f75e5097 TG |
532 | struct nand_hw_control hwcontrol; |
533 | ||
8593fbc6 TG |
534 | struct mtd_oob_ops ops; |
535 | ||
b46daf7e SAS |
536 | uint8_t *bbt; |
537 | struct nand_bbt_descr *bbt_td; | |
538 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 539 | |
b46daf7e | 540 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 541 | |
b46daf7e | 542 | void *priv; |
1da177e4 LT |
543 | }; |
544 | ||
545 | /* | |
546 | * NAND Flash Manufacturer ID Codes | |
547 | */ | |
548 | #define NAND_MFR_TOSHIBA 0x98 | |
549 | #define NAND_MFR_SAMSUNG 0xec | |
550 | #define NAND_MFR_FUJITSU 0x04 | |
551 | #define NAND_MFR_NATIONAL 0x8f | |
552 | #define NAND_MFR_RENESAS 0x07 | |
553 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 554 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 555 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 556 | #define NAND_MFR_AMD 0x01 |
1da177e4 LT |
557 | |
558 | /** | |
559 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
2c0a2bed TG |
560 | * @name: Identify the device type |
561 | * @id: device ID code | |
562 | * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 | |
61ecfa87 | 563 | * If the pagesize is 0, then the real pagesize |
1da177e4 LT |
564 | * and the eraseize are determined from the |
565 | * extended id bytes in the chip | |
2c0a2bed TG |
566 | * @erasesize: Size of an erase block in the flash device. |
567 | * @chipsize: Total chipsize in Mega Bytes | |
1da177e4 LT |
568 | * @options: Bitfield to store chip relevant options |
569 | */ | |
570 | struct nand_flash_dev { | |
571 | char *name; | |
572 | int id; | |
573 | unsigned long pagesize; | |
574 | unsigned long chipsize; | |
575 | unsigned long erasesize; | |
576 | unsigned long options; | |
577 | }; | |
578 | ||
579 | /** | |
580 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
581 | * @name: Manufacturer name | |
2c0a2bed | 582 | * @id: manufacturer ID code of device. |
1da177e4 LT |
583 | */ |
584 | struct nand_manufacturers { | |
585 | int id; | |
a0491fc4 | 586 | char *name; |
1da177e4 LT |
587 | }; |
588 | ||
589 | extern struct nand_flash_dev nand_flash_ids[]; | |
590 | extern struct nand_manufacturers nand_manuf_ids[]; | |
591 | ||
f5bbdacc TG |
592 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
593 | extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); | |
594 | extern int nand_default_bbt(struct mtd_info *mtd); | |
595 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); | |
596 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
597 | int allowbbt); | |
598 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
a0491fc4 | 599 | size_t *retlen, uint8_t *buf); |
1da177e4 | 600 | |
41796c2e TG |
601 | /** |
602 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 603 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 604 | * @chip_offset: chip number offset |
8be834f7 | 605 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
606 | * @partitions: mtd partition list |
607 | * @chip_delay: R/B delay value in us | |
608 | * @options: Option flags, e.g. 16bit buswidth | |
5bd34c09 | 609 | * @ecclayout: ecc layout info structure |
972edcb7 | 610 | * @part_probe_types: NULL-terminated array of probe types |
f36e20c0 | 611 | * @set_parts: platform specific function to set partitions |
41796c2e TG |
612 | * @priv: hardware controller specific settings |
613 | */ | |
614 | struct platform_nand_chip { | |
b46daf7e SAS |
615 | int nr_chips; |
616 | int chip_offset; | |
617 | int nr_partitions; | |
618 | struct mtd_partition *partitions; | |
619 | struct nand_ecclayout *ecclayout; | |
620 | int chip_delay; | |
621 | unsigned int options; | |
622 | const char **part_probe_types; | |
623 | void (*set_parts)(uint64_t size, struct platform_nand_chip *chip); | |
624 | void *priv; | |
41796c2e TG |
625 | }; |
626 | ||
bf95efd4 HS |
627 | /* Keep gcc happy */ |
628 | struct platform_device; | |
629 | ||
41796c2e TG |
630 | /** |
631 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
632 | * @probe: platform specific function to probe/setup hardware |
633 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
634 | * @hwcontrol: platform specific hardware control structure |
635 | * @dev_ready: platform specific function to read ready/busy pin | |
636 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
637 | * @cmd_ctrl: platform specific function for controlling |
638 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
639 | * @write_buf: platform specific function for write buffer |
640 | * @read_buf: platform specific function for read buffer | |
844d3b42 | 641 | * @priv: private data to transport driver specific settings |
41796c2e TG |
642 | * |
643 | * All fields are optional and depend on the hardware driver requirements | |
644 | */ | |
645 | struct platform_nand_ctrl { | |
b46daf7e SAS |
646 | int (*probe)(struct platform_device *pdev); |
647 | void (*remove)(struct platform_device *pdev); | |
648 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
649 | int (*dev_ready)(struct mtd_info *mtd); | |
650 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
651 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
652 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
653 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
654 | void *priv; | |
41796c2e TG |
655 | }; |
656 | ||
972edcb7 VW |
657 | /** |
658 | * struct platform_nand_data - container structure for platform-specific data | |
659 | * @chip: chip level chip structure | |
660 | * @ctrl: controller level device structure | |
661 | */ | |
662 | struct platform_nand_data { | |
b46daf7e SAS |
663 | struct platform_nand_chip chip; |
664 | struct platform_nand_ctrl ctrl; | |
972edcb7 VW |
665 | }; |
666 | ||
41796c2e TG |
667 | /* Some helpers to access the data structures */ |
668 | static inline | |
669 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
670 | { | |
671 | struct nand_chip *chip = mtd->priv; | |
672 | ||
673 | return chip->priv; | |
674 | } | |
675 | ||
1da177e4 | 676 | #endif /* __LINUX_MTD_NAND_H */ |