[net-next-2.6.git] / include / linux / mtd / cfi.h

/*
 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */

#ifndef __MTD_CFI_H__
#define __MTD_CFI_H__

#include <linux/delay.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/mtd/flashchip.h>
#include <linux/mtd/map.h>
#include <linux/mtd/cfi_endian.h>
#include <linux/mtd/xip.h>

#ifdef CONFIG_MTD_CFI_I1
#define cfi_interleave(cfi) 1
#define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
#else
#define cfi_interleave_is_1(cfi) (0)
#endif

#ifdef CONFIG_MTD_CFI_I2
# ifdef cfi_interleave
#  undef cfi_interleave
#  define cfi_interleave(cfi) ((cfi)->interleave)
# else
#  define cfi_interleave(cfi) 2
# endif
#define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
#else
#define cfi_interleave_is_2(cfi) (0)
#endif

#ifdef CONFIG_MTD_CFI_I4
# ifdef cfi_interleave
#  undef cfi_interleave
#  define cfi_interleave(cfi) ((cfi)->interleave)
# else
#  define cfi_interleave(cfi) 4
# endif
#define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
#else
#define cfi_interleave_is_4(cfi) (0)
#endif

#ifdef CONFIG_MTD_CFI_I8
# ifdef cfi_interleave
#  undef cfi_interleave
#  define cfi_interleave(cfi) ((cfi)->interleave)
# else
#  define cfi_interleave(cfi) 8
# endif
#define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
#else
#define cfi_interleave_is_8(cfi) (0)
#endif

#ifndef cfi_interleave
#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
static inline int cfi_interleave(void *cfi)
{
	BUG();
	return 0;
}
#endif

static inline int cfi_interleave_supported(int i)
{
	switch (i) {
#ifdef CONFIG_MTD_CFI_I1
	case 1:
#endif
#ifdef CONFIG_MTD_CFI_I2
	case 2:
#endif
#ifdef CONFIG_MTD_CFI_I4
	case 4:
#endif
#ifdef CONFIG_MTD_CFI_I8
	case 8:
#endif
		return 1;

	default:
		return 0;
	}
}


/* NB: these values must represents the number of bytes needed to meet the
 *     device type (x8, x16, x32).  Eg. a 32 bit device is 4 x 8 bytes.
 *     These numbers are used in calculations.
 */
#define CFI_DEVICETYPE_X8  (8 / 8)
#define CFI_DEVICETYPE_X16 (16 / 8)
#define CFI_DEVICETYPE_X32 (32 / 8)
#define CFI_DEVICETYPE_X64 (64 / 8)


/* Device Interface Code Assignments from the "Common Flash Memory Interface
 * Publication 100" dated December 1, 2001.
 */
#define CFI_INTERFACE_X8_ASYNC		0x0000
#define CFI_INTERFACE_X16_ASYNC		0x0001
#define CFI_INTERFACE_X8_BY_X16_ASYNC	0x0002
#define CFI_INTERFACE_X32_ASYNC		0x0003
#define CFI_INTERFACE_X16_BY_X32_ASYNC	0x0005
#define CFI_INTERFACE_NOT_ALLOWED	0xffff


/* NB: We keep these structures in memory in HOST byteorder, except
 * where individually noted.
 */

/* Basic Query Structure */
struct cfi_ident {
	uint8_t  qry[3];
	uint16_t P_ID;
	uint16_t P_ADR;
	uint16_t A_ID;
	uint16_t A_ADR;
	uint8_t  VccMin;
	uint8_t  VccMax;
	uint8_t  VppMin;
	uint8_t  VppMax;
	uint8_t  WordWriteTimeoutTyp;
	uint8_t  BufWriteTimeoutTyp;
	uint8_t  BlockEraseTimeoutTyp;
	uint8_t  ChipEraseTimeoutTyp;
	uint8_t  WordWriteTimeoutMax;
	uint8_t  BufWriteTimeoutMax;
	uint8_t  BlockEraseTimeoutMax;
	uint8_t  ChipEraseTimeoutMax;
	uint8_t  DevSize;
	uint16_t InterfaceDesc;
	uint16_t MaxBufWriteSize;
	uint8_t  NumEraseRegions;
	uint32_t EraseRegionInfo[0]; /* Not host ordered */
} __attribute__((packed));

/* Extended Query Structure for both PRI and ALT */

struct cfi_extquery {
	uint8_t  pri[3];
	uint8_t  MajorVersion;
	uint8_t  MinorVersion;
} __attribute__((packed));

/* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */

struct cfi_pri_intelext {
	uint8_t  pri[3];
	uint8_t  MajorVersion;
	uint8_t  MinorVersion;
	uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
				    block follows - FIXME - not currently supported */
	uint8_t  SuspendCmdSupport;
	uint16_t BlkStatusRegMask;
	uint8_t  VccOptimal;
	uint8_t  VppOptimal;
	uint8_t  NumProtectionFields;
	uint16_t ProtRegAddr;
	uint8_t  FactProtRegSize;
	uint8_t  UserProtRegSize;
	uint8_t  extra[0];
} __attribute__((packed));

struct cfi_intelext_otpinfo {
	uint32_t ProtRegAddr;
	uint16_t FactGroups;
	uint8_t  FactProtRegSize;
	uint16_t UserGroups;
	uint8_t  UserProtRegSize;
} __attribute__((packed));

struct cfi_intelext_blockinfo {
	uint16_t NumIdentBlocks;
	uint16_t BlockSize;
	uint16_t MinBlockEraseCycles;
	uint8_t  BitsPerCell;
	uint8_t  BlockCap;
} __attribute__((packed));

struct cfi_intelext_regioninfo {
	uint16_t NumIdentPartitions;
	uint8_t  NumOpAllowed;
	uint8_t  NumOpAllowedSimProgMode;
	uint8_t  NumOpAllowedSimEraMode;
	uint8_t  NumBlockTypes;
	struct cfi_intelext_blockinfo BlockTypes[1];
} __attribute__((packed));

struct cfi_intelext_programming_regioninfo {
	uint8_t  ProgRegShift;
	uint8_t  Reserved1;
	uint8_t  ControlValid;
	uint8_t  Reserved2;
	uint8_t  ControlInvalid;
	uint8_t  Reserved3;
} __attribute__((packed));

/* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */

struct cfi_pri_amdstd {
	uint8_t  pri[3];
	uint8_t  MajorVersion;
	uint8_t  MinorVersion;
	uint8_t  SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
	uint8_t  EraseSuspend;
	uint8_t  BlkProt;
	uint8_t  TmpBlkUnprotect;
	uint8_t  BlkProtUnprot;
	uint8_t  SimultaneousOps;
	uint8_t  BurstMode;
	uint8_t  PageMode;
	uint8_t  VppMin;
	uint8_t  VppMax;
	uint8_t  TopBottom;
} __attribute__((packed));

/* Vendor-Specific PRI for Atmel chips (command set 0x0002) */

struct cfi_pri_atmel {
	uint8_t pri[3];
	uint8_t MajorVersion;
	uint8_t MinorVersion;
	uint8_t Features;
	uint8_t BottomBoot;
	uint8_t BurstMode;
	uint8_t PageMode;
} __attribute__((packed));

struct cfi_pri_query {
	uint8_t  NumFields;
	uint32_t ProtField[1]; /* Not host ordered */
} __attribute__((packed));

struct cfi_bri_query {
	uint8_t  PageModeReadCap;
	uint8_t  NumFields;
	uint32_t ConfField[1]; /* Not host ordered */
} __attribute__((packed));

#define P_ID_NONE               0x0000
#define P_ID_INTEL_EXT          0x0001
#define P_ID_AMD_STD            0x0002
#define P_ID_INTEL_STD          0x0003
#define P_ID_AMD_EXT            0x0004
#define P_ID_WINBOND            0x0006
#define P_ID_ST_ADV             0x0020
#define P_ID_MITSUBISHI_STD     0x0100
#define P_ID_MITSUBISHI_EXT     0x0101
#define P_ID_SST_PAGE           0x0102
#define P_ID_SST_OLD            0x0701
#define P_ID_INTEL_PERFORMANCE  0x0200
#define P_ID_INTEL_DATA         0x0210
#define P_ID_RESERVED           0xffff


#define CFI_MODE_CFI	1
#define CFI_MODE_JEDEC	0

struct cfi_private {
	uint16_t cmdset;
	void *cmdset_priv;
	int interleave;
	int device_type;
	int cfi_mode;		/* Are we a JEDEC device pretending to be CFI? */
	int addr_unlock1;
	int addr_unlock2;
	struct mtd_info *(*cmdset_setup)(struct map_info *);
	struct cfi_ident *cfiq; /* For now only one. We insist that all devs
				  must be of the same type. */
	int mfr, id;
	int numchips;
	map_word sector_erase_cmd;
	unsigned long chipshift; /* Because they're of the same type */
	const char *im_name;	 /* inter_module name for cmdset_setup */
	struct flchip chips[0];  /* per-chip data structure for each chip */
};

/*
 * Returns the command address according to the given geometry.
 */
static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs,
				struct map_info *map, struct cfi_private *cfi)
{
	unsigned bankwidth = map_bankwidth(map);
	unsigned interleave = cfi_interleave(cfi);
	unsigned type = cfi->device_type;
	uint32_t addr;
	
	addr = (cmd_ofs * type) * interleave;

	/* Modify the unlock address if we are in compatiblity mode.
	 * For 16bit devices on 8 bit busses
	 * and 32bit devices on 16 bit busses
	 * set the low bit of the alternating bit sequence of the address.
	 */
	if (((type * interleave) > bankwidth) && ((cmd_ofs & 0xff) == 0xaa))
		addr |= (type >> 1)*interleave;

	return  addr;
}

/*
 * Transforms the CFI command for the given geometry (bus width & interleave).
 * It looks too long to be inline, but in the common case it should almost all
 * get optimised away.
 */
static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi)
{
	map_word val = { {0} };
	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	unsigned long onecmd;
	int i;

	/* We do it this way to give the compiler a fighting chance
	   of optimising away all the crap for 'bankwidth' larger than
	   an unsigned long, in the common case where that support is
	   disabled */
	if (map_bankwidth_is_large(map)) {
		wordwidth = sizeof(unsigned long);
		words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	} else {
		wordwidth = map_bankwidth(map);
		words_per_bus = 1;
	}

	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);

	/* First, determine what the bit-pattern should be for a single
	   device, according to chip mode and endianness... */
	switch (chip_mode) {
	default: BUG();
	case 1:
		onecmd = cmd;
		break;
	case 2:
		onecmd = cpu_to_cfi16(cmd);
		break;
	case 4:
		onecmd = cpu_to_cfi32(cmd);
		break;
	}

	/* Now replicate it across the size of an unsigned long, or
	   just to the bus width as appropriate */
	switch (chips_per_word) {
	default: BUG();
#if BITS_PER_LONG >= 64
	case 8:
		onecmd |= (onecmd << (chip_mode * 32));
#endif
	case 4:
		onecmd |= (onecmd << (chip_mode * 16));
	case 2:
		onecmd |= (onecmd << (chip_mode * 8));
	case 1:
		;
	}

	/* And finally, for the multi-word case, replicate it
	   in all words in the structure */
	for (i=0; i < words_per_bus; i++) {
		val.x[i] = onecmd;
	}

	return val;
}
#define CMD(x)  cfi_build_cmd((x), map, cfi)


static inline unsigned long cfi_merge_status(map_word val, struct map_info *map,
					   struct cfi_private *cfi)
{
	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	unsigned long onestat, res = 0;
	int i;

	/* We do it this way to give the compiler a fighting chance
	   of optimising away all the crap for 'bankwidth' larger than
	   an unsigned long, in the common case where that support is
	   disabled */
	if (map_bankwidth_is_large(map)) {
		wordwidth = sizeof(unsigned long);
		words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	} else {
		wordwidth = map_bankwidth(map);
		words_per_bus = 1;
	}

	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);

	onestat = val.x[0];
	/* Or all status words together */
	for (i=1; i < words_per_bus; i++) {
		onestat |= val.x[i];
	}

	res = onestat;
	switch(chips_per_word) {
	default: BUG();
#if BITS_PER_LONG >= 64
	case 8:
		res |= (onestat >> (chip_mode * 32));
#endif
	case 4:
		res |= (onestat >> (chip_mode * 16));
	case 2:
		res |= (onestat >> (chip_mode * 8));
	case 1:
		;
	}

	/* Last, determine what the bit-pattern should be for a single
	   device, according to chip mode and endianness... */
	switch (chip_mode) {
	case 1:
		break;
	case 2:
		res = cfi16_to_cpu(res);
		break;
	case 4:
		res = cfi32_to_cpu(res);
		break;
	default: BUG();
	}
	return res;
}

#define MERGESTATUS(x) cfi_merge_status((x), map, cfi)


/*
 * Sends a CFI command to a bank of flash for the given geometry.
 *
 * Returns the offset in flash where the command was written.
 * If prev_val is non-null, it will be set to the value at the command address,
 * before the command was written.
 */
static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
				struct map_info *map, struct cfi_private *cfi,
				int type, map_word *prev_val)
{
	map_word val;
	uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi);
	val = cfi_build_cmd(cmd, map, cfi);

	if (prev_val)
		*prev_val = map_read(map, addr);

	map_write(map, val, addr);

	return addr - base;
}

static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
{
	map_word val = map_read(map, addr);

	if (map_bankwidth_is_1(map)) {
		return val.x[0];
	} else if (map_bankwidth_is_2(map)) {
		return cfi16_to_cpu(val.x[0]);
	} else {
		/* No point in a 64-bit byteswap since that would just be
		   swapping the responses from different chips, and we are
		   only interested in one chip (a representative sample) */
		return cfi32_to_cpu(val.x[0]);
	}
}

static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr)
{
	map_word val = map_read(map, addr);

	if (map_bankwidth_is_1(map)) {
		return val.x[0] & 0xff;
	} else if (map_bankwidth_is_2(map)) {
		return cfi16_to_cpu(val.x[0]);
	} else {
		/* No point in a 64-bit byteswap since that would just be
		   swapping the responses from different chips, and we are
		   only interested in one chip (a representative sample) */
		return cfi32_to_cpu(val.x[0]);
	}
}

static inline void cfi_udelay(int us)
{
	if (us >= 1000) {
		msleep((us+999)/1000);
	} else {
		udelay(us);
		cond_resched();
	}
}

int __xipram cfi_qry_present(struct map_info *map, __u32 base,
			     struct cfi_private *cfi);
int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map,
			     struct cfi_private *cfi);
void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
			       struct cfi_private *cfi);

struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
			     const char* name);
struct cfi_fixup {
	uint16_t mfr;
	uint16_t id;
	void (*fixup)(struct mtd_info *mtd, void* param);
	void* param;
};

#define CFI_MFR_ANY		0xFFFF
#define CFI_ID_ANY		0xFFFF
#define CFI_MFR_CONTINUATION	0x007F

#define CFI_MFR_AMD		0x0001
#define CFI_MFR_ATMEL		0x001F
#define CFI_MFR_EON		0x001C
#define CFI_MFR_FUJITSU		0x0004
#define CFI_MFR_HYUNDAI		0x00AD
#define CFI_MFR_INTEL		0x0089
#define CFI_MFR_MACRONIX	0x00C2
#define CFI_MFR_NEC		0x0010
#define CFI_MFR_PMC		0x009D
#define CFI_MFR_SAMSUNG		0x00EC
#define CFI_MFR_SHARP		0x00B0
#define CFI_MFR_SST		0x00BF
#define CFI_MFR_ST		0x0020 /* STMicroelectronics */
#define CFI_MFR_TOSHIBA		0x0098
#define CFI_MFR_WINBOND		0x00DA

void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups);

typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip,
			      unsigned long adr, int len, void *thunk);

int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
	loff_t ofs, size_t len, void *thunk);


#endif /* __MTD_CFI_H__ */
Commit	Line	Data
a1452a37 DW	1	/*
	2	* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> et al.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	17	*
1da177e4 LT	18	*/
	19
	20	#ifndef __MTD_CFI_H__
	21	#define __MTD_CFI_H__
	22
1da177e4 LT	23	#include <linux/delay.h>
	24	#include <linux/types.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/mtd/flashchip.h>
	27	#include <linux/mtd/map.h>
	28	#include <linux/mtd/cfi_endian.h>
2e489e07	29	#include <linux/mtd/xip.h>
1da177e4 LT	30
	31	#ifdef CONFIG_MTD_CFI_I1
	32	#define cfi_interleave(cfi) 1
	33	#define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
	34	#else
	35	#define cfi_interleave_is_1(cfi) (0)
	36	#endif
	37
	38	#ifdef CONFIG_MTD_CFI_I2
	39	# ifdef cfi_interleave
	40	# undef cfi_interleave
	41	# define cfi_interleave(cfi) ((cfi)->interleave)
	42	# else
	43	# define cfi_interleave(cfi) 2
	44	# endif
	45	#define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
	46	#else
	47	#define cfi_interleave_is_2(cfi) (0)
	48	#endif
	49
	50	#ifdef CONFIG_MTD_CFI_I4
	51	# ifdef cfi_interleave
	52	# undef cfi_interleave
	53	# define cfi_interleave(cfi) ((cfi)->interleave)
	54	# else
	55	# define cfi_interleave(cfi) 4
	56	# endif
	57	#define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
	58	#else
	59	#define cfi_interleave_is_4(cfi) (0)
	60	#endif
	61
	62	#ifdef CONFIG_MTD_CFI_I8
	63	# ifdef cfi_interleave
	64	# undef cfi_interleave
	65	# define cfi_interleave(cfi) ((cfi)->interleave)
	66	# else
	67	# define cfi_interleave(cfi) 8
	68	# endif
	69	#define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
	70	#else
	71	#define cfi_interleave_is_8(cfi) (0)
	72	#endif
	73
241651d0 DW	74	#ifndef cfi_interleave
	75	#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
	76	static inline int cfi_interleave(void *cfi)
	77	{
	78	BUG();
	79	return 0;
	80	}
	81	#endif
	82
1da177e4 LT	83	static inline int cfi_interleave_supported(int i)
	84	{
	85	switch (i) {
	86	#ifdef CONFIG_MTD_CFI_I1
	87	case 1:
	88	#endif
	89	#ifdef CONFIG_MTD_CFI_I2
	90	case 2:
	91	#endif
	92	#ifdef CONFIG_MTD_CFI_I4
	93	case 4:
	94	#endif
	95	#ifdef CONFIG_MTD_CFI_I8
	96	case 8:
	97	#endif
	98	return 1;
	99
	100	default:
	101	return 0;
	102	}
	103	}
	104
	105
61ecfa87 TG	106	/* NB: these values must represents the number of bytes needed to meet the
61ecfa87 TG	107	* device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes.
1da177e4 LT	108	* These numbers are used in calculations.
	109	*/
	110	#define CFI_DEVICETYPE_X8 (8 / 8)
	111	#define CFI_DEVICETYPE_X16 (16 / 8)
	112	#define CFI_DEVICETYPE_X32 (32 / 8)
	113	#define CFI_DEVICETYPE_X64 (64 / 8)
	114
de7921f0 BS	115
	116	/* Device Interface Code Assignments from the "Common Flash Memory Interface
	117	* Publication 100" dated December 1, 2001.
	118	*/
	119	#define CFI_INTERFACE_X8_ASYNC 0x0000
	120	#define CFI_INTERFACE_X16_ASYNC 0x0001
	121	#define CFI_INTERFACE_X8_BY_X16_ASYNC 0x0002
	122	#define CFI_INTERFACE_X32_ASYNC 0x0003
	123	#define CFI_INTERFACE_X16_BY_X32_ASYNC 0x0005
	124	#define CFI_INTERFACE_NOT_ALLOWED 0xffff
	125
	126
1da177e4 LT	127	/* NB: We keep these structures in memory in HOST byteorder, except
	128	* where individually noted.
	129	*/
	130
	131	/* Basic Query Structure */
	132	struct cfi_ident {
	133	uint8_t qry[3];
	134	uint16_t P_ID;
	135	uint16_t P_ADR;
	136	uint16_t A_ID;
	137	uint16_t A_ADR;
	138	uint8_t VccMin;
	139	uint8_t VccMax;
	140	uint8_t VppMin;
	141	uint8_t VppMax;
	142	uint8_t WordWriteTimeoutTyp;
	143	uint8_t BufWriteTimeoutTyp;
	144	uint8_t BlockEraseTimeoutTyp;
	145	uint8_t ChipEraseTimeoutTyp;
	146	uint8_t WordWriteTimeoutMax;
	147	uint8_t BufWriteTimeoutMax;
	148	uint8_t BlockEraseTimeoutMax;
	149	uint8_t ChipEraseTimeoutMax;
	150	uint8_t DevSize;
	151	uint16_t InterfaceDesc;
	152	uint16_t MaxBufWriteSize;
	153	uint8_t NumEraseRegions;
	154	uint32_t EraseRegionInfo[0]; /* Not host ordered */
	155	} __attribute__((packed));
	156
	157	/* Extended Query Structure for both PRI and ALT */
	158
	159	struct cfi_extquery {
	160	uint8_t pri[3];
	161	uint8_t MajorVersion;
	162	uint8_t MinorVersion;
	163	} __attribute__((packed));
	164
	165	/* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
	166
	167	struct cfi_pri_intelext {
	168	uint8_t pri[3];
	169	uint8_t MajorVersion;
	170	uint8_t MinorVersion;
	171	uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
	172	block follows - FIXME - not currently supported */
	173	uint8_t SuspendCmdSupport;
	174	uint16_t BlkStatusRegMask;
	175	uint8_t VccOptimal;
	176	uint8_t VppOptimal;
	177	uint8_t NumProtectionFields;
	178	uint16_t ProtRegAddr;
	179	uint8_t FactProtRegSize;
	180	uint8_t UserProtRegSize;
	181	uint8_t extra[0];
	182	} __attribute__((packed));
	183
72b56a2d NP	184	struct cfi_intelext_otpinfo {
	185	uint32_t ProtRegAddr;
	186	uint16_t FactGroups;
	187	uint8_t FactProtRegSize;
	188	uint16_t UserGroups;
	189	uint8_t UserProtRegSize;
	190	} __attribute__((packed));
	191
1da177e4 LT	192	struct cfi_intelext_blockinfo {
	193	uint16_t NumIdentBlocks;
	194	uint16_t BlockSize;
	195	uint16_t MinBlockEraseCycles;
	196	uint8_t BitsPerCell;
	197	uint8_t BlockCap;
	198	} __attribute__((packed));
	199
	200	struct cfi_intelext_regioninfo {
	201	uint16_t NumIdentPartitions;
	202	uint8_t NumOpAllowed;
	203	uint8_t NumOpAllowedSimProgMode;
	204	uint8_t NumOpAllowedSimEraMode;
	205	uint8_t NumBlockTypes;
	206	struct cfi_intelext_blockinfo BlockTypes[1];
	207	} __attribute__((packed));
	208
638d9838 NP	209	struct cfi_intelext_programming_regioninfo {
	210	uint8_t ProgRegShift;
	211	uint8_t Reserved1;
	212	uint8_t ControlValid;
	213	uint8_t Reserved2;
	214	uint8_t ControlInvalid;
	215	uint8_t Reserved3;
	216	} __attribute__((packed));
	217
1da177e4 LT	218	/* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
	219
	220	struct cfi_pri_amdstd {
	221	uint8_t pri[3];
	222	uint8_t MajorVersion;
	223	uint8_t MinorVersion;
	224	uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
	225	uint8_t EraseSuspend;
	226	uint8_t BlkProt;
	227	uint8_t TmpBlkUnprotect;
	228	uint8_t BlkProtUnprot;
	229	uint8_t SimultaneousOps;
	230	uint8_t BurstMode;
	231	uint8_t PageMode;
	232	uint8_t VppMin;
	233	uint8_t VppMax;
	234	uint8_t TopBottom;
	235	} __attribute__((packed));
	236
5b0c5c2c HS	237	/* Vendor-Specific PRI for Atmel chips (command set 0x0002) */
	238
	239	struct cfi_pri_atmel {
	240	uint8_t pri[3];
	241	uint8_t MajorVersion;
	242	uint8_t MinorVersion;
	243	uint8_t Features;
	244	uint8_t BottomBoot;
	245	uint8_t BurstMode;
	246	uint8_t PageMode;
	247	} __attribute__((packed));
	248
1da177e4 LT	249	struct cfi_pri_query {
	250	uint8_t NumFields;
	251	uint32_t ProtField[1]; /* Not host ordered */
	252	} __attribute__((packed));
	253
	254	struct cfi_bri_query {
	255	uint8_t PageModeReadCap;
	256	uint8_t NumFields;
	257	uint32_t ConfField[1]; /* Not host ordered */
	258	} __attribute__((packed));
	259
	260	#define P_ID_NONE 0x0000
	261	#define P_ID_INTEL_EXT 0x0001
	262	#define P_ID_AMD_STD 0x0002
	263	#define P_ID_INTEL_STD 0x0003
	264	#define P_ID_AMD_EXT 0x0004
	265	#define P_ID_WINBOND 0x0006
	266	#define P_ID_ST_ADV 0x0020
	267	#define P_ID_MITSUBISHI_STD 0x0100
	268	#define P_ID_MITSUBISHI_EXT 0x0101
	269	#define P_ID_SST_PAGE 0x0102
54b93a49	270	#define P_ID_SST_OLD 0x0701
1da177e4 LT	271	#define P_ID_INTEL_PERFORMANCE 0x0200
	272	#define P_ID_INTEL_DATA 0x0210
	273	#define P_ID_RESERVED 0xffff
	274
	275
	276	#define CFI_MODE_CFI 1
	277	#define CFI_MODE_JEDEC 0
	278
	279	struct cfi_private {
	280	uint16_t cmdset;
	281	void *cmdset_priv;
	282	int interleave;
	283	int device_type;
	284	int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */
	285	int addr_unlock1;
	286	int addr_unlock2;
	287	struct mtd_info (cmdset_setup)(struct map_info *);
	288	struct cfi_ident cfiq; / For now only one. We insist that all devs
	289	must be of the same type. */
	290	int mfr, id;
	291	int numchips;
08968041	292	map_word sector_erase_cmd;
1da177e4 LT	293	unsigned long chipshift; /* Because they're of the same type */
	294	const char im_name; / inter_module name for cmdset_setup */
	295	struct flchip chips[0]; /* per-chip data structure for each chip */
	296	};
	297
	298	/*
	299	* Returns the command address according to the given geometry.
	300	*/
467622ef EB	301	static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs,
467622ef EB	302	struct map_info map, struct cfi_private cfi)
1da177e4	303	{
467622ef EB	304	unsigned bankwidth = map_bankwidth(map);
	305	unsigned interleave = cfi_interleave(cfi);
	306	unsigned type = cfi->device_type;
	307	uint32_t addr;
	308
	309	addr = (cmd_ofs * type) * interleave;
	310
	311	/* Modify the unlock address if we are in compatiblity mode.
	312	* For 16bit devices on 8 bit busses
	313	* and 32bit devices on 16 bit busses
	314	* set the low bit of the alternating bit sequence of the address.
	315	*/
1449c5d0	316	if (((type * interleave) > bankwidth) && ((cmd_ofs & 0xff) == 0xaa))
467622ef EB	317	addr \|= (type >> 1)*interleave;
	318
	319	return addr;
1da177e4 LT	320	}
	321
	322	/*
	323	* Transforms the CFI command for the given geometry (bus width & interleave).
	324	* It looks too long to be inline, but in the common case it should almost all
61ecfa87	325	* get optimised away.
1da177e4	326	*/
f77814dd	327	static inline map_word cfi_build_cmd(u_long cmd, struct map_info map, struct cfi_private cfi)
1da177e4 LT	328	{
	329	map_word val = { {0} };
	330	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	331	unsigned long onecmd;
	332	int i;
	333
61ecfa87	334	/* We do it this way to give the compiler a fighting chance
1da177e4 LT	335	of optimising away all the crap for 'bankwidth' larger than
	336	an unsigned long, in the common case where that support is
	337	disabled */
	338	if (map_bankwidth_is_large(map)) {
	339	wordwidth = sizeof(unsigned long);
	340	words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	341	} else {
	342	wordwidth = map_bankwidth(map);
	343	words_per_bus = 1;
	344	}
61ecfa87	345
1da177e4 LT	346	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	347	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
	348
	349	/* First, determine what the bit-pattern should be for a single
	350	device, according to chip mode and endianness... */
	351	switch (chip_mode) {
	352	default: BUG();
	353	case 1:
	354	onecmd = cmd;
	355	break;
	356	case 2:
	357	onecmd = cpu_to_cfi16(cmd);
	358	break;
	359	case 4:
	360	onecmd = cpu_to_cfi32(cmd);
	361	break;
	362	}
	363
61ecfa87	364	/* Now replicate it across the size of an unsigned long, or
1da177e4 LT	365	just to the bus width as appropriate */
	366	switch (chips_per_word) {
	367	default: BUG();
	368	#if BITS_PER_LONG >= 64
	369	case 8:
	370	onecmd \|= (onecmd << (chip_mode * 32));
	371	#endif
	372	case 4:
	373	onecmd \|= (onecmd << (chip_mode * 16));
	374	case 2:
	375	onecmd \|= (onecmd << (chip_mode * 8));
	376	case 1:
	377	;
	378	}
	379
61ecfa87	380	/* And finally, for the multi-word case, replicate it
1da177e4 LT	381	in all words in the structure */
	382	for (i=0; i < words_per_bus; i++) {
	383	val.x[i] = onecmd;
	384	}
	385
	386	return val;
	387	}
	388	#define CMD(x) cfi_build_cmd((x), map, cfi)
	389
c927cd3a	390
61ecfa87	391	static inline unsigned long cfi_merge_status(map_word val, struct map_info *map,
c927cd3a TG	392	struct cfi_private *cfi)
	393	{
	394	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	395	unsigned long onestat, res = 0;
	396	int i;
	397
61ecfa87	398	/* We do it this way to give the compiler a fighting chance
c927cd3a TG	399	of optimising away all the crap for 'bankwidth' larger than
	400	an unsigned long, in the common case where that support is
	401	disabled */
	402	if (map_bankwidth_is_large(map)) {
	403	wordwidth = sizeof(unsigned long);
	404	words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	405	} else {
	406	wordwidth = map_bankwidth(map);
	407	words_per_bus = 1;
	408	}
61ecfa87	409
c927cd3a TG	410	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	411	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
	412
	413	onestat = val.x[0];
	414	/* Or all status words together */
	415	for (i=1; i < words_per_bus; i++) {
	416	onestat \|= val.x[i];
	417	}
	418
	419	res = onestat;
	420	switch(chips_per_word) {
	421	default: BUG();
	422	#if BITS_PER_LONG >= 64
	423	case 8:
	424	res \|= (onestat >> (chip_mode * 32));
	425	#endif
	426	case 4:
	427	res \|= (onestat >> (chip_mode * 16));
	428	case 2:
	429	res \|= (onestat >> (chip_mode * 8));
	430	case 1:
	431	;
	432	}
	433
	434	/* Last, determine what the bit-pattern should be for a single
	435	device, according to chip mode and endianness... */
	436	switch (chip_mode) {
	437	case 1:
	438	break;
	439	case 2:
	440	res = cfi16_to_cpu(res);
	441	break;
	442	case 4:
	443	res = cfi32_to_cpu(res);
	444	break;
	445	default: BUG();
	446	}
	447	return res;
	448	}
	449
	450	#define MERGESTATUS(x) cfi_merge_status((x), map, cfi)
	451
	452
1da177e4 LT	453	/*
	454	* Sends a CFI command to a bank of flash for the given geometry.
	455	*
	456	* Returns the offset in flash where the command was written.
	457	* If prev_val is non-null, it will be set to the value at the command address,
	458	* before the command was written.
	459	*/
	460	static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
	461	struct map_info map, struct cfi_private cfi,
	462	int type, map_word *prev_val)
	463	{
	464	map_word val;
467622ef	465	uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi);
1da177e4 LT	466	val = cfi_build_cmd(cmd, map, cfi);
	467
	468	if (prev_val)
	469	*prev_val = map_read(map, addr);
	470
	471	map_write(map, val, addr);
	472
	473	return addr - base;
	474	}
	475
	476	static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
	477	{
	478	map_word val = map_read(map, addr);
	479
	480	if (map_bankwidth_is_1(map)) {
	481	return val.x[0];
	482	} else if (map_bankwidth_is_2(map)) {
	483	return cfi16_to_cpu(val.x[0]);
987d2401 TP	484	} else {
	485	/* No point in a 64-bit byteswap since that would just be
	486	swapping the responses from different chips, and we are
	487	only interested in one chip (a representative sample) */
	488	return cfi32_to_cpu(val.x[0]);
	489	}
	490	}
	491
	492	static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr)
	493	{
	494	map_word val = map_read(map, addr);
	495
	496	if (map_bankwidth_is_1(map)) {
	497	return val.x[0] & 0xff;
	498	} else if (map_bankwidth_is_2(map)) {
	499	return cfi16_to_cpu(val.x[0]);
1da177e4 LT	500	} else {
	501	/* No point in a 64-bit byteswap since that would just be
	502	swapping the responses from different chips, and we are
	503	only interested in one chip (a representative sample) */
	504	return cfi32_to_cpu(val.x[0]);
	505	}
	506	}
	507
	508	static inline void cfi_udelay(int us)
	509	{
	510	if (us >= 1000) {
	511	msleep((us+999)/1000);
	512	} else {
	513	udelay(us);
	514	cond_resched();
	515	}
	516	}
	517
c314dfdc DW	518	int __xipram cfi_qry_present(struct map_info *map, __u32 base,
	519	struct cfi_private *cfi);
	520	int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map,
	521	struct cfi_private *cfi);
	522	void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
	523	struct cfi_private *cfi);
2e489e07	524
1da177e4 LT	525	struct cfi_extquery cfi_read_pri(struct map_info map, uint16_t adr, uint16_t size,
	526	const char* name);
	527	struct cfi_fixup {
	528	uint16_t mfr;
	529	uint16_t id;
	530	void (fixup)(struct mtd_info mtd, void* param);
	531	void* param;
	532	};
	533
ae731822 WS	534	#define CFI_MFR_ANY 0xFFFF
	535	#define CFI_ID_ANY 0xFFFF
	536	#define CFI_MFR_CONTINUATION 0x007F
1da177e4	537
f3e69c65 GL	538	#define CFI_MFR_AMD 0x0001
f3e69c65 GL	539	#define CFI_MFR_ATMEL 0x001F
ae731822 WS	540	#define CFI_MFR_EON 0x001C
	541	#define CFI_MFR_FUJITSU 0x0004
	542	#define CFI_MFR_HYUNDAI 0x00AD
f3e69c65 GL	543	#define CFI_MFR_INTEL 0x0089
f3e69c65 GL	544	#define CFI_MFR_MACRONIX 0x00C2
ae731822 WS	545	#define CFI_MFR_NEC 0x0010
ae731822 WS	546	#define CFI_MFR_PMC 0x009D
f3e69c65	547	#define CFI_MFR_SAMSUNG 0x00EC
ae731822	548	#define CFI_MFR_SHARP 0x00B0
f3e69c65 GL	549	#define CFI_MFR_SST 0x00BF
f3e69c65 GL	550	#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
ae731822 WS	551	#define CFI_MFR_TOSHIBA 0x0098
ae731822 WS	552	#define CFI_MFR_WINBOND 0x00DA
1da177e4 LT	553
	554	void cfi_fixup(struct mtd_info mtd, struct cfi_fixup fixups);
	555
	556	typedef int (varsize_frob_t)(struct map_info map, struct flchip *chip,
	557	unsigned long adr, int len, void *thunk);
	558
	559	int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
	560	loff_t ofs, size_t len, void *thunk);
	561
	562
	563	#endif /* __MTD_CFI_H__ */