git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| f024ff10 DES |
1 | #ifndef MFD_TMIO_H |
| 2 | #define MFD_TMIO_H | |
| 3 | ||
| b53cde35 | 4 | #include <linux/fb.h> |
| 64e8867b IM |
5 | #include <linux/io.h> |
| 6 | #include <linux/platform_device.h> | |
| b53cde35 | 7 | |
| d3a2f718 IM |
8 | #define tmio_ioread8(addr) readb(addr) |
| 9 | #define tmio_ioread16(addr) readw(addr) | |
| 10 | #define tmio_ioread16_rep(r, b, l) readsw(r, b, l) | |
| 11 | #define tmio_ioread32(addr) \ | |
| 12 | (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16)) | |
| 13 | ||
| 14 | #define tmio_iowrite8(val, addr) writeb((val), (addr)) | |
| 15 | #define tmio_iowrite16(val, addr) writew((val), (addr)) | |
| 16 | #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l) | |
| 17 | #define tmio_iowrite32(val, addr) \ | |
| 18 | do { \ | |
| 19 | writew((val), (addr)); \ | |
| 20 | writew((val) >> 16, (addr) + 2); \ | |
| 21 | } while (0) | |
| 22 | ||
| 64e8867b IM |
23 | #define CNF_CMD 0x04 |
| 24 | #define CNF_CTL_BASE 0x10 | |
| 25 | #define CNF_INT_PIN 0x3d | |
| 26 | #define CNF_STOP_CLK_CTL 0x40 | |
| 27 | #define CNF_GCLK_CTL 0x41 | |
| 28 | #define CNF_SD_CLK_MODE 0x42 | |
| 29 | #define CNF_PIN_STATUS 0x44 | |
| 30 | #define CNF_PWR_CTL_1 0x48 | |
| 31 | #define CNF_PWR_CTL_2 0x49 | |
| 32 | #define CNF_PWR_CTL_3 0x4a | |
| 33 | #define CNF_CARD_DETECT_MODE 0x4c | |
| 34 | #define CNF_SD_SLOT 0x50 | |
| 35 | #define CNF_EXT_GCLK_CTL_1 0xf0 | |
| 36 | #define CNF_EXT_GCLK_CTL_2 0xf1 | |
| 37 | #define CNF_EXT_GCLK_CTL_3 0xf9 | |
| 38 | #define CNF_SD_LED_EN_1 0xfa | |
| 39 | #define CNF_SD_LED_EN_2 0xfe | |
| 40 | ||
| 41 | #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ | |
| 42 | ||
| 43 | #define sd_config_write8(base, shift, reg, val) \ | |
| 44 | tmio_iowrite8((val), (base) + ((reg) << (shift))) | |
| 45 | #define sd_config_write16(base, shift, reg, val) \ | |
| 46 | tmio_iowrite16((val), (base) + ((reg) << (shift))) | |
| 47 | #define sd_config_write32(base, shift, reg, val) \ | |
| 48 | do { \ | |
| 49 | tmio_iowrite16((val), (base) + ((reg) << (shift))); \ | |
| 50 | tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ | |
| 51 | } while (0) | |
| 52 | ||
| 53 | int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); | |
| 54 | int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); | |
| 55 | void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); | |
| 56 | void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); | |
| 57 | ||
| f0e46cc4 PZ |
58 | /* |
| 59 | * data for the MMC controller | |
| 60 | */ | |
| 61 | struct tmio_mmc_data { | |
| 4d3792e0 | 62 | const unsigned int hclk; |
| 64e8867b IM |
63 | void (*set_pwr)(struct platform_device *host, int state); |
| 64 | void (*set_clk_div)(struct platform_device *host, int state); | |
| f0e46cc4 PZ |
65 | }; |
| 66 | ||
| f024ff10 DES |
67 | /* |
| 68 | * data for the NAND controller | |
| 69 | */ | |
| 70 | struct tmio_nand_data { | |
| 71 | struct nand_bbt_descr *badblock_pattern; | |
| 72 | struct mtd_partition *partition; | |
| 73 | unsigned int num_partitions; | |
| 74 | }; | |
| 75 | ||
| b53cde35 DES |
76 | #define FBIO_TMIO_ACC_WRITE 0x7C639300 |
| 77 | #define FBIO_TMIO_ACC_SYNC 0x7C639301 | |
| 78 | ||
| 79 | struct tmio_fb_data { | |
| 80 | int (*lcd_set_power)(struct platform_device *fb_dev, | |
| 81 | bool on); | |
| 82 | int (*lcd_mode)(struct platform_device *fb_dev, | |
| 83 | const struct fb_videomode *mode); | |
| 84 | int num_modes; | |
| 85 | struct fb_videomode *modes; | |
| 86 | ||
| 87 | /* in mm: size of screen */ | |
| 88 | int height; | |
| 89 | int width; | |
| 90 | }; | |
| 91 | ||
| 92 | ||
| f024ff10 | 93 | #endif |