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06fcb0c6
IM
1#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
1da177e4
LT
3
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
23f9b317 12#include <linux/smp.h>
1da177e4 13
06fcb0c6 14#ifndef CONFIG_S390
1da177e4
LT
15
16#include <linux/linkage.h>
17#include <linux/cache.h>
18#include <linux/spinlock.h>
19#include <linux/cpumask.h>
503e5763 20#include <linux/gfp.h>
908dcecd 21#include <linux/irqreturn.h>
dd3a1db9 22#include <linux/irqnr.h>
77904fd6 23#include <linux/errno.h>
503e5763 24#include <linux/topology.h>
3aa551c9 25#include <linux/wait.h>
1da177e4
LT
26
27#include <asm/irq.h>
28#include <asm/ptrace.h>
7d12e780 29#include <asm/irq_regs.h>
1da177e4 30
57a58a94 31struct irq_desc;
ec701584 32typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780 33 struct irq_desc *desc);
57a58a94
DH
34
35
1da177e4
LT
36/*
37 * IRQ line status.
6e213616 38 *
950f4427 39 * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
6e213616
TG
40 *
41 * IRQ types
1da177e4 42 */
6e213616
TG
43#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
44#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
45#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
46#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
47#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
48#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
49#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
50#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
51
52/* Internal flags */
950f4427
TG
53#define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */
54#define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */
55#define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */
56#define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */
57#define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */
58#define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */
59#define IRQ_LEVEL 0x00004000 /* IRQ level triggered */
60#define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */
61#define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */
62#define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */
63#define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */
64#define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */
d7e25f33
IM
65#define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */
66#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
67#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
1adb0850 68#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
f6d87f4b
TG
69#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
70#define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/
0a0c5168 71#define IRQ_SUSPENDED 0x04000000 /* IRQ has gone through suspend sequence */
b25c340c 72#define IRQ_ONESHOT 0x08000000 /* IRQ is not unmasked after hardirq */
399b5da2 73#define IRQ_NESTED_THREAD 0x10000000 /* IRQ is nested into another, no own handler thread */
950f4427 74
0d7012a9 75#ifdef CONFIG_IRQ_PER_CPU
f26fdd59 76# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
950f4427 77# define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
f26fdd59
KW
78#else
79# define CHECK_IRQ_PER_CPU(var) 0
950f4427 80# define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING
f26fdd59 81#endif
1da177e4 82
6a6de9ef 83struct proc_dir_entry;
5b912c10 84struct msi_desc;
6a6de9ef 85
8fee5c36 86/**
6a6de9ef 87 * struct irq_chip - hardware interrupt chip descriptor
8fee5c36
IM
88 *
89 * @name: name for /proc/interrupts
90 * @startup: start up the interrupt (defaults to ->enable if NULL)
91 * @shutdown: shut down the interrupt (defaults to ->disable if NULL)
92 * @enable: enable the interrupt (defaults to chip->unmask if NULL)
599faa0e 93 * @disable: disable the interrupt
8fee5c36
IM
94 * @ack: start of a new interrupt
95 * @mask: mask an interrupt source
96 * @mask_ack: ack and mask an interrupt source
97 * @unmask: unmask an interrupt source
47c2a3aa
IM
98 * @eoi: end of interrupt - chip level
99 * @end: end of interrupt - flow level
8fee5c36
IM
100 * @set_affinity: set the CPU affinity on SMP machines
101 * @retrigger: resend an IRQ to the CPU
102 * @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
103 * @set_wake: enable/disable power-management wake-on of an IRQ
104 *
70aedd24
TG
105 * @bus_lock: function to lock access to slow bus (i2c) chips
106 * @bus_sync_unlock: function to sync and unlock slow bus (i2c) chips
107 *
8fee5c36 108 * @release: release function solely used by UML
6a6de9ef 109 * @typename: obsoleted by name, kept as migration helper
1da177e4 110 */
6a6de9ef
TG
111struct irq_chip {
112 const char *name;
71d218b7
IM
113 unsigned int (*startup)(unsigned int irq);
114 void (*shutdown)(unsigned int irq);
115 void (*enable)(unsigned int irq);
116 void (*disable)(unsigned int irq);
6a6de9ef 117
71d218b7 118 void (*ack)(unsigned int irq);
6a6de9ef
TG
119 void (*mask)(unsigned int irq);
120 void (*mask_ack)(unsigned int irq);
121 void (*unmask)(unsigned int irq);
47c2a3aa 122 void (*eoi)(unsigned int irq);
6a6de9ef 123
71d218b7 124 void (*end)(unsigned int irq);
d5dedd45 125 int (*set_affinity)(unsigned int irq,
0de26520 126 const struct cpumask *dest);
c0ad90a3 127 int (*retrigger)(unsigned int irq);
6a6de9ef
TG
128 int (*set_type)(unsigned int irq, unsigned int flow_type);
129 int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3 130
70aedd24
TG
131 void (*bus_lock)(unsigned int irq);
132 void (*bus_sync_unlock)(unsigned int irq);
133
b77d6adc
PBG
134 /* Currently used only by UML, might disappear one day.*/
135#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7 136 void (*release)(unsigned int irq, void *dev_id);
b77d6adc 137#endif
6a6de9ef
TG
138 /*
139 * For compatibility, ->typename is copied into ->name.
140 * Will disappear.
141 */
142 const char *typename;
1da177e4
LT
143};
144
0b8f1efa
YL
145struct timer_rand_state;
146struct irq_2_iommu;
8fee5c36
IM
147/**
148 * struct irq_desc - interrupt descriptor
2ed1cdcf 149 * @irq: interrupt number for this descriptor
078a55db
YL
150 * @timer_rand_state: pointer to timer rand state struct
151 * @kstat_irqs: irq stats per cpu
152 * @irq_2_iommu: iommu with this irq
6a6de9ef
TG
153 * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
154 * @chip: low level interrupt hardware access
472900b8 155 * @msi_desc: MSI descriptor
6a6de9ef
TG
156 * @handler_data: per-IRQ data for the irq_chip methods
157 * @chip_data: platform-specific per-chip private data for the chip
158 * methods, to allow shared chip implementations
8fee5c36
IM
159 * @action: the irq action chain
160 * @status: status information
161 * @depth: disable-depth, for nested irq_disable() calls
15a647eb 162 * @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36 163 * @irq_count: stats field to detect stalled irqs
5ac4d823 164 * @last_unhandled: aging timer for unhandled count
e262a7ba 165 * @irqs_unhandled: stats field for spurious unhandled interrupts
8fee5c36
IM
166 * @lock: locking for SMP
167 * @affinity: IRQ affinity on SMP
ab33dcff 168 * @node: node index useful for balancing
8fee5c36 169 * @pending_mask: pending rebalanced interrupts
3aa551c9
TG
170 * @threads_active: number of irqaction threads currently running
171 * @wait_for_threads: wait queue for sync_irq to wait for threaded handlers
8fee5c36 172 * @dir: /proc/irq/ procfs entry
a460e745 173 * @name: flow handler name for /proc/interrupts output
1da177e4 174 */
34ffdb72 175struct irq_desc {
08678b08 176 unsigned int irq;
0b8f1efa
YL
177 struct timer_rand_state *timer_rand_state;
178 unsigned int *kstat_irqs;
d7e51e66 179#ifdef CONFIG_INTR_REMAP
0b8f1efa 180 struct irq_2_iommu *irq_2_iommu;
0b8f1efa 181#endif
57a58a94 182 irq_flow_handler_t handle_irq;
6a6de9ef 183 struct irq_chip *chip;
5b912c10 184 struct msi_desc *msi_desc;
6a6de9ef 185 void *handler_data;
71d218b7
IM
186 void *chip_data;
187 struct irqaction *action; /* IRQ action list */
188 unsigned int status; /* IRQ status */
6a6de9ef 189
71d218b7 190 unsigned int depth; /* nested irq disables */
15a647eb 191 unsigned int wake_depth; /* nested wake enables */
71d218b7 192 unsigned int irq_count; /* For detecting broken IRQs */
4f27c00b 193 unsigned long last_unhandled; /* Aging timer for unhandled count */
e262a7ba 194 unsigned int irqs_unhandled;
239007b8 195 raw_spinlock_t lock;
a53da52f 196#ifdef CONFIG_SMP
7f7ace0c 197 cpumask_var_t affinity;
e7a297b0 198 const struct cpumask *affinity_hint;
85ac16d0 199 unsigned int node;
8b8e8c1b 200#ifdef CONFIG_GENERIC_PENDING_IRQ
7f7ace0c
MT
201 cpumask_var_t pending_mask;
202#endif
54d5d424 203#endif
3aa551c9
TG
204 atomic_t threads_active;
205 wait_queue_head_t wait_for_threads;
4a733ee1 206#ifdef CONFIG_PROC_FS
a460e745 207 struct proc_dir_entry *dir;
4a733ee1 208#endif
a460e745 209 const char *name;
e729aa16 210} ____cacheline_internodealigned_in_smp;
1da177e4 211
0b8f1efa 212extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
85ac16d0 213 struct irq_desc *desc, int node);
0b8f1efa 214extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc);
9059d8fa 215
0b8f1efa 216#ifndef CONFIG_SPARSE_IRQ
34ffdb72 217extern struct irq_desc irq_desc[NR_IRQS];
15e957d0
YL
218#endif
219
220#ifdef CONFIG_NUMA_IRQ_DESC
85ac16d0 221extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int node);
15e957d0
YL
222#else
223static inline struct irq_desc *move_irq_desc(struct irq_desc *desc, int node)
224{
225 return desc;
226}
227#endif
0b8f1efa 228
85ac16d0 229extern struct irq_desc *irq_to_desc_alloc_node(unsigned int irq, int node);
0b8f1efa 230
34ffdb72
IM
231/*
232 * Pick up the arch-dependent methods:
233 */
234#include <asm/hw_irq.h>
1da177e4 235
06fcb0c6 236extern int setup_irq(unsigned int irq, struct irqaction *new);
cbf94f06 237extern void remove_irq(unsigned int irq, struct irqaction *act);
1da177e4
LT
238
239#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6 240
54d5d424
AR
241#ifdef CONFIG_SMP
242
8b8e8c1b 243#ifdef CONFIG_GENERIC_PENDING_IRQ
54d5d424 244
c777ac55 245void move_native_irq(int irq);
e7b946e9 246void move_masked_irq(int irq);
54d5d424 247
8b8e8c1b 248#else /* CONFIG_GENERIC_PENDING_IRQ */
06fcb0c6
IM
249
250static inline void move_irq(int irq)
251{
252}
253
254static inline void move_native_irq(int irq)
255{
256}
257
e7b946e9
EB
258static inline void move_masked_irq(int irq)
259{
260}
261
06fcb0c6 262#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424 263
06fcb0c6 264#else /* CONFIG_SMP */
54d5d424 265
54d5d424 266#define move_native_irq(x)
e7b946e9 267#define move_masked_irq(x)
54d5d424 268
06fcb0c6 269#endif /* CONFIG_SMP */
54d5d424 270
1da177e4 271extern int no_irq_affinity;
1da177e4 272
950f4427
TG
273static inline int irq_balancing_disabled(unsigned int irq)
274{
08678b08
YL
275 struct irq_desc *desc;
276
277 desc = irq_to_desc(irq);
278 return desc->status & IRQ_NO_BALANCING_MASK;
950f4427
TG
279}
280
6a6de9ef 281/* Handle irq action chains: */
bedd30d9 282extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);
6a6de9ef
TG
283
284/*
285 * Built-in IRQ handlers for various IRQ types,
bebd04cc 286 * callable via desc->handle_irq()
6a6de9ef 287 */
ec701584
HH
288extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
289extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
290extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
291extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
292extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
293extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
31b47cf7 294extern void handle_nested_irq(unsigned int irq);
6a6de9ef 295
2e60bbb6 296/*
6a6de9ef 297 * Monolithic do_IRQ implementation.
2e60bbb6 298 */
af8c65b5 299#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
ec701584 300extern unsigned int __do_IRQ(unsigned int irq);
af8c65b5 301#endif
2e60bbb6 302
dae86204
IM
303/*
304 * Architectures call this to let the generic IRQ layer
305 * handle an interrupt. If the descriptor is attached to an
306 * irqchip-style controller then we call the ->handle_irq() handler,
307 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
308 */
46926b67 309static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
dae86204 310{
af8c65b5 311#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
7d12e780 312 desc->handle_irq(irq, desc);
af8c65b5 313#else
dae86204 314 if (likely(desc->handle_irq))
7d12e780 315 desc->handle_irq(irq, desc);
dae86204 316 else
7d12e780 317 __do_IRQ(irq);
af8c65b5 318#endif
dae86204
IM
319}
320
46926b67
YL
321static inline void generic_handle_irq(unsigned int irq)
322{
323 generic_handle_irq_desc(irq, irq_to_desc(irq));
324}
325
6a6de9ef 326/* Handling of unhandled and spurious interrupts: */
34ffdb72 327extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
bedd30d9 328 irqreturn_t action_ret);
1da177e4 329
a4633adc
TG
330/* Resending of interrupts :*/
331void check_irq_resend(struct irq_desc *desc, unsigned int irq);
332
6a6de9ef
TG
333/* Enable/disable irq debugging output: */
334extern int noirqdebug_setup(char *str);
335
336/* Checks whether the interrupt can be requested by request_irq(): */
337extern int can_request_irq(unsigned int irq, unsigned long irqflags);
338
f8b5473f 339/* Dummy irq-chip implementations: */
6a6de9ef 340extern struct irq_chip no_irq_chip;
f8b5473f 341extern struct irq_chip dummy_irq_chip;
6a6de9ef 342
145fc655
IM
343extern void
344set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
345 irq_flow_handler_t handle);
6a6de9ef 346extern void
a460e745
IM
347set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
348 irq_flow_handler_t handle, const char *name);
349
6a6de9ef 350extern void
a460e745
IM
351__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
352 const char *name);
1da177e4 353
b019e573
KH
354/* caller has locked the irq_desc and both params are valid */
355static inline void __set_irq_handler_unlocked(int irq,
356 irq_flow_handler_t handler)
357{
08678b08
YL
358 struct irq_desc *desc;
359
360 desc = irq_to_desc(irq);
361 desc->handle_irq = handler;
b019e573
KH
362}
363
6a6de9ef
TG
364/*
365 * Set a highlevel flow handler for a given IRQ:
366 */
367static inline void
57a58a94 368set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef 369{
a460e745 370 __set_irq_handler(irq, handle, 0, NULL);
6a6de9ef
TG
371}
372
373/*
374 * Set a highlevel chained flow handler for a given IRQ.
375 * (a chained handler is automatically enabled and set to
376 * IRQ_NOREQUEST and IRQ_NOPROBE)
377 */
378static inline void
379set_irq_chained_handler(unsigned int irq,
57a58a94 380 irq_flow_handler_t handle)
6a6de9ef 381{
a460e745 382 __set_irq_handler(irq, handle, 1, NULL);
6a6de9ef
TG
383}
384
399b5da2
TG
385extern void set_irq_nested_thread(unsigned int irq, int nest);
386
46f4f8f6
RB
387extern void set_irq_noprobe(unsigned int irq);
388extern void set_irq_probe(unsigned int irq);
389
3a16d713 390/* Handle dynamic irq creation and destruction */
d047f53a 391extern unsigned int create_irq_nr(unsigned int irq_want, int node);
3a16d713
EB
392extern int create_irq(void);
393extern void destroy_irq(unsigned int irq);
394
1f80025e
EB
395/* Test to see if a driver has successfully requested an irq */
396static inline int irq_has_action(unsigned int irq)
397{
08678b08 398 struct irq_desc *desc = irq_to_desc(irq);
1f80025e
EB
399 return desc->action != NULL;
400}
401
3a16d713
EB
402/* Dynamic irq helper functions */
403extern void dynamic_irq_init(unsigned int irq);
ced5b697 404void dynamic_irq_init_keep_chip_data(unsigned int irq);
3a16d713 405extern void dynamic_irq_cleanup(unsigned int irq);
ced5b697 406void dynamic_irq_cleanup_keep_chip_data(unsigned int irq);
dd87eb3a 407
3a16d713 408/* Set/get chip/data for an IRQ: */
dd87eb3a
TG
409extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
410extern int set_irq_data(unsigned int irq, void *data);
411extern int set_irq_chip_data(unsigned int irq, void *data);
412extern int set_irq_type(unsigned int irq, unsigned int type);
5b912c10 413extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
dd87eb3a 414
08678b08
YL
415#define get_irq_chip(irq) (irq_to_desc(irq)->chip)
416#define get_irq_chip_data(irq) (irq_to_desc(irq)->chip_data)
417#define get_irq_data(irq) (irq_to_desc(irq)->handler_data)
418#define get_irq_msi(irq) (irq_to_desc(irq)->msi_desc)
dd87eb3a 419
0b8f1efa
YL
420#define get_irq_desc_chip(desc) ((desc)->chip)
421#define get_irq_desc_chip_data(desc) ((desc)->chip_data)
422#define get_irq_desc_data(desc) ((desc)->handler_data)
423#define get_irq_desc_msi(desc) ((desc)->msi_desc)
424
6a6de9ef 425#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4 426
06fcb0c6 427#endif /* !CONFIG_S390 */
1da177e4 428
7f7ace0c
MT
429#ifdef CONFIG_SMP
430/**
9ec4fa27 431 * alloc_desc_masks - allocate cpumasks for irq_desc
7f7ace0c 432 * @desc: pointer to irq_desc struct
ab33dcff 433 * @node: node which will be handling the cpumasks
7f7ace0c
MT
434 * @boot: true if need bootmem
435 *
436 * Allocates affinity and pending_mask cpumask if required.
437 * Returns true if successful (or not required).
7f7ace0c 438 */
85ac16d0 439static inline bool alloc_desc_masks(struct irq_desc *desc, int node,
38c7fed2 440 bool boot)
7f7ace0c 441{
38c7fed2 442 gfp_t gfp = GFP_ATOMIC;
7f7ace0c 443
38c7fed2
YL
444 if (boot)
445 gfp = GFP_NOWAIT;
7f7ace0c 446
38c7fed2
YL
447#ifdef CONFIG_CPUMASK_OFFSTACK
448 if (!alloc_cpumask_var_node(&desc->affinity, gfp, node))
7f7ace0c 449 return false;
7f7ace0c
MT
450
451#ifdef CONFIG_GENERIC_PENDING_IRQ
38c7fed2 452 if (!alloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
7f7ace0c
MT
453 free_cpumask_var(desc->affinity);
454 return false;
455 }
9ec4fa27 456#endif
7f7ace0c
MT
457#endif
458 return true;
459}
460
9ec4fa27
YL
461static inline void init_desc_masks(struct irq_desc *desc)
462{
463 cpumask_setall(desc->affinity);
464#ifdef CONFIG_GENERIC_PENDING_IRQ
465 cpumask_clear(desc->pending_mask);
466#endif
467}
468
7f7ace0c
MT
469/**
470 * init_copy_desc_masks - copy cpumasks for irq_desc
471 * @old_desc: pointer to old irq_desc struct
472 * @new_desc: pointer to new irq_desc struct
473 *
474 * Insures affinity and pending_masks are copied to new irq_desc.
475 * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
476 * irq_desc struct so the copy is redundant.
477 */
478
479static inline void init_copy_desc_masks(struct irq_desc *old_desc,
480 struct irq_desc *new_desc)
481{
9ec4fa27 482#ifdef CONFIG_CPUMASK_OFFSTACK
7f7ace0c
MT
483 cpumask_copy(new_desc->affinity, old_desc->affinity);
484
485#ifdef CONFIG_GENERIC_PENDING_IRQ
486 cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
487#endif
488#endif
489}
490
9756b15e
YL
491static inline void free_desc_masks(struct irq_desc *old_desc,
492 struct irq_desc *new_desc)
493{
494 free_cpumask_var(old_desc->affinity);
495
496#ifdef CONFIG_GENERIC_PENDING_IRQ
497 free_cpumask_var(old_desc->pending_mask);
498#endif
499}
500
7f7ace0c
MT
501#else /* !CONFIG_SMP */
502
85ac16d0 503static inline bool alloc_desc_masks(struct irq_desc *desc, int node,
7f7ace0c
MT
504 bool boot)
505{
506 return true;
507}
508
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YL
509static inline void init_desc_masks(struct irq_desc *desc)
510{
511}
512
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513static inline void init_copy_desc_masks(struct irq_desc *old_desc,
514 struct irq_desc *new_desc)
515{
516}
517
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518static inline void free_desc_masks(struct irq_desc *old_desc,
519 struct irq_desc *new_desc)
520{
521}
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522#endif /* CONFIG_SMP */
523
06fcb0c6 524#endif /* _LINUX_IRQ_H */