git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 5f0a96b0 AS |
1 | /* |
| 2 | * AMD CS5535/CS5536 definitions | |
| 3 | * Copyright (C) 2006 Advanced Micro Devices, Inc. | |
| 4 | * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of version 2 of the GNU General Public License | |
| 8 | * as published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef _CS5535_H | |
| 12 | #define _CS5535_H | |
| 13 | ||
| 14 | /* MSRs */ | |
| 15 | #define MSR_LBAR_SMB 0x5140000B | |
| 16 | #define MSR_LBAR_GPIO 0x5140000C | |
| 17 | #define MSR_LBAR_MFGPT 0x5140000D | |
| 18 | #define MSR_LBAR_ACPI 0x5140000E | |
| 19 | #define MSR_LBAR_PMS 0x5140000F | |
| 20 | ||
| 82dca611 AS |
21 | #define MSR_PIC_YSEL_LOW 0x51400020 |
| 22 | #define MSR_PIC_YSEL_HIGH 0x51400021 | |
| 23 | #define MSR_PIC_ZSEL_LOW 0x51400022 | |
| 24 | #define MSR_PIC_ZSEL_HIGH 0x51400023 | |
| 25 | #define MSR_PIC_IRQM_LPC 0x51400025 | |
| 26 | ||
| 27 | #define MSR_MFGPT_IRQ 0x51400028 | |
| 28 | #define MSR_MFGPT_NR 0x51400029 | |
| 29 | #define MSR_MFGPT_SETUP 0x5140002B | |
| 30 | ||
| 5f0a96b0 AS |
31 | /* resource sizes */ |
| 32 | #define LBAR_GPIO_SIZE 0xFF | |
| 33 | #define LBAR_MFGPT_SIZE 0x40 | |
| 34 | #define LBAR_ACPI_SIZE 0x40 | |
| 35 | #define LBAR_PMS_SIZE 0x80 | |
| 36 | ||
| 37 | /* GPIOs */ | |
| 38 | #define GPIO_OUTPUT_VAL 0x00 | |
| 39 | #define GPIO_OUTPUT_ENABLE 0x04 | |
| 40 | #define GPIO_OUTPUT_OPEN_DRAIN 0x08 | |
| 41 | #define GPIO_OUTPUT_INVERT 0x0C | |
| 42 | #define GPIO_OUTPUT_AUX1 0x10 | |
| 43 | #define GPIO_OUTPUT_AUX2 0x14 | |
| 44 | #define GPIO_PULL_UP 0x18 | |
| 45 | #define GPIO_PULL_DOWN 0x1C | |
| 46 | #define GPIO_INPUT_ENABLE 0x20 | |
| 47 | #define GPIO_INPUT_INVERT 0x24 | |
| 48 | #define GPIO_INPUT_FILTER 0x28 | |
| 49 | #define GPIO_INPUT_EVENT_COUNT 0x2C | |
| 50 | #define GPIO_READ_BACK 0x30 | |
| 51 | #define GPIO_INPUT_AUX1 0x34 | |
| 52 | #define GPIO_EVENTS_ENABLE 0x38 | |
| 53 | #define GPIO_LOCK_ENABLE 0x3C | |
| 54 | #define GPIO_POSITIVE_EDGE_EN 0x40 | |
| 55 | #define GPIO_NEGATIVE_EDGE_EN 0x44 | |
| 56 | #define GPIO_POSITIVE_EDGE_STS 0x48 | |
| 57 | #define GPIO_NEGATIVE_EDGE_STS 0x4C | |
| 58 | ||
| 59 | #define GPIO_MAP_X 0xE0 | |
| 60 | #define GPIO_MAP_Y 0xE4 | |
| 61 | #define GPIO_MAP_Z 0xE8 | |
| 62 | #define GPIO_MAP_W 0xEC | |
| 63 | ||
| 64 | void cs5535_gpio_set(unsigned offset, unsigned int reg); | |
| 65 | void cs5535_gpio_clear(unsigned offset, unsigned int reg); | |
| 66 | int cs5535_gpio_isset(unsigned offset, unsigned int reg); | |
| 67 | ||
| 82dca611 AS |
68 | /* MFGPTs */ |
| 69 | ||
| 70 | #define MFGPT_MAX_TIMERS 8 | |
| 71 | #define MFGPT_TIMER_ANY (-1) | |
| 72 | ||
| 73 | #define MFGPT_DOMAIN_WORKING 1 | |
| 74 | #define MFGPT_DOMAIN_STANDBY 2 | |
| 75 | #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY) | |
| 76 | ||
| 77 | #define MFGPT_CMP1 0 | |
| 78 | #define MFGPT_CMP2 1 | |
| 79 | ||
| 80 | #define MFGPT_EVENT_IRQ 0 | |
| 81 | #define MFGPT_EVENT_NMI 1 | |
| 82 | #define MFGPT_EVENT_RESET 3 | |
| 83 | ||
| 84 | #define MFGPT_REG_CMP1 0 | |
| 85 | #define MFGPT_REG_CMP2 2 | |
| 86 | #define MFGPT_REG_COUNTER 4 | |
| 87 | #define MFGPT_REG_SETUP 6 | |
| 88 | ||
| 89 | #define MFGPT_SETUP_CNTEN (1 << 15) | |
| 90 | #define MFGPT_SETUP_CMP2 (1 << 14) | |
| 91 | #define MFGPT_SETUP_CMP1 (1 << 13) | |
| 92 | #define MFGPT_SETUP_SETUP (1 << 12) | |
| 93 | #define MFGPT_SETUP_STOPEN (1 << 11) | |
| 94 | #define MFGPT_SETUP_EXTEN (1 << 10) | |
| 95 | #define MFGPT_SETUP_REVEN (1 << 5) | |
| 96 | #define MFGPT_SETUP_CLKSEL (1 << 4) | |
| 97 | ||
| 98 | struct cs5535_mfgpt_timer; | |
| 99 | ||
| 100 | extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, | |
| 101 | uint16_t reg); | |
| 102 | extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, | |
| 103 | uint16_t value); | |
| 104 | ||
| 105 | extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp, | |
| 106 | int event, int enable); | |
| 107 | extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, | |
| 108 | int *irq, int enable); | |
| 109 | extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer, | |
| 110 | int domain); | |
| 111 | extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer); | |
| 112 | ||
| 113 | static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer, | |
| 114 | int cmp, int *irq) | |
| 115 | { | |
| 116 | return cs5535_mfgpt_set_irq(timer, cmp, irq, 1); | |
| 117 | } | |
| 118 | ||
| 119 | static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer, | |
| 120 | int cmp, int *irq) | |
| 121 | { | |
| 122 | return cs5535_mfgpt_set_irq(timer, cmp, irq, 0); | |
| 123 | } | |
| 124 | ||
| 5f0a96b0 | 125 | #endif |