[net-next-2.6.git] / include / asm-xtensa / xtensa / config-linux_be / system.h

/*
 * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
 *
 *  NOTE: The location and contents of this file are highly subject to change.
 *
 *  Source for configuration-independent binaries (which link in a
 *  configuration-specific HAL library) must NEVER include this file.
 *  The HAL itself has historically included this file in some instances,
 *  but this is not appropriate either, because the HAL is meant to be
 *  core-specific but system independent.
 */

/*
 * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it would be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Further, this software is distributed without any warranty that it is
 * free of the rightful claim of any third person regarding infringement
 * or the like.  Any license provided herein, whether implied or
 * otherwise, applies only to this software file.  Patent licenses, if
 * any, provided herein do not apply to combinations of this program with
 * other software, or any other product whatsoever.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this program; if not, write the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
 * USA.
 */


#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H

/*#include <xtensa/hal.h>*/


/*----------------------------------------------------------------------
				DEVICE ADDRESSES
  ----------------------------------------------------------------------*/

/*
 *  Strange place to find these, but the configuration GUI
 *  allows moving these around to account for various core
 *  configurations.  Specific boards (and their BSP software)
 *  will have specific meanings for these components.
 */

/*  I/O Block areas:  */
#define XSHAL_IOBLOCK_CACHED_VADDR	0xE0000000
#define XSHAL_IOBLOCK_CACHED_PADDR	0xF0000000
#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000

#define XSHAL_IOBLOCK_BYPASS_VADDR	0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR	0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000

/*  System ROM:  */
#define XSHAL_ROM_VADDR		0xEE000000
#define XSHAL_ROM_PADDR		0xFE000000
#define XSHAL_ROM_SIZE		0x00400000
/*  Largest available area (free of vectors):  */
#define XSHAL_ROM_AVAIL_VADDR	0xEE00052C
#define XSHAL_ROM_AVAIL_VSIZE	0x003FFAD4

/*  System RAM:  */
#define XSHAL_RAM_VADDR		0xD0000000
#define XSHAL_RAM_PADDR		0x00000000
#define XSHAL_RAM_VSIZE		0x08000000
#define XSHAL_RAM_PSIZE		0x10000000
#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
/*  Largest available area (free of vectors):  */
#define XSHAL_RAM_AVAIL_VADDR	0xD0000370
#define XSHAL_RAM_AVAIL_VSIZE	0x07FFFC90

/*
 *  Shadow system RAM (same device as system RAM, at different address).
 *  (Emulation boards need this for the SONIC Ethernet driver
 *   when data caches are configured for writeback mode.)
 *  NOTE: on full MMU configs, this points to the BYPASS virtual address
 *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
 *  addresses are viewed through the BYPASS static map rather than
 *  the CACHED static map.
 */
#define XSHAL_RAM_BYPASS_VADDR		0xD8000000
#define XSHAL_RAM_BYPASS_PADDR		0x00000000
#define XSHAL_RAM_BYPASS_PSIZE		0x08000000

/*  Alternate system RAM (different device than system RAM):  */
#define XSHAL_ALTRAM_VADDR		0xCEE00000
#define XSHAL_ALTRAM_PADDR		0xC0000000
#define XSHAL_ALTRAM_SIZE		0x00200000


/*----------------------------------------------------------------------
 *			DEVICE-ADDRESS DEPENDENT...
 *
 *  Values written to CACHEATTR special register (or its equivalent)
 *  to enable and disable caches in various modes.
 *----------------------------------------------------------------------*/

/*----------------------------------------------------------------------
			BACKWARD COMPATIBILITY ...
  ----------------------------------------------------------------------*/

/*
 *  NOTE:  the following two macros are DEPRECATED.  Use the latter
 *  board-specific macros instead, which are specially tuned for the
 *  particular target environments' memory maps.
 */
#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */

/*----------------------------------------------------------------------
			ISS (Instruction Set Simulator) SPECIFIC ...
  ----------------------------------------------------------------------*/

#define XSHAL_ISS_CACHEATTR_WRITEBACK	0x1122222F	/* enable caches in write-back mode */
#define XSHAL_ISS_CACHEATTR_WRITEALLOC	0x1122222F	/* enable caches in write-allocate mode */
#define XSHAL_ISS_CACHEATTR_WRITETHRU	0x1122222F	/* enable caches in write-through mode */
#define XSHAL_ISS_CACHEATTR_BYPASS	0x2222222F	/* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_ISS_CACHEATTR_WRITEBACK	/* default setting to enable caches */

/*  For Coware only:  */
#define XSHAL_COWARE_CACHEATTR_WRITEBACK	0x11222222	/* enable caches in write-back mode */
#define XSHAL_COWARE_CACHEATTR_WRITEALLOC	0x11222222	/* enable caches in write-allocate mode */
#define XSHAL_COWARE_CACHEATTR_WRITETHRU	0x11222222	/* enable caches in write-through mode */
#define XSHAL_COWARE_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
#define XSHAL_COWARE_CACHEATTR_DEFAULT		XSHAL_COWARE_CACHEATTR_WRITEBACK	/* default setting to enable caches */

/*  For BFM and other purposes:  */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x11222222	/* enable caches without any invalid regions */
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting for caches without any invalid regions */

#define XSHAL_ISS_PIPE_REGIONS	0
#define XSHAL_ISS_SDRAM_REGIONS	0


/*----------------------------------------------------------------------
			XT2000 BOARD SPECIFIC ...
  ----------------------------------------------------------------------*/

#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0x22FFFFFF	/* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0x22FFFFFF	/* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0x22FFFFFF	/* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS		0x22FFFFFF	/* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */

#define XSHAL_XT2000_PIPE_REGIONS	0x00001000	/* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS	0x00000005	/* BusInt SDRAM regions */


/*----------------------------------------------------------------------
				VECTOR SIZES
  ----------------------------------------------------------------------*/

/*
 *  Sizes allocated to vectors by the system (memory map) configuration.
 *  These sizes are constrained by core configuration (eg. one vector's
 *  code cannot overflow into another vector) but are dependent on the
 *  system or board (or LSP) memory map configuration.
 *
 *  Whether or not each vector happens to be in a system ROM is also
 *  a system configuration matter, sometimes useful, included here also:
 */
#define XSHAL_RESET_VECTOR_SIZE	0x000004E0
#define XSHAL_RESET_VECTOR_ISROM	1
#define XSHAL_USER_VECTOR_SIZE	0x0000001C
#define XSHAL_USER_VECTOR_ISROM	0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
#define XSHAL_KERNEL_VECTOR_ISROM	0
#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x000000E0
#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
#define XSHAL_WINDOW_VECTORS_SIZE	0x00000180
#define XSHAL_WINDOW_VECTORS_ISROM	0
#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000000C
#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x0000000C
#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x0000000C
#define XSHAL_INTLEVEL4_VECTOR_ISROM	1
#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL4_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL4_VECTOR_ISROM


#endif /*XTENSA_CONFIG_SYSTEM_H*/
Commit	Line	Data
e344b63e CZ	1	/*
	2	* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
	3	*
	4	* NOTE: The location and contents of this file are highly subject to change.
	5	*
	6	* Source for configuration-independent binaries (which link in a
	7	* configuration-specific HAL library) must NEVER include this file.
	8	* The HAL itself has historically included this file in some instances,
	9	* but this is not appropriate either, because the HAL is meant to be
	10	* core-specific but system independent.
	11	*/
	12
	13	/*
	14	* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of version 2.1 of the GNU Lesser General Public
	18	* License as published by the Free Software Foundation.
	19	*
	20	* This program is distributed in the hope that it would be useful, but
	21	* WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	23	*
	24	* Further, this software is distributed without any warranty that it is
	25	* free of the rightful claim of any third person regarding infringement
	26	* or the like. Any license provided herein, whether implied or
	27	* otherwise, applies only to this software file. Patent licenses, if
	28	* any, provided herein do not apply to combinations of this program with
	29	* other software, or any other product whatsoever.
	30	*
	31	* You should have received a copy of the GNU Lesser General Public
	32	* License along with this program; if not, write the Free Software
	33	* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
	34	* USA.
	35	*/
	36
	37
	38	#ifndef XTENSA_CONFIG_SYSTEM_H
	39	#define XTENSA_CONFIG_SYSTEM_H
	40
	41	/#include <xtensa/hal.h>/
	42
	43
	44
	45	/*----------------------------------------------------------------------
	46	DEVICE ADDRESSES
	47	----------------------------------------------------------------------*/
	48
	49	/*
	50	* Strange place to find these, but the configuration GUI
	51	* allows moving these around to account for various core
	52	* configurations. Specific boards (and their BSP software)
	53	* will have specific meanings for these components.
	54	*/
	55
	56	/* I/O Block areas: */
	57	#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
	58	#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
	59	#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
	60
	61	#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
	62	#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
	63	#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
	64
65	/* System ROM: */
66	#define XSHAL_ROM_VADDR 0xEE000000
67	#define XSHAL_ROM_PADDR 0xFE000000
68	#define XSHAL_ROM_SIZE 0x00400000
69	/* Largest available area (free of vectors): */
70	#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
71	#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
72
73	/* System RAM: */
74	#define XSHAL_RAM_VADDR 0xD0000000
75	#define XSHAL_RAM_PADDR 0x00000000
76	#define XSHAL_RAM_VSIZE 0x08000000
77	#define XSHAL_RAM_PSIZE 0x10000000
78	#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
79	/* Largest available area (free of vectors): */
80	#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
81	#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
82
83	/*
84	* Shadow system RAM (same device as system RAM, at different address).
85	* (Emulation boards need this for the SONIC Ethernet driver
86	* when data caches are configured for writeback mode.)
87	* NOTE: on full MMU configs, this points to the BYPASS virtual address
88	* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
89	* addresses are viewed through the BYPASS static map rather than
90	* the CACHED static map.
91	*/
92	#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
93	#define XSHAL_RAM_BYPASS_PADDR 0x00000000
94	#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
95
96	/* Alternate system RAM (different device than system RAM): */
97	#define XSHAL_ALTRAM_VADDR 0xCEE00000
98	#define XSHAL_ALTRAM_PADDR 0xC0000000
99	#define XSHAL_ALTRAM_SIZE 0x00200000
100
101
102	/*----------------------------------------------------------------------
103	* DEVICE-ADDRESS DEPENDENT...
104	*
105	* Values written to CACHEATTR special register (or its equivalent)
106	* to enable and disable caches in various modes.
107	----------------------------------------------------------------------/
108
109	/*----------------------------------------------------------------------
110	BACKWARD COMPATIBILITY ...
111	----------------------------------------------------------------------*/
112
113	/*
114	* NOTE: the following two macros are DEPRECATED. Use the latter
115	* board-specific macros instead, which are specially tuned for the
116	* particular target environments' memory maps.
117	*/
118	#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
119	#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
120
121	/*----------------------------------------------------------------------
122	ISS (Instruction Set Simulator) SPECIFIC ...
123	----------------------------------------------------------------------*/
124
125	#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
126	#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
127	#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
128	#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
129	#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
130
131	/* For Coware only: */
132	#define XSHAL_COWARE_CACHEATTR_WRITEBACK 0x11222222 /* enable caches in write-back mode */
133	#define XSHAL_COWARE_CACHEATTR_WRITEALLOC 0x11222222 /* enable caches in write-allocate mode */
134	#define XSHAL_COWARE_CACHEATTR_WRITETHRU 0x11222222 /* enable caches in write-through mode */
135	#define XSHAL_COWARE_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
136	#define XSHAL_COWARE_CACHEATTR_DEFAULT XSHAL_COWARE_CACHEATTR_WRITEBACK /* default setting to enable caches */
137
138	/* For BFM and other purposes: */
139	#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x11222222 /* enable caches without any invalid regions */
140	#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting for caches without any invalid regions */
141
142	#define XSHAL_ISS_PIPE_REGIONS 0
143	#define XSHAL_ISS_SDRAM_REGIONS 0
144
145
146	/*----------------------------------------------------------------------
147	XT2000 BOARD SPECIFIC ...
148	----------------------------------------------------------------------*/
149
150	#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
151	#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
152	#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
153	#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
154	#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
155
156	#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
157	#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
158
159
160	/*----------------------------------------------------------------------
161	VECTOR SIZES
162	----------------------------------------------------------------------*/
163
164	/*
165	* Sizes allocated to vectors by the system (memory map) configuration.
166	* These sizes are constrained by core configuration (eg. one vector's
167	* code cannot overflow into another vector) but are dependent on the
168	* system or board (or LSP) memory map configuration.
169	*
170	* Whether or not each vector happens to be in a system ROM is also
171	* a system configuration matter, sometimes useful, included here also:
172	*/
173	#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
174	#define XSHAL_RESET_VECTOR_ISROM 1
175	#define XSHAL_USER_VECTOR_SIZE 0x0000001C
176	#define XSHAL_USER_VECTOR_ISROM 0
177	#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
178	#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
179	#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
180	#define XSHAL_KERNEL_VECTOR_ISROM 0
181	#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
182	#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
183	#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
184	#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
185	#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
186	#define XSHAL_WINDOW_VECTORS_ISROM 0
187	#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
188	#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
189	#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
190	#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
191	#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
192	#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
193	#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
194	#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
195
196
197	#endif /XTENSA_CONFIG_SYSTEM_H/
198