[net-next-2.6.git] / include / asm-x86_64 / io_apic.h

#ifndef __ASM_IO_APIC_H
#define __ASM_IO_APIC_H

#include <asm/types.h>
#include <asm/mpspec.h>
#include <asm/apicdef.h>

/*
 * Intel IO-APIC support for SMP and UP systems.
 *
 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
 */

#define APIC_MISMATCH_DEBUG

/*
 * The structure of the IO-APIC:
 */
union IO_APIC_reg_00 {
	u32	raw;
	struct {
		u32	__reserved_2	: 14,
			LTS		:  1,
			delivery_type	:  1,
			__reserved_1	:  8,
			ID		:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_01 {
	u32	raw;
	struct {
		u32	version		:  8,
		__reserved_2	:  7,
		PRQ		:  1,
		entries		:  8,
		__reserved_1	:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_02 {
	u32	raw;
	struct {
		u32	__reserved_2	: 24,
		arbitration	:  4,
		__reserved_1	:  4;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_03 {
	u32	raw;
	struct {
		u32	boot_DT		:  1,
			__reserved_1	: 31;
	} __attribute__ ((packed)) bits;
};

/*
 * # of IO-APICs and # of IRQ routing registers
 */
extern int nr_ioapics;
extern int nr_ioapic_registers[MAX_IO_APICS];

enum ioapic_irq_destination_types {
	dest_Fixed = 0,
	dest_LowestPrio = 1,
	dest_SMI = 2,
	dest__reserved_1 = 3,
	dest_NMI = 4,
	dest_INIT = 5,
	dest__reserved_2 = 6,
	dest_ExtINT = 7
};

struct IO_APIC_route_entry {
	__u32	vector		:  8,
		delivery_mode	:  3,	/* 000: FIXED
					 * 001: lowest prio
					 * 111: ExtINT
					 */
		dest_mode	:  1,	/* 0: physical, 1: logical */
		delivery_status	:  1,
		polarity	:  1,
		irr		:  1,
		trigger		:  1,	/* 0: edge, 1: level */
		mask		:  1,	/* 0: enabled, 1: disabled */
		__reserved_2	: 15;

	__u32	__reserved_3	: 24,
		dest		:  8;
} __attribute__ ((packed));

/*
 * MP-BIOS irq configuration table structures:
 */

/* I/O APIC entries */
extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];

/* # of MP IRQ source entries */
extern int mp_irq_entries;

/* MP IRQ source entries */
extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* non-0 if default (table-less) MP configuration */
extern int mpc_default_type;

/* 1 if "noapic" boot option passed */
extern int skip_ioapic_setup;

static inline void disable_ioapic_setup(void)
{
	skip_ioapic_setup = 1;
}


/*
 * If we use the IO-APIC for IRQ routing, disable automatic
 * assignment of PCI IRQ's.
 */
#define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)

#ifdef CONFIG_ACPI
extern int io_apic_get_version (int ioapic);
extern int io_apic_get_redir_entries (int ioapic);
extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
#endif

extern int sis_apic_bug; /* dummy */ 

void enable_NMI_through_LVT0 (void * dummy);

extern spinlock_t i8259A_lock;

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_IO_APIC_H
	2	#define __ASM_IO_APIC_H
	3
1da177e4 LT	4	#include <asm/types.h>
1da177e4 LT	5	#include <asm/mpspec.h>
58a53b24	6	#include <asm/apicdef.h>
1da177e4 LT	7
	8	/*
	9	* Intel IO-APIC support for SMP and UP systems.
	10	*
	11	* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
	12	*/
	13
1da177e4 LT	14	#define APIC_MISMATCH_DEBUG
1da177e4 LT	15
1da177e4 LT	16	/*
	17	* The structure of the IO-APIC:
	18	*/
	19	union IO_APIC_reg_00 {
	20	u32 raw;
	21	struct {
	22	u32 __reserved_2 : 14,
	23	LTS : 1,
	24	delivery_type : 1,
	25	__reserved_1 : 8,
	26	ID : 8;
	27	} __attribute__ ((packed)) bits;
	28	};
	29
	30	union IO_APIC_reg_01 {
	31	u32 raw;
	32	struct {
	33	u32 version : 8,
	34	__reserved_2 : 7,
	35	PRQ : 1,
	36	entries : 8,
	37	__reserved_1 : 8;
	38	} __attribute__ ((packed)) bits;
	39	};
	40
	41	union IO_APIC_reg_02 {
	42	u32 raw;
	43	struct {
	44	u32 __reserved_2 : 24,
	45	arbitration : 4,
	46	__reserved_1 : 4;
	47	} __attribute__ ((packed)) bits;
	48	};
	49
	50	union IO_APIC_reg_03 {
	51	u32 raw;
	52	struct {
	53	u32 boot_DT : 1,
	54	__reserved_1 : 31;
	55	} __attribute__ ((packed)) bits;
	56	};
	57
	58	/*
	59	* # of IO-APICs and # of IRQ routing registers
	60	*/
	61	extern int nr_ioapics;
	62	extern int nr_ioapic_registers[MAX_IO_APICS];
	63
	64	enum ioapic_irq_destination_types {
	65	dest_Fixed = 0,
	66	dest_LowestPrio = 1,
	67	dest_SMI = 2,
	68	dest__reserved_1 = 3,
	69	dest_NMI = 4,
	70	dest_INIT = 5,
	71	dest__reserved_2 = 6,
	72	dest_ExtINT = 7
	73	};
	74
	75	struct IO_APIC_route_entry {
	76	__u32 vector : 8,
	77	delivery_mode : 3, /* 000: FIXED
	78	* 001: lowest prio
	79	* 111: ExtINT
80	*/
81	dest_mode : 1, /* 0: physical, 1: logical */
82	delivery_status : 1,
83	polarity : 1,
84	irr : 1,
85	trigger : 1, /* 0: edge, 1: level */
86	mask : 1, /* 0: enabled, 1: disabled */
87	__reserved_2 : 15;
88
ee4eff6f BR	89	__u32 __reserved_3 : 24,
ee4eff6f BR	90	dest : 8;
1da177e4 LT	91	} __attribute__ ((packed));
	92
	93	/*
	94	* MP-BIOS irq configuration table structures:
	95	*/
	96
	97	/* I/O APIC entries */
	98	extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
	99
	100	/* # of MP IRQ source entries */
	101	extern int mp_irq_entries;
	102
	103	/* MP IRQ source entries */
	104	extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
	105
	106	/* non-0 if default (table-less) MP configuration */
	107	extern int mpc_default_type;
	108
1da177e4 LT	109	/* 1 if "noapic" boot option passed */
	110	extern int skip_ioapic_setup;
	111
61ec7567 LB	112	static inline void disable_ioapic_setup(void)
	113	{
	114	skip_ioapic_setup = 1;
	115	}
	116
	117
1da177e4 LT	118	/*
	119	* If we use the IO-APIC for IRQ routing, disable automatic
	120	* assignment of PCI IRQ's.
	121	*/
	122	#define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
	123
888ba6c6	124	#ifdef CONFIG_ACPI
1da177e4 LT	125	extern int io_apic_get_version (int ioapic);
	126	extern int io_apic_get_redir_entries (int ioapic);
	127	extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
	128	#endif
	129
	130	extern int sis_apic_bug; /* dummy */
	131
1da177e4 LT	132	void enable_NMI_through_LVT0 (void * dummy);
1da177e4 LT	133
306e440d IM	134	extern spinlock_t i8259A_lock;
306e440d IM	135
1da177e4	136	#endif