[net-next-2.6.git] / include / asm-x86 / apic.h

#ifndef _ASM_X86_APIC_H
#define _ASM_X86_APIC_H

#include <linux/pm.h>
#include <linux/delay.h>
#include <asm/fixmap.h>
#include <asm/apicdef.h>
#include <asm/processor.h>
#include <asm/system.h>

#define ARCH_APICTIMER_STOPS_ON_C3	1

#define Dprintk(x...)

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)


extern void generic_apic_probe(void);

#ifdef CONFIG_X86_LOCAL_APIC

extern int apic_verbosity;
extern int local_apic_timer_c2_ok;

extern int ioapic_force;

extern int disable_apic;
/*
 * Basic functions accessing APICs.
 */
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define apic_write native_apic_write
#define apic_write_atomic native_apic_write_atomic
#define apic_read native_apic_read
#define setup_boot_clock setup_boot_APIC_clock
#define setup_secondary_clock setup_secondary_APIC_clock
#endif

extern int is_vsmp_box(void);

static inline void native_apic_write(unsigned long reg, u32 v)
{
	*((volatile u32 *)(APIC_BASE + reg)) = v;
}

static inline void native_apic_write_atomic(unsigned long reg, u32 v)
{
	(void)xchg((u32 *)(APIC_BASE + reg), v);
}

static inline u32 native_apic_read(unsigned long reg)
{
	return *((volatile u32 *)(APIC_BASE + reg));
}

extern void apic_wait_icr_idle(void);
extern u32 safe_apic_wait_icr_idle(void);
extern int get_physical_broadcast(void);

#ifdef CONFIG_X86_GOOD_APIC
# define FORCE_READ_AROUND_WRITE 0
# define apic_read_around(x)
# define apic_write_around(x, y) apic_write((x), (y))
#else
# define FORCE_READ_AROUND_WRITE 1
# define apic_read_around(x) apic_read(x)
# define apic_write_around(x, y) apic_write_atomic((x), (y))
#endif

static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction:
	 * - a single rmw on Pentium/82489DX
	 * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
	 * ... yummie.
	 */

	/* Docs say use 0 for future compatibility */
	apic_write_around(APIC_EOI, 0);
}

extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
extern void lapic_shutdown(void);
extern int verify_local_APIC(void);
extern void cache_APIC_registers(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void setup_local_APIC(void);
extern void end_local_APIC_setup(void);
extern void init_apic_mappings(void);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern int APIC_init_uniprocessor(void);
extern void enable_NMI_through_LVT0(void);

/*
 * On 32bit this is mach-xxx local
 */
#ifdef CONFIG_X86_64
extern void early_init_lapic_mapping(void);
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
	return 0;
}
#endif

extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);


#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok		1
static inline void init_apic_mappings(void) { }

#endif /* !CONFIG_X86_LOCAL_APIC */

#endif /* __ASM_APIC_H */
Commit	Line	Data
67c5fc5c TG	1	#ifndef _ASM_X86_APIC_H
	2	#define _ASM_X86_APIC_H
	3
	4	#include <linux/pm.h>
	5	#include <linux/delay.h>
	6	#include <asm/fixmap.h>
	7	#include <asm/apicdef.h>
	8	#include <asm/processor.h>
	9	#include <asm/system.h>
	10
	11	#define ARCH_APICTIMER_STOPS_ON_C3 1
	12
	13	#define Dprintk(x...)
	14
	15	/*
	16	* Debugging macros
	17	*/
	18	#define APIC_QUIET 0
	19	#define APIC_VERBOSE 1
	20	#define APIC_DEBUG 2
	21
	22	/*
	23	* Define the default level of output to be very little
	24	* This can be turned up by using apic=verbose for more
	25	* information and apic=debug for _lots_ of information.
	26	* apic_verbosity is defined in apic.c
	27	*/
	28	#define apic_printk(v, s, a...) do { \
	29	if ((v) <= apic_verbosity) \
	30	printk(s, ##a); \
	31	} while (0)
	32
	33
	34	extern void generic_apic_probe(void);
	35
	36	#ifdef CONFIG_X86_LOCAL_APIC
	37
	38	extern int apic_verbosity;
67c5fc5c	39	extern int local_apic_timer_c2_ok;
67c5fc5c	40
67c5fc5c	41	extern int ioapic_force;
67c5fc5c	42
3c999f14	43	extern int disable_apic;
67c5fc5c TG	44	/*
	45	* Basic functions accessing APICs.
	46	*/
	47	#ifdef CONFIG_PARAVIRT
	48	#include <asm/paravirt.h>
96a388de	49	#else
67c5fc5c TG	50	#define apic_write native_apic_write
	51	#define apic_write_atomic native_apic_write_atomic
	52	#define apic_read native_apic_read
	53	#define setup_boot_clock setup_boot_APIC_clock
	54	#define setup_secondary_clock setup_secondary_APIC_clock
96a388de	55	#endif
67c5fc5c	56
aa7d8e25 RT	57	extern int is_vsmp_box(void);
aa7d8e25 RT	58
341d8854	59	static inline void native_apic_write(unsigned long reg, u32 v)
67c5fc5c TG	60	{
	61	((volatile u32 )(APIC_BASE + reg)) = v;
	62	}
	63
341d8854	64	static inline void native_apic_write_atomic(unsigned long reg, u32 v)
67c5fc5c	65	{
3c311feb	66	(void)xchg((u32 *)(APIC_BASE + reg), v);
67c5fc5c TG	67	}
67c5fc5c TG	68
341d8854	69	static inline u32 native_apic_read(unsigned long reg)
67c5fc5c TG	70	{
	71	return ((volatile u32 )(APIC_BASE + reg));
	72	}
	73
	74	extern void apic_wait_icr_idle(void);
	75	extern u32 safe_apic_wait_icr_idle(void);
	76	extern int get_physical_broadcast(void);
	77
	78	#ifdef CONFIG_X86_GOOD_APIC
	79	# define FORCE_READ_AROUND_WRITE 0
	80	# define apic_read_around(x)
	81	# define apic_write_around(x, y) apic_write((x), (y))
	82	#else
	83	# define FORCE_READ_AROUND_WRITE 1
	84	# define apic_read_around(x) apic_read(x)
	85	# define apic_write_around(x, y) apic_write_atomic((x), (y))
	86	#endif
	87
	88	static inline void ack_APIC_irq(void)
	89	{
	90	/*
	91	* ack_APIC_irq() actually gets compiled as a single instruction:
	92	* - a single rmw on Pentium/82489DX
	93	* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
	94	* ... yummie.
	95	*/
	96
	97	/* Docs say use 0 for future compatibility */
	98	apic_write_around(APIC_EOI, 0);
	99	}
	100
	101	extern int lapic_get_maxlvt(void);
	102	extern void clear_local_APIC(void);
	103	extern void connect_bsp_APIC(void);
	104	extern void disconnect_bsp_APIC(int virt_wire_setup);
	105	extern void disable_local_APIC(void);
	106	extern void lapic_shutdown(void);
	107	extern int verify_local_APIC(void);
	108	extern void cache_APIC_registers(void);
	109	extern void sync_Arb_IDs(void);
	110	extern void init_bsp_APIC(void);
	111	extern void setup_local_APIC(void);
739f33b3	112	extern void end_local_APIC_setup(void);
67c5fc5c	113	extern void init_apic_mappings(void);
67c5fc5c TG	114	extern void setup_boot_APIC_clock(void);
	115	extern void setup_secondary_APIC_clock(void);
	116	extern int APIC_init_uniprocessor(void);
e9427101	117	extern void enable_NMI_through_LVT0(void);
67c5fc5c TG	118
	119	/*
	120	* On 32bit this is mach-xxx local
	121	*/
	122	#ifdef CONFIG_X86_64
8643f9d0	123	extern void early_init_lapic_mapping(void);
8fbbc4b4 AK	124	extern int apic_is_clustered_box(void);
	125	#else
	126	static inline int apic_is_clustered_box(void)
	127	{
	128	return 0;
	129	}
67c5fc5c TG	130	#endif
67c5fc5c TG	131
7b83dae7 RR	132	extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
7b83dae7 RR	133	extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
67c5fc5c	134
67c5fc5c TG	135
	136	#else /* !CONFIG_X86_LOCAL_APIC */
	137	static inline void lapic_shutdown(void) { }
	138	#define local_apic_timer_c2_ok 1
f3294a33	139	static inline void init_apic_mappings(void) { }
67c5fc5c TG	140
	141	#endif /* !CONFIG_X86_LOCAL_APIC */
	142
	143	#endif /* __ASM_APIC_H */