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1da177e4
LT		 1/* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#ifndef _SPARC64_PGTABLE_H
9#define _SPARC64_PGTABLE_H
10
11/* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15#include <asm-generic/pgtable-nopud.h>
16
17#include <linux/config.h>
18#include <linux/compiler.h>
19#include <asm/types.h>
20#include <asm/spitfire.h>
21#include <asm/asi.h>
22#include <asm/system.h>
23#include <asm/page.h>
24#include <asm/processor.h>
25#include <asm/const.h>
26
27/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 16MB).
28 * The page copy blockops use 0x1000000 to 0x18000000 (16MB --> 24MB).
29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
30 * The vmalloc area spans 0x140000000 to 0x200000000.
31 * There is a single static kernel PMD which maps from 0x0 to address
32 * 0x400000000.
33 */
34#define TLBTEMP_BASE _AC(0x0000000001000000,UL)
35#define MODULES_VADDR _AC(0x0000000002000000,UL)
36#define MODULES_LEN _AC(0x000000007e000000,UL)
37#define MODULES_END _AC(0x0000000080000000,UL)
38#define VMALLOC_START _AC(0x0000000140000000,UL)
39#define VMALLOC_END _AC(0x0000000200000000,UL)
40#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42
43/* XXX All of this needs to be rethought so we can take advantage
44 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
45 * XXX in the middle like on spitfire. -DaveM
46 */
47/*
48 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
49 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
50 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
51 * table is a single page long). The next higher PMD_BITS determine pmd#
52 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
53 * since the pmd entries are 4 bytes, and each pmd page is a single page
54 * long). Finally, the higher few bits determine pgde#.
55 */
56
57/* PMD_SHIFT determines the size of the area a second-level page
58 * table can map
59 */
60#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
61#define PMD_SIZE (1UL << PMD_SHIFT)
62#define PMD_MASK (~(PMD_SIZE-1))
63#define PMD_BITS (PAGE_SHIFT - 2)
64
65/* PGDIR_SHIFT determines what a third-level page table entry can map */
66#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
67#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
68#define PGDIR_MASK (~(PGDIR_SIZE-1))
69#define PGDIR_BITS (PAGE_SHIFT - 2)
70
71#ifndef __ASSEMBLY__
72
73#include <linux/sched.h>
74
75/* Entries per page directory level. */
76#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
77#define PTRS_PER_PMD (1UL << PMD_BITS)
78#define PTRS_PER_PGD (1UL << PGDIR_BITS)
79
80/* Kernel has a separate 44bit address space. */
d455a369 81#define FIRST_USER_ADDRESS 0
1da177e4
LT		 82
83#define pte_ERROR(e) __builtin_trap()
84#define pmd_ERROR(e) __builtin_trap()
85#define pgd_ERROR(e) __builtin_trap()
86
87#endif /* !(__ASSEMBLY__) */
88
89/* Spitfire/Cheetah TTE bits. */
90#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
91#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/
92#define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */
93#define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */
94#define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */
95#define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */
96#define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */
97#define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */
98#define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
99#define _PAGE_RES1 _AC(0x0003000000000000,UL) /* Reserved */
100#define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
101#define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */
102#define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/
103#define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */
104#define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */
105#define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */
106#define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
107#define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
108#define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */
109#define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */
110#define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */
111#define _PAGE_G _AC(0x0000000000000001,UL) /* Global */
112
113/* Here are the SpitFire software bits we use in the TTE's.
114 *
115 * WARNING: If you are going to try and start using some
116 * of the soft2 bits, you will need to make
117 * modifications to the swap entry implementation.
118 * For example, one thing that could happen is that
119 * swp_entry_to_pte() would BUG_ON() if you tried
120 * to use one of the soft2 bits for _PAGE_FILE.
121 *
122 * Like other architectures, I have aliased _PAGE_FILE with
123 * _PAGE_MODIFIED. This works because _PAGE_FILE is never
124 * interpreted that way unless _PAGE_PRESENT is clear.
125 */
126#define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */
127#define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */
128#define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */
129#define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
130#define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */
131#define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */
132#define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */
133
134#if PAGE_SHIFT == 13
135#define _PAGE_SZBITS _PAGE_SZ8K
136#elif PAGE_SHIFT == 16
137#define _PAGE_SZBITS _PAGE_SZ64K
138#elif PAGE_SHIFT == 19
139#define _PAGE_SZBITS _PAGE_SZ512K
140#elif PAGE_SHIFT == 22
141#define _PAGE_SZBITS _PAGE_SZ4MB
142#else
143#error Wrong PAGE_SHIFT specified
144#endif
145
146#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
147#define _PAGE_SZHUGE _PAGE_SZ4MB
148#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
149#define _PAGE_SZHUGE _PAGE_SZ512K
150#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
151#define _PAGE_SZHUGE _PAGE_SZ64K
152#endif
153
154#define _PAGE_CACHE (_PAGE_CP | _PAGE_CV)
155
156#define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
157#define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
158#define __PRIV_BITS _PAGE_P
159
160#define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE)
161
162/* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
163#define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
164 __ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC)
165
166#define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
167 __ACCESS_BITS | _PAGE_EXEC)
168
169#define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
170 __ACCESS_BITS | _PAGE_EXEC)
171
172#define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
173 __PRIV_BITS | \
174 __ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC)
175
176#define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
177 _PAGE_CACHE | \
178 __ACCESS_BITS | _PAGE_WRITE)
179
180#define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
181 _PAGE_CACHE | __ACCESS_BITS)
182
183#define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
184 _PAGE_CACHE | __ACCESS_BITS)
185
186#define _PFN_MASK _PAGE_PADDR
187
188#define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \
189 __ACCESS_BITS | _PAGE_E)
190
191#define __P000 PAGE_NONE
192#define __P001 PAGE_READONLY_NOEXEC
193#define __P010 PAGE_COPY_NOEXEC
194#define __P011 PAGE_COPY_NOEXEC
195#define __P100 PAGE_READONLY
196#define __P101 PAGE_READONLY
197#define __P110 PAGE_COPY
198#define __P111 PAGE_COPY
199
200#define __S000 PAGE_NONE
201#define __S001 PAGE_READONLY_NOEXEC
202#define __S010 PAGE_SHARED_NOEXEC
203#define __S011 PAGE_SHARED_NOEXEC
204#define __S100 PAGE_READONLY
205#define __S101 PAGE_READONLY
206#define __S110 PAGE_SHARED
207#define __S111 PAGE_SHARED
208
209#ifndef __ASSEMBLY__
210
211extern unsigned long phys_base;
212extern unsigned long pfn_base;
213
214extern struct page *mem_map_zero;
215#define ZERO_PAGE(vaddr) (mem_map_zero)
216
217/* PFNs are real physical page numbers. However, mem_map only begins to record
218 * per-page information starting at pfn_base. This is to handle systems where
219 * the first physical page in the machine is at some huge physical address,
220 * such as 4GB. This is common on a partitioned E10000, for example.
221 */
222
223#define pfn_pte(pfn, prot) \
224 __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS)
225#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
226
227#define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT)
228#define pte_page(x) pfn_to_page(pte_pfn(x))
229
230#define page_pte_prot(page, prot) mk_pte(page, prot)
231#define page_pte(page) page_pte_prot(page, __pgprot(0))
232
233static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
234{
235 pte_t __pte;
236 const unsigned long preserve_mask = (_PFN_MASK |
237 _PAGE_MODIFIED | _PAGE_ACCESSED |
238 _PAGE_CACHE | _PAGE_E |
239 _PAGE_PRESENT | _PAGE_SZBITS);
240
241 pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) |
242 (pgprot_val(new_prot) & ~preserve_mask);
243
244 return __pte;
245}
246#define pmd_set(pmdp, ptep) \
247 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
248#define pud_set(pudp, pmdp) \
249 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
250#define __pmd_page(pmd) \
251 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
252#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
253#define pud_page(pud) \
254 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
255#define pte_none(pte) (!pte_val(pte))
256#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
257#define pmd_none(pmd) (!pmd_val(pmd))
258#define pmd_bad(pmd) (0)
259#define pmd_present(pmd) (pmd_val(pmd) != 0U)
260#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
261#define pud_none(pud) (!pud_val(pud))
262#define pud_bad(pud) (0)
263#define pud_present(pud) (pud_val(pud) != 0U)
264#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
265
266/* The following only work if pte_present() is true.
267 * Undefined behaviour if not..
268 */
269#define pte_read(pte) (pte_val(pte) & _PAGE_READ)
270#define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC)
271#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
272#define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
273#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
274#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
275#define pte_rdprotect(pte) \
276 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
277#define pte_mkclean(pte) \
278 (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
279#define pte_mkold(pte) \
280 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
281
282/* Permanent address of a page. */
283#define __page_address(page) page_address(page)
284
285/* Be very careful when you change these three, they are delicate. */
286#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
287#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
288#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
63551ae0 289#define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE))
1da177e4
LT		 290
291/* to find an entry in a page-table-directory. */
292#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
293#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
294
295/* to find an entry in a kernel page-table-directory */
296#define pgd_offset_k(address) pgd_offset(&init_mm, address)
297
298/* extract the pgd cache used for optimizing the tlb miss
299 * slow path when executing 32-bit compat processes
300 */
301#define get_pgd_cache(pgd) ((unsigned long) pgd_val(*pgd) << 11)
302
303/* Find an entry in the second-level page table.. */
304#define pmd_offset(pudp, address) \
305 ((pmd_t *) pud_page(*(pudp)) + \
306 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
307
308/* Find an entry in the third-level page table.. */
309#define pte_index(dir, address) \
310 ((pte_t *) __pmd_page(*(dir)) + \
311 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
312#define pte_offset_kernel pte_index
313#define pte_offset_map pte_index
314#define pte_offset_map_nested pte_index
315#define pte_unmap(pte) do { } while (0)
316#define pte_unmap_nested(pte) do { } while (0)
317
318/* Actual page table PTE updates. */
319extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
320
321static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
322{
323 pte_t orig = *ptep;
324
325 *ptep = pte;
326
327 /* It is more efficient to let flush_tlb_kernel_range()
328 * handle init_mm tlb flushes.
329 */
330 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
331 tlb_batch_add(mm, addr, ptep, orig);
332}
333
334#define pte_clear(mm,addr,ptep) \
335 set_pte_at((mm), (addr), (ptep), __pte(0UL))
336
337extern pgd_t swapper_pg_dir[1];
338
339/* These do nothing with the way I have things setup. */
340#define mmu_lockarea(vaddr, len) (vaddr)
341#define mmu_unlockarea(vaddr, len) do { } while(0)
342
343struct vm_area_struct;
344extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
345
346/* Make a non-present pseudo-TTE. */
347static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
348{
349 pte_t pte;
350 pte_val(pte) = (((page) | pgprot_val(prot) | _PAGE_E) &
351 ~(unsigned long)_PAGE_CACHE);
352 pte_val(pte) |= (((unsigned long)space) << 32);
353 return pte;
354}
355
356/* Encode and de-code a swap entry */
357#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
358#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
359#define __swp_entry(type, offset) \
360 ( (swp_entry_t) \
361 { \
362 (((long)(type) << PAGE_SHIFT) | \
363 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
364 } )
365#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
366#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
367
368/* File offset in PTE support. */
369#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
370#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
371#define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE))
372#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
373
374extern unsigned long prom_virt_to_phys(unsigned long, int *);
375
376static __inline__ unsigned long
377sun4u_get_pte (unsigned long addr)
378{
379 pgd_t *pgdp;
380 pud_t *pudp;
381 pmd_t *pmdp;
382 pte_t *ptep;
383
384 if (addr >= PAGE_OFFSET)
385 return addr & _PAGE_PADDR;
386 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
387 return prom_virt_to_phys(addr, NULL);
388 pgdp = pgd_offset_k(addr);
389 pudp = pud_offset(pgdp, addr);
390 pmdp = pmd_offset(pudp, addr);
391 ptep = pte_offset_kernel(pmdp, addr);
392 return pte_val(*ptep) & _PAGE_PADDR;
393}
394
395static __inline__ unsigned long
396__get_phys (unsigned long addr)
397{
398 return sun4u_get_pte (addr);
399}
400
401static __inline__ int
402__get_iospace (unsigned long addr)
403{
404 return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
405}
406
407extern unsigned long *sparc64_valid_addr_bitmap;
408
409/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
410#define kern_addr_valid(addr) \
411 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
412
413extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from,
414 unsigned long offset,
415 unsigned long size, pgprot_t prot, int space);
416extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
417 unsigned long pfn,
418 unsigned long size, pgprot_t prot);
419
d7be828e
DM		 420/* Clear virtual and physical cachability, set side-effect bit. */
421#define pgprot_noncached(prot) \
422 (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
423 _PAGE_E))
424
1da177e4
LT		 425/*
426 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
427 * its high 4 bits. These macros/functions put it there or get it from there.
428 */
429#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
430#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
431#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
432
1da177e4
LT		 433#include <asm-generic/pgtable.h>
434
435/* We provide our own get_unmapped_area to cope with VA holes for userland */
436#define HAVE_ARCH_UNMAPPED_AREA
437
438/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
439 * the largest alignment possible such that larget PTEs can be used.
440 */
441extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
442 unsigned long, unsigned long,
443 unsigned long);
444#define HAVE_ARCH_FB_UNMAPPED_AREA
445
446/*
447 * No page table caches to initialise
448 */
449#define pgtable_cache_init() do { } while (0)
450
451extern void check_pgt_cache(void);
452
453#endif /* !(__ASSEMBLY__) */
454
455#endif /* !(_SPARC64_PGTABLE_H) */
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