]> bbs.cooldavid.org Git - net-next-2.6.git/blame - include/asm-powerpc/ppc-pci.h
Fix occurrences of "the the "
[net-next-2.6.git] / include / asm-powerpc / ppc-pci.h
CommitLineData
1da177e4
LT
1/*
2 * c 2001 PPC 64 Team, IBM Corp
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
d387899f
SR
9#ifndef _ASM_POWERPC_PPC_PCI_H
10#define _ASM_POWERPC_PPC_PCI_H
88ced031 11#ifdef __KERNEL__
1da177e4 12
bed59275
SR
13#ifdef CONFIG_PCI
14
1da177e4
LT
15#include <linux/pci.h>
16#include <asm/pci-bridge.h>
17
18extern unsigned long isa_io_base;
19
1da177e4
LT
20extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
21extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
22
23
24extern struct list_head hose_list;
25extern int global_phb_number;
26
36241ce6 27extern void find_and_init_phbs(void);
1da177e4
LT
28
29extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */
30
ae65a391
LV
31/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
32#define BUID_HI(buid) ((buid) >> 32)
33#define BUID_LO(buid) ((buid) & 0xffffffff)
34
1da177e4
LT
35/* PCI device_node operations */
36struct device_node;
37typedef void *(*traverse_func)(struct device_node *me, void *data);
38void *traverse_pci_devices(struct device_node *start, traverse_func pre,
39 void *data);
40
4c9d2800
BH
41extern void pci_devs_phb_init(void);
42extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
43extern void scan_phb(struct pci_controller *hose);
1da177e4 44
dad32bbf 45/* From rtas_pci.h */
4c9d2800
BH
46extern void init_pci_config_tokens (void);
47extern unsigned long get_phb_buid (struct device_node *);
48extern int rtas_setup_phb(struct pci_controller *phb);
1da177e4 49
dad32bbf
JR
50/* From pSeries_pci.h */
51extern void pSeries_final_fixup(void);
dad32bbf 52
1da177e4 53extern unsigned long pci_probe_only;
1da177e4 54
6dee3fb9
LV
55/* ---- EEH internal-use-only related routines ---- */
56#ifdef CONFIG_EEH
5d5a0936
LV
57
58void pci_addr_cache_insert_device(struct pci_dev *dev);
59void pci_addr_cache_remove_device(struct pci_dev *dev);
60void pci_addr_cache_build(void);
61struct pci_dev *pci_get_device_by_addr(unsigned long addr);
62
77bd7415
LV
63/**
64 * eeh_slot_error_detail -- record and EEH error condition to the log
65 * @severity: 1 if temporary, 2 if permanent failure.
66 *
59c51591 67 * Obtains the EEH error details from the RTAS subsystem,
77bd7415
LV
68 * and then logs these details with the RTAS error log system.
69 */
70void eeh_slot_error_detail (struct pci_dn *pdn, int severity);
71
47b5c838 72/**
9c547768 73 * rtas_pci_enable - enable IO transfers for this slot
47b5c838
LV
74 * @pdn: pci device node
75 * @function: either EEH_THAW_MMIO or EEH_THAW_DMA
76 *
77 * Enable I/O transfers to this slot
78 */
79#define EEH_THAW_MMIO 2
80#define EEH_THAW_DMA 3
81int rtas_pci_enable(struct pci_dn *pdn, int function);
82
6dee3fb9
LV
83/**
84 * rtas_set_slot_reset -- unfreeze a frozen slot
85 *
86 * Clear the EEH-frozen condition on a slot. This routine
87 * does this by asserting the PCI #RST line for 1/8th of
88 * a second; this routine will sleep while the adapter is
89 * being reset.
b6495c0c
LV
90 *
91 * Returns a non-zero value if the reset failed.
6dee3fb9 92 */
b6495c0c 93int rtas_set_slot_reset (struct pci_dn *);
9c547768 94int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs);
6dee3fb9 95
8b553f32
LV
96/**
97 * eeh_restore_bars - Restore device configuration info.
98 *
99 * A reset of a PCI device will clear out its config space.
100 * This routines will restore the config space for this
101 * device, and is children, to values previously obtained
102 * from the firmware.
103 */
104void eeh_restore_bars(struct pci_dn *);
105
106/**
107 * rtas_configure_bridge -- firmware initialization of pci bridge
108 *
109 * Ask the firmware to configure all PCI bridges devices
110 * located behind the indicated node. Required after a
111 * pci device reset. Does essentially the same hing as
112 * eeh_restore_bars, but for brdges, and lets firmware
113 * do the work.
114 */
115void rtas_configure_bridge(struct pci_dn *);
116
117int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
7684b40c 118int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
8b553f32 119
d9564ad1
LV
120/**
121 * mark and clear slots: find "partition endpoint" PE and set or
122 * clear the flags for each subnode of the PE.
123 */
124void eeh_mark_slot (struct device_node *dn, int mode_flag);
125void eeh_clear_slot (struct device_node *dn, int mode_flag);
126
9fb40eb8
LV
127/* Find the associated "Partiationable Endpoint" PE */
128struct device_node * find_device_pe(struct device_node *dn);
129
6dee3fb9
LV
130#endif
131
bed59275
SR
132#else /* CONFIG_PCI */
133static inline void find_and_init_phbs(void) { }
134static inline void init_pci_config_tokens(void) { }
135#endif /* !CONFIG_PCI */
136
88ced031 137#endif /* __KERNEL__ */
d387899f 138#endif /* _ASM_POWERPC_PPC_PCI_H */