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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[net-next-2.6.git] / include / asm-powerpc / irq.h
CommitLineData
1da177e4 1#ifdef __KERNEL__
1b92313d
PM		 2#ifndef _ASM_POWERPC_IRQ_H
3#define _ASM_POWERPC_IRQ_H
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
1da177e4 11
1b92313d 12#include <linux/threads.h>
0ebfff14
BH		 13#include <linux/list.h>
14#include <linux/radix-tree.h>
1b92313d
PM		 15
16#include <asm/types.h>
1da177e4
LT		 17#include <asm/atomic.h>
18
1da177e4 19
b671ad2b
KG		 20#define get_irq_desc(irq) (&irq_desc[(irq)])
21
22/* Define a way to iterate across irqs. */
23#define for_each_irq(i) \
24 for ((i) = 0; (i) < NR_IRQS; ++(i))
25
0ebfff14 26extern atomic_t ppc_n_lost_interrupts;
1b92313d 27
0ebfff14
BH		 28#ifdef CONFIG_PPC_MERGE
29
30/* This number is used when no interrupt has been assigned */
31#define NO_IRQ (0)
32
33/* This is a special irq number to return from get_irq() to tell that
34 * no interrupt happened _and_ ignore it (don't count it as bad). Some
35 * platforms like iSeries rely on that.
1b92313d 36 */
0ebfff14
BH		 37#define NO_IRQ_IGNORE ((unsigned int)-1)
38
39/* Total number of virq in the platform (make it a CONFIG_* option ? */
1b92313d
PM		 40#define NR_IRQS 512
41
0ebfff14
BH		 42/* Number of irqs reserved for the legacy controller */
43#define NUM_ISA_INTERRUPTS 16
44
45/* This type is the placeholder for a hardware interrupt number. It has to
46 * be big enough to enclose whatever representation is used by a given
47 * platform.
48 */
49typedef unsigned long irq_hw_number_t;
50
51/* Interrupt controller "host" data structure. This could be defined as a
52 * irq domain controller. That is, it handles the mapping between hardware
53 * and virtual interrupt numbers for a given interrupt domain. The host
54 * structure is generally created by the PIC code for a given PIC instance
55 * (though a host can cover more than one PIC if they have a flat number
56 * model). It's the host callbacks that are responsible for setting the
57 * irq_chip on a given irq_desc after it's been mapped.
58 *
59 * The host code and data structures are fairly agnostic to the fact that
60 * we use an open firmware device-tree. We do have references to struct
61 * device_node in two places: in irq_find_host() to find the host matching
62 * a given interrupt controller node, and of course as an argument to its
63 * counterpart host->ops->match() callback. However, those are treated as
64 * generic pointers by the core and the fact that it's actually a device-node
65 * pointer is purely a convention between callers and implementation. This
66 * code could thus be used on other architectures by replacing those two
67 * by some sort of arch-specific void * "token" used to identify interrupt
68 * controllers.
69 */
70struct irq_host;
71struct radix_tree_root;
72
73/* Functions below are provided by the host and called whenever a new mapping
74 * is created or an old mapping is disposed. The host can then proceed to
75 * whatever internal data structures management is required. It also needs
76 * to setup the irq_desc when returning from map().
77 */
78struct irq_host_ops {
79 /* Match an interrupt controller device node to a host, returns
80 * 1 on a match
81 */
82 int (*match)(struct irq_host *h, struct device_node *node);
83
84 /* Create or update a mapping between a virtual irq number and a hw
6e99e458 85 * irq number. This is called only once for a given mapping.
0ebfff14 86 */
6e99e458 87 int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
0ebfff14
BH		 88
89 /* Dispose of such a mapping */
90 void (*unmap)(struct irq_host *h, unsigned int virq);
91
92 /* Translate device-tree interrupt specifier from raw format coming
93 * from the firmware to a irq_hw_number_t (interrupt line number) and
6e99e458
BH		 94 * type (sense) that can be passed to set_irq_type(). In the absence
95 * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
96 * will return the hw number in the first cell and IRQ_TYPE_NONE for
97 * the type (which amount to keeping whatever default value the
98 * interrupt controller has for that line)
0ebfff14
BH		 99 */
100 int (*xlate)(struct irq_host *h, struct device_node *ctrler,
101 u32 *intspec, unsigned int intsize,
6e99e458 102 irq_hw_number_t *out_hwirq, unsigned int *out_type);
0ebfff14
BH		 103};
104
105struct irq_host {
106 struct list_head link;
107
108 /* type of reverse mapping technique */
109 unsigned int revmap_type;
110#define IRQ_HOST_MAP_LEGACY 0 /* legacy 8259, gets irqs 1..15 */
111#define IRQ_HOST_MAP_NOMAP 1 /* no fast reverse mapping */
112#define IRQ_HOST_MAP_LINEAR 2 /* linear map of interrupts */
113#define IRQ_HOST_MAP_TREE 3 /* radix tree */
114 union {
115 struct {
116 unsigned int size;
117 unsigned int *revmap;
118 } linear;
119 struct radix_tree_root tree;
120 } revmap_data;
121 struct irq_host_ops *ops;
122 void *host_data;
123 irq_hw_number_t inval_irq;
124};
125
126/* The main irq map itself is an array of NR_IRQ entries containing the
127 * associate host and irq number. An entry with a host of NULL is free.
128 * An entry can be allocated if it's free, the allocator always then sets
129 * hwirq first to the host's invalid irq number and then fills ops.
130 */
131struct irq_map_entry {
132 irq_hw_number_t hwirq;
133 struct irq_host *host;
134};
135
136extern struct irq_map_entry irq_map[NR_IRQS];
137
138
40681b95 139/**
0ebfff14
BH		 140 * irq_alloc_host - Allocate a new irq_host data structure
141 * @node: device-tree node of the interrupt controller
142 * @revmap_type: type of reverse mapping to use
143 * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
144 * @ops: map/unmap host callbacks
145 * @inval_irq: provide a hw number in that host space that is always invalid
146 *
147 * Allocates and initialize and irq_host structure. Note that in the case of
148 * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
149 * for all legacy interrupts except 0 (which is always the invalid irq for
150 * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
151 * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
152 * later during boot automatically (the reverse mapping will use the slow path
153 * until that happens).
154 */
155extern struct irq_host *irq_alloc_host(unsigned int revmap_type,
156 unsigned int revmap_arg,
157 struct irq_host_ops *ops,
158 irq_hw_number_t inval_irq);
159
160
40681b95 161/**
0ebfff14
BH		 162 * irq_find_host - Locates a host for a given device node
163 * @node: device-tree node of the interrupt controller
164 */
165extern struct irq_host *irq_find_host(struct device_node *node);
166
167
40681b95 168/**
0ebfff14
BH		 169 * irq_set_default_host - Set a "default" host
170 * @host: default host pointer
171 *
172 * For convenience, it's possible to set a "default" host that will be used
173 * whenever NULL is passed to irq_create_mapping(). It makes life easier for
174 * platforms that want to manipulate a few hard coded interrupt numbers that
175 * aren't properly represented in the device-tree.
176 */
177extern void irq_set_default_host(struct irq_host *host);
178
179
40681b95 180/**
0ebfff14
BH		 181 * irq_set_virq_count - Set the maximum number of virt irqs
182 * @count: number of linux virtual irqs, capped with NR_IRQS
183 *
184 * This is mainly for use by platforms like iSeries who want to program
185 * the virtual irq number in the controller to avoid the reverse mapping
186 */
187extern void irq_set_virq_count(unsigned int count);
188
189
40681b95 190/**
0ebfff14
BH		 191 * irq_create_mapping - Map a hardware interrupt into linux virq space
192 * @host: host owning this hardware interrupt or NULL for default host
193 * @hwirq: hardware irq number in that host space
0ebfff14
BH		 194 *
195 * Only one mapping per hardware interrupt is permitted. Returns a linux
6e99e458
BH		 196 * virq number.
197 * If the sense/trigger is to be specified, set_irq_type() should be called
198 * on the number returned from that call.
0ebfff14
BH		 199 */
200extern unsigned int irq_create_mapping(struct irq_host *host,
6e99e458 201 irq_hw_number_t hwirq);
0ebfff14
BH		 202
203
40681b95 204/**
0ebfff14
BH		 205 * irq_dispose_mapping - Unmap an interrupt
206 * @virq: linux virq number of the interrupt to unmap
1b92313d 207 */
0ebfff14 208extern void irq_dispose_mapping(unsigned int virq);
1b92313d 209
40681b95 210/**
0ebfff14
BH		 211 * irq_find_mapping - Find a linux virq from an hw irq number.
212 * @host: host owning this hardware interrupt
213 * @hwirq: hardware irq number in that host space
214 *
215 * This is a slow path, for use by generic code. It's expected that an
216 * irq controller implementation directly calls the appropriate low level
217 * mapping function.
7d01c880 218 */
0ebfff14
BH		 219extern unsigned int irq_find_mapping(struct irq_host *host,
220 irq_hw_number_t hwirq);
7d01c880 221
0ebfff14 222
40681b95 223/**
0ebfff14
BH		 224 * irq_radix_revmap - Find a linux virq from a hw irq number.
225 * @host: host owning this hardware interrupt
226 * @hwirq: hardware irq number in that host space
227 *
228 * This is a fast path, for use by irq controller code that uses radix tree
229 * revmaps
230 */
231extern unsigned int irq_radix_revmap(struct irq_host *host,
232 irq_hw_number_t hwirq);
233
40681b95 234/**
0ebfff14
BH		 235 * irq_linear_revmap - Find a linux virq from a hw irq number.
236 * @host: host owning this hardware interrupt
237 * @hwirq: hardware irq number in that host space
238 *
239 * This is a fast path, for use by irq controller code that uses linear
240 * revmaps. It does fallback to the slow path if the revmap doesn't exist
241 * yet and will create the revmap entry with appropriate locking
242 */
243
244extern unsigned int irq_linear_revmap(struct irq_host *host,
245 irq_hw_number_t hwirq);
246
247
248
40681b95 249/**
0ebfff14
BH		 250 * irq_alloc_virt - Allocate virtual irq numbers
251 * @host: host owning these new virtual irqs
252 * @count: number of consecutive numbers to allocate
253 * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
254 *
255 * This is a low level function that is used internally by irq_create_mapping()
256 * and that can be used by some irq controllers implementations for things
257 * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
1b92313d 258 */
0ebfff14
BH		 259extern unsigned int irq_alloc_virt(struct irq_host *host,
260 unsigned int count,
261 unsigned int hint);
262
40681b95 263/**
0ebfff14
BH		 264 * irq_free_virt - Free virtual irq numbers
265 * @virq: virtual irq number of the first interrupt to free
266 * @count: number of interrupts to free
267 *
268 * This function is the opposite of irq_alloc_virt. It will not clear reverse
269 * maps, this should be done previously by unmap'ing the interrupt. In fact,
270 * all interrupts covered by the range being freed should have been unmapped
271 * prior to calling this.
272 */
273extern void irq_free_virt(unsigned int virq, unsigned int count);
274
275
276/* -- OF helpers -- */
277
278/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
279 * @controller: Device node of the interrupt controller
280 * @inspec: Interrupt specifier from the device-tree
281 * @intsize: Size of the interrupt specifier from the device-tree
282 *
283 * This function is identical to irq_create_mapping except that it takes
284 * as input informations straight from the device-tree (typically the results
6e99e458 285 * of the of_irq_map_*() functions.
0ebfff14
BH		 286 */
287extern unsigned int irq_create_of_mapping(struct device_node *controller,
288 u32 *intspec, unsigned int intsize);
289
290
291/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
292 * @device: Device node of the device whose interrupt is to be mapped
293 * @index: Index of the interrupt to map
294 *
295 * This function is a wrapper that chains of_irq_map_one() and
296 * irq_create_of_mapping() to make things easier to callers
297 */
298extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
299
300/* -- End OF helpers -- */
1b92313d 301
40681b95 302/**
0ebfff14
BH		 303 * irq_early_init - Init irq remapping subsystem
304 */
305extern void irq_early_init(void);
306
307static __inline__ int irq_canonicalize(int irq)
1b92313d 308{
0ebfff14 309 return irq;
1b92313d
PM		 310}
311
0ebfff14
BH		 312
313#else /* CONFIG_PPC_MERGE */
314
315/* This number is used when no interrupt has been assigned */
316#define NO_IRQ (-1)
317#define NO_IRQ_IGNORE (-2)
318
1b92313d
PM		 319
320/*
0ebfff14
BH		 321 * These constants are used for passing information about interrupt
322 * signal polarity and level/edge sensing to the low-level PIC chip
323 * drivers.
1b92313d 324 */
0ebfff14
BH		 325#define IRQ_SENSE_MASK 0x1
326#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
327#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
1b92313d 328
0ebfff14
BH		 329#define IRQ_POLARITY_MASK 0x2
330#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
331#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
1b92313d 332
1b92313d 333
1da177e4
LT		 334#if defined(CONFIG_40x)
335#include <asm/ibm4xx.h>
336
337#ifndef NR_BOARD_IRQS
338#define NR_BOARD_IRQS 0
339#endif
340
341#ifndef UIC_WIDTH /* Number of interrupts per device */
342#define UIC_WIDTH 32
343#endif
344
345#ifndef NR_UICS /* number of UIC devices */
346#define NR_UICS 1
347#endif
348
349#if defined (CONFIG_403)
350/*
351 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
352 * 32 possible interrupts, a majority of which are not implemented on
353 * all cores. There are six configurable, external interrupt pins and
354 * there are eight internal interrupts for the on-chip serial port
355 * (SPU), DMA controller, and JTAG controller.
356 *
357 */
358
359#define NR_AIC_IRQS 32
360#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
361
362#elif !defined (CONFIG_403)
363
364/*
365 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
366 * possible interrupts as well. There are seven, configurable external
367 * interrupt pins and there are 17 internal interrupts for the on-chip
368 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
369 *
370 */
371
372
373#define NR_UIC_IRQS UIC_WIDTH
374#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
375#endif
1da177e4
LT		 376
377#elif defined(CONFIG_44x)
378#include <asm/ibm44x.h>
379
380#define NR_UIC_IRQS 32
381#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
382
1da177e4
LT		 383#elif defined(CONFIG_8xx)
384
385/* Now include the board configuration specific associations.
386*/
387#include <asm/mpc8xx.h>
388
389/* The MPC8xx cores have 16 possible interrupts. There are eight
390 * possible level sensitive interrupts assigned and generated internally
391 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
392 * There are eight external interrupts (IRQs) that can be configured
393 * as either level or edge sensitive.
394 *
395 * On some implementations, there is also the possibility of an 8259
396 * through the PCI and PCI-ISA bridges.
397 *
398 * We are "flattening" the interrupt vectors of the cascaded CPM
399 * and 8259 interrupt controllers so that we can uniquely identify
400 * any interrupt source with a single integer.
401 */
402#define NR_SIU_INTS 16
403#define NR_CPM_INTS 32
404#ifndef NR_8259_INTS
405#define NR_8259_INTS 0
406#endif
407
408#define SIU_IRQ_OFFSET 0
409#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
410#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
411
412#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
413
414/* These values must be zero-based and map 1:1 with the SIU configuration.
415 * They are used throughout the 8xx I/O subsystem to generate
416 * interrupt masks, flags, and other control patterns. This is why the
417 * current kernel assumption of the 8259 as the base controller is such
418 * a pain in the butt.
419 */
420#define SIU_IRQ0 (0) /* Highest priority */
421#define SIU_LEVEL0 (1)
422#define SIU_IRQ1 (2)
423#define SIU_LEVEL1 (3)
424#define SIU_IRQ2 (4)
425#define SIU_LEVEL2 (5)
426#define SIU_IRQ3 (6)
427#define SIU_LEVEL3 (7)
428#define SIU_IRQ4 (8)
429#define SIU_LEVEL4 (9)
430#define SIU_IRQ5 (10)
431#define SIU_LEVEL5 (11)
432#define SIU_IRQ6 (12)
433#define SIU_LEVEL6 (13)
434#define SIU_IRQ7 (14)
435#define SIU_LEVEL7 (15)
436
514ccd4e
VB		 437#define MPC8xx_INT_FEC1 SIU_LEVEL1
438#define MPC8xx_INT_FEC2 SIU_LEVEL3
439
440#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
441#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
442#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
443#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
444#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
445#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
446
1da177e4
LT		 447/* The internal interrupts we can configure as we see fit.
448 * My personal preference is CPM at level 2, which puts it above the
449 * MBX PCI/ISA/IDE interrupts.
450 */
451#ifndef PIT_INTERRUPT
452#define PIT_INTERRUPT SIU_LEVEL0
453#endif
454#ifndef CPM_INTERRUPT
455#define CPM_INTERRUPT SIU_LEVEL2
456#endif
457#ifndef PCMCIA_INTERRUPT
458#define PCMCIA_INTERRUPT SIU_LEVEL6
459#endif
460#ifndef DEC_INTERRUPT
461#define DEC_INTERRUPT SIU_LEVEL7
462#endif
463
464/* Some internal interrupt registers use an 8-bit mask for the interrupt
465 * level instead of a number.
466 */
467#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
468
1da177e4
LT		 469#elif defined(CONFIG_83xx)
470#include <asm/mpc83xx.h>
471
1da177e4
LT		 472#define NR_IRQS (NR_IPIC_INTS)
473
474#elif defined(CONFIG_85xx)
475/* Now include the board configuration specific associations.
476*/
477#include <asm/mpc85xx.h>
478
65145e06 479/* The MPC8548 openpic has 48 internal interrupts and 12 external
1da177e4
LT		 480 * interrupts.
481 *
482 * We are "flattening" the interrupt vectors of the cascaded CPM
483 * so that we can uniquely identify any interrupt source with a
484 * single integer.
485 */
486#define NR_CPM_INTS 64
65145e06 487#define NR_EPIC_INTS 60
1da177e4
LT		 488#ifndef NR_8259_INTS
489#define NR_8259_INTS 0
490#endif
491#define NUM_8259_INTERRUPTS NR_8259_INTS
492
493#ifndef CPM_IRQ_OFFSET
494#define CPM_IRQ_OFFSET 0
495#endif
496
497#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
498
499/* Internal IRQs on MPC85xx OpenPIC */
500
501#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
502#ifdef CONFIG_CPM2
503#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
504#else
505#define MPC85xx_OPENPIC_IRQ_OFFSET 0
506#endif
507#endif
508
509/* Not all of these exist on all MPC85xx implementations */
510#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
511#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
512#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
513#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
514#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
515#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
516#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
517#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
518#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
519#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
520#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
521#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
522#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
523#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
524#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
525#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
5b37b700
KG		 526#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
527#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
528#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
1da177e4
LT		 529#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
530#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
531#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
5b37b700
KG		 532#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
533#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
534#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
1da177e4
LT		 535#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
536#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
537#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
538#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
539#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
540#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
541#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
542
543/* The 12 external interrupt lines */
65145e06
KG		 544#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
545#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
546#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
547#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
548#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
549#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
550#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
551#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
552#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
553#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
554#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
555#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
1da177e4
LT		 556
557/* CPM related interrupts */
558#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
559#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
560#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
561#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
562#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
563#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
564#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
565#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
566#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
567#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
568#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
569#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
570#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
571#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
572#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
573#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
574#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
575#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
576#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
577#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
578#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
579#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
580#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
581#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
582#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
583#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
584#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
585#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
586#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
587#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
588#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
589#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
590#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
591#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
592#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
593#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
594
6b543404
JL		 595#elif defined(CONFIG_PPC_86xx)
596#include <asm/mpc86xx.h>
597
598#define NR_EPIC_INTS 48
599#ifndef NR_8259_INTS
600#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
601#endif
602#define NUM_8259_INTERRUPTS NR_8259_INTS
603
604#ifndef I8259_OFFSET
605#define I8259_OFFSET 0
606#endif
607
608#define NR_IRQS 256
609
610/* Internal IRQs on MPC86xx OpenPIC */
611
612#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
613#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
614#endif
615
616/* The 48 internal sources */
617#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
618#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
619#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
620#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
621#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
622#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
623#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
624#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
625
626/* no 10,11 */
627#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
628#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
629#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
630#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
631#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
632#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
633#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
634#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
635#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
636#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
637#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
638#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
639#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
640/* no 25 */
641#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
642#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
643#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
644/* no 29,30,31 */
645#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
646#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
647#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
648/* no 35,36 */
649#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
650#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
651#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
652#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
653
654/* The 12 external interrupt lines */
655#define MPC86xx_IRQ_EXT_BASE 48
656#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
657 + MPC86xx_OPENPIC_IRQ_OFFSET)
658#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
659 + MPC86xx_OPENPIC_IRQ_OFFSET)
660#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
661 + MPC86xx_OPENPIC_IRQ_OFFSET)
662#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
663 + MPC86xx_OPENPIC_IRQ_OFFSET)
664#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
665 + MPC86xx_OPENPIC_IRQ_OFFSET)
666#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
667 + MPC86xx_OPENPIC_IRQ_OFFSET)
668#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
669 + MPC86xx_OPENPIC_IRQ_OFFSET)
670#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
671 + MPC86xx_OPENPIC_IRQ_OFFSET)
672#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
673 + MPC86xx_OPENPIC_IRQ_OFFSET)
674#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
675 + MPC86xx_OPENPIC_IRQ_OFFSET)
676#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
677 + MPC86xx_OPENPIC_IRQ_OFFSET)
678#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
679 + MPC86xx_OPENPIC_IRQ_OFFSET)
680
1da177e4
LT		 681#else /* CONFIG_40x + CONFIG_8xx */
682/*
683 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
684 * so it is the max of them all
685 */
686#define NR_IRQS 256
1b92313d 687#define __DO_IRQ_CANON 1
1da177e4
LT		 688
689#ifndef CONFIG_8260
690
691#define NUM_8259_INTERRUPTS 16
692
693#else /* CONFIG_8260 */
694
695/* The 8260 has an internal interrupt controller with a maximum of
696 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
697 * Don't be confused by the 8260 documentation where they list an
698 * "interrupt number" and "interrupt vector". We are only interested
699 * in the interrupt vector. There are "reserved" holes where the
700 * vector number increases, but the interrupt number in the table does not.
701 * (Document errata updates have fixed this...make sure you have up to
702 * date processor documentation -- Dan).
703 */
704
705#ifndef CPM_IRQ_OFFSET
706#define CPM_IRQ_OFFSET 0
707#endif
708
709#define NR_CPM_INTS 64
710
711#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
712#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
713#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
714#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
715#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
716#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
717#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
718#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
719#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
720#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
721#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
8e8fff09 722#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
1da177e4
LT		 723#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
724#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
725#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
726#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
727#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
728#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
7f7fda04 729#define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
1da177e4
LT		 730#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
731#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
732#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
733#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
734#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
735#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
736#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
737#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
738#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
739#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
740#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
741#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
742#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
743#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
744#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
745#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
746#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
747#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
748#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
749#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
750#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
751#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
752#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
753#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
754#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
755#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
756#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
757#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
758#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
759#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
760#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
761#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
762
763#endif /* CONFIG_8260 */
764
0ebfff14 765#endif /* Whatever way too big #ifdef */
1b92313d
PM		 766
767#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
768/* pedantic: these are long because they are used with set_bit --RR */
769extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
1b92313d 770
1da177e4 771/*
1b92313d
PM		 772 * Because many systems have two overlapping names spaces for
773 * interrupts (ISA and XICS for example), and the ISA interrupts
774 * have historically not been easy to renumber, we allow ISA
775 * interrupts to take values 0 - 15, and shift up the remaining
776 * interrupts by 0x10.
1da177e4 777 */
1b92313d
PM		 778#define NUM_ISA_INTERRUPTS 0x10
779extern int __irq_offset_value;
780
781static inline int irq_offset_up(int irq)
782{
783 return(irq + __irq_offset_value);
784}
785
786static inline int irq_offset_down(int irq)
787{
788 return(irq - __irq_offset_value);
789}
790
791static inline int irq_offset_value(void)
792{
793 return __irq_offset_value;
794}
795
796#ifdef __DO_IRQ_CANON
797extern int ppc_do_canonicalize_irqs;
798#else
799#define ppc_do_canonicalize_irqs 0
800#endif
801
1da177e4
LT		 802static __inline__ int irq_canonicalize(int irq)
803{
1b92313d
PM		 804 if (ppc_do_canonicalize_irqs && irq == 2)
805 irq = 9;
1da177e4
LT		 806 return irq;
807}
0ebfff14 808#endif /* CONFIG_PPC_MERGE */
1da177e4 809
1b92313d 810extern int distribute_irqs;
1da177e4 811
1b92313d
PM		 812struct irqaction;
813struct pt_regs;
814
c6622f63
PM		 815#define __ARCH_HAS_DO_SOFTIRQ
816
817extern void __do_softirq(void);
818
1b92313d
PM		 819#ifdef CONFIG_IRQSTACKS
820/*
821 * Per-cpu stacks for handling hard and soft interrupts.
822 */
823extern struct thread_info *hardirq_ctx[NR_CPUS];
824extern struct thread_info *softirq_ctx[NR_CPUS];
825
826extern void irq_ctx_init(void);
827extern void call_do_softirq(struct thread_info *tp);
7d12e780 828extern int call_handle_irq(int irq, void *p1,
b9e5b4e6 829 struct thread_info *tp, void *func);
1b92313d
PM		 830#else
831#define irq_ctx_init()
832
833#endif /* CONFIG_IRQSTACKS */
1da177e4 834
f2783c15
PM		 835extern void do_IRQ(struct pt_regs *regs);
836
1da177e4
LT		 837#endif /* _ASM_IRQ_H */
838#endif /* __KERNEL__ */
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