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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Defines of the Malta board specific address-MAP, registers, etc. | |
19 | */ | |
20 | #ifndef __ASM_MIPS_BOARDS_MALTA_H | |
21 | #define __ASM_MIPS_BOARDS_MALTA_H | |
22 | ||
23 | #include <asm/addrspace.h> | |
24 | #include <asm/io.h> | |
25 | #include <asm/mips-boards/msc01_pci.h> | |
26 | #include <asm/gt64120.h> | |
27 | ||
28 | /* | |
29 | * Malta I/O ports base address for the Galileo GT64120 and Algorithmics | |
30 | * Bonito system controllers. | |
31 | */ | |
32 | #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) | |
33 | #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) | |
34 | #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) | |
35 | ||
36 | static inline unsigned long get_gt_port_base(unsigned long reg) | |
37 | { | |
38 | unsigned long addr; | |
39 | addr = GT_READ(reg); | |
40 | return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); | |
41 | } | |
42 | ||
43 | static inline unsigned long get_msc_port_base(unsigned long reg) | |
44 | { | |
45 | unsigned long addr; | |
46 | MSC_READ(reg, addr); | |
47 | return (unsigned long) ioremap(addr, 0x10000); | |
48 | } | |
49 | ||
50 | /* | |
51 | * Malta RTC-device indirect register access. | |
52 | */ | |
53 | #define MALTA_RTC_ADR_REG 0x70 | |
54 | #define MALTA_RTC_DAT_REG 0x71 | |
55 | ||
56 | /* | |
57 | * Malta SMSC FDC37M817 Super I/O Controller register. | |
58 | */ | |
59 | #define SMSC_CONFIG_REG 0x3f0 | |
60 | #define SMSC_DATA_REG 0x3f1 | |
61 | ||
62 | #define SMSC_CONFIG_DEVNUM 0x7 | |
63 | #define SMSC_CONFIG_ACTIVATE 0x30 | |
64 | #define SMSC_CONFIG_ENTER 0x55 | |
65 | #define SMSC_CONFIG_EXIT 0xaa | |
66 | ||
67 | #define SMSC_CONFIG_DEVNUM_FLOPPY 0 | |
68 | ||
69 | #define SMSC_CONFIG_ACTIVATE_ENABLE 1 | |
70 | ||
71 | #define SMSC_WRITE(x,a) outb(x,a) | |
72 | ||
73 | #define MALTA_JMPRS_REG 0x1f000210 | |
74 | ||
75 | #endif /* __ASM_MIPS_BOARDS_MALTA_H */ |