[net-next-2.6.git] / include / asm-ia64 / sn / tiocp.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
 */
#ifndef _ASM_IA64_SN_PCI_TIOCP_H
#define _ASM_IA64_SN_PCI_TIOCP_H

#define TIOCP_HOST_INTR_ADDR            0x003FFFFFFFFFFFFFUL
#define TIOCP_PCI64_CMDTYPE_MEM         (0x1ull << 60)


/*****************************************************************************
 *********************** TIOCP MMR structure mapping ***************************
 *****************************************************************************/

struct tiocp{

    /* 0x000000-0x00FFFF -- Local Registers */

    /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
    u64		cp_id;				/* 0x000000 */
    u64		cp_stat;			/* 0x000008 */
    u64		cp_err_upper;			/* 0x000010 */
    u64		cp_err_lower;			/* 0x000018 */
    #define cp_err cp_err_lower
    u64		cp_control;			/* 0x000020 */
    u64		cp_req_timeout;			/* 0x000028 */
    u64		cp_intr_upper;			/* 0x000030 */
    u64		cp_intr_lower;			/* 0x000038 */
    #define cp_intr cp_intr_lower
    u64		cp_err_cmdword;			/* 0x000040 */
    u64		_pad_000048;			/* 0x000048 */
    u64		cp_tflush;			/* 0x000050 */

    /* 0x000058-0x00007F -- Bridge-specific Configuration */
    u64		cp_aux_err;			/* 0x000058 */
    u64		cp_resp_upper;			/* 0x000060 */
    u64		cp_resp_lower;			/* 0x000068 */
    #define cp_resp cp_resp_lower
    u64		cp_tst_pin_ctrl;		/* 0x000070 */
    u64		cp_addr_lkerr;			/* 0x000078 */

    /* 0x000080-0x00008F -- PMU & MAP */
    u64		cp_dir_map;			/* 0x000080 */
    u64		_pad_000088;			/* 0x000088 */

    /* 0x000090-0x00009F -- SSRAM */
    u64		cp_map_fault;			/* 0x000090 */
    u64		_pad_000098;			/* 0x000098 */

    /* 0x0000A0-0x0000AF -- Arbitration */
    u64		cp_arb;				/* 0x0000A0 */
    u64		_pad_0000A8;			/* 0x0000A8 */

    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
    u64		cp_ate_parity_err;		/* 0x0000B0 */
    u64		_pad_0000B8;			/* 0x0000B8 */

    /* 0x0000C0-0x0000FF -- PCI/GIO */
    u64		cp_bus_timeout;			/* 0x0000C0 */
    u64		cp_pci_cfg;			/* 0x0000C8 */
    u64		cp_pci_err_upper;		/* 0x0000D0 */
    u64		cp_pci_err_lower;		/* 0x0000D8 */
    #define cp_pci_err cp_pci_err_lower
    u64		_pad_0000E0[4];			/* 0x0000{E0..F8} */

    /* 0x000100-0x0001FF -- Interrupt */
    u64		cp_int_status;			/* 0x000100 */
    u64		cp_int_enable;			/* 0x000108 */
    u64		cp_int_rst_stat;		/* 0x000110 */
    u64		cp_int_mode;			/* 0x000118 */
    u64		cp_int_device;			/* 0x000120 */
    u64		cp_int_host_err;		/* 0x000128 */
    u64		cp_int_addr[8];			/* 0x0001{30,,,68} */
    u64		cp_err_int_view;		/* 0x000170 */
    u64		cp_mult_int;			/* 0x000178 */
    u64		cp_force_always[8];		/* 0x0001{80,,,B8} */
    u64		cp_force_pin[8];		/* 0x0001{C0,,,F8} */

    /* 0x000200-0x000298 -- Device */
    u64		cp_device[4];			/* 0x0002{00,,,18} */
    u64		_pad_000220[4];			/* 0x0002{20,,,38} */
    u64		cp_wr_req_buf[4];		/* 0x0002{40,,,58} */
    u64		_pad_000260[4];			/* 0x0002{60,,,78} */
    u64		cp_rrb_map[2];			/* 0x0002{80,,,88} */
    #define cp_even_resp cp_rrb_map[0]			/* 0x000280 */
    #define cp_odd_resp  cp_rrb_map[1]			/* 0x000288 */
    u64		cp_resp_status;			/* 0x000290 */
    u64		cp_resp_clear;			/* 0x000298 */

    u64		_pad_0002A0[12];		/* 0x0002{A0..F8} */

    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
    struct {
	u64	upper;				/* 0x0003{00,,,F0} */
	u64	lower;				/* 0x0003{08,,,F8} */
    } cp_buf_addr_match[16];

    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
    struct {
	u64	flush_w_touch;			/* 0x000{400,,,5C0} */
	u64	flush_wo_touch;			/* 0x000{408,,,5C8} */
	u64	inflight;			/* 0x000{410,,,5D0} */
	u64	prefetch;			/* 0x000{418,,,5D8} */
	u64	total_pci_retry;		/* 0x000{420,,,5E0} */
	u64	max_pci_retry;			/* 0x000{428,,,5E8} */
	u64	max_latency;			/* 0x000{430,,,5F0} */
	u64	clear_all;			/* 0x000{438,,,5F8} */
    } cp_buf_count[8];


    /* 0x000600-0x0009FF -- PCI/X registers */
    u64		cp_pcix_bus_err_addr;		/* 0x000600 */
    u64		cp_pcix_bus_err_attr;		/* 0x000608 */
    u64		cp_pcix_bus_err_data;		/* 0x000610 */
    u64		cp_pcix_pio_split_addr;		/* 0x000618 */
    u64		cp_pcix_pio_split_attr;		/* 0x000620 */
    u64		cp_pcix_dma_req_err_attr;	/* 0x000628 */
    u64		cp_pcix_dma_req_err_addr;	/* 0x000630 */
    u64		cp_pcix_timeout;		/* 0x000638 */

    u64		_pad_000640[24];		/* 0x000{640,,,6F8} */

    /* 0x000700-0x000737 -- Debug Registers */
    u64		cp_ct_debug_ctl;		/* 0x000700 */
    u64		cp_br_debug_ctl;		/* 0x000708 */
    u64		cp_mux3_debug_ctl;		/* 0x000710 */
    u64		cp_mux4_debug_ctl;		/* 0x000718 */
    u64		cp_mux5_debug_ctl;		/* 0x000720 */
    u64		cp_mux6_debug_ctl;		/* 0x000728 */
    u64		cp_mux7_debug_ctl;		/* 0x000730 */

    u64		_pad_000738[89];		/* 0x000{738,,,9F8} */

    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
    struct {
	u64	cp_buf_addr;			/* 0x000{A00,,,AF0} */
	u64	cp_buf_attr;			/* 0X000{A08,,,AF8} */
    } cp_pcix_read_buf_64[16];

    struct {
	u64	cp_buf_addr;			/* 0x000{B00,,,BE0} */
	u64	cp_buf_attr;			/* 0x000{B08,,,BE8} */
	u64	cp_buf_valid;			/* 0x000{B10,,,BF0} */
	u64	__pad1;				/* 0x000{B18,,,BF8} */
    } cp_pcix_write_buf_64[8];

    /* End of Local Registers -- Start of Address Map space */

    char	_pad_000c00[0x010000 - 0x000c00];

    /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
    u64		cp_int_ate_ram[1024];		/* 0x010000-0x011FF8 */

    char	_pad_012000[0x14000 - 0x012000];

    /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
    u64		cp_int_ate_ram_mp[1024];	/* 0x014000-0x015FF8 */

    char	_pad_016000[0x18000 - 0x016000];

    /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
    u64		cp_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
    u64		cp_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
    u64		cp_wr_req_parity[256];		/* 0x19000 - 0x197F8 */

    char	_pad_019800[0x1C000 - 0x019800];

    /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
    u64		cp_rd_resp_lower[512];		/* 0x1C000 - 0x1CFF8 */
    u64		cp_rd_resp_upper[512];		/* 0x1D000 - 0x1DFF8 */
    u64		cp_rd_resp_parity[512];		/* 0x1E000 - 0x1EFF8 */

    char	_pad_01F000[0x20000 - 0x01F000];

    /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used)  */
    char	_pad_020000[0x021000 - 0x20000];

    /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
    union {
	u8	c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
	u16	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
	u32	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
	u64	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
	union {
	    u8	c[0x100 / 1];
	    u16	s[0x100 / 2];
	    u32	l[0x100 / 4];
	    u64	d[0x100 / 8];
	} f[8];
    } cp_type0_cfg_dev[7];				/* 0x02{1000,,,7FFF} */

    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
    union {
	u8	c[0x1000 / 1];			/* 0x028000-0x029000 */
	u16	s[0x1000 / 2];			/* 0x028000-0x029000 */
	u32	l[0x1000 / 4];			/* 0x028000-0x029000 */
	u64	d[0x1000 / 8];			/* 0x028000-0x029000 */
	union {
	    u8	c[0x100 / 1];
	    u16	s[0x100 / 2];
	    u32	l[0x100 / 4];
	    u64	d[0x100 / 8];
	} f[8];
    } cp_type1_cfg;					/* 0x028000-0x029000 */

    char		_pad_029000[0x030000-0x029000];

    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
    union {
	u8	c[8 / 1];
	u16	s[8 / 2];
	u32	l[8 / 4];
	u64	d[8 / 8];
    } cp_pci_iack;					/* 0x030000-0x030007 */

    char		_pad_030007[0x040000-0x030008];

    /* 0x040000-0x040007 -- PCIX Special Cycle */
    union {
	u8	c[8 / 1];
	u16	s[8 / 2];
	u32	l[8 / 4];
	u64	d[8 / 8];
    } cp_pcix_cycle;					/* 0x040000-0x040007 */

    char		_pad_040007[0x200000-0x040008];

    /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
    union {
	u8	c[0x100000 / 1];
	u16	s[0x100000 / 2];
	u32	l[0x100000 / 4];
	u64	d[0x100000 / 8];
    } cp_devio_raw[6];					/* 0x200000-0x7FFFFF */

    #define cp_devio(n)  cp_devio_raw[((n)<2)?(n*2):(n+2)]

    char		_pad_800000[0xA00000-0x800000];

    /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush  */
    union {
	u8	c[0x100000 / 1];
	u16	s[0x100000 / 2];
	u32	l[0x100000 / 4];
	u64	d[0x100000 / 8];
    } cp_devio_raw_flush[6];				/* 0xA00000-0xBFFFFF */

    #define cp_devio_flush(n)  cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]

};

#endif 	/* _ASM_IA64_SN_PCI_TIOCP_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
	7	*/
	8	#ifndef _ASM_IA64_SN_PCI_TIOCP_H
	9	#define _ASM_IA64_SN_PCI_TIOCP_H
	10
	11	#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
	12	#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
	13
	14
	15	/*****************************************************************************
	16	********************* TIOCP MMR structure mapping *************************
	17	*****************************************************************************/
	18
	19	struct tiocp{
	20
	21	/* 0x000000-0x00FFFF -- Local Registers */
	22
	23	/* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
53493dcf PB	24	u64 cp_id; /* 0x000000 */
	25	u64 cp_stat; /* 0x000008 */
	26	u64 cp_err_upper; /* 0x000010 */
	27	u64 cp_err_lower; /* 0x000018 */
1da177e4	28	#define cp_err cp_err_lower
53493dcf PB	29	u64 cp_control; /* 0x000020 */
	30	u64 cp_req_timeout; /* 0x000028 */
	31	u64 cp_intr_upper; /* 0x000030 */
	32	u64 cp_intr_lower; /* 0x000038 */
1da177e4	33	#define cp_intr cp_intr_lower
53493dcf PB	34	u64 cp_err_cmdword; /* 0x000040 */
	35	u64 _pad_000048; /* 0x000048 */
	36	u64 cp_tflush; /* 0x000050 */
1da177e4 LT	37
1da177e4 LT	38	/* 0x000058-0x00007F -- Bridge-specific Configuration */
53493dcf PB	39	u64 cp_aux_err; /* 0x000058 */
	40	u64 cp_resp_upper; /* 0x000060 */
	41	u64 cp_resp_lower; /* 0x000068 */
1da177e4	42	#define cp_resp cp_resp_lower
53493dcf PB	43	u64 cp_tst_pin_ctrl; /* 0x000070 */
53493dcf PB	44	u64 cp_addr_lkerr; /* 0x000078 */
1da177e4 LT	45
1da177e4 LT	46	/* 0x000080-0x00008F -- PMU & MAP */
53493dcf PB	47	u64 cp_dir_map; /* 0x000080 */
53493dcf PB	48	u64 _pad_000088; /* 0x000088 */
1da177e4 LT	49
1da177e4 LT	50	/* 0x000090-0x00009F -- SSRAM */
53493dcf PB	51	u64 cp_map_fault; /* 0x000090 */
53493dcf PB	52	u64 _pad_000098; /* 0x000098 */
1da177e4 LT	53
1da177e4 LT	54	/* 0x0000A0-0x0000AF -- Arbitration */
53493dcf PB	55	u64 cp_arb; /* 0x0000A0 */
53493dcf PB	56	u64 _pad_0000A8; /* 0x0000A8 */
1da177e4 LT	57
1da177e4 LT	58	/* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
53493dcf PB	59	u64 cp_ate_parity_err; /* 0x0000B0 */
53493dcf PB	60	u64 _pad_0000B8; /* 0x0000B8 */
1da177e4 LT	61
1da177e4 LT	62	/* 0x0000C0-0x0000FF -- PCI/GIO */
53493dcf PB	63	u64 cp_bus_timeout; /* 0x0000C0 */
	64	u64 cp_pci_cfg; /* 0x0000C8 */
	65	u64 cp_pci_err_upper; /* 0x0000D0 */
	66	u64 cp_pci_err_lower; /* 0x0000D8 */
1da177e4	67	#define cp_pci_err cp_pci_err_lower
53493dcf	68	u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
1da177e4 LT	69
1da177e4 LT	70	/* 0x000100-0x0001FF -- Interrupt */
53493dcf PB	71	u64 cp_int_status; /* 0x000100 */
	72	u64 cp_int_enable; /* 0x000108 */
	73	u64 cp_int_rst_stat; /* 0x000110 */
	74	u64 cp_int_mode; /* 0x000118 */
	75	u64 cp_int_device; /* 0x000120 */
	76	u64 cp_int_host_err; /* 0x000128 */
	77	u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
	78	u64 cp_err_int_view; /* 0x000170 */
	79	u64 cp_mult_int; /* 0x000178 */
	80	u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
	81	u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
1da177e4 LT	82
1da177e4 LT	83	/* 0x000200-0x000298 -- Device */
53493dcf PB	84	u64 cp_device[4]; /* 0x0002{00,,,18} */
	85	u64 _pad_000220[4]; /* 0x0002{20,,,38} */
	86	u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
	87	u64 _pad_000260[4]; /* 0x0002{60,,,78} */
	88	u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
1da177e4 LT	89	#define cp_even_resp cp_rrb_map[0] /* 0x000280 */
1da177e4 LT	90	#define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
53493dcf PB	91	u64 cp_resp_status; /* 0x000290 */
53493dcf PB	92	u64 cp_resp_clear; /* 0x000298 */
1da177e4	93
53493dcf	94	u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
1da177e4 LT	95
	96	/* 0x000300-0x0003F8 -- Buffer Address Match Registers */
	97	struct {
53493dcf PB	98	u64 upper; /* 0x0003{00,,,F0} */
53493dcf PB	99	u64 lower; /* 0x0003{08,,,F8} */
1da177e4 LT	100	} cp_buf_addr_match[16];
	101
	102	/* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
	103	struct {
53493dcf PB	104	u64 flush_w_touch; /* 0x000{400,,,5C0} */
	105	u64 flush_wo_touch; /* 0x000{408,,,5C8} */
	106	u64 inflight; /* 0x000{410,,,5D0} */
	107	u64 prefetch; /* 0x000{418,,,5D8} */
	108	u64 total_pci_retry; /* 0x000{420,,,5E0} */
	109	u64 max_pci_retry; /* 0x000{428,,,5E8} */
	110	u64 max_latency; /* 0x000{430,,,5F0} */
	111	u64 clear_all; /* 0x000{438,,,5F8} */
1da177e4 LT	112	} cp_buf_count[8];
1da177e4 LT	113
c13cf371	114
1da177e4	115	/* 0x000600-0x0009FF -- PCI/X registers */
53493dcf PB	116	u64 cp_pcix_bus_err_addr; /* 0x000600 */
	117	u64 cp_pcix_bus_err_attr; /* 0x000608 */
	118	u64 cp_pcix_bus_err_data; /* 0x000610 */
	119	u64 cp_pcix_pio_split_addr; /* 0x000618 */
	120	u64 cp_pcix_pio_split_attr; /* 0x000620 */
	121	u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
	122	u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
	123	u64 cp_pcix_timeout; /* 0x000638 */
1da177e4	124
53493dcf	125	u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
1da177e4 LT	126
1da177e4 LT	127	/* 0x000700-0x000737 -- Debug Registers */
53493dcf PB	128	u64 cp_ct_debug_ctl; /* 0x000700 */
	129	u64 cp_br_debug_ctl; /* 0x000708 */
	130	u64 cp_mux3_debug_ctl; /* 0x000710 */
	131	u64 cp_mux4_debug_ctl; /* 0x000718 */
	132	u64 cp_mux5_debug_ctl; /* 0x000720 */
	133	u64 cp_mux6_debug_ctl; /* 0x000728 */
	134	u64 cp_mux7_debug_ctl; /* 0x000730 */
1da177e4	135
53493dcf	136	u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
1da177e4 LT	137
	138	/* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
	139	struct {
53493dcf PB	140	u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
53493dcf PB	141	u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
1da177e4 LT	142	} cp_pcix_read_buf_64[16];
	143
	144	struct {
53493dcf PB	145	u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
	146	u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
	147	u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
	148	u64 __pad1; /* 0x000{B18,,,BF8} */
1da177e4 LT	149	} cp_pcix_write_buf_64[8];
	150
	151	/* End of Local Registers -- Start of Address Map space */
	152
53493dcf	153	char _pad_000c00[0x010000 - 0x000c00];
1da177e4 LT	154
1da177e4 LT	155	/* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
53493dcf	156	u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
1da177e4	157
53493dcf	158	char _pad_012000[0x14000 - 0x012000];
1da177e4 LT	159
1da177e4 LT	160	/* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
53493dcf	161	u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
1da177e4	162
53493dcf	163	char _pad_016000[0x18000 - 0x016000];
1da177e4 LT	164
1da177e4 LT	165	/* 0x18000-0x197F8 -- TIOCP Write Request Ram */
53493dcf PB	166	u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
	167	u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
	168	u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
1da177e4	169
53493dcf	170	char _pad_019800[0x1C000 - 0x019800];
1da177e4 LT	171
1da177e4 LT	172	/* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
53493dcf PB	173	u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
	174	u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
	175	u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
1da177e4	176
53493dcf	177	char _pad_01F000[0x20000 - 0x01F000];
1da177e4 LT	178
1da177e4 LT	179	/* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
53493dcf	180	char _pad_020000[0x021000 - 0x20000];
1da177e4 LT	181
	182	/* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
	183	union {
53493dcf PB	184	u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
	185	u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
	186	u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
	187	u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
1da177e4	188	union {
53493dcf PB	189	u8 c[0x100 / 1];
	190	u16 s[0x100 / 2];
	191	u32 l[0x100 / 4];
	192	u64 d[0x100 / 8];
1da177e4 LT	193	} f[8];
	194	} cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
	195
	196	/* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
	197	union {
53493dcf PB	198	u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
	199	u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
	200	u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
	201	u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
1da177e4	202	union {
53493dcf PB	203	u8 c[0x100 / 1];
	204	u16 s[0x100 / 2];
	205	u32 l[0x100 / 4];
	206	u64 d[0x100 / 8];
1da177e4 LT	207	} f[8];
	208	} cp_type1_cfg; /* 0x028000-0x029000 */
	209
	210	char _pad_029000[0x030000-0x029000];
	211
	212	/* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
	213	union {
53493dcf PB	214	u8 c[8 / 1];
	215	u16 s[8 / 2];
	216	u32 l[8 / 4];
	217	u64 d[8 / 8];
1da177e4 LT	218	} cp_pci_iack; /* 0x030000-0x030007 */
	219
	220	char _pad_030007[0x040000-0x030008];
	221
	222	/* 0x040000-0x040007 -- PCIX Special Cycle */
	223	union {
53493dcf PB	224	u8 c[8 / 1];
	225	u16 s[8 / 2];
	226	u32 l[8 / 4];
	227	u64 d[8 / 8];
1da177e4 LT	228	} cp_pcix_cycle; /* 0x040000-0x040007 */
	229
	230	char _pad_040007[0x200000-0x040008];
	231
	232	/* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
	233	union {
53493dcf PB	234	u8 c[0x100000 / 1];
	235	u16 s[0x100000 / 2];
	236	u32 l[0x100000 / 4];
	237	u64 d[0x100000 / 8];
1da177e4 LT	238	} cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
	239
	240	#define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
	241
	242	char _pad_800000[0xA00000-0x800000];
	243
	244	/* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
	245	union {
53493dcf PB	246	u8 c[0x100000 / 1];
	247	u16 s[0x100000 / 2];
	248	u32 l[0x100000 / 4];
	249	u64 d[0x100000 / 8];
1da177e4 LT	250	} cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
	251
	252	#define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
	253
	254	};
	255
	256	#endif /* _ASM_IA64_SN_PCI_TIOCP_H */