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[PATCH] x86: make IOPL explicit
[net-next-2.6.git] / include / asm-i386 / processor.h
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1da177e4
LT		 1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
20#include <linux/config.h>
21#include <linux/threads.h>
22#include <asm/percpu.h>
23
24/* flag for disabling the tsc */
25extern int tsc_disable;
26
27struct desc_struct {
28 unsigned long a,b;
29};
30
31#define desc_empty(desc) \
12aaa085 32 (!((desc)->a | (desc)->b))
1da177e4
LT		 33
34#define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36/*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41
42/*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
47
48struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 int fdiv_bug;
65 int f00f_bug;
66 int coma_bug;
67 unsigned long loops_per_jiffy;
68 unsigned char x86_num_cores;
69} __attribute__((__aligned__(SMP_CACHE_BYTES)));
70
71#define X86_VENDOR_INTEL 0
72#define X86_VENDOR_CYRIX 1
73#define X86_VENDOR_AMD 2
74#define X86_VENDOR_UMC 3
75#define X86_VENDOR_NEXGEN 4
76#define X86_VENDOR_CENTAUR 5
77#define X86_VENDOR_RISE 6
78#define X86_VENDOR_TRANSMETA 7
79#define X86_VENDOR_NSC 8
80#define X86_VENDOR_NUM 9
81#define X86_VENDOR_UNKNOWN 0xff
82
83/*
84 * capabilities of CPUs
85 */
86
87extern struct cpuinfo_x86 boot_cpu_data;
88extern struct cpuinfo_x86 new_cpu_data;
89extern struct tss_struct doublefault_tss;
90DECLARE_PER_CPU(struct tss_struct, init_tss);
91
92#ifdef CONFIG_SMP
93extern struct cpuinfo_x86 cpu_data[];
94#define current_cpu_data cpu_data[smp_processor_id()]
95#else
96#define cpu_data (&boot_cpu_data)
97#define current_cpu_data boot_cpu_data
98#endif
99
100extern int phys_proc_id[NR_CPUS];
3dd9d514 101extern int cpu_core_id[NR_CPUS];
1da177e4
LT		 102extern char ignore_fpu_irq;
103
104extern void identify_cpu(struct cpuinfo_x86 *);
105extern void print_cpu_info(struct cpuinfo_x86 *);
106extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
107
108#ifdef CONFIG_X86_HT
109extern void detect_ht(struct cpuinfo_x86 *c);
110#else
111static inline void detect_ht(struct cpuinfo_x86 *c) {}
112#endif
113
114/*
115 * EFLAGS bits
116 */
117#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
118#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
119#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
120#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
121#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
122#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
123#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
124#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
125#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
126#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
127#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
128#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
129#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
130#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
131#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
132#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
133#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
134
135/*
136 * Generic CPUID function
137 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
138 * resulting in stale register contents being returned.
139 */
140static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
141{
142 __asm__("cpuid"
143 : "=a" (*eax),
144 "=b" (*ebx),
145 "=c" (*ecx),
146 "=d" (*edx)
147 : "0" (op), "c"(0));
148}
149
150/* Some CPUID calls want 'count' to be placed in ecx */
151static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
152 int *edx)
153{
154 __asm__("cpuid"
155 : "=a" (*eax),
156 "=b" (*ebx),
157 "=c" (*ecx),
158 "=d" (*edx)
159 : "0" (op), "c" (count));
160}
161
162/*
163 * CPUID functions returning a single datum
164 */
165static inline unsigned int cpuid_eax(unsigned int op)
166{
167 unsigned int eax;
168
169 __asm__("cpuid"
170 : "=a" (eax)
171 : "0" (op)
172 : "bx", "cx", "dx");
173 return eax;
174}
175static inline unsigned int cpuid_ebx(unsigned int op)
176{
177 unsigned int eax, ebx;
178
179 __asm__("cpuid"
180 : "=a" (eax), "=b" (ebx)
181 : "0" (op)
182 : "cx", "dx" );
183 return ebx;
184}
185static inline unsigned int cpuid_ecx(unsigned int op)
186{
187 unsigned int eax, ecx;
188
189 __asm__("cpuid"
190 : "=a" (eax), "=c" (ecx)
191 : "0" (op)
192 : "bx", "dx" );
193 return ecx;
194}
195static inline unsigned int cpuid_edx(unsigned int op)
196{
197 unsigned int eax, edx;
198
199 __asm__("cpuid"
200 : "=a" (eax), "=d" (edx)
201 : "0" (op)
202 : "bx", "cx");
203 return edx;
204}
205
4bb0d3ec 206#define load_cr3(pgdir) write_cr3(__pa(pgdir))
1da177e4
LT		 207
208/*
209 * Intel CPU features in CR4
210 */
211#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
212#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
213#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
214#define X86_CR4_DE 0x0008 /* enable debugging extensions */
215#define X86_CR4_PSE 0x0010 /* enable page size extensions */
216#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
217#define X86_CR4_MCE 0x0040 /* Machine check enable */
218#define X86_CR4_PGE 0x0080 /* enable global pages */
219#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
220#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
221#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
222
223/*
224 * Save the cr4 feature set we're using (ie
225 * Pentium 4MB enable and PPro Global page
226 * enable), so that any CPU's that boot up
227 * after us can get the correct flags.
228 */
229extern unsigned long mmu_cr4_features;
230
231static inline void set_in_cr4 (unsigned long mask)
232{
4bb0d3ec 233 unsigned cr4;
1da177e4 234 mmu_cr4_features |= mask;
4bb0d3ec
ZA		 235 cr4 = read_cr4();
236 cr4 |= mask;
237 write_cr4(cr4);
1da177e4
LT		 238}
239
240static inline void clear_in_cr4 (unsigned long mask)
241{
4bb0d3ec 242 unsigned cr4;
1da177e4 243 mmu_cr4_features &= ~mask;
4bb0d3ec
ZA		 244 cr4 = read_cr4();
245 cr4 &= ~mask;
246 write_cr4(cr4);
1da177e4
LT		 247}
248
249/*
250 * NSC/Cyrix CPU configuration register indexes
251 */
252
253#define CX86_PCR0 0x20
254#define CX86_GCR 0xb8
255#define CX86_CCR0 0xc0
256#define CX86_CCR1 0xc1
257#define CX86_CCR2 0xc2
258#define CX86_CCR3 0xc3
259#define CX86_CCR4 0xe8
260#define CX86_CCR5 0xe9
261#define CX86_CCR6 0xea
262#define CX86_CCR7 0xeb
263#define CX86_PCR1 0xf0
264#define CX86_DIR0 0xfe
265#define CX86_DIR1 0xff
266#define CX86_ARR_BASE 0xc4
267#define CX86_RCR_BASE 0xdc
268
269/*
270 * NSC/Cyrix CPU indexed register access macros
271 */
272
273#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
274
275#define setCx86(reg, data) do { \
276 outb((reg), 0x22); \
277 outb((data), 0x23); \
278} while (0)
279
245067d1
ZA		 280static inline void serialize_cpu(void)
281{
282 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
283}
284
1da177e4
LT		 285static inline void __monitor(const void *eax, unsigned long ecx,
286 unsigned long edx)
287{
288 /* "monitor %eax,%ecx,%edx;" */
289 asm volatile(
290 ".byte 0x0f,0x01,0xc8;"
291 : :"a" (eax), "c" (ecx), "d"(edx));
292}
293
294static inline void __mwait(unsigned long eax, unsigned long ecx)
295{
296 /* "mwait %eax,%ecx;" */
297 asm volatile(
298 ".byte 0x0f,0x01,0xc9;"
299 : :"a" (eax), "c" (ecx));
300}
301
302/* from system description table in BIOS. Mostly for MCA use, but
303others may find it useful. */
304extern unsigned int machine_id;
305extern unsigned int machine_submodel_id;
306extern unsigned int BIOS_revision;
307extern unsigned int mca_pentium_flag;
308
309/* Boot loader type from the setup header */
310extern int bootloader_type;
311
312/*
313 * User space process size: 3GB (default).
314 */
315#define TASK_SIZE (PAGE_OFFSET)
316
317/* This decides where the kernel will search for a free chunk of vm
318 * space during mmap's.
319 */
320#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
321
322#define HAVE_ARCH_PICK_MMAP_LAYOUT
323
324/*
325 * Size of io_bitmap.
326 */
327#define IO_BITMAP_BITS 65536
328#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
329#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
330#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
331#define INVALID_IO_BITMAP_OFFSET 0x8000
332#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
333
334struct i387_fsave_struct {
335 long cwd;
336 long swd;
337 long twd;
338 long fip;
339 long fcs;
340 long foo;
341 long fos;
342 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
343 long status; /* software status information */
344};
345
346struct i387_fxsave_struct {
347 unsigned short cwd;
348 unsigned short swd;
349 unsigned short twd;
350 unsigned short fop;
351 long fip;
352 long fcs;
353 long foo;
354 long fos;
355 long mxcsr;
356 long mxcsr_mask;
357 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
358 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
359 long padding[56];
360} __attribute__ ((aligned (16)));
361
362struct i387_soft_struct {
363 long cwd;
364 long swd;
365 long twd;
366 long fip;
367 long fcs;
368 long foo;
369 long fos;
370 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
371 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
372 struct info *info;
373 unsigned long entry_eip;
374};
375
376union i387_union {
377 struct i387_fsave_struct fsave;
378 struct i387_fxsave_struct fxsave;
379 struct i387_soft_struct soft;
380};
381
382typedef struct {
383 unsigned long seg;
384} mm_segment_t;
385
386struct thread_struct;
387
388struct tss_struct {
389 unsigned short back_link,__blh;
390 unsigned long esp0;
391 unsigned short ss0,__ss0h;
392 unsigned long esp1;
393 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
394 unsigned long esp2;
395 unsigned short ss2,__ss2h;
396 unsigned long __cr3;
397 unsigned long eip;
398 unsigned long eflags;
399 unsigned long eax,ecx,edx,ebx;
400 unsigned long esp;
401 unsigned long ebp;
402 unsigned long esi;
403 unsigned long edi;
404 unsigned short es, __esh;
405 unsigned short cs, __csh;
406 unsigned short ss, __ssh;
407 unsigned short ds, __dsh;
408 unsigned short fs, __fsh;
409 unsigned short gs, __gsh;
410 unsigned short ldt, __ldth;
411 unsigned short trace, io_bitmap_base;
412 /*
413 * The extra 1 is there because the CPU will access an
414 * additional byte beyond the end of the IO permission
415 * bitmap. The extra byte must be all 1 bits, and must
416 * be within the limit.
417 */
418 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
419 /*
420 * Cache the current maximum and the last task that used the bitmap:
421 */
422 unsigned long io_bitmap_max;
423 struct thread_struct *io_bitmap_owner;
424 /*
425 * pads the TSS to be cacheline-aligned (size is 0x100)
426 */
427 unsigned long __cacheline_filler[35];
428 /*
429 * .. and then another 0x100 bytes for emergency kernel stack
430 */
431 unsigned long stack[64];
432} __attribute__((packed));
433
434#define ARCH_MIN_TASKALIGN 16
435
436struct thread_struct {
437/* cached TLS descriptors. */
438 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
439 unsigned long esp0;
440 unsigned long sysenter_cs;
441 unsigned long eip;
442 unsigned long esp;
443 unsigned long fs;
444 unsigned long gs;
445/* Hardware debugging registers */
446 unsigned long debugreg[8]; /* %%db0-7 debug registers */
447/* fault info */
448 unsigned long cr2, trap_no, error_code;
449/* floating point info */
450 union i387_union i387;
451/* virtual 86 mode info */
452 struct vm86_struct __user * vm86_info;
453 unsigned long screen_bitmap;
454 unsigned long v86flags, v86mask, saved_esp0;
455 unsigned int saved_fs, saved_gs;
456/* IO permissions */
457 unsigned long *io_bitmap_ptr;
a5201129 458 unsigned long iopl;
1da177e4
LT		 459/* max allowed port in the bitmap, in bytes: */
460 unsigned long io_bitmap_max;
461};
462
463#define INIT_THREAD { \
464 .vm86_info = NULL, \
465 .sysenter_cs = __KERNEL_CS, \
466 .io_bitmap_ptr = NULL, \
467}
468
469/*
470 * Note that the .io_bitmap member must be extra-big. This is because
471 * the CPU will access an additional byte beyond the end of the IO
472 * permission bitmap. The extra byte must be all 1 bits, and must
473 * be within the limit.
474 */
475#define INIT_TSS { \
476 .esp0 = sizeof(init_stack) + (long)&init_stack, \
477 .ss0 = __KERNEL_DS, \
478 .ss1 = __KERNEL_CS, \
1da177e4
LT		 479 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
480 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
481}
482
483static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
484{
485 tss->esp0 = thread->esp0;
486 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
487 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
488 tss->ss1 = thread->sysenter_cs;
489 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
490 }
491}
492
493#define start_thread(regs, new_eip, new_esp) do { \
494 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
495 set_fs(USER_DS); \
496 regs->xds = __USER_DS; \
497 regs->xes = __USER_DS; \
498 regs->xss = __USER_DS; \
499 regs->xcs = __USER_CS; \
500 regs->eip = new_eip; \
501 regs->esp = new_esp; \
502} while (0)
503
ecd02ddd 504/*
f5012310 505 * These special macros can be used to get or set a debugging register
ecd02ddd 506 */
f5012310
VH		 507#define get_debugreg(var, register) \
508 __asm__("movl %%db" #register ", %0" \
509 :"=r" (var))
510#define set_debugreg(value, register) \
511 __asm__("movl %0,%%db" #register \
512 : /* no output */ \
513 :"r" (value))
514
a5201129
ZA		 515/*
516 * Set IOPL bits in EFLAGS from given mask
517 */
518static inline void set_iopl_mask(unsigned mask)
519{
520 unsigned int reg;
521 __asm__ __volatile__ ("pushfl;"
522 "popl %0;"
523 "andl %1, %0;"
524 "orl %2, %0;"
525 "pushl %0;"
526 "popfl"
527 : "=&r" (reg)
528 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
529}
ecd02ddd 530
1da177e4
LT		 531/* Forward declaration, a strange C thing */
532struct task_struct;
533struct mm_struct;
534
535/* Free all resources held by a thread. */
536extern void release_thread(struct task_struct *);
537
538/* Prepare to copy thread state - unlazy all lazy status */
539extern void prepare_to_copy(struct task_struct *tsk);
540
541/*
542 * create a kernel thread without removing it from tasklists
543 */
544extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
545
546extern unsigned long thread_saved_pc(struct task_struct *tsk);
547void show_trace(struct task_struct *task, unsigned long *stack);
548
549unsigned long get_wchan(struct task_struct *p);
550
551#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
552#define KSTK_TOP(info) \
553({ \
554 unsigned long *__ptr = (unsigned long *)(info); \
555 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
556})
557
558#define task_pt_regs(task) \
559({ \
560 struct pt_regs *__regs__; \
561 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
562 __regs__ - 1; \
563})
564
565#define KSTK_EIP(task) (task_pt_regs(task)->eip)
566#define KSTK_ESP(task) (task_pt_regs(task)->esp)
567
568
569struct microcode_header {
570 unsigned int hdrver;
571 unsigned int rev;
572 unsigned int date;
573 unsigned int sig;
574 unsigned int cksum;
575 unsigned int ldrver;
576 unsigned int pf;
577 unsigned int datasize;
578 unsigned int totalsize;
579 unsigned int reserved[3];
580};
581
582struct microcode {
583 struct microcode_header hdr;
584 unsigned int bits[0];
585};
586
587typedef struct microcode microcode_t;
588typedef struct microcode_header microcode_header_t;
589
590/* microcode format is extended from prescott processors */
591struct extended_signature {
592 unsigned int sig;
593 unsigned int pf;
594 unsigned int cksum;
595};
596
597struct extended_sigtable {
598 unsigned int count;
599 unsigned int cksum;
600 unsigned int reserved[3];
601 struct extended_signature sigs[0];
602};
603/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
604#define MICROCODE_IOCFREE _IO('6',0)
605
606/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
607static inline void rep_nop(void)
608{
609 __asm__ __volatile__("rep;nop": : :"memory");
610}
611
612#define cpu_relax() rep_nop()
613
614/* generic versions from gas */
615#define GENERIC_NOP1 ".byte 0x90\n"
616#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
617#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
618#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
619#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
620#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
621#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
622#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
623
624/* Opteron nops */
625#define K8_NOP1 GENERIC_NOP1
626#define K8_NOP2 ".byte 0x66,0x90\n"
627#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
628#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
629#define K8_NOP5 K8_NOP3 K8_NOP2
630#define K8_NOP6 K8_NOP3 K8_NOP3
631#define K8_NOP7 K8_NOP4 K8_NOP3
632#define K8_NOP8 K8_NOP4 K8_NOP4
633
634/* K7 nops */
635/* uses eax dependencies (arbitary choice) */
636#define K7_NOP1 GENERIC_NOP1
637#define K7_NOP2 ".byte 0x8b,0xc0\n"
638#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
639#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
640#define K7_NOP5 K7_NOP4 ASM_NOP1
641#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
642#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
643#define K7_NOP8 K7_NOP7 ASM_NOP1
644
645#ifdef CONFIG_MK8
646#define ASM_NOP1 K8_NOP1
647#define ASM_NOP2 K8_NOP2
648#define ASM_NOP3 K8_NOP3
649#define ASM_NOP4 K8_NOP4
650#define ASM_NOP5 K8_NOP5
651#define ASM_NOP6 K8_NOP6
652#define ASM_NOP7 K8_NOP7
653#define ASM_NOP8 K8_NOP8
654#elif defined(CONFIG_MK7)
655#define ASM_NOP1 K7_NOP1
656#define ASM_NOP2 K7_NOP2
657#define ASM_NOP3 K7_NOP3
658#define ASM_NOP4 K7_NOP4
659#define ASM_NOP5 K7_NOP5
660#define ASM_NOP6 K7_NOP6
661#define ASM_NOP7 K7_NOP7
662#define ASM_NOP8 K7_NOP8
663#else
664#define ASM_NOP1 GENERIC_NOP1
665#define ASM_NOP2 GENERIC_NOP2
666#define ASM_NOP3 GENERIC_NOP3
667#define ASM_NOP4 GENERIC_NOP4
668#define ASM_NOP5 GENERIC_NOP5
669#define ASM_NOP6 GENERIC_NOP6
670#define ASM_NOP7 GENERIC_NOP7
671#define ASM_NOP8 GENERIC_NOP8
672#endif
673
674#define ASM_NOP_MAX 8
675
676/* Prefetch instructions for Pentium III and AMD Athlon */
677/* It's not worth to care about 3dnow! prefetches for the K6
678 because they are microcoded there and very slow.
679 However we don't do prefetches for pre XP Athlons currently
680 That should be fixed. */
681#define ARCH_HAS_PREFETCH
682extern inline void prefetch(const void *x)
683{
684 alternative_input(ASM_NOP4,
685 "prefetchnta (%1)",
686 X86_FEATURE_XMM,
687 "r" (x));
688}
689
690#define ARCH_HAS_PREFETCH
691#define ARCH_HAS_PREFETCHW
692#define ARCH_HAS_SPINLOCK_PREFETCH
693
694/* 3dnow! prefetch to get an exclusive cache line. Useful for
695 spinlocks to avoid one state transition in the cache coherency protocol. */
696extern inline void prefetchw(const void *x)
697{
698 alternative_input(ASM_NOP4,
699 "prefetchw (%1)",
700 X86_FEATURE_3DNOW,
701 "r" (x));
702}
703#define spin_lock_prefetch(x) prefetchw(x)
704
705extern void select_idle_routine(const struct cpuinfo_x86 *c);
706
707#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
708
709extern unsigned long boot_option_idle_override;
6fe940d6
LS		 710extern void enable_sep_cpu(void);
711extern int sysenter_setup(void);
1da177e4 712
3b520b23
SL		 713#ifdef CONFIG_MTRR
714extern void mtrr_ap_init(void);
715extern void mtrr_bp_init(void);
716#else
717#define mtrr_ap_init() do {} while (0)
718#define mtrr_bp_init() do {} while (0)
719#endif
720
1da177e4 721#endif /* __ASM_I386_PROCESSOR_H */
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