[net-next-2.6.git] / include / asm-i386 / mach-default / mach_apic.h

#ifndef __ASM_MACH_APIC_H
#define __ASM_MACH_APIC_H

#include <mach_apicdef.h>
#include <asm/smp.h>

#define APIC_DFR_VALUE	(APIC_DFR_FLAT)

static inline cpumask_t target_cpus(void)
{ 
#ifdef CONFIG_SMP
	return cpu_online_map;
#else
	return cpumask_of_cpu(0);
#endif
} 
#define TARGET_CPUS (target_cpus())

#define NO_BALANCE_IRQ (0)
#define esr_disable (0)

#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */

static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
	return physid_isset(apicid, bitmap);
}

static inline unsigned long check_apicid_present(int bit)
{
	return physid_isset(bit, phys_cpu_present_map);
}

/*
 * Set up the logical destination ID.
 *
 * Intel recommends to set DFR, LDR and TPR before enabling
 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 * document number 292116).  So here it goes...
 */
static inline void init_apic_ldr(void)
{
	unsigned long val;

	apic_write_around(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write_around(APIC_LDR, val);
}

static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
{
	return phys_map;
}

static inline void setup_apic_routing(void)
{
	printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
					"Flat", nr_ioapics);
}

static inline int multi_timer_check(int apic, int irq)
{
	return 0;
}

static inline int apicid_to_node(int logical_apicid)
{
	return 0;
}

/* Mapping from cpu number to logical apicid */
static inline int cpu_to_logical_apicid(int cpu)
{
	return 1 << cpu;
}

static inline int cpu_present_to_apicid(int mps_cpu)
{
	if (mps_cpu < get_physical_broadcast())
		return  mps_cpu;
	else
		return BAD_APICID;
}

static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
{
	return physid_mask_of_physid(phys_apicid);
}

static inline int mpc_apic_id(struct mpc_config_processor *m, 
			struct mpc_config_translation *translation_record)
{
	printk("Processor #%d %ld:%ld APIC version %d\n",
			m->mpc_apicid,
			(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
			(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
			m->mpc_apicver);
	return (m->mpc_apicid);
}

static inline void setup_portio_remap(void)
{
}

static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
{
	return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
}

static inline int apic_id_registered(void)
{
	return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map);
}

static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
{
	return cpus_addr(cpumask)[0];
}

static inline void enable_apic_mode(void)
{
}

static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
	return cpuid_apic >> index_msb;
}

#endif /* __ASM_MACH_APIC_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_MACH_APIC_H
	2	#define __ASM_MACH_APIC_H
	3
	4	#include <mach_apicdef.h>
	5	#include <asm/smp.h>
	6
	7	#define APIC_DFR_VALUE (APIC_DFR_FLAT)
	8
	9	static inline cpumask_t target_cpus(void)
	10	{
	11	#ifdef CONFIG_SMP
	12	return cpu_online_map;
	13	#else
	14	return cpumask_of_cpu(0);
	15	#endif
	16	}
	17	#define TARGET_CPUS (target_cpus())
	18
	19	#define NO_BALANCE_IRQ (0)
	20	#define esr_disable (0)
	21
1da177e4 LT	22	#define INT_DELIVERY_MODE dest_LowestPrio
	23	#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
	24
	25	static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
	26	{
	27	return physid_isset(apicid, bitmap);
	28	}
	29
	30	static inline unsigned long check_apicid_present(int bit)
	31	{
	32	return physid_isset(bit, phys_cpu_present_map);
	33	}
	34
	35	/*
	36	* Set up the logical destination ID.
	37	*
	38	* Intel recommends to set DFR, LDR and TPR before enabling
	39	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	40	* document number 292116). So here it goes...
	41	*/
	42	static inline void init_apic_ldr(void)
	43	{
	44	unsigned long val;
	45
	46	apic_write_around(APIC_DFR, APIC_DFR_VALUE);
	47	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	48	val \|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	49	apic_write_around(APIC_LDR, val);
	50	}
	51
	52	static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
	53	{
	54	return phys_map;
	55	}
	56
3c43f039	57	static inline void setup_apic_routing(void)
1da177e4 LT	58	{
	59	printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
	60	"Flat", nr_ioapics);
	61	}
	62
	63	static inline int multi_timer_check(int apic, int irq)
	64	{
	65	return 0;
	66	}
	67
	68	static inline int apicid_to_node(int logical_apicid)
	69	{
	70	return 0;
	71	}
	72
	73	/* Mapping from cpu number to logical apicid */
	74	static inline int cpu_to_logical_apicid(int cpu)
	75	{
	76	return 1 << cpu;
	77	}
	78
	79	static inline int cpu_present_to_apicid(int mps_cpu)
	80	{
	81	if (mps_cpu < get_physical_broadcast())
	82	return mps_cpu;
	83	else
	84	return BAD_APICID;
	85	}
	86
	87	static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
	88	{
	89	return physid_mask_of_physid(phys_apicid);
	90	}
	91
	92	static inline int mpc_apic_id(struct mpc_config_processor *m,
	93	struct mpc_config_translation *translation_record)
	94	{
	95	printk("Processor #%d %ld:%ld APIC version %d\n",
	96	m->mpc_apicid,
	97	(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
	98	(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
	99	m->mpc_apicver);
	100	return (m->mpc_apicid);
	101	}
	102
	103	static inline void setup_portio_remap(void)
	104	{
	105	}
	106
	107	static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
	108	{
	109	return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
	110	}
	111
	112	static inline int apic_id_registered(void)
	113	{
	114	return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map);
	115	}
	116
	117	static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
	118	{
	119	return cpus_addr(cpumask)[0];
	120	}
	121
122	static inline void enable_apic_mode(void)
123	{
124	}
125
126	static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
127	{
128	return cpuid_apic >> index_msb;
129	}
130
131	#endif /* __ASM_MACH_APIC_H */