[net-next-2.6.git] / include / asm-frv / bitops.h

/* bitops.h: bit operations for the Fujitsu FR-V CPUs
 *
 * For an explanation of how atomic ops work in this arch, see:
 *   Documentation/fujitsu/frv/atomic-ops.txt
 *
 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H

#include <linux/compiler.h>
#include <asm/byteorder.h>
#include <asm/system.h>
#include <asm/atomic.h>

#ifdef __KERNEL__

#include <asm-generic/bitops/ffz.h>

/*
 * clear_bit() doesn't provide any barrier for the compiler.
 */
#define smp_mb__before_clear_bit()	barrier()
#define smp_mb__after_clear_bit()	barrier()

static inline int test_and_clear_bit(int nr, volatile void *addr)
{
	volatile unsigned long *ptr = addr;
	unsigned long mask = 1UL << (nr & 31);
	ptr += nr >> 5;
	return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
}

static inline int test_and_set_bit(int nr, volatile void *addr)
{
	volatile unsigned long *ptr = addr;
	unsigned long mask = 1UL << (nr & 31);
	ptr += nr >> 5;
	return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
}

static inline int test_and_change_bit(int nr, volatile void *addr)
{
	volatile unsigned long *ptr = addr;
	unsigned long mask = 1UL << (nr & 31);
	ptr += nr >> 5;
	return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
}

static inline void clear_bit(int nr, volatile void *addr)
{
	test_and_clear_bit(nr, addr);
}

static inline void set_bit(int nr, volatile void *addr)
{
	test_and_set_bit(nr, addr);
}

static inline void change_bit(int nr, volatile void * addr)
{
	test_and_change_bit(nr, addr);
}

static inline void __clear_bit(int nr, volatile void * addr)
{
	volatile unsigned long *a = addr;
	int mask;

	a += nr >> 5;
	mask = 1 << (nr & 31);
	*a &= ~mask;
}

static inline void __set_bit(int nr, volatile void * addr)
{
	volatile unsigned long *a = addr;
	int mask;

	a += nr >> 5;
	mask = 1 << (nr & 31);
	*a |= mask;
}

static inline void __change_bit(int nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask;

	a += nr >> 5;
	mask = 1 << (nr & 31);
	*a ^= mask;
}

static inline int __test_and_clear_bit(int nr, volatile void * addr)
{
	volatile unsigned long *a = addr;
	int mask, retval;

	a += nr >> 5;
	mask = 1 << (nr & 31);
	retval = (mask & *a) != 0;
	*a &= ~mask;
	return retval;
}

static inline int __test_and_set_bit(int nr, volatile void * addr)
{
	volatile unsigned long *a = addr;
	int mask, retval;

	a += nr >> 5;
	mask = 1 << (nr & 31);
	retval = (mask & *a) != 0;
	*a |= mask;
	return retval;
}

static inline int __test_and_change_bit(int nr, volatile void * addr)
{
	volatile unsigned long *a = addr;
	int mask, retval;

	a += nr >> 5;
	mask = 1 << (nr & 31);
	retval = (mask & *a) != 0;
	*a ^= mask;
	return retval;
}

/*
 * This routine doesn't need to be atomic.
 */
static inline int __constant_test_bit(int nr, const volatile void * addr)
{
	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
}

static inline int __test_bit(int nr, const volatile void * addr)
{
	int 	* a = (int *) addr;
	int	mask;

	a += nr >> 5;
	mask = 1 << (nr & 0x1f);
	return ((mask & *a) != 0);
}

#define test_bit(nr,addr) \
(__builtin_constant_p(nr) ? \
 __constant_test_bit((nr),(addr)) : \
 __test_bit((nr),(addr)))

#include <asm-generic/bitops/find.h>

/**
 * fls - find last bit set
 * @x: the word to search
 *
 * This is defined the same way as ffs:
 * - return 32..1 to indicate bit 31..0 most significant bit set
 * - return 0 to indicate no bits set
 */
#define fls(x)						\
({							\
	int bit;					\
							\
	asm("	subcc	%1,gr0,gr0,icc0		\n"	\
	    "	ckne	icc0,cc4		\n"	\
	    "	cscan.p	%1,gr0,%0	,cc4,#1	\n"	\
	    "	csub	%0,%0,%0	,cc4,#0	\n"	\
	    "   csub    %2,%0,%0	,cc4,#1	\n"	\
	    : "=&r"(bit)				\
	    : "r"(x), "r"(32)				\
	    : "icc0", "cc4"				\
	    );						\
							\
	bit;						\
})

/**
 * fls64 - find last bit set in a 64-bit value
 * @n: the value to search
 *
 * This is defined the same way as ffs:
 * - return 64..1 to indicate bit 63..0 most significant bit set
 * - return 0 to indicate no bits set
 */
static inline __attribute__((const))
int fls64(u64 n)
{
	union {
		u64 ll;
		struct { u32 h, l; };
	} _;
	int bit, x, y;

	_.ll = n;

	asm("	subcc.p		%3,gr0,gr0,icc0		\n"
	    "	subcc		%4,gr0,gr0,icc1		\n"
	    "	ckne		icc0,cc4		\n"
	    "	ckne		icc1,cc5		\n"
	    "	norcr		cc4,cc5,cc6		\n"
	    "	csub.p		%0,%0,%0	,cc6,1	\n"
	    "	orcr		cc5,cc4,cc4		\n"
	    "	andcr		cc4,cc5,cc4		\n"
	    "	cscan.p		%3,gr0,%0	,cc4,0	\n"
	    "   setlos		#64,%1			\n"
	    "	cscan.p		%4,gr0,%0	,cc4,1	\n"
	    "   setlos		#32,%2			\n"
	    "	csub.p		%1,%0,%0	,cc4,0	\n"
	    "	csub		%2,%0,%0	,cc4,1	\n"
	    : "=&r"(bit), "=r"(x), "=r"(y)
	    : "0r"(_.h), "r"(_.l)
	    : "icc0", "icc1", "cc4", "cc5", "cc6"
	    );
	return bit;

}

/**
 * ffs - find first bit set
 * @x: the word to search
 *
 * - return 32..1 to indicate bit 31..0 most least significant bit set
 * - return 0 to indicate no bits set
 */
static inline __attribute__((const))
int ffs(int x)
{
	/* Note: (x & -x) gives us a mask that is the least significant
	 * (rightmost) 1-bit of the value in x.
	 */
	return fls(x & -x);
}

/**
 * __ffs - find first bit set
 * @x: the word to search
 *
 * - return 31..0 to indicate bit 31..0 most least significant bit set
 * - if no bits are set in x, the result is undefined
 */
static inline __attribute__((const))
int __ffs(unsigned long x)
{
	int bit;
	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
	return 31 - bit;
}

/*
 * special slimline version of fls() for calculating ilog2_u32()
 * - note: no protection against n == 0
 */
#define ARCH_HAS_ILOG2_U32
static inline __attribute__((const))
int __ilog2_u32(u32 n)
{
	int bit;
	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
	return 31 - bit;
}

/*
 * special slimline version of fls64() for calculating ilog2_u64()
 * - note: no protection against n == 0
 */
#define ARCH_HAS_ILOG2_U64
static inline __attribute__((const))
int __ilog2_u64(u64 n)
{
	union {
		u64 ll;
		struct { u32 h, l; };
	} _;
	int bit, x, y;

	_.ll = n;

	asm("	subcc		%3,gr0,gr0,icc0		\n"
	    "	ckeq		icc0,cc4		\n"
	    "	cscan.p		%3,gr0,%0	,cc4,0	\n"
	    "   setlos		#63,%1			\n"
	    "	cscan.p		%4,gr0,%0	,cc4,1	\n"
	    "   setlos		#31,%2			\n"
	    "	csub.p		%1,%0,%0	,cc4,0	\n"
	    "	csub		%2,%0,%0	,cc4,1	\n"
	    : "=&r"(bit), "=r"(x), "=r"(y)
	    : "0r"(_.h), "r"(_.l)
	    : "icc0", "cc4"
	    );
	return bit;
}

#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>

#include <asm-generic/bitops/ext2-non-atomic.h>

#define ext2_set_bit_atomic(lock,nr,addr)	test_and_set_bit  ((nr) ^ 0x18, (addr))
#define ext2_clear_bit_atomic(lock,nr,addr)	test_and_clear_bit((nr) ^ 0x18, (addr))

#include <asm-generic/bitops/minix-le.h>

#endif /* __KERNEL__ */

#endif /* _ASM_BITOPS_H */
Commit	Line	Data
1da177e4 LT	1	/* bitops.h: bit operations for the Fujitsu FR-V CPUs
	2	*
	3	* For an explanation of how atomic ops work in this arch, see:
	4	* Documentation/fujitsu/frv/atomic-ops.txt
	5	*
	6	* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
	7	* Written by David Howells (dhowells@redhat.com)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14	#ifndef _ASM_BITOPS_H
	15	#define _ASM_BITOPS_H
	16
1da177e4 LT	17	#include <linux/compiler.h>
	18	#include <asm/byteorder.h>
	19	#include <asm/system.h>
	20	#include <asm/atomic.h>
	21
	22	#ifdef __KERNEL__
	23
1f6d7a93	24	#include <asm-generic/bitops/ffz.h>
1da177e4 LT	25
	26	/*
	27	* clear_bit() doesn't provide any barrier for the compiler.
	28	*/
	29	#define smp_mb__before_clear_bit() barrier()
	30	#define smp_mb__after_clear_bit() barrier()
	31
	32	static inline int test_and_clear_bit(int nr, volatile void *addr)
	33	{
	34	volatile unsigned long *ptr = addr;
	35	unsigned long mask = 1UL << (nr & 31);
	36	ptr += nr >> 5;
	37	return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
	38	}
	39
	40	static inline int test_and_set_bit(int nr, volatile void *addr)
	41	{
	42	volatile unsigned long *ptr = addr;
	43	unsigned long mask = 1UL << (nr & 31);
	44	ptr += nr >> 5;
	45	return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
	46	}
	47
	48	static inline int test_and_change_bit(int nr, volatile void *addr)
	49	{
	50	volatile unsigned long *ptr = addr;
	51	unsigned long mask = 1UL << (nr & 31);
	52	ptr += nr >> 5;
	53	return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
	54	}
	55
	56	static inline void clear_bit(int nr, volatile void *addr)
	57	{
	58	test_and_clear_bit(nr, addr);
	59	}
	60
	61	static inline void set_bit(int nr, volatile void *addr)
	62	{
	63	test_and_set_bit(nr, addr);
	64	}
	65
	66	static inline void change_bit(int nr, volatile void * addr)
	67	{
	68	test_and_change_bit(nr, addr);
	69	}
	70
	71	static inline void __clear_bit(int nr, volatile void * addr)
	72	{
	73	volatile unsigned long *a = addr;
	74	int mask;
	75
	76	a += nr >> 5;
	77	mask = 1 << (nr & 31);
	78	*a &= ~mask;
	79	}
	80
	81	static inline void __set_bit(int nr, volatile void * addr)
	82	{
	83	volatile unsigned long *a = addr;
	84	int mask;
	85
	86	a += nr >> 5;
	87	mask = 1 << (nr & 31);
	88	*a \|= mask;
89	}
90
91	static inline void __change_bit(int nr, volatile void *addr)
92	{
93	volatile unsigned long *a = addr;
94	int mask;
95
96	a += nr >> 5;
97	mask = 1 << (nr & 31);
98	*a ^= mask;
99	}
100
101	static inline int __test_and_clear_bit(int nr, volatile void * addr)
102	{
103	volatile unsigned long *a = addr;
104	int mask, retval;
105
106	a += nr >> 5;
107	mask = 1 << (nr & 31);
108	retval = (mask & *a) != 0;
109	*a &= ~mask;
110	return retval;
111	}
112
113	static inline int __test_and_set_bit(int nr, volatile void * addr)
114	{
115	volatile unsigned long *a = addr;
116	int mask, retval;
117
118	a += nr >> 5;
119	mask = 1 << (nr & 31);
120	retval = (mask & *a) != 0;
121	*a \|= mask;
122	return retval;
123	}
124
125	static inline int __test_and_change_bit(int nr, volatile void * addr)
126	{
127	volatile unsigned long *a = addr;
128	int mask, retval;
129
130	a += nr >> 5;
131	mask = 1 << (nr & 31);
132	retval = (mask & *a) != 0;
133	*a ^= mask;
134	return retval;
135	}
136
137	/*
138	* This routine doesn't need to be atomic.
139	*/
140	static inline int __constant_test_bit(int nr, const volatile void * addr)
141	{
142	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
143	}
144
145	static inline int __test_bit(int nr, const volatile void * addr)
146	{
147	int * a = (int *) addr;
148	int mask;
149
150	a += nr >> 5;
151	mask = 1 << (nr & 0x1f);
152	return ((mask & *a) != 0);
153	}
154
155	#define test_bit(nr,addr) \
156	(__builtin_constant_p(nr) ? \
157	__constant_test_bit((nr),(addr)) : \
158	__test_bit((nr),(addr)))
159
1f6d7a93	160	#include <asm-generic/bitops/find.h>
1da177e4	161
92fc7072 DH	162	/**
	163	* fls - find last bit set
	164	* @x: the word to search
	165	*
	166	* This is defined the same way as ffs:
	167	* - return 32..1 to indicate bit 31..0 most significant bit set
	168	* - return 0 to indicate no bits set
1da177e4 LT	169	*/
	170	#define fls(x) \
	171	({ \
	172	int bit; \
	173	\
92fc7072 DH	174	asm(" subcc %1,gr0,gr0,icc0 \n" \
	175	" ckne icc0,cc4 \n" \
	176	" cscan.p %1,gr0,%0 ,cc4,#1 \n" \
	177	" csub %0,%0,%0 ,cc4,#0 \n" \
	178	" csub %2,%0,%0 ,cc4,#1 \n" \
	179	: "=&r"(bit) \
	180	: "r"(x), "r"(32) \
	181	: "icc0", "cc4" \
	182	); \
1da177e4	183	\
92fc7072	184	bit; \
1da177e4 LT	185	})
1da177e4 LT	186
a8ad27d0 DH	187	/**
	188	* fls64 - find last bit set in a 64-bit value
	189	* @n: the value to search
	190	*
	191	* This is defined the same way as ffs:
	192	* - return 64..1 to indicate bit 63..0 most significant bit set
	193	* - return 0 to indicate no bits set
	194	*/
	195	static inline __attribute__((const))
	196	int fls64(u64 n)
	197	{
	198	union {
	199	u64 ll;
	200	struct { u32 h, l; };
	201	} _;
	202	int bit, x, y;
	203
	204	_.ll = n;
	205
	206	asm(" subcc.p %3,gr0,gr0,icc0 \n"
	207	" subcc %4,gr0,gr0,icc1 \n"
	208	" ckne icc0,cc4 \n"
	209	" ckne icc1,cc5 \n"
	210	" norcr cc4,cc5,cc6 \n"
	211	" csub.p %0,%0,%0 ,cc6,1 \n"
	212	" orcr cc5,cc4,cc4 \n"
	213	" andcr cc4,cc5,cc4 \n"
	214	" cscan.p %3,gr0,%0 ,cc4,0 \n"
	215	" setlos #64,%1 \n"
	216	" cscan.p %4,gr0,%0 ,cc4,1 \n"
	217	" setlos #32,%2 \n"
	218	" csub.p %1,%0,%0 ,cc4,0 \n"
	219	" csub %2,%0,%0 ,cc4,1 \n"
	220	: "=&r"(bit), "=r"(x), "=r"(y)
	221	: "0r"(_.h), "r"(_.l)
	222	: "icc0", "icc1", "cc4", "cc5", "cc6"
	223	);
	224	return bit;
	225
	226	}
	227
cf134483 DH	228	/**
	229	* ffs - find first bit set
	230	* @x: the word to search
	231	*
	232	* - return 32..1 to indicate bit 31..0 most least significant bit set
	233	* - return 0 to indicate no bits set
	234	*/
	235	static inline __attribute__((const))
	236	int ffs(int x)
	237	{
	238	/* Note: (x & -x) gives us a mask that is the least significant
	239	* (rightmost) 1-bit of the value in x.
	240	*/
	241	return fls(x & -x);
	242	}
	243
	244	/**
	245	* __ffs - find first bit set
	246	* @x: the word to search
	247	*
	248	* - return 31..0 to indicate bit 31..0 most least significant bit set
	249	* - if no bits are set in x, the result is undefined
	250	*/
	251	static inline __attribute__((const))
	252	int __ffs(unsigned long x)
	253	{
	254	int bit;
	255	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
	256	return 31 - bit;
	257	}
	258
f0d1b0b3 DH	259	/*
	260	* special slimline version of fls() for calculating ilog2_u32()
	261	* - note: no protection against n == 0
	262	*/
	263	#define ARCH_HAS_ILOG2_U32
	264	static inline __attribute__((const))
	265	int __ilog2_u32(u32 n)
	266	{
	267	int bit;
	268	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
	269	return 31 - bit;
	270	}
	271
	272	/*
	273	* special slimline version of fls64() for calculating ilog2_u64()
	274	* - note: no protection against n == 0
	275	*/
	276	#define ARCH_HAS_ILOG2_U64
	277	static inline __attribute__((const))
	278	int __ilog2_u64(u64 n)
	279	{
	280	union {
	281	u64 ll;
	282	struct { u32 h, l; };
	283	} _;
	284	int bit, x, y;
	285
	286	_.ll = n;
	287
	288	asm(" subcc %3,gr0,gr0,icc0 \n"
	289	" ckeq icc0,cc4 \n"
	290	" cscan.p %3,gr0,%0 ,cc4,0 \n"
	291	" setlos #63,%1 \n"
	292	" cscan.p %4,gr0,%0 ,cc4,1 \n"
	293	" setlos #31,%2 \n"
	294	" csub.p %1,%0,%0 ,cc4,0 \n"
	295	" csub %2,%0,%0 ,cc4,1 \n"
	296	: "=&r"(bit), "=r"(x), "=r"(y)
	297	: "0r"(_.h), "r"(_.l)
	298	: "icc0", "cc4"
	299	);
	300	return bit;
	301	}
	302
1f6d7a93 AM	303	#include <asm-generic/bitops/sched.h>
1f6d7a93 AM	304	#include <asm-generic/bitops/hweight.h>
26333576	305	#include <asm-generic/bitops/lock.h>
1da177e4	306
1f6d7a93	307	#include <asm-generic/bitops/ext2-non-atomic.h>
1da177e4	308
67b0ad57 AM	309	#define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit ((nr) ^ 0x18, (addr))
67b0ad57 AM	310	#define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr) ^ 0x18, (addr))
1da177e4	311
1f6d7a93	312	#include <asm-generic/bitops/minix-le.h>
1da177e4 LT	313
	314	#endif /* __KERNEL__ */
	315
	316	#endif /* _ASM_BITOPS_H */