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stmmac: tidy-up stmmac_priv structure
[net-next-2.6.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
01557baf 108static int nr_pirqs;
e46cdb66 109
b21ddbf5 110static int *evtchn_to_irq;
c7a3589e
MT
111struct cpu_evtchn_s {
112 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
113};
3b32f574
JF
114
115static __initdata struct cpu_evtchn_s init_evtchn_mask = {
116 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
117};
118static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
119
c7a3589e
MT
120static inline unsigned long *cpu_evtchn_mask(int cpu)
121{
122 return cpu_evtchn_mask_p[cpu].bits;
123}
e46cdb66 124
e46cdb66
JF
125/* Xen will never allocate port zero for any purpose. */
126#define VALID_EVTCHN(chn) ((chn) != 0)
127
e46cdb66 128static struct irq_chip xen_dynamic_chip;
aaca4964 129static struct irq_chip xen_percpu_chip;
d46a78b0 130static struct irq_chip xen_pirq_chip;
e46cdb66
JF
131
132/* Constructor for packed IRQ information. */
ced40d0f
JF
133static struct irq_info mk_unbound_info(void)
134{
135 return (struct irq_info) { .type = IRQT_UNBOUND };
136}
137
138static struct irq_info mk_evtchn_info(unsigned short evtchn)
139{
90af9514
IC
140 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
141 .cpu = 0 };
ced40d0f
JF
142}
143
144static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 145{
ced40d0f 146 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 147 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
148}
149
150static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
151{
152 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 153 .cpu = 0, .u.virq = virq };
ced40d0f
JF
154}
155
7a043f11 156static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
157 unsigned short gsi, unsigned short vector)
158{
159 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
160 .cpu = 0,
161 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
162}
163
164/*
165 * Accessors for packed IRQ information.
166 */
ced40d0f 167static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 168{
ced40d0f 169 return &irq_info[irq];
e46cdb66
JF
170}
171
ced40d0f 172static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 173{
ced40d0f 174 return info_for_irq(irq)->evtchn;
e46cdb66
JF
175}
176
d4c04536
IC
177unsigned irq_from_evtchn(unsigned int evtchn)
178{
179 return evtchn_to_irq[evtchn];
180}
181EXPORT_SYMBOL_GPL(irq_from_evtchn);
182
ced40d0f 183static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 184{
ced40d0f
JF
185 struct irq_info *info = info_for_irq(irq);
186
187 BUG_ON(info == NULL);
188 BUG_ON(info->type != IRQT_IPI);
189
190 return info->u.ipi;
191}
192
193static unsigned virq_from_irq(unsigned irq)
194{
195 struct irq_info *info = info_for_irq(irq);
196
197 BUG_ON(info == NULL);
198 BUG_ON(info->type != IRQT_VIRQ);
199
200 return info->u.virq;
201}
202
7a043f11
SS
203static unsigned pirq_from_irq(unsigned irq)
204{
205 struct irq_info *info = info_for_irq(irq);
206
207 BUG_ON(info == NULL);
208 BUG_ON(info->type != IRQT_PIRQ);
209
210 return info->u.pirq.pirq;
211}
212
ced40d0f
JF
213static unsigned gsi_from_irq(unsigned irq)
214{
215 struct irq_info *info = info_for_irq(irq);
216
217 BUG_ON(info == NULL);
218 BUG_ON(info->type != IRQT_PIRQ);
219
220 return info->u.pirq.gsi;
221}
222
223static unsigned vector_from_irq(unsigned irq)
224{
225 struct irq_info *info = info_for_irq(irq);
226
227 BUG_ON(info == NULL);
228 BUG_ON(info->type != IRQT_PIRQ);
229
230 return info->u.pirq.vector;
231}
232
233static enum xen_irq_type type_from_irq(unsigned irq)
234{
235 return info_for_irq(irq)->type;
236}
237
238static unsigned cpu_from_irq(unsigned irq)
239{
240 return info_for_irq(irq)->cpu;
241}
242
243static unsigned int cpu_from_evtchn(unsigned int evtchn)
244{
245 int irq = evtchn_to_irq[evtchn];
246 unsigned ret = 0;
247
248 if (irq != -1)
249 ret = cpu_from_irq(irq);
250
251 return ret;
e46cdb66
JF
252}
253
d46a78b0
JF
254static bool pirq_needs_eoi(unsigned irq)
255{
256 struct irq_info *info = info_for_irq(irq);
257
258 BUG_ON(info->type != IRQT_PIRQ);
259
260 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
261}
262
e46cdb66
JF
263static inline unsigned long active_evtchns(unsigned int cpu,
264 struct shared_info *sh,
265 unsigned int idx)
266{
267 return (sh->evtchn_pending[idx] &
c7a3589e 268 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
269 ~sh->evtchn_mask[idx]);
270}
271
272static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
273{
274 int irq = evtchn_to_irq[chn];
275
276 BUG_ON(irq == -1);
277#ifdef CONFIG_SMP
7f7ace0c 278 cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
e46cdb66
JF
279#endif
280
ced40d0f 281 __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
c7a3589e 282 __set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 283
ced40d0f 284 irq_info[irq].cpu = cpu;
e46cdb66
JF
285}
286
287static void init_evtchn_cpu_bindings(void)
288{
289#ifdef CONFIG_SMP
10e58084 290 struct irq_desc *desc;
e46cdb66 291 int i;
10e58084 292
e46cdb66 293 /* By default all event channels notify CPU#0. */
0b8f1efa 294 for_each_irq_desc(i, desc) {
7f7ace0c 295 cpumask_copy(desc->affinity, cpumask_of(0));
0b8f1efa 296 }
e46cdb66
JF
297#endif
298
b0097ade 299 memset(cpu_evtchn_mask(0), ~0, sizeof(struct cpu_evtchn_s));
e46cdb66
JF
300}
301
e46cdb66
JF
302static inline void clear_evtchn(int port)
303{
304 struct shared_info *s = HYPERVISOR_shared_info;
305 sync_clear_bit(port, &s->evtchn_pending[0]);
306}
307
308static inline void set_evtchn(int port)
309{
310 struct shared_info *s = HYPERVISOR_shared_info;
311 sync_set_bit(port, &s->evtchn_pending[0]);
312}
313
168d2f46
JF
314static inline int test_evtchn(int port)
315{
316 struct shared_info *s = HYPERVISOR_shared_info;
317 return sync_test_bit(port, &s->evtchn_pending[0]);
318}
319
e46cdb66
JF
320
321/**
322 * notify_remote_via_irq - send event to remote end of event channel via irq
323 * @irq: irq of event channel to send event to
324 *
325 * Unlike notify_remote_via_evtchn(), this is safe to use across
326 * save/restore. Notifications on a broken connection are silently
327 * dropped.
328 */
329void notify_remote_via_irq(int irq)
330{
331 int evtchn = evtchn_from_irq(irq);
332
333 if (VALID_EVTCHN(evtchn))
334 notify_remote_via_evtchn(evtchn);
335}
336EXPORT_SYMBOL_GPL(notify_remote_via_irq);
337
338static void mask_evtchn(int port)
339{
340 struct shared_info *s = HYPERVISOR_shared_info;
341 sync_set_bit(port, &s->evtchn_mask[0]);
342}
343
344static void unmask_evtchn(int port)
345{
346 struct shared_info *s = HYPERVISOR_shared_info;
347 unsigned int cpu = get_cpu();
348
349 BUG_ON(!irqs_disabled());
350
351 /* Slow path (hypercall) if this is a non-local port. */
352 if (unlikely(cpu != cpu_from_evtchn(port))) {
353 struct evtchn_unmask unmask = { .port = port };
354 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
355 } else {
356 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
357
358 sync_clear_bit(port, &s->evtchn_mask[0]);
359
360 /*
361 * The following is basically the equivalent of
362 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
363 * the interrupt edge' if the channel is masked.
364 */
365 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
366 !sync_test_and_set_bit(port / BITS_PER_LONG,
367 &vcpu_info->evtchn_pending_sel))
368 vcpu_info->evtchn_upcall_pending = 1;
369 }
370
371 put_cpu();
372}
373
0794bfc7
KRW
374static int get_nr_hw_irqs(void)
375{
376 int ret = 1;
377
378#ifdef CONFIG_X86_IO_APIC
379 ret = get_nr_irqs_gsi();
380#endif
381
382 return ret;
383}
384
01557baf
SS
385/* callers of this function should make sure that PHYSDEVOP_get_nr_pirqs
386 * succeeded otherwise nr_pirqs won't hold the right value */
7a043f11
SS
387static int find_unbound_pirq(void)
388{
389 int i;
01557baf 390 for (i = nr_pirqs-1; i >= 0; i--) {
7a043f11
SS
391 if (pirq_to_irq[i] < 0)
392 return i;
393 }
394 return -1;
395}
396
e46cdb66
JF
397static int find_unbound_irq(void)
398{
77dff1c7
TG
399 struct irq_data *data;
400 int irq, res;
3a69e916 401 int start = get_nr_hw_irqs();
e46cdb66 402
3a69e916
KRW
403 if (start == nr_irqs)
404 goto no_irqs;
405
406 /* nr_irqs is a magic value. Must not use it.*/
407 for (irq = nr_irqs-1; irq > start; irq--) {
77dff1c7 408 data = irq_get_irq_data(irq);
99ad198c 409 /* only 0->15 have init'd desc; handle irq > 16 */
77dff1c7 410 if (!data)
99ad198c 411 break;
77dff1c7 412 if (data->chip == &no_irq_chip)
99ad198c 413 break;
77dff1c7 414 if (data->chip != &xen_dynamic_chip)
99ad198c 415 continue;
d77bbd4d 416 if (irq_info[irq].type == IRQT_UNBOUND)
77dff1c7 417 return irq;
99ad198c 418 }
e46cdb66 419
3a69e916
KRW
420 if (irq == start)
421 goto no_irqs;
e46cdb66 422
77dff1c7 423 res = irq_alloc_desc_at(irq, 0);
6f8a0ed4 424
77dff1c7
TG
425 if (WARN_ON(res != irq))
426 return -1;
ced40d0f 427
e46cdb66 428 return irq;
3a69e916
KRW
429
430no_irqs:
431 panic("No available IRQ to bind to: increase nr_irqs!\n");
e46cdb66
JF
432}
433
d46a78b0
JF
434static bool identity_mapped_irq(unsigned irq)
435{
0794bfc7
KRW
436 /* identity map all the hardware irqs */
437 return irq < get_nr_hw_irqs();
d46a78b0
JF
438}
439
440static void pirq_unmask_notify(int irq)
441{
7a043f11 442 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
443
444 if (unlikely(pirq_needs_eoi(irq))) {
445 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
446 WARN_ON(rc);
447 }
448}
449
450static void pirq_query_unmask(int irq)
451{
452 struct physdev_irq_status_query irq_status;
453 struct irq_info *info = info_for_irq(irq);
454
455 BUG_ON(info->type != IRQT_PIRQ);
456
7a043f11 457 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
458 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
459 irq_status.flags = 0;
460
461 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
462 if (irq_status.flags & XENIRQSTAT_needs_eoi)
463 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
464}
465
466static bool probing_irq(int irq)
467{
468 struct irq_desc *desc = irq_to_desc(irq);
469
470 return desc && desc->action == NULL;
471}
472
473static unsigned int startup_pirq(unsigned int irq)
474{
475 struct evtchn_bind_pirq bind_pirq;
476 struct irq_info *info = info_for_irq(irq);
477 int evtchn = evtchn_from_irq(irq);
15ebbb82 478 int rc;
d46a78b0
JF
479
480 BUG_ON(info->type != IRQT_PIRQ);
481
482 if (VALID_EVTCHN(evtchn))
483 goto out;
484
7a043f11 485 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 486 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
487 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
488 BIND_PIRQ__WILL_SHARE : 0;
489 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
490 if (rc != 0) {
d46a78b0
JF
491 if (!probing_irq(irq))
492 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
493 irq);
494 return 0;
495 }
496 evtchn = bind_pirq.port;
497
498 pirq_query_unmask(irq);
499
500 evtchn_to_irq[evtchn] = irq;
501 bind_evtchn_to_cpu(evtchn, 0);
502 info->evtchn = evtchn;
503
504out:
505 unmask_evtchn(evtchn);
506 pirq_unmask_notify(irq);
507
508 return 0;
509}
510
511static void shutdown_pirq(unsigned int irq)
512{
513 struct evtchn_close close;
514 struct irq_info *info = info_for_irq(irq);
515 int evtchn = evtchn_from_irq(irq);
516
517 BUG_ON(info->type != IRQT_PIRQ);
518
519 if (!VALID_EVTCHN(evtchn))
520 return;
521
522 mask_evtchn(evtchn);
523
524 close.port = evtchn;
525 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
526 BUG();
527
528 bind_evtchn_to_cpu(evtchn, 0);
529 evtchn_to_irq[evtchn] = -1;
530 info->evtchn = 0;
531}
532
533static void enable_pirq(unsigned int irq)
534{
535 startup_pirq(irq);
536}
537
538static void disable_pirq(unsigned int irq)
539{
540}
541
542static void ack_pirq(unsigned int irq)
543{
544 int evtchn = evtchn_from_irq(irq);
545
546 move_native_irq(irq);
547
548 if (VALID_EVTCHN(evtchn)) {
549 mask_evtchn(evtchn);
550 clear_evtchn(evtchn);
551 }
552}
553
554static void end_pirq(unsigned int irq)
555{
556 int evtchn = evtchn_from_irq(irq);
557 struct irq_desc *desc = irq_to_desc(irq);
558
559 if (WARN_ON(!desc))
560 return;
561
562 if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
563 (IRQ_DISABLED|IRQ_PENDING)) {
564 shutdown_pirq(irq);
565 } else if (VALID_EVTCHN(evtchn)) {
566 unmask_evtchn(evtchn);
567 pirq_unmask_notify(irq);
568 }
569}
570
571static int find_irq_by_gsi(unsigned gsi)
572{
573 int irq;
574
b21ddbf5 575 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
576 struct irq_info *info = info_for_irq(irq);
577
578 if (info == NULL || info->type != IRQT_PIRQ)
579 continue;
580
581 if (gsi_from_irq(irq) == gsi)
582 return irq;
583 }
584
585 return -1;
586}
587
7a043f11
SS
588int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
589{
590 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
591}
592
593/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
594 * consequence don't assume that the irq number returned has a low value
595 * or can be used as a pirq number unless you know otherwise.
596 *
7a043f11 597 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 598 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
599 * matches the gsi number passed as second argument.
600 *
601 * Note: We don't assign an event channel until the irq actually started
602 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 603 */
7a043f11 604int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 605{
7a043f11 606 int irq = 0;
d46a78b0
JF
607 struct physdev_irq irq_op;
608
609 spin_lock(&irq_mapping_update_lock);
610
01557baf
SS
611 if ((pirq > nr_pirqs) || (gsi > nr_irqs)) {
612 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
613 pirq > nr_pirqs ? "nr_pirqs" :"",
614 gsi > nr_irqs ? "nr_irqs" : "");
615 goto out;
616 }
617
d46a78b0
JF
618 irq = find_irq_by_gsi(gsi);
619 if (irq != -1) {
7a043f11 620 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
621 irq, gsi);
622 goto out; /* XXX need refcount? */
623 }
624
b5401a96
AN
625 /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore
626 * we are using the !xen_initial_domain() to drop in the function.*/
3942b740
SS
627 if (identity_mapped_irq(gsi) || (!xen_initial_domain() &&
628 xen_pv_domain())) {
d46a78b0 629 irq = gsi;
2c52f8d3 630 irq_alloc_desc_at(irq, 0);
d46a78b0
JF
631 } else
632 irq = find_unbound_irq();
633
634 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 635 handle_level_irq, name);
d46a78b0
JF
636
637 irq_op.irq = irq;
b5401a96
AN
638 irq_op.vector = 0;
639
640 /* Only the privileged domain can do this. For non-priv, the pcifront
641 * driver provides a PCI bus that does the call to do exactly
642 * this in the priv domain. */
643 if (xen_initial_domain() &&
644 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
2c52f8d3 645 irq_free_desc(irq);
d46a78b0
JF
646 irq = -ENOSPC;
647 goto out;
648 }
649
7a043f11 650 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 651 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 652 pirq_to_irq[pirq] = irq;
d46a78b0
JF
653
654out:
655 spin_unlock(&irq_mapping_update_lock);
656
657 return irq;
658}
659
f731e3ef
QH
660#ifdef CONFIG_PCI_MSI
661#include <linux/msi.h>
662#include "../pci/msi.h"
663
809f9267
SS
664void xen_allocate_pirq_msi(char *name, int *irq, int *pirq)
665{
666 spin_lock(&irq_mapping_update_lock);
667
668 *irq = find_unbound_irq();
669 if (*irq == -1)
670 goto out;
671
672 *pirq = find_unbound_pirq();
673 if (*pirq == -1)
674 goto out;
675
676 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
677 handle_level_irq, name);
678
679 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
680 pirq_to_irq[*pirq] = *irq;
681
682out:
683 spin_unlock(&irq_mapping_update_lock);
684}
685
f731e3ef
QH
686int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
687{
688 int irq = -1;
689 struct physdev_map_pirq map_irq;
690 int rc;
691 int pos;
692 u32 table_offset, bir;
693
694 memset(&map_irq, 0, sizeof(map_irq));
695 map_irq.domid = DOMID_SELF;
696 map_irq.type = MAP_PIRQ_TYPE_MSI;
697 map_irq.index = -1;
698 map_irq.pirq = -1;
699 map_irq.bus = dev->bus->number;
700 map_irq.devfn = dev->devfn;
701
702 if (type == PCI_CAP_ID_MSIX) {
703 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
704
705 pci_read_config_dword(dev, msix_table_offset_reg(pos),
706 &table_offset);
707 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
708
709 map_irq.table_base = pci_resource_start(dev, bir);
710 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
711 }
712
713 spin_lock(&irq_mapping_update_lock);
714
715 irq = find_unbound_irq();
716
717 if (irq == -1)
718 goto out;
719
720 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
721 if (rc) {
722 printk(KERN_WARNING "xen map irq failed %d\n", rc);
723
724 irq_free_desc(irq);
725
726 irq = -1;
727 goto out;
728 }
729 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
730
731 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
732 handle_level_irq,
733 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
734
735out:
736 spin_unlock(&irq_mapping_update_lock);
737 return irq;
738}
739#endif
740
b5401a96
AN
741int xen_destroy_irq(int irq)
742{
743 struct irq_desc *desc;
38aa66fc
JF
744 struct physdev_unmap_pirq unmap_irq;
745 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
746 int rc = -ENOENT;
747
748 spin_lock(&irq_mapping_update_lock);
749
750 desc = irq_to_desc(irq);
751 if (!desc)
752 goto out;
753
38aa66fc
JF
754 if (xen_initial_domain()) {
755 unmap_irq.pirq = info->u.pirq.gsi;
756 unmap_irq.domid = DOMID_SELF;
757 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
758 if (rc) {
759 printk(KERN_WARNING "unmap irq failed %d\n", rc);
760 goto out;
761 }
762 }
b5401a96
AN
763 irq_info[irq] = mk_unbound_info();
764
2c52f8d3 765 irq_free_desc(irq);
b5401a96
AN
766
767out:
768 spin_unlock(&irq_mapping_update_lock);
769 return rc;
770}
771
d46a78b0
JF
772int xen_vector_from_irq(unsigned irq)
773{
774 return vector_from_irq(irq);
775}
776
777int xen_gsi_from_irq(unsigned irq)
778{
779 return gsi_from_irq(irq);
e46cdb66
JF
780}
781
b536b4b9 782int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
783{
784 int irq;
785
786 spin_lock(&irq_mapping_update_lock);
787
788 irq = evtchn_to_irq[evtchn];
789
790 if (irq == -1) {
791 irq = find_unbound_irq();
792
e46cdb66 793 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 794 handle_fasteoi_irq, "event");
e46cdb66
JF
795
796 evtchn_to_irq[evtchn] = irq;
ced40d0f 797 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
798 }
799
e46cdb66
JF
800 spin_unlock(&irq_mapping_update_lock);
801
802 return irq;
803}
b536b4b9 804EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 805
f87e4cac
JF
806static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
807{
808 struct evtchn_bind_ipi bind_ipi;
809 int evtchn, irq;
810
811 spin_lock(&irq_mapping_update_lock);
812
813 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 814
f87e4cac
JF
815 if (irq == -1) {
816 irq = find_unbound_irq();
817 if (irq < 0)
818 goto out;
819
aaca4964
JF
820 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
821 handle_percpu_irq, "ipi");
f87e4cac
JF
822
823 bind_ipi.vcpu = cpu;
824 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
825 &bind_ipi) != 0)
826 BUG();
827 evtchn = bind_ipi.port;
828
829 evtchn_to_irq[evtchn] = irq;
ced40d0f 830 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
831 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
832
833 bind_evtchn_to_cpu(evtchn, cpu);
834 }
835
f87e4cac
JF
836 out:
837 spin_unlock(&irq_mapping_update_lock);
838 return irq;
839}
840
841
4fe7d5a7 842int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
843{
844 struct evtchn_bind_virq bind_virq;
845 int evtchn, irq;
846
847 spin_lock(&irq_mapping_update_lock);
848
849 irq = per_cpu(virq_to_irq, cpu)[virq];
850
851 if (irq == -1) {
a52521f1
JF
852 irq = find_unbound_irq();
853
854 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
855 handle_percpu_irq, "virq");
856
e46cdb66
JF
857 bind_virq.virq = virq;
858 bind_virq.vcpu = cpu;
859 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
860 &bind_virq) != 0)
861 BUG();
862 evtchn = bind_virq.port;
863
e46cdb66 864 evtchn_to_irq[evtchn] = irq;
ced40d0f 865 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
866
867 per_cpu(virq_to_irq, cpu)[virq] = irq;
868
869 bind_evtchn_to_cpu(evtchn, cpu);
870 }
871
e46cdb66
JF
872 spin_unlock(&irq_mapping_update_lock);
873
874 return irq;
875}
876
877static void unbind_from_irq(unsigned int irq)
878{
879 struct evtchn_close close;
880 int evtchn = evtchn_from_irq(irq);
881
882 spin_lock(&irq_mapping_update_lock);
883
d77bbd4d 884 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
885 close.port = evtchn;
886 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
887 BUG();
888
889 switch (type_from_irq(irq)) {
890 case IRQT_VIRQ:
891 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 892 [virq_from_irq(irq)] = -1;
e46cdb66 893 break;
d68d82af
AN
894 case IRQT_IPI:
895 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 896 [ipi_from_irq(irq)] = -1;
d68d82af 897 break;
e46cdb66
JF
898 default:
899 break;
900 }
901
902 /* Closed ports are implicitly re-bound to VCPU0. */
903 bind_evtchn_to_cpu(evtchn, 0);
904
905 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
906 }
907
908 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 909 irq_info[irq] = mk_unbound_info();
e46cdb66 910
77dff1c7 911 irq_free_desc(irq);
e46cdb66
JF
912 }
913
914 spin_unlock(&irq_mapping_update_lock);
915}
916
917int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 918 irq_handler_t handler,
e46cdb66
JF
919 unsigned long irqflags,
920 const char *devname, void *dev_id)
921{
922 unsigned int irq;
923 int retval;
924
925 irq = bind_evtchn_to_irq(evtchn);
926 retval = request_irq(irq, handler, irqflags, devname, dev_id);
927 if (retval != 0) {
928 unbind_from_irq(irq);
929 return retval;
930 }
931
932 return irq;
933}
934EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
935
936int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 937 irq_handler_t handler,
e46cdb66
JF
938 unsigned long irqflags, const char *devname, void *dev_id)
939{
940 unsigned int irq;
941 int retval;
942
943 irq = bind_virq_to_irq(virq, cpu);
944 retval = request_irq(irq, handler, irqflags, devname, dev_id);
945 if (retval != 0) {
946 unbind_from_irq(irq);
947 return retval;
948 }
949
950 return irq;
951}
952EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
953
f87e4cac
JF
954int bind_ipi_to_irqhandler(enum ipi_vector ipi,
955 unsigned int cpu,
956 irq_handler_t handler,
957 unsigned long irqflags,
958 const char *devname,
959 void *dev_id)
960{
961 int irq, retval;
962
963 irq = bind_ipi_to_irq(ipi, cpu);
964 if (irq < 0)
965 return irq;
966
4877c737 967 irqflags |= IRQF_NO_SUSPEND;
f87e4cac
JF
968 retval = request_irq(irq, handler, irqflags, devname, dev_id);
969 if (retval != 0) {
970 unbind_from_irq(irq);
971 return retval;
972 }
973
974 return irq;
975}
976
e46cdb66
JF
977void unbind_from_irqhandler(unsigned int irq, void *dev_id)
978{
979 free_irq(irq, dev_id);
980 unbind_from_irq(irq);
981}
982EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
983
f87e4cac
JF
984void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
985{
986 int irq = per_cpu(ipi_to_irq, cpu)[vector];
987 BUG_ON(irq < 0);
988 notify_remote_via_irq(irq);
989}
990
ee523ca1
JF
991irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
992{
993 struct shared_info *sh = HYPERVISOR_shared_info;
994 int cpu = smp_processor_id();
cb52e6d9 995 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
996 int i;
997 unsigned long flags;
998 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 999 struct vcpu_info *v;
ee523ca1
JF
1000
1001 spin_lock_irqsave(&debug_lock, flags);
1002
cb52e6d9 1003 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1004
1005 for_each_online_cpu(i) {
cb52e6d9
IC
1006 int pending;
1007 v = per_cpu(xen_vcpu, i);
1008 pending = (get_irq_regs() && i == cpu)
1009 ? xen_irqs_disabled(get_irq_regs())
1010 : v->evtchn_upcall_mask;
1011 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1012 pending, v->evtchn_upcall_pending,
1013 (int)(sizeof(v->evtchn_pending_sel)*2),
1014 v->evtchn_pending_sel);
1015 }
1016 v = per_cpu(xen_vcpu, cpu);
1017
1018 printk("\npending:\n ");
1019 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1020 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1021 sh->evtchn_pending[i],
1022 i % 8 == 0 ? "\n " : " ");
1023 printk("\nglobal mask:\n ");
1024 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1025 printk("%0*lx%s",
1026 (int)(sizeof(sh->evtchn_mask[0])*2),
1027 sh->evtchn_mask[i],
1028 i % 8 == 0 ? "\n " : " ");
1029
1030 printk("\nglobally unmasked:\n ");
1031 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1032 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1033 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1034 i % 8 == 0 ? "\n " : " ");
1035
1036 printk("\nlocal cpu%d mask:\n ", cpu);
1037 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1038 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1039 cpu_evtchn[i],
1040 i % 8 == 0 ? "\n " : " ");
1041
1042 printk("\nlocally unmasked:\n ");
1043 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1044 unsigned long pending = sh->evtchn_pending[i]
1045 & ~sh->evtchn_mask[i]
1046 & cpu_evtchn[i];
1047 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1048 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1049 }
ee523ca1
JF
1050
1051 printk("\npending list:\n");
cb52e6d9 1052 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1053 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1054 int word_idx = i / BITS_PER_LONG;
1055 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1056 cpu_from_evtchn(i), i,
cb52e6d9
IC
1057 evtchn_to_irq[i],
1058 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1059 ? "" : " l2-clear",
1060 !sync_test_bit(i, sh->evtchn_mask)
1061 ? "" : " globally-masked",
1062 sync_test_bit(i, cpu_evtchn)
1063 ? "" : " locally-masked");
ee523ca1
JF
1064 }
1065 }
1066
1067 spin_unlock_irqrestore(&debug_lock, flags);
1068
1069 return IRQ_HANDLED;
1070}
1071
245b2e70
TH
1072static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1073
e46cdb66
JF
1074/*
1075 * Search the CPUs pending events bitmasks. For each one found, map
1076 * the event number to an irq, and feed it into do_IRQ() for
1077 * handling.
1078 *
1079 * Xen uses a two-level bitmap to speed searching. The first level is
1080 * a bitset of words which contain pending event bits. The second
1081 * level is a bitset of pending events themselves.
1082 */
38e20b07 1083static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1084{
1085 int cpu = get_cpu();
1086 struct shared_info *s = HYPERVISOR_shared_info;
1087 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
229664be 1088 unsigned count;
e46cdb66 1089
229664be
JF
1090 do {
1091 unsigned long pending_words;
e46cdb66 1092
229664be 1093 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1094
245b2e70 1095 if (__get_cpu_var(xed_nesting_count)++)
229664be 1096 goto out;
e46cdb66 1097
e849c3e9
IY
1098#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1099 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1100 wmb();
e849c3e9 1101#endif
229664be
JF
1102 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1103 while (pending_words != 0) {
1104 unsigned long pending_bits;
1105 int word_idx = __ffs(pending_words);
1106 pending_words &= ~(1UL << word_idx);
1107
1108 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1109 int bit_idx = __ffs(pending_bits);
1110 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1111 int irq = evtchn_to_irq[port];
ca4dbc66 1112 struct irq_desc *desc;
229664be 1113
3588fe2e
JF
1114 mask_evtchn(port);
1115 clear_evtchn(port);
1116
ca4dbc66
EB
1117 if (irq != -1) {
1118 desc = irq_to_desc(irq);
1119 if (desc)
1120 generic_handle_irq_desc(irq, desc);
1121 }
e46cdb66
JF
1122 }
1123 }
e46cdb66 1124
229664be
JF
1125 BUG_ON(!irqs_disabled());
1126
245b2e70
TH
1127 count = __get_cpu_var(xed_nesting_count);
1128 __get_cpu_var(xed_nesting_count) = 0;
183d03cc 1129 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1130
1131out:
38e20b07
SY
1132
1133 put_cpu();
1134}
1135
1136void xen_evtchn_do_upcall(struct pt_regs *regs)
1137{
1138 struct pt_regs *old_regs = set_irq_regs(regs);
1139
1140 exit_idle();
1141 irq_enter();
1142
1143 __xen_evtchn_do_upcall();
1144
3445a8fd
JF
1145 irq_exit();
1146 set_irq_regs(old_regs);
38e20b07 1147}
3445a8fd 1148
38e20b07
SY
1149void xen_hvm_evtchn_do_upcall(void)
1150{
1151 __xen_evtchn_do_upcall();
e46cdb66 1152}
183d03cc 1153EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1154
eb1e305f
JF
1155/* Rebind a new event channel to an existing irq. */
1156void rebind_evtchn_irq(int evtchn, int irq)
1157{
d77bbd4d
JF
1158 struct irq_info *info = info_for_irq(irq);
1159
eb1e305f
JF
1160 /* Make sure the irq is masked, since the new event channel
1161 will also be masked. */
1162 disable_irq(irq);
1163
1164 spin_lock(&irq_mapping_update_lock);
1165
1166 /* After resume the irq<->evtchn mappings are all cleared out */
1167 BUG_ON(evtchn_to_irq[evtchn] != -1);
1168 /* Expect irq to have been bound before,
d77bbd4d
JF
1169 so there should be a proper type */
1170 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1171
1172 evtchn_to_irq[evtchn] = irq;
ced40d0f 1173 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1174
1175 spin_unlock(&irq_mapping_update_lock);
1176
1177 /* new event channels are always bound to cpu 0 */
0de26520 1178 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1179
1180 /* Unmask the event channel. */
1181 enable_irq(irq);
1182}
1183
e46cdb66 1184/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1185static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1186{
1187 struct evtchn_bind_vcpu bind_vcpu;
1188 int evtchn = evtchn_from_irq(irq);
1189
183d03cc
SS
1190 /* events delivered via platform PCI interrupts are always
1191 * routed to vcpu 0 */
1192 if (!VALID_EVTCHN(evtchn) ||
1193 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1194 return -1;
e46cdb66
JF
1195
1196 /* Send future instances of this interrupt to other vcpu. */
1197 bind_vcpu.port = evtchn;
1198 bind_vcpu.vcpu = tcpu;
1199
1200 /*
1201 * If this fails, it usually just indicates that we're dealing with a
1202 * virq or IPI channel, which don't actually need to be rebound. Ignore
1203 * it, but don't do the xenlinux-level rebind in that case.
1204 */
1205 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1206 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1207
d5dedd45
YL
1208 return 0;
1209}
e46cdb66 1210
d5dedd45 1211static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
e46cdb66 1212{
0de26520 1213 unsigned tcpu = cpumask_first(dest);
d5dedd45
YL
1214
1215 return rebind_irq_to_cpu(irq, tcpu);
e46cdb66
JF
1216}
1217
642e0c88
IY
1218int resend_irq_on_evtchn(unsigned int irq)
1219{
1220 int masked, evtchn = evtchn_from_irq(irq);
1221 struct shared_info *s = HYPERVISOR_shared_info;
1222
1223 if (!VALID_EVTCHN(evtchn))
1224 return 1;
1225
1226 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1227 sync_set_bit(evtchn, s->evtchn_pending);
1228 if (!masked)
1229 unmask_evtchn(evtchn);
1230
1231 return 1;
1232}
1233
e46cdb66
JF
1234static void enable_dynirq(unsigned int irq)
1235{
1236 int evtchn = evtchn_from_irq(irq);
1237
1238 if (VALID_EVTCHN(evtchn))
1239 unmask_evtchn(evtchn);
1240}
1241
1242static void disable_dynirq(unsigned int irq)
1243{
1244 int evtchn = evtchn_from_irq(irq);
1245
1246 if (VALID_EVTCHN(evtchn))
1247 mask_evtchn(evtchn);
1248}
1249
1250static void ack_dynirq(unsigned int irq)
1251{
1252 int evtchn = evtchn_from_irq(irq);
1253
3588fe2e 1254 move_masked_irq(irq);
e46cdb66
JF
1255
1256 if (VALID_EVTCHN(evtchn))
3588fe2e 1257 unmask_evtchn(evtchn);
e46cdb66
JF
1258}
1259
1260static int retrigger_dynirq(unsigned int irq)
1261{
1262 int evtchn = evtchn_from_irq(irq);
ee8fa1c6 1263 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1264 int ret = 0;
1265
1266 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1267 int masked;
1268
1269 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1270 sync_set_bit(evtchn, sh->evtchn_pending);
1271 if (!masked)
1272 unmask_evtchn(evtchn);
e46cdb66
JF
1273 ret = 1;
1274 }
1275
1276 return ret;
1277}
1278
0e91398f
JF
1279static void restore_cpu_virqs(unsigned int cpu)
1280{
1281 struct evtchn_bind_virq bind_virq;
1282 int virq, irq, evtchn;
1283
1284 for (virq = 0; virq < NR_VIRQS; virq++) {
1285 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1286 continue;
1287
ced40d0f 1288 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1289
1290 /* Get a new binding from Xen. */
1291 bind_virq.virq = virq;
1292 bind_virq.vcpu = cpu;
1293 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1294 &bind_virq) != 0)
1295 BUG();
1296 evtchn = bind_virq.port;
1297
1298 /* Record the new mapping. */
1299 evtchn_to_irq[evtchn] = irq;
ced40d0f 1300 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1301 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1302 }
1303}
1304
1305static void restore_cpu_ipis(unsigned int cpu)
1306{
1307 struct evtchn_bind_ipi bind_ipi;
1308 int ipi, irq, evtchn;
1309
1310 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1311 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1312 continue;
1313
ced40d0f 1314 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1315
1316 /* Get a new binding from Xen. */
1317 bind_ipi.vcpu = cpu;
1318 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1319 &bind_ipi) != 0)
1320 BUG();
1321 evtchn = bind_ipi.port;
1322
1323 /* Record the new mapping. */
1324 evtchn_to_irq[evtchn] = irq;
ced40d0f 1325 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1326 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1327 }
1328}
1329
2d9e1e2f
JF
1330/* Clear an irq's pending state, in preparation for polling on it */
1331void xen_clear_irq_pending(int irq)
1332{
1333 int evtchn = evtchn_from_irq(irq);
1334
1335 if (VALID_EVTCHN(evtchn))
1336 clear_evtchn(evtchn);
1337}
d9a8814f 1338EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1339void xen_set_irq_pending(int irq)
1340{
1341 int evtchn = evtchn_from_irq(irq);
1342
1343 if (VALID_EVTCHN(evtchn))
1344 set_evtchn(evtchn);
1345}
1346
1347bool xen_test_irq_pending(int irq)
1348{
1349 int evtchn = evtchn_from_irq(irq);
1350 bool ret = false;
1351
1352 if (VALID_EVTCHN(evtchn))
1353 ret = test_evtchn(evtchn);
1354
1355 return ret;
1356}
1357
d9a8814f
KRW
1358/* Poll waiting for an irq to become pending with timeout. In the usual case,
1359 * the irq will be disabled so it won't deliver an interrupt. */
1360void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1361{
1362 evtchn_port_t evtchn = evtchn_from_irq(irq);
1363
1364 if (VALID_EVTCHN(evtchn)) {
1365 struct sched_poll poll;
1366
1367 poll.nr_ports = 1;
d9a8814f 1368 poll.timeout = timeout;
ff3c5362 1369 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1370
1371 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1372 BUG();
1373 }
1374}
d9a8814f
KRW
1375EXPORT_SYMBOL(xen_poll_irq_timeout);
1376/* Poll waiting for an irq to become pending. In the usual case, the
1377 * irq will be disabled so it won't deliver an interrupt. */
1378void xen_poll_irq(int irq)
1379{
1380 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1381}
2d9e1e2f 1382
0e91398f
JF
1383void xen_irq_resume(void)
1384{
1385 unsigned int cpu, irq, evtchn;
6903591f 1386 struct irq_desc *desc;
0e91398f
JF
1387
1388 init_evtchn_cpu_bindings();
1389
1390 /* New event-channel space is not 'live' yet. */
1391 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1392 mask_evtchn(evtchn);
1393
1394 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1395 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1396 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1397
1398 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1399 evtchn_to_irq[evtchn] = -1;
1400
1401 for_each_possible_cpu(cpu) {
1402 restore_cpu_virqs(cpu);
1403 restore_cpu_ipis(cpu);
1404 }
6903591f
IC
1405
1406 /*
1407 * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
1408 * are not handled by the IRQ core.
1409 */
1410 for_each_irq_desc(irq, desc) {
1411 if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
1412 continue;
1413 if (desc->status & IRQ_DISABLED)
1414 continue;
1415
1416 evtchn = evtchn_from_irq(irq);
1417 if (evtchn == -1)
1418 continue;
1419
1420 unmask_evtchn(evtchn);
1421 }
0e91398f
JF
1422}
1423
e46cdb66
JF
1424static struct irq_chip xen_dynamic_chip __read_mostly = {
1425 .name = "xen-dyn",
54a353a0
JF
1426
1427 .disable = disable_dynirq,
e46cdb66
JF
1428 .mask = disable_dynirq,
1429 .unmask = enable_dynirq,
54a353a0 1430
3588fe2e 1431 .eoi = ack_dynirq,
e46cdb66
JF
1432 .set_affinity = set_affinity_irq,
1433 .retrigger = retrigger_dynirq,
1434};
1435
d46a78b0
JF
1436static struct irq_chip xen_pirq_chip __read_mostly = {
1437 .name = "xen-pirq",
1438
1439 .startup = startup_pirq,
1440 .shutdown = shutdown_pirq,
1441
1442 .enable = enable_pirq,
1443 .unmask = enable_pirq,
1444
1445 .disable = disable_pirq,
1446 .mask = disable_pirq,
1447
1448 .ack = ack_pirq,
1449 .end = end_pirq,
1450
1451 .set_affinity = set_affinity_irq,
1452
1453 .retrigger = retrigger_dynirq,
1454};
1455
aaca4964
JF
1456static struct irq_chip xen_percpu_chip __read_mostly = {
1457 .name = "xen-percpu",
1458
1459 .disable = disable_dynirq,
1460 .mask = disable_dynirq,
1461 .unmask = enable_dynirq,
1462
1463 .ack = ack_dynirq,
1464};
1465
38e20b07
SY
1466int xen_set_callback_via(uint64_t via)
1467{
1468 struct xen_hvm_param a;
1469 a.domid = DOMID_SELF;
1470 a.index = HVM_PARAM_CALLBACK_IRQ;
1471 a.value = via;
1472 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1473}
1474EXPORT_SYMBOL_GPL(xen_set_callback_via);
1475
ca65f9fc 1476#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1477/* Vector callbacks are better than PCI interrupts to receive event
1478 * channel notifications because we can receive vector callbacks on any
1479 * vcpu and we don't need PCI support or APIC interactions. */
1480void xen_callback_vector(void)
1481{
1482 int rc;
1483 uint64_t callback_via;
1484 if (xen_have_vector_callback) {
1485 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1486 rc = xen_set_callback_via(callback_via);
1487 if (rc) {
1488 printk(KERN_ERR "Request for Xen HVM callback vector"
1489 " failed.\n");
1490 xen_have_vector_callback = 0;
1491 return;
1492 }
1493 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1494 "enabled\n");
1495 /* in the restore case the vector has already been allocated */
1496 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1497 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1498 }
1499}
ca65f9fc
SS
1500#else
1501void xen_callback_vector(void) {}
1502#endif
38e20b07 1503
e46cdb66
JF
1504void __init xen_init_IRQ(void)
1505{
01557baf
SS
1506 int i, rc;
1507 struct physdev_nr_pirqs op_nr_pirqs;
c7a3589e 1508
a70c352a
PE
1509 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1510 GFP_KERNEL);
b21ddbf5
JF
1511 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1512
01557baf
SS
1513 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_nr_pirqs, &op_nr_pirqs);
1514 if (rc < 0) {
1515 nr_pirqs = nr_irqs;
1516 if (rc != -ENOSYS)
1517 printk(KERN_WARNING "PHYSDEVOP_get_nr_pirqs returned rc=%d\n", rc);
1518 } else {
1519 if (xen_pv_domain() && !xen_initial_domain())
1520 nr_pirqs = max((int)op_nr_pirqs.nr_pirqs, nr_irqs);
1521 else
1522 nr_pirqs = op_nr_pirqs.nr_pirqs;
1523 }
1524 pirq_to_irq = kcalloc(nr_pirqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1525 for (i = 0; i < nr_pirqs; i++)
7a043f11
SS
1526 pirq_to_irq[i] = -1;
1527
b21ddbf5
JF
1528 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1529 GFP_KERNEL);
1530 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1531 evtchn_to_irq[i] = -1;
e46cdb66
JF
1532
1533 init_evtchn_cpu_bindings();
1534
1535 /* No event channels are 'live' right now. */
1536 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1537 mask_evtchn(i);
1538
38e20b07
SY
1539 if (xen_hvm_domain()) {
1540 xen_callback_vector();
1541 native_init_IRQ();
3942b740
SS
1542 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1543 * __acpi_register_gsi can point at the right function */
1544 pci_xen_hvm_init();
38e20b07
SY
1545 } else {
1546 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1547 if (xen_initial_domain())
1548 xen_setup_pirqs();
38e20b07 1549 }
e46cdb66 1550}