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[net-next-2.6.git] / drivers / watchdog / s3c2410_wdt.c
CommitLineData
1da177e4
LT
1/* linux/drivers/char/watchdog/s3c2410_wdt.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Watchdog Timer Support
7 *
8 * Based on, softdog.c by Alan Cox,
29fa0586 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4
LT
24*/
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
1da177e4
LT
28#include <linux/types.h>
29#include <linux/timer.h>
30#include <linux/miscdevice.h>
31#include <linux/watchdog.h>
32#include <linux/fs.h>
1da177e4 33#include <linux/init.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4 35#include <linux/interrupt.h>
f8ce2547 36#include <linux/clk.h>
41dc8b72
AC
37#include <linux/uaccess.h>
38#include <linux/io.h>
e02f838e 39#include <linux/cpufreq.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4 41
a09e64fb 42#include <mach/map.h>
1da177e4 43
b430708a
BD
44#undef S3C_VA_WATCHDOG
45#define S3C_VA_WATCHDOG (0)
1da177e4 46
180ee700 47#include <plat/regs-watchdog.h>
1da177e4
LT
48
49#define PFX "s3c2410-wdt: "
50
51#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
52#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
53
25ff3780 54static int nowayout = WATCHDOG_NOWAYOUT;
1da177e4
LT
55static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
56static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
41dc8b72
AC
57static int soft_noboot;
58static int debug;
1da177e4
LT
59
60module_param(tmr_margin, int, 0);
61module_param(tmr_atboot, int, 0);
62module_param(nowayout, int, 0);
63module_param(soft_noboot, int, 0);
64module_param(debug, int, 0);
65
41dc8b72
AC
66MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
67 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
68MODULE_PARM_DESC(tmr_atboot,
69 "Watchdog is started at boot time if set to 1, default="
70 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
71MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
72 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
a77dba7e
WVS
73MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
74 "0 to reboot (default depends on ONLY_TESTING)");
1da177e4
LT
75MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
76
41dc8b72 77static unsigned long open_lock;
e8ef92b8 78static struct device *wdt_dev; /* platform device attached to */
1da177e4
LT
79static struct resource *wdt_mem;
80static struct resource *wdt_irq;
81static struct clk *wdt_clock;
82static void __iomem *wdt_base;
83static unsigned int wdt_count;
a77dba7e 84static char expect_close;
41dc8b72 85static DEFINE_SPINLOCK(wdt_lock);
1da177e4
LT
86
87/* watchdog control routines */
88
89#define DBG(msg...) do { \
90 if (debug) \
91 printk(KERN_INFO msg); \
41dc8b72 92 } while (0)
1da177e4
LT
93
94/* functions */
95
41dc8b72 96static void s3c2410wdt_keepalive(void)
1da177e4 97{
41dc8b72 98 spin_lock(&wdt_lock);
1da177e4 99 writel(wdt_count, wdt_base + S3C2410_WTCNT);
41dc8b72 100 spin_unlock(&wdt_lock);
1da177e4
LT
101}
102
41dc8b72
AC
103static void __s3c2410wdt_stop(void)
104{
105 unsigned long wtcon;
106
107 wtcon = readl(wdt_base + S3C2410_WTCON);
108 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
109 writel(wtcon, wdt_base + S3C2410_WTCON);
110}
111
112static void s3c2410wdt_stop(void)
113{
114 spin_lock(&wdt_lock);
115 __s3c2410wdt_stop();
116 spin_unlock(&wdt_lock);
1da177e4
LT
117}
118
41dc8b72 119static void s3c2410wdt_start(void)
1da177e4
LT
120{
121 unsigned long wtcon;
122
41dc8b72
AC
123 spin_lock(&wdt_lock);
124
125 __s3c2410wdt_stop();
1da177e4
LT
126
127 wtcon = readl(wdt_base + S3C2410_WTCON);
128 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
129
130 if (soft_noboot) {
131 wtcon |= S3C2410_WTCON_INTEN;
132 wtcon &= ~S3C2410_WTCON_RSTEN;
133 } else {
134 wtcon &= ~S3C2410_WTCON_INTEN;
135 wtcon |= S3C2410_WTCON_RSTEN;
136 }
137
138 DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
fa9363c5 139 __func__, wdt_count, wtcon);
1da177e4
LT
140
141 writel(wdt_count, wdt_base + S3C2410_WTDAT);
142 writel(wdt_count, wdt_base + S3C2410_WTCNT);
143 writel(wtcon, wdt_base + S3C2410_WTCON);
41dc8b72 144 spin_unlock(&wdt_lock);
1da177e4
LT
145}
146
e02f838e
BD
147static inline int s3c2410wdt_is_running(void)
148{
149 return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
150}
151
1da177e4
LT
152static int s3c2410wdt_set_heartbeat(int timeout)
153{
e02f838e 154 unsigned long freq = clk_get_rate(wdt_clock);
1da177e4
LT
155 unsigned int count;
156 unsigned int divisor = 1;
157 unsigned long wtcon;
158
159 if (timeout < 1)
160 return -EINVAL;
161
162 freq /= 128;
163 count = timeout * freq;
164
e02f838e 165 DBG("%s: count=%d, timeout=%d, freq=%lu\n",
fa9363c5 166 __func__, count, timeout, freq);
1da177e4
LT
167
168 /* if the count is bigger than the watchdog register,
169 then work out what we need to do (and if) we can
170 actually make this value
171 */
172
173 if (count >= 0x10000) {
174 for (divisor = 1; divisor <= 0x100; divisor++) {
175 if ((count / divisor) < 0x10000)
176 break;
177 }
178
179 if ((count / divisor) >= 0x10000) {
e8ef92b8 180 dev_err(wdt_dev, "timeout %d too big\n", timeout);
1da177e4
LT
181 return -EINVAL;
182 }
183 }
184
185 tmr_margin = timeout;
186
187 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
fa9363c5 188 __func__, timeout, divisor, count, count/divisor);
1da177e4
LT
189
190 count /= divisor;
191 wdt_count = count;
192
193 /* update the pre-scaler */
194 wtcon = readl(wdt_base + S3C2410_WTCON);
195 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
196 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
197
198 writel(count, wdt_base + S3C2410_WTDAT);
199 writel(wtcon, wdt_base + S3C2410_WTCON);
200
201 return 0;
202}
203
204/*
205 * /dev/watchdog handling
206 */
207
208static int s3c2410wdt_open(struct inode *inode, struct file *file)
209{
41dc8b72 210 if (test_and_set_bit(0, &open_lock))
1da177e4
LT
211 return -EBUSY;
212
25ff3780 213 if (nowayout)
1da177e4 214 __module_get(THIS_MODULE);
25ff3780 215
a77dba7e 216 expect_close = 0;
1da177e4
LT
217
218 /* start the timer */
219 s3c2410wdt_start();
220 return nonseekable_open(inode, file);
221}
222
223static int s3c2410wdt_release(struct inode *inode, struct file *file)
224{
225 /*
226 * Shut off the timer.
227 * Lock it in if it's a module and we set nowayout
228 */
25ff3780 229
a77dba7e 230 if (expect_close == 42)
1da177e4 231 s3c2410wdt_stop();
41dc8b72 232 else {
e8ef92b8 233 dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
1da177e4
LT
234 s3c2410wdt_keepalive();
235 }
a77dba7e 236 expect_close = 0;
41dc8b72 237 clear_bit(0, &open_lock);
1da177e4
LT
238 return 0;
239}
240
241static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
242 size_t len, loff_t *ppos)
243{
244 /*
245 * Refresh the timer.
246 */
41dc8b72 247 if (len) {
1da177e4
LT
248 if (!nowayout) {
249 size_t i;
250
251 /* In case it was set long ago */
a77dba7e 252 expect_close = 0;
1da177e4
LT
253
254 for (i = 0; i != len; i++) {
255 char c;
256
257 if (get_user(c, data + i))
258 return -EFAULT;
259 if (c == 'V')
a77dba7e 260 expect_close = 42;
1da177e4
LT
261 }
262 }
1da177e4
LT
263 s3c2410wdt_keepalive();
264 }
265 return len;
266}
267
a77dba7e 268#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
1da177e4 269
41dc8b72 270static const struct watchdog_info s3c2410_wdt_ident = {
1da177e4
LT
271 .options = OPTIONS,
272 .firmware_version = 0,
273 .identity = "S3C2410 Watchdog",
274};
275
276
41dc8b72
AC
277static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
278 unsigned long arg)
1da177e4
LT
279{
280 void __user *argp = (void __user *)arg;
281 int __user *p = argp;
282 int new_margin;
283
284 switch (cmd) {
41dc8b72
AC
285 case WDIOC_GETSUPPORT:
286 return copy_to_user(argp, &s3c2410_wdt_ident,
287 sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
288 case WDIOC_GETSTATUS:
289 case WDIOC_GETBOOTSTATUS:
290 return put_user(0, p);
291 case WDIOC_KEEPALIVE:
292 s3c2410wdt_keepalive();
293 return 0;
294 case WDIOC_SETTIMEOUT:
295 if (get_user(new_margin, p))
296 return -EFAULT;
297 if (s3c2410wdt_set_heartbeat(new_margin))
298 return -EINVAL;
299 s3c2410wdt_keepalive();
300 return put_user(tmr_margin, p);
301 case WDIOC_GETTIMEOUT:
302 return put_user(tmr_margin, p);
0c06090c
WVS
303 default:
304 return -ENOTTY;
1da177e4
LT
305 }
306}
307
1da177e4
LT
308/* kernel interface */
309
62322d25 310static const struct file_operations s3c2410wdt_fops = {
1da177e4
LT
311 .owner = THIS_MODULE,
312 .llseek = no_llseek,
313 .write = s3c2410wdt_write,
41dc8b72 314 .unlocked_ioctl = s3c2410wdt_ioctl,
1da177e4
LT
315 .open = s3c2410wdt_open,
316 .release = s3c2410wdt_release,
317};
318
319static struct miscdevice s3c2410wdt_miscdev = {
320 .minor = WATCHDOG_MINOR,
321 .name = "watchdog",
322 .fops = &s3c2410wdt_fops,
323};
324
1da177e4
LT
325/* interrupt handler code */
326
7d12e780 327static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
1da177e4 328{
e8ef92b8 329 dev_info(wdt_dev, "watchdog timer expired (irq)\n");
1da177e4
LT
330
331 s3c2410wdt_keepalive();
332 return IRQ_HANDLED;
333}
e02f838e
BD
334
335
336#ifdef CONFIG_CPU_FREQ
337
338static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
339 unsigned long val, void *data)
340{
341 int ret;
342
343 if (!s3c2410wdt_is_running())
344 goto done;
345
346 if (val == CPUFREQ_PRECHANGE) {
347 /* To ensure that over the change we don't cause the
348 * watchdog to trigger, we perform an keep-alive if
349 * the watchdog is running.
350 */
351
352 s3c2410wdt_keepalive();
353 } else if (val == CPUFREQ_POSTCHANGE) {
354 s3c2410wdt_stop();
355
356 ret = s3c2410wdt_set_heartbeat(tmr_margin);
357
358 if (ret >= 0)
359 s3c2410wdt_start();
360 else
361 goto err;
362 }
363
364done:
365 return 0;
366
367 err:
368 dev_err(wdt_dev, "cannot set new value for timeout %d\n", tmr_margin);
369 return ret;
370}
371
372static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
373 .notifier_call = s3c2410wdt_cpufreq_transition,
374};
375
376static inline int s3c2410wdt_cpufreq_register(void)
377{
378 return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
379 CPUFREQ_TRANSITION_NOTIFIER);
380}
381
382static inline void s3c2410wdt_cpufreq_deregister(void)
383{
384 cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
385 CPUFREQ_TRANSITION_NOTIFIER);
386}
387
388#else
389static inline int s3c2410wdt_cpufreq_register(void)
390{
391 return 0;
392}
393
394static inline void s3c2410wdt_cpufreq_deregister(void)
395{
396}
397#endif
398
399
400
1da177e4
LT
401/* device interface */
402
a77dba7e 403static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
1da177e4 404{
1da177e4 405 struct resource *res;
e8ef92b8 406 struct device *dev;
46b814d6 407 unsigned int wtcon;
1da177e4
LT
408 int started = 0;
409 int ret;
410 int size;
411
fa9363c5 412 DBG("%s: probe=%p\n", __func__, pdev);
1da177e4 413
e8ef92b8
BD
414 dev = &pdev->dev;
415 wdt_dev = &pdev->dev;
416
1da177e4
LT
417 /* get the memory region for the watchdog timer */
418
419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 if (res == NULL) {
e8ef92b8 421 dev_err(dev, "no memory resource specified\n");
1da177e4
LT
422 return -ENOENT;
423 }
424
b782a563 425 size = resource_size(res);
1da177e4
LT
426 wdt_mem = request_mem_region(res->start, size, pdev->name);
427 if (wdt_mem == NULL) {
e8ef92b8 428 dev_err(dev, "failed to get memory region\n");
0b6dd8a6
BD
429 ret = -ENOENT;
430 goto err_req;
1da177e4
LT
431 }
432
433 wdt_base = ioremap(res->start, size);
b4253f8f 434 if (wdt_base == NULL) {
e8ef92b8 435 dev_err(dev, "failed to ioremap() region\n");
0b6dd8a6
BD
436 ret = -EINVAL;
437 goto err_req;
1da177e4
LT
438 }
439
440 DBG("probe: mapped wdt_base=%p\n", wdt_base);
441
62be0741
AP
442 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
443 if (wdt_irq == NULL) {
e8ef92b8 444 dev_err(dev, "no irq resource specified\n");
0b6dd8a6
BD
445 ret = -ENOENT;
446 goto err_map;
1da177e4
LT
447 }
448
62be0741 449 ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
1da177e4 450 if (ret != 0) {
e8ef92b8 451 dev_err(dev, "failed to install irq (%d)\n", ret);
0b6dd8a6 452 goto err_map;
1da177e4
LT
453 }
454
3ae5eaec 455 wdt_clock = clk_get(&pdev->dev, "watchdog");
9cd44619 456 if (IS_ERR(wdt_clock)) {
e8ef92b8 457 dev_err(dev, "failed to find watchdog clock source\n");
9cd44619 458 ret = PTR_ERR(wdt_clock);
0b6dd8a6 459 goto err_irq;
1da177e4
LT
460 }
461
1da177e4
LT
462 clk_enable(wdt_clock);
463
e02f838e
BD
464 if (s3c2410wdt_cpufreq_register() < 0) {
465 printk(KERN_ERR PFX "failed to register cpufreq\n");
466 goto err_clk;
467 }
468
1da177e4
LT
469 /* see if we can actually set the requested timer margin, and if
470 * not, try the default value */
471
472 if (s3c2410wdt_set_heartbeat(tmr_margin)) {
41dc8b72
AC
473 started = s3c2410wdt_set_heartbeat(
474 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
1da177e4 475
41dc8b72
AC
476 if (started == 0)
477 dev_info(dev,
478 "tmr_margin value out of range, default %d used\n",
1da177e4 479 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
41dc8b72 480 else
a77dba7e
WVS
481 dev_info(dev, "default timer value is out of range, "
482 "cannot start\n");
1da177e4
LT
483 }
484
1da177e4
LT
485 ret = misc_register(&s3c2410wdt_miscdev);
486 if (ret) {
e8ef92b8 487 dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
1da177e4 488 WATCHDOG_MINOR, ret);
e02f838e 489 goto err_cpufreq;
1da177e4
LT
490 }
491
492 if (tmr_atboot && started == 0) {
e8ef92b8 493 dev_info(dev, "starting watchdog timer\n");
1da177e4 494 s3c2410wdt_start();
655516c8
BD
495 } else if (!tmr_atboot) {
496 /* if we're not enabling the watchdog, then ensure it is
497 * disabled if it has been left running from the bootloader
498 * or other source */
499
500 s3c2410wdt_stop();
1da177e4
LT
501 }
502
46b814d6
BD
503 /* print out a statement of readiness */
504
505 wtcon = readl(wdt_base + S3C2410_WTCON);
506
e8ef92b8 507 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
46b814d6
BD
508 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
509 (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
510 (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
41dc8b72 511
1da177e4 512 return 0;
0b6dd8a6 513
e02f838e
BD
514 err_cpufreq:
515 s3c2410wdt_cpufreq_deregister();
516
0b6dd8a6
BD
517 err_clk:
518 clk_disable(wdt_clock);
519 clk_put(wdt_clock);
520
521 err_irq:
522 free_irq(wdt_irq->start, pdev);
523
524 err_map:
525 iounmap(wdt_base);
526
527 err_req:
528 release_resource(wdt_mem);
529 kfree(wdt_mem);
530
531 return ret;
1da177e4
LT
532}
533
a77dba7e 534static int __devexit s3c2410wdt_remove(struct platform_device *dev)
1da177e4 535{
e02f838e
BD
536 s3c2410wdt_cpufreq_deregister();
537
0b6dd8a6
BD
538 release_resource(wdt_mem);
539 kfree(wdt_mem);
540 wdt_mem = NULL;
1da177e4 541
0b6dd8a6
BD
542 free_irq(wdt_irq->start, dev);
543 wdt_irq = NULL;
1da177e4 544
0b6dd8a6
BD
545 clk_disable(wdt_clock);
546 clk_put(wdt_clock);
547 wdt_clock = NULL;
1da177e4 548
e34477e9 549 iounmap(wdt_base);
1da177e4
LT
550 misc_deregister(&s3c2410wdt_miscdev);
551 return 0;
552}
553
3ae5eaec 554static void s3c2410wdt_shutdown(struct platform_device *dev)
94f1e9f3 555{
41dc8b72 556 s3c2410wdt_stop();
94f1e9f3
BD
557}
558
af4bb822
BD
559#ifdef CONFIG_PM
560
561static unsigned long wtcon_save;
562static unsigned long wtdat_save;
563
3ae5eaec 564static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
af4bb822 565{
9480e307
RK
566 /* Save watchdog state, and turn it off. */
567 wtcon_save = readl(wdt_base + S3C2410_WTCON);
568 wtdat_save = readl(wdt_base + S3C2410_WTDAT);
af4bb822 569
9480e307
RK
570 /* Note that WTCNT doesn't need to be saved. */
571 s3c2410wdt_stop();
af4bb822
BD
572
573 return 0;
574}
575
3ae5eaec 576static int s3c2410wdt_resume(struct platform_device *dev)
af4bb822 577{
9480e307 578 /* Restore watchdog state. */
af4bb822 579
9480e307
RK
580 writel(wtdat_save, wdt_base + S3C2410_WTDAT);
581 writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
582 writel(wtcon_save, wdt_base + S3C2410_WTCON);
af4bb822 583
9480e307
RK
584 printk(KERN_INFO PFX "watchdog %sabled\n",
585 (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
af4bb822
BD
586
587 return 0;
588}
589
590#else
591#define s3c2410wdt_suspend NULL
592#define s3c2410wdt_resume NULL
593#endif /* CONFIG_PM */
594
595
3ae5eaec 596static struct platform_driver s3c2410wdt_driver = {
1da177e4 597 .probe = s3c2410wdt_probe,
a77dba7e 598 .remove = __devexit_p(s3c2410wdt_remove),
94f1e9f3 599 .shutdown = s3c2410wdt_shutdown,
af4bb822
BD
600 .suspend = s3c2410wdt_suspend,
601 .resume = s3c2410wdt_resume,
3ae5eaec
RK
602 .driver = {
603 .owner = THIS_MODULE,
604 .name = "s3c2410-wdt",
605 },
1da177e4
LT
606};
607
608
41dc8b72
AC
609static char banner[] __initdata =
610 KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
1da177e4
LT
611
612static int __init watchdog_init(void)
613{
614 printk(banner);
3ae5eaec 615 return platform_driver_register(&s3c2410wdt_driver);
1da177e4
LT
616}
617
618static void __exit watchdog_exit(void)
619{
3ae5eaec 620 platform_driver_unregister(&s3c2410wdt_driver);
1da177e4
LT
621}
622
623module_init(watchdog_init);
624module_exit(watchdog_exit);
625
af4bb822
BD
626MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
627 "Dimitry Andric <dimitry.andric@tomtom.com>");
1da177e4
LT
628MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
629MODULE_LICENSE("GPL");
630MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 631MODULE_ALIAS("platform:s3c2410-wdt");