[net-next-2.6.git] / drivers / watchdog / omap_wdt.c

/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@redhat.com>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/clk.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <mach/hardware.h>
#include <mach/prcm.h>

#include "omap_wdt.h"

static struct platform_device *omap_wdt_dev;

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

static unsigned int wdt_trgr_pattern = 0x1234;
static spinlock_t wdt_lock;

struct omap_wdt_dev {
	void __iomem    *base;          /* physical */
	struct device   *dev;
	int             omap_wdt_users;
	struct clk      *armwdt_ck;
	struct clk      *mpu_wdt_ick;
	struct clk      *mpu_wdt_fck;
	struct resource *mem;
	struct miscdevice omap_wdt_miscdev;
};

static void omap_wdt_ping(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;
	/* wait for posted write to complete */
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	wdt_trgr_pattern = ~wdt_trgr_pattern;
	__raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
	/* wait for posted write to complete */
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base;
	base = wdev->base;
	/* Sequence to enable the watchdog */
	__raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
	__raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base;
	base = wdev->base;
	/* sequence required to disable watchdog */
	__raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
	__raw_writel(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_adjust_timeout(unsigned new_timeout)
{
	if (new_timeout < TIMER_MARGIN_MIN)
		new_timeout = TIMER_MARGIN_DEFAULT;
	if (new_timeout > TIMER_MARGIN_MAX)
		new_timeout = TIMER_MARGIN_MAX;
	timer_margin = new_timeout;
}

static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
{
	u32 pre_margin = GET_WLDR_VAL(timer_margin);
	void __iomem *base;
	base = wdev->base;

	/* just count up at 32 KHz */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
	__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

/*
 *	Allow only one task to hold it open
 */

static int omap_wdt_open(struct inode *inode, struct file *file)
{
	struct omap_wdt_dev *wdev;
	void __iomem *base;
	wdev = platform_get_drvdata(omap_wdt_dev);
	base = wdev->base;
	if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
		return -EBUSY;

	if (cpu_is_omap16xx())
		clk_enable(wdev->armwdt_ck);	/* Enable the clock */

	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
		clk_enable(wdev->mpu_wdt_ick);    /* Enable the interface clock */
		clk_enable(wdev->mpu_wdt_fck);    /* Enable the functional clock */
	}

	/* initialize prescaler */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();
	__raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	file->private_data = (void *) wdev;

	omap_wdt_set_timeout(wdev);
	omap_wdt_enable(wdev);
	return nonseekable_open(inode, file);
}

static int omap_wdt_release(struct inode *inode, struct file *file)
{
	struct omap_wdt_dev *wdev;
	wdev = file->private_data;
	/*
	 *      Shut off the timer unless NOWAYOUT is defined.
	 */
#ifndef CONFIG_WATCHDOG_NOWAYOUT

	omap_wdt_disable(wdev);

	if (cpu_is_omap16xx())
		clk_disable(wdev->armwdt_ck);	/* Disable the clock */

	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
		clk_disable(wdev->mpu_wdt_ick);	/* Disable the clock */
		clk_disable(wdev->mpu_wdt_fck);	/* Disable the clock */
	}
#else
	printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
#endif
	wdev->omap_wdt_users = 0;
	return 0;
}

static ssize_t omap_wdt_write(struct file *file, const char __user *data,
		size_t len, loff_t *ppos)
{
	struct omap_wdt_dev *wdev;
	wdev = file->private_data;
	/* Refresh LOAD_TIME. */
	if (len) {
		spin_lock(&wdt_lock);
		omap_wdt_ping(wdev);
		spin_unlock(&wdt_lock);
	}
	return len;
}

static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
						unsigned long arg)
{
	struct omap_wdt_dev *wdev;
	int new_margin;
	static const struct watchdog_info ident = {
		.identity = "OMAP Watchdog",
		.options = WDIOF_SETTIMEOUT,
		.firmware_version = 0,
	};
	wdev = file->private_data;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		return copy_to_user((struct watchdog_info __user *)arg, &ident,
				sizeof(ident));
	case WDIOC_GETSTATUS:
		return put_user(0, (int __user *)arg);
	case WDIOC_GETBOOTSTATUS:
		if (cpu_is_omap16xx())
			return put_user(__raw_readw(ARM_SYSST),
					(int __user *)arg);
		if (cpu_is_omap24xx())
			return put_user(omap_prcm_get_reset_sources(),
					(int __user *)arg);
	case WDIOC_KEEPALIVE:
		spin_lock(&wdt_lock);
		omap_wdt_ping(wdev);
		spin_unlock(&wdt_lock);
		return 0;
	case WDIOC_SETTIMEOUT:
		if (get_user(new_margin, (int __user *)arg))
			return -EFAULT;
		omap_wdt_adjust_timeout(new_margin);

		spin_lock(&wdt_lock);
		omap_wdt_disable(wdev);
		omap_wdt_set_timeout(wdev);
		omap_wdt_enable(wdev);

		omap_wdt_ping(wdev);
		spin_unlock(&wdt_lock);
		/* Fall */
	case WDIOC_GETTIMEOUT:
		return put_user(timer_margin, (int __user *)arg);
	default:
		return -ENOTTY;
	}
}

static const struct file_operations omap_wdt_fops = {
	.owner = THIS_MODULE,
	.write = omap_wdt_write,
	.unlocked_ioctl = omap_wdt_ioctl,
	.open = omap_wdt_open,
	.release = omap_wdt_release,
};


static int __init omap_wdt_probe(struct platform_device *pdev)
{
	struct resource *res, *mem;
	int ret;
	struct omap_wdt_dev *wdev;

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOENT;

	if (omap_wdt_dev)
		return -EBUSY;

	mem = request_mem_region(res->start, res->end - res->start + 1,
				 pdev->name);
	if (mem == NULL)
		return -EBUSY;

	wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
	if (!wdev) {
		ret = -ENOMEM;
		goto fail;
	}
	wdev->omap_wdt_users = 0;
	wdev->mem = mem;

	if (cpu_is_omap16xx()) {
		wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
		if (IS_ERR(wdev->armwdt_ck)) {
			ret = PTR_ERR(wdev->armwdt_ck);
			wdev->armwdt_ck = NULL;
			goto fail;
		}
	}

	if (cpu_is_omap24xx()) {
		wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
		if (IS_ERR(wdev->mpu_wdt_ick)) {
			ret = PTR_ERR(wdev->mpu_wdt_ick);
			wdev->mpu_wdt_ick = NULL;
			goto fail;
		}
		wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
		if (IS_ERR(wdev->mpu_wdt_fck)) {
			ret = PTR_ERR(wdev->mpu_wdt_fck);
			wdev->mpu_wdt_fck = NULL;
			goto fail;
		}
	}

	if (cpu_is_omap34xx()) {
		wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick");
		if (IS_ERR(wdev->mpu_wdt_ick)) {
			ret = PTR_ERR(wdev->mpu_wdt_ick);
			wdev->mpu_wdt_ick = NULL;
			goto fail;
		}
		wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck");
		if (IS_ERR(wdev->mpu_wdt_fck)) {
			ret = PTR_ERR(wdev->mpu_wdt_fck);
			wdev->mpu_wdt_fck = NULL;
			goto fail;
		}
	}
	wdev->base = ioremap(res->start, res->end - res->start + 1);
	if (!wdev->base) {
		ret = -ENOMEM;
		goto fail;
	}

	platform_set_drvdata(pdev, wdev);

	omap_wdt_disable(wdev);
	omap_wdt_adjust_timeout(timer_margin);

	wdev->omap_wdt_miscdev.parent = &pdev->dev;
	wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
	wdev->omap_wdt_miscdev.name = "watchdog";
	wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;

	ret = misc_register(&(wdev->omap_wdt_miscdev));
	if (ret)
		goto fail;

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		timer_margin);

	/* autogate OCP interface clock */
	__raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);

	omap_wdt_dev = pdev;

	return 0;

fail:
	if (wdev) {
		platform_set_drvdata(pdev, NULL);
		if (wdev->armwdt_ck)
			clk_put(wdev->armwdt_ck);
		if (wdev->mpu_wdt_ick)
			clk_put(wdev->mpu_wdt_ick);
		if (wdev->mpu_wdt_fck)
			clk_put(wdev->mpu_wdt_fck);
		iounmap(wdev->base);
		kfree(wdev);
	}
	if (mem) {
		release_mem_region(res->start, res->end - res->start + 1);
	}
	return ret;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev;
	wdev = platform_get_drvdata(pdev);

	if (wdev->omap_wdt_users)
		omap_wdt_disable(wdev);
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev;
	wdev = platform_get_drvdata(pdev);
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res)
		return -ENOENT;

	misc_deregister(&(wdev->omap_wdt_miscdev));
	release_mem_region(res->start, res->end - res->start + 1);
	platform_set_drvdata(pdev, NULL);
	if (wdev->armwdt_ck) {
		clk_put(wdev->armwdt_ck);
		wdev->armwdt_ck = NULL;
	}
	if (wdev->mpu_wdt_ick) {
		clk_put(wdev->mpu_wdt_ick);
		wdev->mpu_wdt_ick = NULL;
	}
	if (wdev->mpu_wdt_fck) {
		clk_put(wdev->mpu_wdt_fck);
		wdev->mpu_wdt_fck = NULL;
	}
	iounmap(wdev->base);

	kfree(wdev);
	omap_wdt_dev = NULL;
	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct omap_wdt_dev *wdev;
	wdev = platform_get_drvdata(pdev);
	if (wdev->omap_wdt_users)
		omap_wdt_disable(wdev);
	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev;
	wdev = platform_get_drvdata(pdev);
	if (wdev->omap_wdt_users) {
		omap_wdt_enable(wdev);
		omap_wdt_ping(wdev);
	}
	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "omap_wdt",
	},
};

static int __init omap_wdt_init(void)
{
	spin_lock_init(&wdt_lock);
	return platform_driver_register(&omap_wdt_driver);
}

static void __exit omap_wdt_exit(void)
{
	platform_driver_unregister(&omap_wdt_driver);
}

module_init(omap_wdt_init);
module_exit(omap_wdt_exit);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c	1	/*
2817142f	2	* omap_wdt.c
7768a13c	3	*
2817142f	4	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <gdavis@mvista.com> or <source@mvista.com>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <gdavis@mvista.com>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
	19	* Based on SoftDog driver by Alan Cox <alan@redhat.com>
	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
	29	#include <linux/module.h>
7768a13c KS	30	#include <linux/types.h>
	31	#include <linux/kernel.h>
	32	#include <linux/fs.h>
	33	#include <linux/mm.h>
	34	#include <linux/miscdevice.h>
	35	#include <linux/watchdog.h>
	36	#include <linux/reboot.h>
7768a13c KS	37	#include <linux/init.h>
	38	#include <linux/err.h>
	39	#include <linux/platform_device.h>
	40	#include <linux/moduleparam.h>
	41	#include <linux/clk.h>
1977f032	42	#include <linux/bitops.h>
089ab079	43	#include <linux/io.h>
12b9df7d	44	#include <linux/uaccess.h>
a09e64fb	45	#include <mach/hardware.h>
a09e64fb	46	#include <mach/prcm.h>
7768a13c KS	47
	48	#include "omap_wdt.h"
	49
2817142f FB	50	static struct platform_device *omap_wdt_dev;
2817142f FB	51
7768a13c KS	52	static unsigned timer_margin;
	53	module_param(timer_margin, uint, 0);
	54	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	55
7768a13c	56	static unsigned int wdt_trgr_pattern = 0x1234;
12b9df7d	57	static spinlock_t wdt_lock;
7768a13c	58
2817142f FB	59	struct omap_wdt_dev {
	60	void __iomem base; / physical */
	61	struct device *dev;
	62	int omap_wdt_users;
	63	struct clk *armwdt_ck;
	64	struct clk *mpu_wdt_ick;
	65	struct clk *mpu_wdt_fck;
	66	struct resource *mem;
	67	struct miscdevice omap_wdt_miscdev;
	68	};
	69
	70	static void omap_wdt_ping(struct omap_wdt_dev *wdev)
7768a13c	71	{
2817142f	72	void __iomem *base = wdev->base;
7768a13c	73	/* wait for posted write to complete */
9f69e3b0	74	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	75	cpu_relax();
7768a13c KS	76	wdt_trgr_pattern = ~wdt_trgr_pattern;
9f69e3b0	77	__raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
7768a13c	78	/* wait for posted write to complete */
9f69e3b0	79	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	80	cpu_relax();
	81	/* reloaded WCRR from WLDR */
	82	}
	83
2817142f	84	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	85	{
2817142f FB	86	void __iomem *base;
2817142f FB	87	base = wdev->base;
7768a13c	88	/* Sequence to enable the watchdog */
9f69e3b0 FB	89	__raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
9f69e3b0 FB	90	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	91	cpu_relax();
9f69e3b0 FB	92	__raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
9f69e3b0 FB	93	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	94	cpu_relax();
	95	}
	96
2817142f	97	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	98	{
2817142f FB	99	void __iomem *base;
2817142f FB	100	base = wdev->base;
7768a13c	101	/* sequence required to disable watchdog */
9f69e3b0 FB	102	__raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
9f69e3b0 FB	103	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	104	cpu_relax();
9f69e3b0 FB	105	__raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
9f69e3b0 FB	106	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	107	cpu_relax();
	108	}
	109
	110	static void omap_wdt_adjust_timeout(unsigned new_timeout)
	111	{
	112	if (new_timeout < TIMER_MARGIN_MIN)
	113	new_timeout = TIMER_MARGIN_DEFAULT;
	114	if (new_timeout > TIMER_MARGIN_MAX)
	115	new_timeout = TIMER_MARGIN_MAX;
	116	timer_margin = new_timeout;
	117	}
	118
2817142f	119	static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
7768a13c KS	120	{
7768a13c KS	121	u32 pre_margin = GET_WLDR_VAL(timer_margin);
2817142f FB	122	void __iomem *base;
2817142f FB	123	base = wdev->base;
7768a13c KS	124
7768a13c KS	125	/* just count up at 32 KHz */
9f69e3b0	126	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	127	cpu_relax();
9f69e3b0 FB	128	__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
9f69e3b0 FB	129	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	130	cpu_relax();
	131	}
	132
	133	/*
	134	* Allow only one task to hold it open
	135	*/
	136
	137	static int omap_wdt_open(struct inode inode, struct file file)
	138	{
2817142f FB	139	struct omap_wdt_dev *wdev;
	140	void __iomem *base;
	141	wdev = platform_get_drvdata(omap_wdt_dev);
	142	base = wdev->base;
	143	if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
7768a13c KS	144	return -EBUSY;
	145
	146	if (cpu_is_omap16xx())
2817142f	147	clk_enable(wdev->armwdt_ck); /* Enable the clock */
7768a13c	148
2817142f FB	149	if (cpu_is_omap24xx() \|\| cpu_is_omap34xx()) {
	150	clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */
	151	clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */
7768a13c KS	152	}
	153
	154	/* initialize prescaler */
9f69e3b0	155	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	156	cpu_relax();
9f69e3b0 FB	157	__raw_writel((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
9f69e3b0 FB	158	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	159	cpu_relax();
7768a13c KS	160
2817142f FB	161	file->private_data = (void *) wdev;
	162
	163	omap_wdt_set_timeout(wdev);
	164	omap_wdt_enable(wdev);
ec9505a7	165	return nonseekable_open(inode, file);
7768a13c KS	166	}
	167
	168	static int omap_wdt_release(struct inode inode, struct file file)
	169	{
2817142f FB	170	struct omap_wdt_dev *wdev;
2817142f FB	171	wdev = file->private_data;
7768a13c KS	172	/*
	173	* Shut off the timer unless NOWAYOUT is defined.
	174	*/
	175	#ifndef CONFIG_WATCHDOG_NOWAYOUT
7768a13c	176
2817142f	177	omap_wdt_disable(wdev);
7768a13c	178
2817142f FB	179	if (cpu_is_omap16xx())
	180	clk_disable(wdev->armwdt_ck); /* Disable the clock */
	181
	182	if (cpu_is_omap24xx() \|\| cpu_is_omap34xx()) {
	183	clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */
	184	clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */
7768a13c KS	185	}
	186	#else
	187	printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
	188	#endif
2817142f	189	wdev->omap_wdt_users = 0;
7768a13c KS	190	return 0;
	191	}
	192
12b9df7d	193	static ssize_t omap_wdt_write(struct file file, const char __user data,
7768a13c KS	194	size_t len, loff_t *ppos)
7768a13c KS	195	{
2817142f FB	196	struct omap_wdt_dev *wdev;
2817142f FB	197	wdev = file->private_data;
7768a13c	198	/* Refresh LOAD_TIME. */
12b9df7d AC	199	if (len) {
12b9df7d AC	200	spin_lock(&wdt_lock);
2817142f	201	omap_wdt_ping(wdev);
12b9df7d AC	202	spin_unlock(&wdt_lock);
12b9df7d AC	203	}
7768a13c KS	204	return len;
	205	}
	206
12b9df7d AC	207	static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
12b9df7d AC	208	unsigned long arg)
7768a13c	209	{
2817142f	210	struct omap_wdt_dev *wdev;
7768a13c	211	int new_margin;
12b9df7d	212	static const struct watchdog_info ident = {
7768a13c KS	213	.identity = "OMAP Watchdog",
	214	.options = WDIOF_SETTIMEOUT,
	215	.firmware_version = 0,
	216	};
2817142f	217	wdev = file->private_data;
7768a13c KS	218
7768a13c KS	219	switch (cmd) {
7768a13c KS	220	case WDIOC_GETSUPPORT:
	221	return copy_to_user((struct watchdog_info __user *)arg, &ident,
	222	sizeof(ident));
	223	case WDIOC_GETSTATUS:
	224	return put_user(0, (int __user *)arg);
	225	case WDIOC_GETBOOTSTATUS:
	226	if (cpu_is_omap16xx())
9f69e3b0	227	return put_user(__raw_readw(ARM_SYSST),
7768a13c KS	228	(int __user *)arg);
	229	if (cpu_is_omap24xx())
	230	return put_user(omap_prcm_get_reset_sources(),
	231	(int __user *)arg);
	232	case WDIOC_KEEPALIVE:
12b9df7d	233	spin_lock(&wdt_lock);
2817142f	234	omap_wdt_ping(wdev);
12b9df7d	235	spin_unlock(&wdt_lock);
7768a13c KS	236	return 0;
	237	case WDIOC_SETTIMEOUT:
	238	if (get_user(new_margin, (int __user *)arg))
	239	return -EFAULT;
	240	omap_wdt_adjust_timeout(new_margin);
	241
12b9df7d	242	spin_lock(&wdt_lock);
2817142f FB	243	omap_wdt_disable(wdev);
	244	omap_wdt_set_timeout(wdev);
	245	omap_wdt_enable(wdev);
7768a13c	246
2817142f	247	omap_wdt_ping(wdev);
12b9df7d	248	spin_unlock(&wdt_lock);
7768a13c KS	249	/* Fall */
	250	case WDIOC_GETTIMEOUT:
	251	return put_user(timer_margin, (int __user *)arg);
0c06090c WVS	252	default:
0c06090c WVS	253	return -ENOTTY;
7768a13c KS	254	}
	255	}
	256
2b8693c0	257	static const struct file_operations omap_wdt_fops = {
7768a13c KS	258	.owner = THIS_MODULE,
7768a13c KS	259	.write = omap_wdt_write,
12b9df7d	260	.unlocked_ioctl = omap_wdt_ioctl,
7768a13c KS	261	.open = omap_wdt_open,
	262	.release = omap_wdt_release,
	263	};
	264
7768a13c KS	265
	266	static int __init omap_wdt_probe(struct platform_device *pdev)
	267	{
	268	struct resource res, mem;
	269	int ret;
2817142f	270	struct omap_wdt_dev *wdev;
7768a13c KS	271
	272	/* reserve static register mappings */
	273	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	274	if (!res)
	275	return -ENOENT;
	276
2817142f FB	277	if (omap_wdt_dev)
	278	return -EBUSY;
	279
7768a13c KS	280	mem = request_mem_region(res->start, res->end - res->start + 1,
	281	pdev->name);
	282	if (mem == NULL)
	283	return -EBUSY;
	284
2817142f FB	285	wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
	286	if (!wdev) {
	287	ret = -ENOMEM;
	288	goto fail;
	289	}
	290	wdev->omap_wdt_users = 0;
	291	wdev->mem = mem;
7768a13c KS	292
7768a13c KS	293	if (cpu_is_omap16xx()) {
2817142f FB	294	wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
	295	if (IS_ERR(wdev->armwdt_ck)) {
	296	ret = PTR_ERR(wdev->armwdt_ck);
	297	wdev->armwdt_ck = NULL;
7768a13c KS	298	goto fail;
	299	}
	300	}
	301
	302	if (cpu_is_omap24xx()) {
2817142f FB	303	wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
	304	if (IS_ERR(wdev->mpu_wdt_ick)) {
	305	ret = PTR_ERR(wdev->mpu_wdt_ick);
	306	wdev->mpu_wdt_ick = NULL;
	307	goto fail;
	308	}
	309	wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
	310	if (IS_ERR(wdev->mpu_wdt_fck)) {
	311	ret = PTR_ERR(wdev->mpu_wdt_fck);
	312	wdev->mpu_wdt_fck = NULL;
	313	goto fail;
	314	}
	315	}
	316
	317	if (cpu_is_omap34xx()) {
	318	wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick");
	319	if (IS_ERR(wdev->mpu_wdt_ick)) {
	320	ret = PTR_ERR(wdev->mpu_wdt_ick);
	321	wdev->mpu_wdt_ick = NULL;
7768a13c KS	322	goto fail;
7768a13c KS	323	}
2817142f FB	324	wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck");
	325	if (IS_ERR(wdev->mpu_wdt_fck)) {
	326	ret = PTR_ERR(wdev->mpu_wdt_fck);
	327	wdev->mpu_wdt_fck = NULL;
7768a13c KS	328	goto fail;
	329	}
	330	}
9f69e3b0 FB	331	wdev->base = ioremap(res->start, res->end - res->start + 1);
	332	if (!wdev->base) {
	333	ret = -ENOMEM;
	334	goto fail;
	335	}
	336
2817142f	337	platform_set_drvdata(pdev, wdev);
7768a13c	338
2817142f	339	omap_wdt_disable(wdev);
7768a13c KS	340	omap_wdt_adjust_timeout(timer_margin);
7768a13c KS	341
2817142f FB	342	wdev->omap_wdt_miscdev.parent = &pdev->dev;
	343	wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
	344	wdev->omap_wdt_miscdev.name = "watchdog";
	345	wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
	346
	347	ret = misc_register(&(wdev->omap_wdt_miscdev));
7768a13c KS	348	if (ret)
	349	goto fail;
	350
2817142f	351	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
9f69e3b0	352	__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
2817142f	353	timer_margin);
7768a13c KS	354
7768a13c KS	355	/* autogate OCP interface clock */
9f69e3b0	356	__raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
2817142f FB	357
	358	omap_wdt_dev = pdev;
	359
7768a13c KS	360	return 0;
	361
	362	fail:
2817142f FB	363	if (wdev) {
	364	platform_set_drvdata(pdev, NULL);
	365	if (wdev->armwdt_ck)
	366	clk_put(wdev->armwdt_ck);
	367	if (wdev->mpu_wdt_ick)
	368	clk_put(wdev->mpu_wdt_ick);
	369	if (wdev->mpu_wdt_fck)
	370	clk_put(wdev->mpu_wdt_fck);
9f69e3b0	371	iounmap(wdev->base);
2817142f FB	372	kfree(wdev);
	373	}
	374	if (mem) {
	375	release_mem_region(res->start, res->end - res->start + 1);
	376	}
7768a13c KS	377	return ret;
	378	}
	379
	380	static void omap_wdt_shutdown(struct platform_device *pdev)
	381	{
2817142f FB	382	struct omap_wdt_dev *wdev;
	383	wdev = platform_get_drvdata(pdev);
	384
	385	if (wdev->omap_wdt_users)
	386	omap_wdt_disable(wdev);
7768a13c KS	387	}
	388
	389	static int omap_wdt_remove(struct platform_device *pdev)
	390	{
2817142f FB	391	struct omap_wdt_dev *wdev;
	392	wdev = platform_get_drvdata(pdev);
	393	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	394
	395	if (!res)
	396	return -ENOENT;
	397
	398	misc_deregister(&(wdev->omap_wdt_miscdev));
	399	release_mem_region(res->start, res->end - res->start + 1);
	400	platform_set_drvdata(pdev, NULL);
	401	if (wdev->armwdt_ck) {
	402	clk_put(wdev->armwdt_ck);
	403	wdev->armwdt_ck = NULL;
	404	}
	405	if (wdev->mpu_wdt_ick) {
	406	clk_put(wdev->mpu_wdt_ick);
	407	wdev->mpu_wdt_ick = NULL;
	408	}
	409	if (wdev->mpu_wdt_fck) {
	410	clk_put(wdev->mpu_wdt_fck);
	411	wdev->mpu_wdt_fck = NULL;
	412	}
9f69e3b0 FB	413	iounmap(wdev->base);
9f69e3b0 FB	414
2817142f FB	415	kfree(wdev);
2817142f FB	416	omap_wdt_dev = NULL;
7768a13c KS	417	return 0;
	418	}
	419
	420	#ifdef CONFIG_PM
	421
	422	/* REVISIT ... not clear this is the best way to handle system suspend; and
	423	* it's very inappropriate for selective device suspend (e.g. suspending this
	424	* through sysfs rather than by stopping the watchdog daemon). Also, this
	425	* may not play well enough with NOWAYOUT...
	426	*/
	427
	428	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	429	{
2817142f FB	430	struct omap_wdt_dev *wdev;
	431	wdev = platform_get_drvdata(pdev);
	432	if (wdev->omap_wdt_users)
	433	omap_wdt_disable(wdev);
7768a13c KS	434	return 0;
	435	}
	436
	437	static int omap_wdt_resume(struct platform_device *pdev)
	438	{
2817142f FB	439	struct omap_wdt_dev *wdev;
	440	wdev = platform_get_drvdata(pdev);
	441	if (wdev->omap_wdt_users) {
	442	omap_wdt_enable(wdev);
	443	omap_wdt_ping(wdev);
7768a13c KS	444	}
	445	return 0;
	446	}
	447
	448	#else
	449	#define omap_wdt_suspend NULL
	450	#define omap_wdt_resume NULL
	451	#endif
	452
	453	static struct platform_driver omap_wdt_driver = {
	454	.probe = omap_wdt_probe,
	455	.remove = omap_wdt_remove,
	456	.shutdown = omap_wdt_shutdown,
	457	.suspend = omap_wdt_suspend,
	458	.resume = omap_wdt_resume,
	459	.driver = {
	460	.owner = THIS_MODULE,
	461	.name = "omap_wdt",
	462	},
	463	};
	464
	465	static int __init omap_wdt_init(void)
	466	{
12b9df7d	467	spin_lock_init(&wdt_lock);
7768a13c KS	468	return platform_driver_register(&omap_wdt_driver);
	469	}
	470
	471	static void __exit omap_wdt_exit(void)
	472	{
	473	platform_driver_unregister(&omap_wdt_driver);
	474	}
	475
	476	module_init(omap_wdt_init);
	477	module_exit(omap_wdt_exit);
	478
	479	MODULE_AUTHOR("George G. Davis");
	480	MODULE_LICENSE("GPL");
	481	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c	482	MODULE_ALIAS("platform:omap_wdt");