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d532134d AP |
1 | /* |
2 | * IBM Automatic Server Restart driver. | |
3 | * | |
4 | * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru> | |
5 | * | |
6 | * Based on driver written by Pete Reynolds. | |
7 | * Copyright (c) IBM Corporation, 1998-2004. | |
8 | * | |
9 | * This software may be used and distributed according to the terms | |
10 | * of the GNU Public License, incorporated herein by reference. | |
11 | */ | |
12 | ||
d532134d AP |
13 | #include <linux/fs.h> |
14 | #include <linux/kernel.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/miscdevice.h> | |
20 | #include <linux/watchdog.h> | |
21 | #include <linux/dmi.h> | |
02355c32 AC |
22 | #include <linux/io.h> |
23 | #include <linux/uaccess.h> | |
d532134d AP |
24 | |
25 | ||
26 | enum { | |
27 | ASMTYPE_UNKNOWN, | |
28 | ASMTYPE_TOPAZ, | |
29 | ASMTYPE_JASPER, | |
30 | ASMTYPE_PEARL, | |
31 | ASMTYPE_JUNIPER, | |
32 | ASMTYPE_SPRUCE, | |
33 | }; | |
34 | ||
35 | #define PFX "ibmasr: " | |
36 | ||
37 | #define TOPAZ_ASR_REG_OFFSET 4 | |
38 | #define TOPAZ_ASR_TOGGLE 0x40 | |
39 | #define TOPAZ_ASR_DISABLE 0x80 | |
40 | ||
41 | /* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */ | |
42 | #define PEARL_BASE 0xe04 | |
43 | #define PEARL_WRITE 0xe06 | |
44 | #define PEARL_READ 0xe07 | |
45 | ||
46 | #define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */ | |
47 | #define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */ | |
48 | ||
49 | /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */ | |
50 | #define JASPER_ASR_REG_OFFSET 0x38 | |
51 | ||
52 | #define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */ | |
53 | #define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */ | |
54 | ||
55 | #define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */ | |
56 | #define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */ | |
57 | #define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */ | |
58 | ||
59 | #define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */ | |
60 | #define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */ | |
61 | #define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */ | |
62 | ||
63 | ||
64 | static int nowayout = WATCHDOG_NOWAYOUT; | |
65 | ||
66 | static unsigned long asr_is_open; | |
67 | static char asr_expect_close; | |
68 | ||
69 | static unsigned int asr_type, asr_base, asr_length; | |
70 | static unsigned int asr_read_addr, asr_write_addr; | |
71 | static unsigned char asr_toggle_mask, asr_disable_mask; | |
02355c32 | 72 | static spinlock_t asr_lock; |
d532134d | 73 | |
02355c32 | 74 | static void __asr_toggle(void) |
d532134d | 75 | { |
02355c32 AC |
76 | unsigned char reg; |
77 | ||
78 | reg = inb(asr_read_addr); | |
d532134d AP |
79 | |
80 | outb(reg & ~asr_toggle_mask, asr_write_addr); | |
81 | reg = inb(asr_read_addr); | |
82 | ||
83 | outb(reg | asr_toggle_mask, asr_write_addr); | |
84 | reg = inb(asr_read_addr); | |
85 | ||
86 | outb(reg & ~asr_toggle_mask, asr_write_addr); | |
87 | reg = inb(asr_read_addr); | |
02355c32 AC |
88 | spin_unlock(&asr_lock); |
89 | } | |
90 | ||
91 | static void asr_toggle(void) | |
92 | { | |
93 | spin_lock(&asr_lock); | |
94 | __asr_toggle(); | |
95 | spin_unlock(&asr_lock); | |
d532134d AP |
96 | } |
97 | ||
98 | static void asr_enable(void) | |
99 | { | |
100 | unsigned char reg; | |
101 | ||
02355c32 | 102 | spin_lock(&asr_lock); |
d532134d AP |
103 | if (asr_type == ASMTYPE_TOPAZ) { |
104 | /* asr_write_addr == asr_read_addr */ | |
105 | reg = inb(asr_read_addr); | |
106 | outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE), | |
107 | asr_read_addr); | |
108 | } else { | |
109 | /* | |
110 | * First make sure the hardware timer is reset by toggling | |
111 | * ASR hardware timer line. | |
112 | */ | |
02355c32 | 113 | __asr_toggle(); |
d532134d AP |
114 | |
115 | reg = inb(asr_read_addr); | |
116 | outb(reg & ~asr_disable_mask, asr_write_addr); | |
117 | } | |
118 | reg = inb(asr_read_addr); | |
02355c32 | 119 | spin_unlock(&asr_lock); |
d532134d AP |
120 | } |
121 | ||
122 | static void asr_disable(void) | |
123 | { | |
02355c32 AC |
124 | unsigned char reg; |
125 | ||
126 | spin_lock(&asr_lock); | |
127 | reg = inb(asr_read_addr); | |
d532134d AP |
128 | |
129 | if (asr_type == ASMTYPE_TOPAZ) | |
130 | /* asr_write_addr == asr_read_addr */ | |
131 | outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE, | |
132 | asr_read_addr); | |
133 | else { | |
134 | outb(reg | asr_toggle_mask, asr_write_addr); | |
135 | reg = inb(asr_read_addr); | |
136 | ||
137 | outb(reg | asr_disable_mask, asr_write_addr); | |
138 | } | |
139 | reg = inb(asr_read_addr); | |
02355c32 | 140 | spin_unlock(&asr_lock); |
d532134d AP |
141 | } |
142 | ||
143 | static int __init asr_get_base_address(void) | |
144 | { | |
145 | unsigned char low, high; | |
146 | const char *type = ""; | |
147 | ||
148 | asr_length = 1; | |
149 | ||
150 | switch (asr_type) { | |
151 | case ASMTYPE_TOPAZ: | |
02355c32 AC |
152 | /* SELECT SuperIO CHIP FOR QUERYING |
153 | (WRITE 0x07 TO BOTH 0x2E and 0x2F) */ | |
d532134d AP |
154 | outb(0x07, 0x2e); |
155 | outb(0x07, 0x2f); | |
156 | ||
157 | /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */ | |
158 | outb(0x60, 0x2e); | |
159 | high = inb(0x2f); | |
160 | ||
161 | /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */ | |
162 | outb(0x61, 0x2e); | |
163 | low = inb(0x2f); | |
164 | ||
165 | asr_base = (high << 16) | low; | |
166 | asr_read_addr = asr_write_addr = | |
167 | asr_base + TOPAZ_ASR_REG_OFFSET; | |
168 | asr_length = 5; | |
169 | ||
170 | break; | |
171 | ||
172 | case ASMTYPE_JASPER: | |
173 | type = "Jaspers "; | |
02355c32 AC |
174 | #if 0 |
175 | u32 r; | |
176 | /* Suggested fix */ | |
177 | pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0)); | |
178 | if (pdev == NULL) | |
179 | return -ENODEV; | |
180 | pci_read_config_dword(pdev, 0x58, &r); | |
181 | asr_base = r & 0xFFFE; | |
182 | pci_dev_put(pdev); | |
183 | #else | |
184 | /* FIXME: need to use pci_config_lock here, | |
185 | but it's not exported */ | |
d532134d AP |
186 | |
187 | /* spin_lock_irqsave(&pci_config_lock, flags);*/ | |
188 | ||
189 | /* Select the SuperIO chip in the PCI I/O port register */ | |
190 | outl(0x8000f858, 0xcf8); | |
191 | ||
02355c32 AC |
192 | /* BUS 0, Slot 1F, fnc 0, offset 58 */ |
193 | ||
d532134d AP |
194 | /* |
195 | * Read the base address for the SuperIO chip. | |
196 | * Only the lower 16 bits are valid, but the address is word | |
197 | * aligned so the last bit must be masked off. | |
198 | */ | |
199 | asr_base = inl(0xcfc) & 0xfffe; | |
200 | ||
201 | /* spin_unlock_irqrestore(&pci_config_lock, flags);*/ | |
02355c32 | 202 | #endif |
d532134d AP |
203 | asr_read_addr = asr_write_addr = |
204 | asr_base + JASPER_ASR_REG_OFFSET; | |
205 | asr_toggle_mask = JASPER_ASR_TOGGLE_MASK; | |
206 | asr_disable_mask = JASPER_ASR_DISABLE_MASK; | |
207 | asr_length = JASPER_ASR_REG_OFFSET + 1; | |
208 | ||
209 | break; | |
210 | ||
211 | case ASMTYPE_PEARL: | |
212 | type = "Pearls "; | |
213 | asr_base = PEARL_BASE; | |
214 | asr_read_addr = PEARL_READ; | |
215 | asr_write_addr = PEARL_WRITE; | |
216 | asr_toggle_mask = PEARL_ASR_TOGGLE_MASK; | |
217 | asr_disable_mask = PEARL_ASR_DISABLE_MASK; | |
218 | asr_length = 4; | |
219 | break; | |
220 | ||
221 | case ASMTYPE_JUNIPER: | |
222 | type = "Junipers "; | |
223 | asr_base = JUNIPER_BASE_ADDRESS; | |
224 | asr_read_addr = asr_write_addr = asr_base; | |
225 | asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK; | |
226 | asr_disable_mask = JUNIPER_ASR_DISABLE_MASK; | |
227 | break; | |
228 | ||
229 | case ASMTYPE_SPRUCE: | |
230 | type = "Spruce's "; | |
231 | asr_base = SPRUCE_BASE_ADDRESS; | |
232 | asr_read_addr = asr_write_addr = asr_base; | |
233 | asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK; | |
234 | asr_disable_mask = SPRUCE_ASR_DISABLE_MASK; | |
235 | break; | |
236 | } | |
237 | ||
238 | if (!request_region(asr_base, asr_length, "ibmasr")) { | |
239 | printk(KERN_ERR PFX "address %#x already in use\n", | |
240 | asr_base); | |
241 | return -EBUSY; | |
242 | } | |
243 | ||
244 | printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | ||
250 | static ssize_t asr_write(struct file *file, const char __user *buf, | |
251 | size_t count, loff_t *ppos) | |
252 | { | |
253 | if (count) { | |
254 | if (!nowayout) { | |
255 | size_t i; | |
256 | ||
257 | /* In case it was set long ago */ | |
258 | asr_expect_close = 0; | |
259 | ||
260 | for (i = 0; i != count; i++) { | |
261 | char c; | |
262 | if (get_user(c, buf + i)) | |
263 | return -EFAULT; | |
264 | if (c == 'V') | |
265 | asr_expect_close = 42; | |
266 | } | |
267 | } | |
268 | asr_toggle(); | |
269 | } | |
270 | return count; | |
271 | } | |
272 | ||
02355c32 | 273 | static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
d532134d AP |
274 | { |
275 | static const struct watchdog_info ident = { | |
02355c32 | 276 | .options = WDIOF_KEEPALIVEPING | |
d532134d AP |
277 | WDIOF_MAGICCLOSE, |
278 | .identity = "IBM ASR" | |
279 | }; | |
280 | void __user *argp = (void __user *)arg; | |
281 | int __user *p = argp; | |
282 | int heartbeat; | |
283 | ||
284 | switch (cmd) { | |
02355c32 AC |
285 | case WDIOC_GETSUPPORT: |
286 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | |
287 | case WDIOC_GETSTATUS: | |
288 | case WDIOC_GETBOOTSTATUS: | |
289 | return put_user(0, p); | |
290 | case WDIOC_KEEPALIVE: | |
291 | asr_toggle(); | |
292 | return 0; | |
293 | /* | |
294 | * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT | |
295 | * and WDIOC_GETTIMEOUT always returns 256. | |
296 | */ | |
297 | case WDIOC_GETTIMEOUT: | |
298 | heartbeat = 256; | |
299 | return put_user(heartbeat, p); | |
300 | case WDIOC_SETOPTIONS: | |
301 | { | |
302 | int new_options, retval = -EINVAL; | |
303 | if (get_user(new_options, p)) | |
304 | return -EFAULT; | |
305 | if (new_options & WDIOS_DISABLECARD) { | |
306 | asr_disable(); | |
307 | retval = 0; | |
308 | } | |
309 | if (new_options & WDIOS_ENABLECARD) { | |
310 | asr_enable(); | |
d532134d | 311 | asr_toggle(); |
02355c32 | 312 | retval = 0; |
d532134d | 313 | } |
02355c32 AC |
314 | return retval; |
315 | } | |
316 | default: | |
317 | return -ENOTTY; | |
d532134d | 318 | } |
d532134d AP |
319 | } |
320 | ||
321 | static int asr_open(struct inode *inode, struct file *file) | |
322 | { | |
02355c32 | 323 | if (test_and_set_bit(0, &asr_is_open)) |
d532134d AP |
324 | return -EBUSY; |
325 | ||
326 | asr_toggle(); | |
327 | asr_enable(); | |
328 | ||
329 | return nonseekable_open(inode, file); | |
330 | } | |
331 | ||
332 | static int asr_release(struct inode *inode, struct file *file) | |
333 | { | |
334 | if (asr_expect_close == 42) | |
335 | asr_disable(); | |
336 | else { | |
02355c32 AC |
337 | printk(KERN_CRIT PFX |
338 | "unexpected close, not stopping watchdog!\n"); | |
d532134d AP |
339 | asr_toggle(); |
340 | } | |
341 | clear_bit(0, &asr_is_open); | |
342 | asr_expect_close = 0; | |
343 | return 0; | |
344 | } | |
345 | ||
62322d25 | 346 | static const struct file_operations asr_fops = { |
02355c32 AC |
347 | .owner = THIS_MODULE, |
348 | .llseek = no_llseek, | |
349 | .write = asr_write, | |
350 | .unlocked_ioctl = asr_ioctl, | |
351 | .open = asr_open, | |
352 | .release = asr_release, | |
d532134d AP |
353 | }; |
354 | ||
355 | static struct miscdevice asr_miscdev = { | |
356 | .minor = WATCHDOG_MINOR, | |
357 | .name = "watchdog", | |
358 | .fops = &asr_fops, | |
359 | }; | |
360 | ||
361 | ||
362 | struct ibmasr_id { | |
363 | const char *desc; | |
364 | int type; | |
365 | }; | |
366 | ||
367 | static struct ibmasr_id __initdata ibmasr_id_table[] = { | |
368 | { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ }, | |
369 | { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL }, | |
370 | { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER }, | |
371 | { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER }, | |
372 | { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE }, | |
373 | { NULL } | |
374 | }; | |
375 | ||
376 | static int __init ibmasr_init(void) | |
377 | { | |
378 | struct ibmasr_id *id; | |
379 | int rc; | |
380 | ||
381 | for (id = ibmasr_id_table; id->desc; id++) { | |
382 | if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) { | |
383 | asr_type = id->type; | |
384 | break; | |
385 | } | |
386 | } | |
387 | ||
388 | if (!asr_type) | |
389 | return -ENODEV; | |
390 | ||
02355c32 AC |
391 | spin_lock_init(&asr_lock); |
392 | ||
fb8f7ba0 AD |
393 | rc = asr_get_base_address(); |
394 | if (rc) | |
395 | return rc; | |
396 | ||
d532134d AP |
397 | rc = misc_register(&asr_miscdev); |
398 | if (rc < 0) { | |
fb8f7ba0 | 399 | release_region(asr_base, asr_length); |
d532134d AP |
400 | printk(KERN_ERR PFX "failed to register misc device\n"); |
401 | return rc; | |
402 | } | |
403 | ||
d532134d AP |
404 | return 0; |
405 | } | |
406 | ||
407 | static void __exit ibmasr_exit(void) | |
408 | { | |
409 | if (!nowayout) | |
410 | asr_disable(); | |
411 | ||
412 | misc_deregister(&asr_miscdev); | |
413 | ||
414 | release_region(asr_base, asr_length); | |
415 | } | |
416 | ||
417 | module_init(ibmasr_init); | |
418 | module_exit(ibmasr_exit); | |
419 | ||
420 | module_param(nowayout, int, 0); | |
02355c32 AC |
421 | MODULE_PARM_DESC(nowayout, |
422 | "Watchdog cannot be stopped once started (default=" | |
423 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
d532134d AP |
424 | |
425 | MODULE_DESCRIPTION("IBM Automatic Server Restart driver"); | |
426 | MODULE_AUTHOR("Andrey Panin"); | |
427 | MODULE_LICENSE("GPL"); | |
428 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |