[net-next-2.6.git] / drivers / watchdog / ibmasr.c

/*
 * IBM Automatic Server Restart driver.
 *
 * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
 *
 * Based on driver written by Pete Reynolds.
 * Copyright (c) IBM Corporation, 1998-2004.
 *
 * This software may be used and distributed according to the terms
 * of the GNU Public License, incorporated herein by reference.
 */

#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/timer.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/dmi.h>
#include <linux/io.h>
#include <linux/uaccess.h>


enum {
	ASMTYPE_UNKNOWN,
	ASMTYPE_TOPAZ,
	ASMTYPE_JASPER,
	ASMTYPE_PEARL,
	ASMTYPE_JUNIPER,
	ASMTYPE_SPRUCE,
};

#define PFX "ibmasr: "

#define TOPAZ_ASR_REG_OFFSET	4
#define TOPAZ_ASR_TOGGLE	0x40
#define TOPAZ_ASR_DISABLE	0x80

/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
#define PEARL_BASE	0xe04
#define PEARL_WRITE	0xe06
#define PEARL_READ	0xe07

#define PEARL_ASR_DISABLE_MASK	0x80	/* bit 7: disable = 1, enable = 0 */
#define PEARL_ASR_TOGGLE_MASK	0x40	/* bit 6: 0, then 1, then 0 */

/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
#define JASPER_ASR_REG_OFFSET	0x38

#define JASPER_ASR_DISABLE_MASK	0x01	/* bit 0: disable = 1, enable = 0 */
#define JASPER_ASR_TOGGLE_MASK	0x02	/* bit 1: 0, then 1, then 0 */

#define JUNIPER_BASE_ADDRESS	0x54b	/* Base address of Juniper ASR */
#define JUNIPER_ASR_DISABLE_MASK 0x01	/* bit 0: disable = 1 enable = 0 */
#define JUNIPER_ASR_TOGGLE_MASK	0x02	/* bit 1: 0, then 1, then 0 */

#define SPRUCE_BASE_ADDRESS	0x118e	/* Base address of Spruce ASR */
#define SPRUCE_ASR_DISABLE_MASK	0x01	/* bit 1: disable = 1 enable = 0 */
#define SPRUCE_ASR_TOGGLE_MASK	0x02	/* bit 0: 0, then 1, then 0 */


static int nowayout = WATCHDOG_NOWAYOUT;

static unsigned long asr_is_open;
static char asr_expect_close;

static unsigned int asr_type, asr_base, asr_length;
static unsigned int asr_read_addr, asr_write_addr;
static unsigned char asr_toggle_mask, asr_disable_mask;
static spinlock_t asr_lock;

static void __asr_toggle(void)
{
	unsigned char reg;

	reg = inb(asr_read_addr);

	outb(reg & ~asr_toggle_mask, asr_write_addr);
	reg = inb(asr_read_addr);

	outb(reg | asr_toggle_mask, asr_write_addr);
	reg = inb(asr_read_addr);

	outb(reg & ~asr_toggle_mask, asr_write_addr);
	reg = inb(asr_read_addr);
}

static void asr_toggle(void)
{
	spin_lock(&asr_lock);
	__asr_toggle();
	spin_unlock(&asr_lock);
}

static void asr_enable(void)
{
	unsigned char reg;

	spin_lock(&asr_lock);
	if (asr_type == ASMTYPE_TOPAZ) {
		/* asr_write_addr == asr_read_addr */
		reg = inb(asr_read_addr);
		outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
		     asr_read_addr);
	} else {
		/*
		 * First make sure the hardware timer is reset by toggling
		 * ASR hardware timer line.
		 */
		__asr_toggle();

		reg = inb(asr_read_addr);
		outb(reg & ~asr_disable_mask, asr_write_addr);
	}
	reg = inb(asr_read_addr);
	spin_unlock(&asr_lock);
}

static void asr_disable(void)
{
	unsigned char reg;

	spin_lock(&asr_lock);
	reg = inb(asr_read_addr);

	if (asr_type == ASMTYPE_TOPAZ)
		/* asr_write_addr == asr_read_addr */
		outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
		     asr_read_addr);
	else {
		outb(reg | asr_toggle_mask, asr_write_addr);
		reg = inb(asr_read_addr);

		outb(reg | asr_disable_mask, asr_write_addr);
	}
	reg = inb(asr_read_addr);
	spin_unlock(&asr_lock);
}

static int __init asr_get_base_address(void)
{
	unsigned char low, high;
	const char *type = "";

	asr_length = 1;

	switch (asr_type) {
	case ASMTYPE_TOPAZ:
		/* SELECT SuperIO CHIP FOR QUERYING
		   (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
		outb(0x07, 0x2e);
		outb(0x07, 0x2f);

		/* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
		outb(0x60, 0x2e);
		high = inb(0x2f);

		/* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
		outb(0x61, 0x2e);
		low = inb(0x2f);

		asr_base = (high << 16) | low;
		asr_read_addr = asr_write_addr =
			asr_base + TOPAZ_ASR_REG_OFFSET;
		asr_length = 5;

		break;

	case ASMTYPE_JASPER:
		type = "Jaspers ";
#if 0
		u32 r;
		/* Suggested fix */
		pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
		if (pdev == NULL)
			return -ENODEV;
		pci_read_config_dword(pdev, 0x58, &r);
		asr_base = r & 0xFFFE;
		pci_dev_put(pdev);
#else
		/* FIXME: need to use pci_config_lock here,
		   but it's not exported */

/*		spin_lock_irqsave(&pci_config_lock, flags);*/

		/* Select the SuperIO chip in the PCI I/O port register */
		outl(0x8000f858, 0xcf8);

		/* BUS 0, Slot 1F, fnc 0, offset 58 */

		/*
		 * Read the base address for the SuperIO chip.
		 * Only the lower 16 bits are valid, but the address is word
		 * aligned so the last bit must be masked off.
		 */
		asr_base = inl(0xcfc) & 0xfffe;

/*		spin_unlock_irqrestore(&pci_config_lock, flags);*/
#endif
		asr_read_addr = asr_write_addr =
			asr_base + JASPER_ASR_REG_OFFSET;
		asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
		asr_disable_mask = JASPER_ASR_DISABLE_MASK;
		asr_length = JASPER_ASR_REG_OFFSET + 1;

		break;

	case ASMTYPE_PEARL:
		type = "Pearls ";
		asr_base = PEARL_BASE;
		asr_read_addr = PEARL_READ;
		asr_write_addr = PEARL_WRITE;
		asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
		asr_disable_mask = PEARL_ASR_DISABLE_MASK;
		asr_length = 4;
		break;

	case ASMTYPE_JUNIPER:
		type = "Junipers ";
		asr_base = JUNIPER_BASE_ADDRESS;
		asr_read_addr = asr_write_addr = asr_base;
		asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
		asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
		break;

	case ASMTYPE_SPRUCE:
		type = "Spruce's ";
		asr_base = SPRUCE_BASE_ADDRESS;
		asr_read_addr = asr_write_addr = asr_base;
		asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
		asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
		break;
	}

	if (!request_region(asr_base, asr_length, "ibmasr")) {
		printk(KERN_ERR PFX "address %#x already in use\n",
			asr_base);
		return -EBUSY;
	}

	printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base);

	return 0;
}


static ssize_t asr_write(struct file *file, const char __user *buf,
			 size_t count, loff_t *ppos)
{
	if (count) {
		if (!nowayout) {
			size_t i;

			/* In case it was set long ago */
			asr_expect_close = 0;

			for (i = 0; i != count; i++) {
				char c;
				if (get_user(c, buf + i))
					return -EFAULT;
				if (c == 'V')
					asr_expect_close = 42;
			}
		}
		asr_toggle();
	}
	return count;
}

static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
	static const struct watchdog_info ident = {
		.options =	WDIOF_KEEPALIVEPING |
				WDIOF_MAGICCLOSE,
		.identity =	"IBM ASR",
	};
	void __user *argp = (void __user *)arg;
	int __user *p = argp;
	int heartbeat;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
	case WDIOC_GETSTATUS:
	case WDIOC_GETBOOTSTATUS:
		return put_user(0, p);
	case WDIOC_SETOPTIONS:
	{
		int new_options, retval = -EINVAL;
		if (get_user(new_options, p))
			return -EFAULT;
		if (new_options & WDIOS_DISABLECARD) {
			asr_disable();
			retval = 0;
		}
		if (new_options & WDIOS_ENABLECARD) {
			asr_enable();
			asr_toggle();
			retval = 0;
		}
		return retval;
	}
	case WDIOC_KEEPALIVE:
		asr_toggle();
		return 0;
	/*
	 * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
	 * and WDIOC_GETTIMEOUT always returns 256.
	 */
	case WDIOC_GETTIMEOUT:
		heartbeat = 256;
		return put_user(heartbeat, p);
	default:
		return -ENOTTY;
	}
}

static int asr_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(0, &asr_is_open))
		return -EBUSY;

	asr_toggle();
	asr_enable();

	return nonseekable_open(inode, file);
}

static int asr_release(struct inode *inode, struct file *file)
{
	if (asr_expect_close == 42)
		asr_disable();
	else {
		printk(KERN_CRIT PFX
				"unexpected close, not stopping watchdog!\n");
		asr_toggle();
	}
	clear_bit(0, &asr_is_open);
	asr_expect_close = 0;
	return 0;
}

static const struct file_operations asr_fops = {
	.owner =		THIS_MODULE,
	.llseek =		no_llseek,
	.write =		asr_write,
	.unlocked_ioctl =	asr_ioctl,
	.open =			asr_open,
	.release =		asr_release,
};

static struct miscdevice asr_miscdev = {
	.minor =	WATCHDOG_MINOR,
	.name =		"watchdog",
	.fops =		&asr_fops,
};


struct ibmasr_id {
	const char *desc;
	int type;
};

static struct ibmasr_id __initdata ibmasr_id_table[] = {
	{ "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
	{ "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
	{ "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
	{ "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
	{ "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
	{ NULL }
};

static int __init ibmasr_init(void)
{
	struct ibmasr_id *id;
	int rc;

	for (id = ibmasr_id_table; id->desc; id++) {
		if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
			asr_type = id->type;
			break;
		}
	}

	if (!asr_type)
		return -ENODEV;

	spin_lock_init(&asr_lock);

	rc = asr_get_base_address();
	if (rc)
		return rc;

	rc = misc_register(&asr_miscdev);
	if (rc < 0) {
		release_region(asr_base, asr_length);
		printk(KERN_ERR PFX "failed to register misc device\n");
		return rc;
	}

	return 0;
}

static void __exit ibmasr_exit(void)
{
	if (!nowayout)
		asr_disable();

	misc_deregister(&asr_miscdev);

	release_region(asr_base, asr_length);
}

module_init(ibmasr_init);
module_exit(ibmasr_exit);

module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
MODULE_AUTHOR("Andrey Panin");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
d532134d AP	1	/*
	2	* IBM Automatic Server Restart driver.
	3	*
	4	* Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
	5	*
	6	* Based on driver written by Pete Reynolds.
	7	* Copyright (c) IBM Corporation, 1998-2004.
	8	*
	9	* This software may be used and distributed according to the terms
	10	* of the GNU Public License, incorporated herein by reference.
	11	*/
	12
d532134d AP	13	#include <linux/fs.h>
d532134d AP	14	#include <linux/kernel.h>
d532134d AP	15	#include <linux/module.h>
	16	#include <linux/pci.h>
	17	#include <linux/timer.h>
	18	#include <linux/miscdevice.h>
	19	#include <linux/watchdog.h>
	20	#include <linux/dmi.h>
02355c32 AC	21	#include <linux/io.h>
02355c32 AC	22	#include <linux/uaccess.h>
d532134d AP	23
	24
	25	enum {
	26	ASMTYPE_UNKNOWN,
	27	ASMTYPE_TOPAZ,
	28	ASMTYPE_JASPER,
	29	ASMTYPE_PEARL,
	30	ASMTYPE_JUNIPER,
	31	ASMTYPE_SPRUCE,
	32	};
	33
	34	#define PFX "ibmasr: "
	35
	36	#define TOPAZ_ASR_REG_OFFSET 4
	37	#define TOPAZ_ASR_TOGGLE 0x40
	38	#define TOPAZ_ASR_DISABLE 0x80
	39
	40	/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
	41	#define PEARL_BASE 0xe04
	42	#define PEARL_WRITE 0xe06
	43	#define PEARL_READ 0xe07
	44
	45	#define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
	46	#define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
	47
	48	/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
	49	#define JASPER_ASR_REG_OFFSET 0x38
	50
	51	#define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
	52	#define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
	53
	54	#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
	55	#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
	56	#define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
	57
	58	#define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
	59	#define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */
	60	#define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */
	61
	62
	63	static int nowayout = WATCHDOG_NOWAYOUT;
	64
	65	static unsigned long asr_is_open;
	66	static char asr_expect_close;
	67
	68	static unsigned int asr_type, asr_base, asr_length;
	69	static unsigned int asr_read_addr, asr_write_addr;
	70	static unsigned char asr_toggle_mask, asr_disable_mask;
02355c32	71	static spinlock_t asr_lock;
d532134d	72
02355c32	73	static void __asr_toggle(void)
d532134d	74	{
02355c32 AC	75	unsigned char reg;
	76
	77	reg = inb(asr_read_addr);
d532134d AP	78
	79	outb(reg & ~asr_toggle_mask, asr_write_addr);
	80	reg = inb(asr_read_addr);
	81
	82	outb(reg \| asr_toggle_mask, asr_write_addr);
	83	reg = inb(asr_read_addr);
	84
	85	outb(reg & ~asr_toggle_mask, asr_write_addr);
	86	reg = inb(asr_read_addr);
02355c32 AC	87	}
	88
	89	static void asr_toggle(void)
	90	{
	91	spin_lock(&asr_lock);
	92	__asr_toggle();
	93	spin_unlock(&asr_lock);
d532134d AP	94	}
	95
	96	static void asr_enable(void)
	97	{
	98	unsigned char reg;
	99
02355c32	100	spin_lock(&asr_lock);
d532134d AP	101	if (asr_type == ASMTYPE_TOPAZ) {
	102	/* asr_write_addr == asr_read_addr */
	103	reg = inb(asr_read_addr);
	104	outb(reg & ~(TOPAZ_ASR_TOGGLE \| TOPAZ_ASR_DISABLE),
	105	asr_read_addr);
	106	} else {
	107	/*
	108	* First make sure the hardware timer is reset by toggling
	109	* ASR hardware timer line.
	110	*/
02355c32	111	__asr_toggle();
d532134d AP	112
	113	reg = inb(asr_read_addr);
	114	outb(reg & ~asr_disable_mask, asr_write_addr);
	115	}
	116	reg = inb(asr_read_addr);
02355c32	117	spin_unlock(&asr_lock);
d532134d AP	118	}
	119
	120	static void asr_disable(void)
	121	{
02355c32 AC	122	unsigned char reg;
	123
	124	spin_lock(&asr_lock);
	125	reg = inb(asr_read_addr);
d532134d AP	126
	127	if (asr_type == ASMTYPE_TOPAZ)
	128	/* asr_write_addr == asr_read_addr */
	129	outb(reg \| TOPAZ_ASR_TOGGLE \| TOPAZ_ASR_DISABLE,
	130	asr_read_addr);
	131	else {
	132	outb(reg \| asr_toggle_mask, asr_write_addr);
	133	reg = inb(asr_read_addr);
	134
	135	outb(reg \| asr_disable_mask, asr_write_addr);
	136	}
	137	reg = inb(asr_read_addr);
02355c32	138	spin_unlock(&asr_lock);
d532134d AP	139	}
	140
	141	static int __init asr_get_base_address(void)
	142	{
	143	unsigned char low, high;
	144	const char *type = "";
	145
	146	asr_length = 1;
	147
	148	switch (asr_type) {
	149	case ASMTYPE_TOPAZ:
02355c32 AC	150	/* SELECT SuperIO CHIP FOR QUERYING
02355c32 AC	151	(WRITE 0x07 TO BOTH 0x2E and 0x2F) */
d532134d AP	152	outb(0x07, 0x2e);
	153	outb(0x07, 0x2f);
	154
	155	/* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
	156	outb(0x60, 0x2e);
	157	high = inb(0x2f);
	158
	159	/* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
	160	outb(0x61, 0x2e);
	161	low = inb(0x2f);
	162
	163	asr_base = (high << 16) \| low;
	164	asr_read_addr = asr_write_addr =
	165	asr_base + TOPAZ_ASR_REG_OFFSET;
	166	asr_length = 5;
	167
	168	break;
	169
	170	case ASMTYPE_JASPER:
	171	type = "Jaspers ";
02355c32 AC	172	#if 0
	173	u32 r;
	174	/* Suggested fix */
	175	pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
	176	if (pdev == NULL)
	177	return -ENODEV;
	178	pci_read_config_dword(pdev, 0x58, &r);
	179	asr_base = r & 0xFFFE;
	180	pci_dev_put(pdev);
	181	#else
	182	/* FIXME: need to use pci_config_lock here,
	183	but it's not exported */
d532134d AP	184
	185	/* spin_lock_irqsave(&pci_config_lock, flags);*/
	186
	187	/* Select the SuperIO chip in the PCI I/O port register */
	188	outl(0x8000f858, 0xcf8);
	189
02355c32 AC	190	/* BUS 0, Slot 1F, fnc 0, offset 58 */
02355c32 AC	191
d532134d AP	192	/*
	193	* Read the base address for the SuperIO chip.
	194	* Only the lower 16 bits are valid, but the address is word
	195	* aligned so the last bit must be masked off.
	196	*/
	197	asr_base = inl(0xcfc) & 0xfffe;
	198
	199	/* spin_unlock_irqrestore(&pci_config_lock, flags);*/
02355c32	200	#endif
d532134d AP	201	asr_read_addr = asr_write_addr =
	202	asr_base + JASPER_ASR_REG_OFFSET;
	203	asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
	204	asr_disable_mask = JASPER_ASR_DISABLE_MASK;
	205	asr_length = JASPER_ASR_REG_OFFSET + 1;
	206
	207	break;
	208
	209	case ASMTYPE_PEARL:
	210	type = "Pearls ";
	211	asr_base = PEARL_BASE;
	212	asr_read_addr = PEARL_READ;
	213	asr_write_addr = PEARL_WRITE;
	214	asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
	215	asr_disable_mask = PEARL_ASR_DISABLE_MASK;
	216	asr_length = 4;
	217	break;
	218
	219	case ASMTYPE_JUNIPER:
	220	type = "Junipers ";
	221	asr_base = JUNIPER_BASE_ADDRESS;
	222	asr_read_addr = asr_write_addr = asr_base;
	223	asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
	224	asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
	225	break;
	226
	227	case ASMTYPE_SPRUCE:
	228	type = "Spruce's ";
	229	asr_base = SPRUCE_BASE_ADDRESS;
	230	asr_read_addr = asr_write_addr = asr_base;
	231	asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
	232	asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
	233	break;
	234	}
	235
	236	if (!request_region(asr_base, asr_length, "ibmasr")) {
	237	printk(KERN_ERR PFX "address %#x already in use\n",
	238	asr_base);
	239	return -EBUSY;
	240	}
	241
	242	printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base);
	243
	244	return 0;
	245	}
	246
	247
	248	static ssize_t asr_write(struct file file, const char __user buf,
	249	size_t count, loff_t *ppos)
	250	{
	251	if (count) {
	252	if (!nowayout) {
	253	size_t i;
	254
	255	/* In case it was set long ago */
	256	asr_expect_close = 0;
	257
	258	for (i = 0; i != count; i++) {
	259	char c;
	260	if (get_user(c, buf + i))
	261	return -EFAULT;
	262	if (c == 'V')
	263	asr_expect_close = 42;
	264	}
265	}
266	asr_toggle();
267	}
268	return count;
269	}
270
02355c32	271	static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
d532134d AP	272	{
d532134d AP	273	static const struct watchdog_info ident = {
02355c32	274	.options = WDIOF_KEEPALIVEPING \|
d532134d	275	WDIOF_MAGICCLOSE,
7944d3a5	276	.identity = "IBM ASR",
d532134d AP	277	};
	278	void __user argp = (void __user )arg;
	279	int __user *p = argp;
	280	int heartbeat;
	281
	282	switch (cmd) {
02355c32 AC	283	case WDIOC_GETSUPPORT:
	284	return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
	285	case WDIOC_GETSTATUS:
	286	case WDIOC_GETBOOTSTATUS:
	287	return put_user(0, p);
02355c32 AC	288	case WDIOC_SETOPTIONS:
	289	{
	290	int new_options, retval = -EINVAL;
	291	if (get_user(new_options, p))
	292	return -EFAULT;
	293	if (new_options & WDIOS_DISABLECARD) {
	294	asr_disable();
	295	retval = 0;
	296	}
	297	if (new_options & WDIOS_ENABLECARD) {
	298	asr_enable();
d532134d	299	asr_toggle();
02355c32	300	retval = 0;
d532134d	301	}
02355c32 AC	302	return retval;
02355c32 AC	303	}
0c06090c WVS	304	case WDIOC_KEEPALIVE:
	305	asr_toggle();
	306	return 0;
	307	/*
	308	* The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
	309	* and WDIOC_GETTIMEOUT always returns 256.
	310	*/
	311	case WDIOC_GETTIMEOUT:
	312	heartbeat = 256;
	313	return put_user(heartbeat, p);
02355c32 AC	314	default:
02355c32 AC	315	return -ENOTTY;
d532134d	316	}
d532134d AP	317	}
	318
	319	static int asr_open(struct inode inode, struct file file)
	320	{
02355c32	321	if (test_and_set_bit(0, &asr_is_open))
d532134d AP	322	return -EBUSY;
	323
	324	asr_toggle();
	325	asr_enable();
	326
	327	return nonseekable_open(inode, file);
	328	}
	329
	330	static int asr_release(struct inode inode, struct file file)
	331	{
	332	if (asr_expect_close == 42)
	333	asr_disable();
	334	else {
02355c32 AC	335	printk(KERN_CRIT PFX
02355c32 AC	336	"unexpected close, not stopping watchdog!\n");
d532134d AP	337	asr_toggle();
	338	}
	339	clear_bit(0, &asr_is_open);
	340	asr_expect_close = 0;
	341	return 0;
	342	}
	343
62322d25	344	static const struct file_operations asr_fops = {
02355c32	345	.owner = THIS_MODULE,
7944d3a5	346	.llseek = no_llseek,
02355c32 AC	347	.write = asr_write,
	348	.unlocked_ioctl = asr_ioctl,
	349	.open = asr_open,
	350	.release = asr_release,
d532134d AP	351	};
	352
	353	static struct miscdevice asr_miscdev = {
	354	.minor = WATCHDOG_MINOR,
	355	.name = "watchdog",
	356	.fops = &asr_fops,
	357	};
	358
	359
	360	struct ibmasr_id {
	361	const char *desc;
	362	int type;
	363	};
	364
	365	static struct ibmasr_id __initdata ibmasr_id_table[] = {
	366	{ "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
	367	{ "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
	368	{ "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
	369	{ "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
	370	{ "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
	371	{ NULL }
	372	};
	373
	374	static int __init ibmasr_init(void)
	375	{
	376	struct ibmasr_id *id;
	377	int rc;
	378
	379	for (id = ibmasr_id_table; id->desc; id++) {
	380	if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
	381	asr_type = id->type;
	382	break;
	383	}
	384	}
	385
	386	if (!asr_type)
	387	return -ENODEV;
	388
02355c32 AC	389	spin_lock_init(&asr_lock);
02355c32 AC	390
fb8f7ba0 AD	391	rc = asr_get_base_address();
	392	if (rc)
	393	return rc;
	394
d532134d AP	395	rc = misc_register(&asr_miscdev);
d532134d AP	396	if (rc < 0) {
fb8f7ba0	397	release_region(asr_base, asr_length);
d532134d AP	398	printk(KERN_ERR PFX "failed to register misc device\n");
	399	return rc;
	400	}
	401
d532134d AP	402	return 0;
	403	}
	404
	405	static void __exit ibmasr_exit(void)
	406	{
	407	if (!nowayout)
	408	asr_disable();
	409
	410	misc_deregister(&asr_miscdev);
	411
	412	release_region(asr_base, asr_length);
	413	}
	414
	415	module_init(ibmasr_init);
	416	module_exit(ibmasr_exit);
	417
	418	module_param(nowayout, int, 0);
02355c32 AC	419	MODULE_PARM_DESC(nowayout,
	420	"Watchdog cannot be stopped once started (default="
	421	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
d532134d AP	422
	423	MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
	424	MODULE_AUTHOR("Andrey Panin");
	425	MODULE_LICENSE("GPL");
	426	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);