[net-next-2.6.git] / drivers / watchdog / iTCO_vendor_support.c

/*
 *	intel TCO vendor specific watchdog driver support
 *
 *	(c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
 *	provide warranty for any of this software. This material is
 *	provided "AS-IS" and at no charge.
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

/* Module and version information */
#define DRV_NAME	"iTCO_vendor_support"
#define DRV_VERSION	"1.04"
#define PFX		DRV_NAME ": "

/* Includes */
#include <linux/module.h>		/* For module specific items */
#include <linux/moduleparam.h>		/* For new moduleparam's */
#include <linux/types.h>		/* For standard types (like size_t) */
#include <linux/errno.h>		/* For the -ENODEV/... values */
#include <linux/kernel.h>		/* For printk/panic/... */
#include <linux/init.h>			/* For __init/__exit/... */
#include <linux/ioport.h>		/* For io-port access */
#include <linux/io.h>			/* For inb/outb/... */

#include "iTCO_vendor.h"

/* iTCO defines */
#define	SMI_EN		(acpibase + 0x30) /* SMI Control and Enable Register */
#define	TCOBASE		(acpibase + 0x60) /* TCO base address */
#define	TCO1_STS	(TCOBASE + 0x04)  /* TCO1 Status Register */

/* List of vendor support modes */
/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
#define SUPERMICRO_OLD_BOARD	1
/* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
#define SUPERMICRO_NEW_BOARD	2
/* Broken BIOS */
#define BROKEN_BIOS		911

static int vendorsupport;
module_param(vendorsupport, int, 0);
MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default="
			"0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+, "
							"911=Broken SMI BIOS");

/*
 *	Vendor Specific Support
 */

/*
 *	Vendor Support: 1
 *	Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
 *	iTCO chipset: ICH2
 *
 *	Code contributed by: R. Seretny <lkpatches@paypc.com>
 *	Documentation obtained by R. Seretny from SuperMicro Technical Support
 *
 *	To enable Watchdog function:
 *	    BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
 *	    This setting enables SMI to clear the watchdog expired flag.
 *	    If BIOS or CPU fail which may cause SMI hang, then system will
 *	    reboot. When application starts to use watchdog function,
 *	    application has to take over the control from SMI.
 *
 *	    For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
 *	    function.
 *
 *	    Note: The system will reboot when Expire Flag is set TWICE.
 *	    So, if the watchdog timer is 20 seconds, then the maximum hang
 *	    time is about 40 seconds, and the minimum hang time is about
 *	    20.6 seconds.
 */

static void supermicro_old_pre_start(unsigned long acpibase)
{
	unsigned long val32;

	/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
	val32 = inl(SMI_EN);
	val32 &= 0xffffdfff;	/* Turn off SMI clearing watchdog */
	outl(val32, SMI_EN);	/* Needed to activate watchdog */
}

static void supermicro_old_pre_stop(unsigned long acpibase)
{
	unsigned long val32;

	/* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
	val32 = inl(SMI_EN);
	val32 |= 0x00002000;	/* Turn on SMI clearing watchdog */
	outl(val32, SMI_EN);	/* Needed to deactivate watchdog */
}

static void supermicro_old_pre_keepalive(unsigned long acpibase)
{
	/* Reload TCO Timer (done in iTCO_wdt_keepalive) + */
	/* Clear "Expire Flag" (Bit 3 of TC01_STS register) */
	outb(0x08, TCO1_STS);
}

/*
 *	Vendor Support: 2
 *	Board: Super Micro Computer Inc. P4SBx, P4DPx
 *	iTCO chipset: ICH4
 *
 *	Code contributed by: R. Seretny <lkpatches@paypc.com>
 *	Documentation obtained by R. Seretny from SuperMicro Technical Support
 *
 *	To enable Watchdog function:
 *	 1. BIOS
 *	  For P4SBx:
 *	  BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
 *	  For P4DPx:
 *	  BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
 *	 This setting enables or disables Watchdog function. When enabled, the
 *	 default watchdog timer is set to be 5 minutes (about 4m35s). It is
 *	 enough to load and run the OS. The application (service or driver) has
 *	 to take over the control once OS is running up and before watchdog
 *	 expires.
 *
 *	 2. JUMPER
 *	  For P4SBx: JP39
 *	  For P4DPx: JP37
 *	  This jumper is used for safety.  Closed is enabled. This jumper
 *	  prevents user enables watchdog in BIOS by accident.
 *
 *	 To enable Watch Dog function, both BIOS and JUMPER must be enabled.
 *
 *	The documentation lists motherboards P4SBx and P4DPx series as of
 *	20-March-2002. However, this code works flawlessly with much newer
 *	motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
 *
 *	The original iTCO driver as written does not actually reset the
 *	watchdog timer on these machines, as a result they reboot after five
 *	minutes.
 *
 *	NOTE: You may leave the Watchdog function disabled in the SuperMicro
 *	BIOS to avoid a "boot-race"... This driver will enable watchdog
 *	functionality even if it's disabled in the BIOS once the /dev/watchdog
 *	file is opened.
 */

/* I/O Port's */
#define SM_REGINDEX	0x2e	/* SuperMicro ICH4+ Register Index */
#define SM_DATAIO	0x2f	/* SuperMicro ICH4+ Register Data I/O */

/* Control Register's */
#define SM_CTLPAGESW	0x07	/* SuperMicro ICH4+ Control Page Switch */
#define SM_CTLPAGE	0x08	/* SuperMicro ICH4+ Control Page Num */

#define SM_WATCHENABLE	0x30	/* Watchdog enable: Bit 0: 0=off, 1=on */

#define SM_WATCHPAGE	0x87	/* Watchdog unlock control page */

#define SM_ENDWATCH	0xAA	/* Watchdog lock control page */

#define SM_COUNTMODE	0xf5	/* Watchdog count mode select */
				/* (Bit 3: 0 = seconds, 1 = minutes */

#define SM_WATCHTIMER	0xf6	/* 8-bits, Watchdog timer counter (RW) */

#define SM_RESETCONTROL	0xf7	/* Watchdog reset control */
				/* Bit 6: timer is reset by kbd interrupt */
				/* Bit 7: timer is reset by mouse interrupt */

static void supermicro_new_unlock_watchdog(void)
{
	/* Write 0x87 to port 0x2e twice */
	outb(SM_WATCHPAGE, SM_REGINDEX);
	outb(SM_WATCHPAGE, SM_REGINDEX);
	/* Switch to watchdog control page */
	outb(SM_CTLPAGESW, SM_REGINDEX);
	outb(SM_CTLPAGE, SM_DATAIO);
}

static void supermicro_new_lock_watchdog(void)
{
	outb(SM_ENDWATCH, SM_REGINDEX);
}

static void supermicro_new_pre_start(unsigned int heartbeat)
{
	unsigned int val;

	supermicro_new_unlock_watchdog();

	/* Watchdog timer setting needs to be in seconds*/
	outb(SM_COUNTMODE, SM_REGINDEX);
	val = inb(SM_DATAIO);
	val &= 0xF7;
	outb(val, SM_DATAIO);

	/* Write heartbeat interval to WDOG */
	outb(SM_WATCHTIMER, SM_REGINDEX);
	outb((heartbeat & 255), SM_DATAIO);

	/* Make sure keyboard/mouse interrupts don't interfere */
	outb(SM_RESETCONTROL, SM_REGINDEX);
	val = inb(SM_DATAIO);
	val &= 0x3f;
	outb(val, SM_DATAIO);

	/* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
	outb(SM_WATCHENABLE, SM_REGINDEX);
	val = inb(SM_DATAIO);
	val |= 0x01;
	outb(val, SM_DATAIO);

	supermicro_new_lock_watchdog();
}

static void supermicro_new_pre_stop(void)
{
	unsigned int val;

	supermicro_new_unlock_watchdog();

	/* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
	outb(SM_WATCHENABLE, SM_REGINDEX);
	val = inb(SM_DATAIO);
	val &= 0xFE;
	outb(val, SM_DATAIO);

	supermicro_new_lock_watchdog();
}

static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
{
	supermicro_new_unlock_watchdog();

	/* reset watchdog timeout to heartveat value */
	outb(SM_WATCHTIMER, SM_REGINDEX);
	outb((heartbeat & 255), SM_DATAIO);

	supermicro_new_lock_watchdog();
}

/*
 *	Vendor Support: 911
 *	Board: Some Intel ICHx based motherboards
 *	iTCO chipset: ICH7+
 *
 *	Some Intel motherboards have a broken BIOS implementation: i.e.
 *	the SMI handler clear's the TIMEOUT bit in the TC01_STS register
 *	and does not reload the time. Thus the TCO watchdog does not reboot
 *	the system.
 *
 *	These are the conclusions of Andriy Gapon <avg@icyb.net.ua> after
 *	debugging: the SMI handler is quite simple - it tests value in
 *	TCO1_CNT against 0x800, i.e. checks TCO_TMR_HLT. If the bit is set
 *	the handler goes into an infinite loop, apparently to allow the
 *	second timeout and reboot. Otherwise it simply clears TIMEOUT bit
 *	in TCO1_STS and that's it.
 *	So the logic seems to be reversed, because it is hard to see how
 *	TIMEOUT can get set to 1 and SMI generated when TCO_TMR_HLT is set
 *	(other than a transitional effect).
 *
 *	The only fix found to get the motherboard(s) to reboot is to put
 *	the glb_smi_en bit to 0. This is a dirty hack that bypasses the
 *	broken code by disabling Global SMI.
 *
 *	WARNING: globally disabling SMI could possibly lead to dramatic
 *	problems, especially on laptops! I.e. various ACPI things where
 *	SMI is used for communication between OS and firmware.
 *
 *	Don't use this fix if you don't need to!!!
 */

static void broken_bios_start(unsigned long acpibase)
{
	unsigned long val32;

	val32 = inl(SMI_EN);
	/* Bit 13: TCO_EN     -> 0 = Disables TCO logic generating an SMI#
	   Bit  0: GBL_SMI_EN -> 0 = No SMI# will be generated by ICH. */
	val32 &= 0xffffdffe;
	outl(val32, SMI_EN);
}

static void broken_bios_stop(unsigned long acpibase)
{
	unsigned long val32;

	val32 = inl(SMI_EN);
	/* Bit 13: TCO_EN     -> 1 = Enables TCO logic generating an SMI#
	   Bit  0: GBL_SMI_EN -> 1 = Turn global SMI on again. */
	val32 |= 0x00002001;
	outl(val32, SMI_EN);
}

/*
 *	Generic Support Functions
 */

void iTCO_vendor_pre_start(unsigned long acpibase,
			   unsigned int heartbeat)
{
	switch (vendorsupport) {
	case SUPERMICRO_OLD_BOARD:
		supermicro_old_pre_start(acpibase);
		break;
	case SUPERMICRO_NEW_BOARD:
		supermicro_new_pre_start(heartbeat);
		break;
	case BROKEN_BIOS:
		broken_bios_start(acpibase);
		break;
	}
}
EXPORT_SYMBOL(iTCO_vendor_pre_start);

void iTCO_vendor_pre_stop(unsigned long acpibase)
{
	switch (vendorsupport) {
	case SUPERMICRO_OLD_BOARD:
		supermicro_old_pre_stop(acpibase);
		break;
	case SUPERMICRO_NEW_BOARD:
		supermicro_new_pre_stop();
		break;
	case BROKEN_BIOS:
		broken_bios_stop(acpibase);
		break;
	}
}
EXPORT_SYMBOL(iTCO_vendor_pre_stop);

void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
{
	if (vendorsupport == SUPERMICRO_OLD_BOARD)
		supermicro_old_pre_keepalive(acpibase);
	else if (vendorsupport == SUPERMICRO_NEW_BOARD)
		supermicro_new_pre_set_heartbeat(heartbeat);
}
EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);

void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
{
	if (vendorsupport == SUPERMICRO_NEW_BOARD)
		supermicro_new_pre_set_heartbeat(heartbeat);
}
EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);

int iTCO_vendor_check_noreboot_on(void)
{
	switch (vendorsupport) {
	case SUPERMICRO_OLD_BOARD:
		return 0;
	default:
		return 1;
	}
}
EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);

static int __init iTCO_vendor_init_module(void)
{
	printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
	return 0;
}

static void __exit iTCO_vendor_exit_module(void)
{
	printk(KERN_INFO PFX "Module Unloaded\n");
}

module_init(iTCO_vendor_init_module);
module_exit(iTCO_vendor_exit_module);

MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, "
		"R. Seretny <lkpatches@paypc.com>");
MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL");
Commit	Line	Data
e033351d WVS	1	/*
	2	* intel TCO vendor specific watchdog driver support
	3	*
12d60e28	4	* (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
e033351d WVS	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*
	11	* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
	12	* provide warranty for any of this software. This material is
	13	* provided "AS-IS" and at no charge.
	14	*/
	15
	16	/*
	17	* Includes, defines, variables, module parameters, ...
	18	*/
	19
	20	/* Module and version information */
7944d3a5	21	#define DRV_NAME "iTCO_vendor_support"
55e8ddec	22	#define DRV_VERSION "1.04"
e033351d WVS	23	#define PFX DRV_NAME ": "
	24
	25	/* Includes */
	26	#include <linux/module.h> /* For module specific items */
	27	#include <linux/moduleparam.h> /* For new moduleparam's */
	28	#include <linux/types.h> /* For standard types (like size_t) */
	29	#include <linux/errno.h> /* For the -ENODEV/... values */
	30	#include <linux/kernel.h> /* For printk/panic/... */
	31	#include <linux/init.h> /* For __init/__exit/... */
	32	#include <linux/ioport.h> /* For io-port access */
0e6fa3fb AC	33	#include <linux/io.h> /* For inb/outb/... */
	34
	35	#include "iTCO_vendor.h"
e033351d WVS	36
e033351d WVS	37	/* iTCO defines */
0a7e6582 WVS	38	#define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */
	39	#define TCOBASE (acpibase + 0x60) /* TCO base address */
	40	#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
e033351d WVS	41
e033351d WVS	42	/* List of vendor support modes */
0e6fa3fb AC	43	/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
	44	#define SUPERMICRO_OLD_BOARD 1
	45	/* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
	46	#define SUPERMICRO_NEW_BOARD 2
55e8ddec WVS	47	/* Broken BIOS */
55e8ddec WVS	48	#define BROKEN_BIOS 911
e033351d	49
0e6fa3fb	50	static int vendorsupport;
e033351d	51	module_param(vendorsupport, int, 0);
143a2e54	52	MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default="
55e8ddec WVS	53	"0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+, "
55e8ddec WVS	54	"911=Broken SMI BIOS");
e033351d WVS	55
	56	/*
	57	* Vendor Specific Support
	58	*/
	59
	60	/*
	61	* Vendor Support: 1
	62	* Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
	63	* iTCO chipset: ICH2
	64	*
	65	* Code contributed by: R. Seretny <lkpatches@paypc.com>
	66	* Documentation obtained by R. Seretny from SuperMicro Technical Support
	67	*
	68	* To enable Watchdog function:
	69	* BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
	70	* This setting enables SMI to clear the watchdog expired flag.
	71	* If BIOS or CPU fail which may cause SMI hang, then system will
	72	* reboot. When application starts to use watchdog function,
	73	* application has to take over the control from SMI.
	74	*
	75	* For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
	76	* function.
	77	*
	78	* Note: The system will reboot when Expire Flag is set TWICE.
	79	* So, if the watchdog timer is 20 seconds, then the maximum hang
	80	* time is about 40 seconds, and the minimum hang time is about
	81	* 20.6 seconds.
	82	*/
	83
12d60e28 WVS	84	static void supermicro_old_pre_start(unsigned long acpibase)
	85	{
	86	unsigned long val32;
	87
	88	/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
	89	val32 = inl(SMI_EN);
	90	val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
	91	outl(val32, SMI_EN); /* Needed to activate watchdog */
	92	}
	93
	94	static void supermicro_old_pre_stop(unsigned long acpibase)
	95	{
	96	unsigned long val32;
	97
	98	/* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
	99	val32 = inl(SMI_EN);
	100	val32 \|= 0x00002000; /* Turn on SMI clearing watchdog */
	101	outl(val32, SMI_EN); /* Needed to deactivate watchdog */
	102	}
	103
e033351d WVS	104	static void supermicro_old_pre_keepalive(unsigned long acpibase)
	105	{
	106	/* Reload TCO Timer (done in iTCO_wdt_keepalive) + */
	107	/* Clear "Expire Flag" (Bit 3 of TC01_STS register) */
	108	outb(0x08, TCO1_STS);
	109	}
	110
	111	/*
	112	* Vendor Support: 2
	113	* Board: Super Micro Computer Inc. P4SBx, P4DPx
	114	* iTCO chipset: ICH4
	115	*
	116	* Code contributed by: R. Seretny <lkpatches@paypc.com>
	117	* Documentation obtained by R. Seretny from SuperMicro Technical Support
	118	*
	119	* To enable Watchdog function:
	120	* 1. BIOS
	121	* For P4SBx:
	122	* BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
	123	* For P4DPx:
	124	* BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
	125	* This setting enables or disables Watchdog function. When enabled, the
96de0e25	126	* default watchdog timer is set to be 5 minutes (about 4m35s). It is
e033351d WVS	127	* enough to load and run the OS. The application (service or driver) has
	128	* to take over the control once OS is running up and before watchdog
	129	* expires.
	130	*
	131	* 2. JUMPER
	132	* For P4SBx: JP39
	133	* For P4DPx: JP37
	134	* This jumper is used for safety. Closed is enabled. This jumper
	135	* prevents user enables watchdog in BIOS by accident.
	136	*
	137	* To enable Watch Dog function, both BIOS and JUMPER must be enabled.
	138	*
	139	* The documentation lists motherboards P4SBx and P4DPx series as of
	140	* 20-March-2002. However, this code works flawlessly with much newer
	141	* motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
	142	*
	143	* The original iTCO driver as written does not actually reset the
	144	* watchdog timer on these machines, as a result they reboot after five
	145	* minutes.
	146	*
	147	* NOTE: You may leave the Watchdog function disabled in the SuperMicro
	148	* BIOS to avoid a "boot-race"... This driver will enable watchdog
	149	* functionality even if it's disabled in the BIOS once the /dev/watchdog
	150	* file is opened.
	151	*/
	152
	153	/* I/O Port's */
0e6fa3fb AC	154	#define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */
0e6fa3fb AC	155	#define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */
e033351d WVS	156
e033351d WVS	157	/* Control Register's */
0e6fa3fb AC	158	#define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */
0e6fa3fb AC	159	#define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */
e033351d	160
0e6fa3fb	161	#define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */
e033351d	162
0e6fa3fb	163	#define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */
e033351d	164
0e6fa3fb	165	#define SM_ENDWATCH 0xAA /* Watchdog lock control page */
e033351d	166
0e6fa3fb AC	167	#define SM_COUNTMODE 0xf5 /* Watchdog count mode select */
0e6fa3fb AC	168	/* (Bit 3: 0 = seconds, 1 = minutes */
e033351d	169
0e6fa3fb	170	#define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */
e033351d	171
0e6fa3fb AC	172	#define SM_RESETCONTROL 0xf7 /* Watchdog reset control */
	173	/* Bit 6: timer is reset by kbd interrupt */
	174	/* Bit 7: timer is reset by mouse interrupt */
e033351d WVS	175
	176	static void supermicro_new_unlock_watchdog(void)
	177	{
0e6fa3fb	178	/* Write 0x87 to port 0x2e twice */
e033351d	179	outb(SM_WATCHPAGE, SM_REGINDEX);
0e6fa3fb AC	180	outb(SM_WATCHPAGE, SM_REGINDEX);
	181	/* Switch to watchdog control page */
	182	outb(SM_CTLPAGESW, SM_REGINDEX);
e033351d WVS	183	outb(SM_CTLPAGE, SM_DATAIO);
	184	}
	185
	186	static void supermicro_new_lock_watchdog(void)
	187	{
	188	outb(SM_ENDWATCH, SM_REGINDEX);
	189	}
	190
	191	static void supermicro_new_pre_start(unsigned int heartbeat)
	192	{
	193	unsigned int val;
	194
	195	supermicro_new_unlock_watchdog();
	196
	197	/* Watchdog timer setting needs to be in seconds*/
	198	outb(SM_COUNTMODE, SM_REGINDEX);
	199	val = inb(SM_DATAIO);
	200	val &= 0xF7;
	201	outb(val, SM_DATAIO);
	202
	203	/* Write heartbeat interval to WDOG */
0e6fa3fb	204	outb(SM_WATCHTIMER, SM_REGINDEX);
e033351d WVS	205	outb((heartbeat & 255), SM_DATAIO);
	206
	207	/* Make sure keyboard/mouse interrupts don't interfere */
	208	outb(SM_RESETCONTROL, SM_REGINDEX);
	209	val = inb(SM_DATAIO);
	210	val &= 0x3f;
	211	outb(val, SM_DATAIO);
	212
	213	/* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
	214	outb(SM_WATCHENABLE, SM_REGINDEX);
	215	val = inb(SM_DATAIO);
	216	val \|= 0x01;
	217	outb(val, SM_DATAIO);
	218
	219	supermicro_new_lock_watchdog();
	220	}
	221
	222	static void supermicro_new_pre_stop(void)
	223	{
	224	unsigned int val;
	225
	226	supermicro_new_unlock_watchdog();
	227
	228	/* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
	229	outb(SM_WATCHENABLE, SM_REGINDEX);
	230	val = inb(SM_DATAIO);
	231	val &= 0xFE;
	232	outb(val, SM_DATAIO);
	233
	234	supermicro_new_lock_watchdog();
	235	}
	236
	237	static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
	238	{
	239	supermicro_new_unlock_watchdog();
	240
	241	/* reset watchdog timeout to heartveat value */
	242	outb(SM_WATCHTIMER, SM_REGINDEX);
	243	outb((heartbeat & 255), SM_DATAIO);
	244
	245	supermicro_new_lock_watchdog();
	246	}
	247
55e8ddec WVS	248	/*
	249	* Vendor Support: 911
	250	* Board: Some Intel ICHx based motherboards
	251	* iTCO chipset: ICH7+
	252	*
	253	* Some Intel motherboards have a broken BIOS implementation: i.e.
	254	* the SMI handler clear's the TIMEOUT bit in the TC01_STS register
	255	* and does not reload the time. Thus the TCO watchdog does not reboot
	256	* the system.
	257	*
	258	* These are the conclusions of Andriy Gapon <avg@icyb.net.ua> after
	259	* debugging: the SMI handler is quite simple - it tests value in
	260	* TCO1_CNT against 0x800, i.e. checks TCO_TMR_HLT. If the bit is set
	261	* the handler goes into an infinite loop, apparently to allow the
	262	* second timeout and reboot. Otherwise it simply clears TIMEOUT bit
	263	* in TCO1_STS and that's it.
	264	* So the logic seems to be reversed, because it is hard to see how
	265	* TIMEOUT can get set to 1 and SMI generated when TCO_TMR_HLT is set
	266	* (other than a transitional effect).
	267	*
	268	* The only fix found to get the motherboard(s) to reboot is to put
	269	* the glb_smi_en bit to 0. This is a dirty hack that bypasses the
	270	* broken code by disabling Global SMI.
	271	*
	272	* WARNING: globally disabling SMI could possibly lead to dramatic
	273	* problems, especially on laptops! I.e. various ACPI things where
	274	* SMI is used for communication between OS and firmware.
	275	*
	276	* Don't use this fix if you don't need to!!!
	277	*/
	278
	279	static void broken_bios_start(unsigned long acpibase)
	280	{
	281	unsigned long val32;
	282
	283	val32 = inl(SMI_EN);
	284	/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI#
	285	Bit 0: GBL_SMI_EN -> 0 = No SMI# will be generated by ICH. */
	286	val32 &= 0xffffdffe;
	287	outl(val32, SMI_EN);
	288	}
	289
	290	static void broken_bios_stop(unsigned long acpibase)
	291	{
	292	unsigned long val32;
	293
	294	val32 = inl(SMI_EN);
	295	/* Bit 13: TCO_EN -> 1 = Enables TCO logic generating an SMI#
	296	Bit 0: GBL_SMI_EN -> 1 = Turn global SMI on again. */
	297	val32 \|= 0x00002001;
	298	outl(val32, SMI_EN);
	299	}
	300
e033351d WVS	301	/*
	302	* Generic Support Functions
	303	*/
	304
	305	void iTCO_vendor_pre_start(unsigned long acpibase,
	306	unsigned int heartbeat)
	307	{
55e8ddec WVS	308	switch (vendorsupport) {
55e8ddec WVS	309	case SUPERMICRO_OLD_BOARD:
12d60e28	310	supermicro_old_pre_start(acpibase);
55e8ddec WVS	311	break;
55e8ddec WVS	312	case SUPERMICRO_NEW_BOARD:
e033351d	313	supermicro_new_pre_start(heartbeat);
55e8ddec WVS	314	break;
	315	case BROKEN_BIOS:
	316	broken_bios_start(acpibase);
	317	break;
	318	}
e033351d WVS	319	}
	320	EXPORT_SYMBOL(iTCO_vendor_pre_start);
	321
	322	void iTCO_vendor_pre_stop(unsigned long acpibase)
	323	{
55e8ddec WVS	324	switch (vendorsupport) {
55e8ddec WVS	325	case SUPERMICRO_OLD_BOARD:
12d60e28	326	supermicro_old_pre_stop(acpibase);
55e8ddec WVS	327	break;
55e8ddec WVS	328	case SUPERMICRO_NEW_BOARD:
e033351d	329	supermicro_new_pre_stop();
55e8ddec WVS	330	break;
	331	case BROKEN_BIOS:
	332	broken_bios_stop(acpibase);
	333	break;
	334	}
e033351d WVS	335	}
	336	EXPORT_SYMBOL(iTCO_vendor_pre_stop);
	337
	338	void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
	339	{
	340	if (vendorsupport == SUPERMICRO_OLD_BOARD)
	341	supermicro_old_pre_keepalive(acpibase);
	342	else if (vendorsupport == SUPERMICRO_NEW_BOARD)
	343	supermicro_new_pre_set_heartbeat(heartbeat);
	344	}
	345	EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);
	346
	347	void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
	348	{
	349	if (vendorsupport == SUPERMICRO_NEW_BOARD)
	350	supermicro_new_pre_set_heartbeat(heartbeat);
	351	}
	352	EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);
	353
	354	int iTCO_vendor_check_noreboot_on(void)
	355	{
0e6fa3fb	356	switch (vendorsupport) {
e033351d WVS	357	case SUPERMICRO_OLD_BOARD:
	358	return 0;
	359	default:
	360	return 1;
	361	}
	362	}
	363	EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);
	364
	365	static int __init iTCO_vendor_init_module(void)
	366	{
0e6fa3fb	367	printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
e033351d WVS	368	return 0;
	369	}
	370
	371	static void __exit iTCO_vendor_exit_module(void)
	372	{
0e6fa3fb	373	printk(KERN_INFO PFX "Module Unloaded\n");
e033351d WVS	374	}
	375
	376	module_init(iTCO_vendor_init_module);
	377	module_exit(iTCO_vendor_exit_module);
	378
143a2e54 WVS	379	MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, "
143a2e54 WVS	380	"R. Seretny <lkpatches@paypc.com>");
e033351d WVS	381	MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
	382	MODULE_VERSION(DRV_VERSION);
	383	MODULE_LICENSE("GPL");
	384