[net-next-2.6.git] / drivers / video / via / accel.c

/*
 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.

 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public
 * License as published by the Free Software Foundation;
 * either version 2, or (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
 * the implied warranty of MERCHANTABILITY or FITNESS FOR
 * A PARTICULAR PURPOSE.See the GNU General Public License
 * for more details.

 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
#include <linux/via-core.h>
#include "global.h"

/*
 * Figure out an appropriate bytes-per-pixel setting.
 */
static int viafb_set_bpp(void __iomem *engine, u8 bpp)
{
	u32 gemode;

	/* Preserve the reserved bits */
	/* Lowest 2 bits to zero gives us no rotation */
	gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
	switch (bpp) {
	case 8:
		gemode |= VIA_GEM_8bpp;
		break;
	case 16:
		gemode |= VIA_GEM_16bpp;
		break;
	case 32:
		gemode |= VIA_GEM_32bpp;
		break;
	default:
		printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
		return -EINVAL;
	}
	writel(gemode, engine + VIA_REG_GEMODE);
	return 0;
}


static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	u32 fg_color, u32 bg_color, u8 fill_rop)
{
	u32 ge_cmd = 0, tmp, i;
	int ret;

	if (!op || op > 3) {
		printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
		return -EINVAL;
	}

	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
		if (src_x < dst_x) {
			ge_cmd |= 0x00008000;
			src_x += width - 1;
			dst_x += width - 1;
		}
		if (src_y < dst_y) {
			ge_cmd |= 0x00004000;
			src_y += height - 1;
			dst_y += height - 1;
		}
	}

	if (op == VIA_BITBLT_FILL) {
		switch (fill_rop) {
		case 0x00: /* blackness */
		case 0x5A: /* pattern inversion */
		case 0xF0: /* pattern copy */
		case 0xFF: /* whiteness */
			break;
		default:
			printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
				"%u\n", fill_rop);
			return -EINVAL;
		}
	}

	ret = viafb_set_bpp(engine, dst_bpp);
	if (ret)
		return ret;

	if (op != VIA_BITBLT_FILL) {
		if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
			|| src_y & 0xFFFFF000) {
			printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
				"x/y %d %d\n", src_x, src_y);
			return -EINVAL;
		}
		tmp = src_x | (src_y << 16);
		writel(tmp, engine + 0x08);
	}

	if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
			"%d %d\n", dst_x, dst_y);
		return -EINVAL;
	}
	tmp = dst_x | (dst_y << 16);
	writel(tmp, engine + 0x0C);

	if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
			"%d %d\n", width, height);
		return -EINVAL;
	}
	tmp = (width - 1) | ((height - 1) << 16);
	writel(tmp, engine + 0x10);

	if (op != VIA_BITBLT_COLOR)
		writel(fg_color, engine + 0x18);

	if (op == VIA_BITBLT_MONO)
		writel(bg_color, engine + 0x1C);

	if (op != VIA_BITBLT_FILL) {
		tmp = src_mem ? 0 : src_addr;
		if (dst_addr & 0xE0000007) {
			printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
				"address %X\n", tmp);
			return -EINVAL;
		}
		tmp >>= 3;
		writel(tmp, engine + 0x30);
	}

	if (dst_addr & 0xE0000007) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
			"address %X\n", dst_addr);
		return -EINVAL;
	}
	tmp = dst_addr >> 3;
	writel(tmp, engine + 0x34);

	if (op == VIA_BITBLT_FILL)
		tmp = 0;
	else
		tmp = src_pitch;
	if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
			tmp, dst_pitch);
		return -EINVAL;
	}
	tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
	writel(tmp, engine + 0x38);

	if (op == VIA_BITBLT_FILL)
		ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
	else {
		ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
		if (src_mem)
			ge_cmd |= 0x00000040;
		if (op == VIA_BITBLT_MONO)
			ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
		else
			ge_cmd |= 0x00000001;
	}
	writel(ge_cmd, engine);

	if (op == VIA_BITBLT_FILL || !src_mem)
		return 0;

	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
		3) >> 2;

	for (i = 0; i < tmp; i++)
		writel(src_mem[i], engine + VIA_MMIO_BLTBASE);

	return 0;
}

static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	u32 fg_color, u32 bg_color, u8 fill_rop)
{
	u32 ge_cmd = 0, tmp, i;
	int ret;

	if (!op || op > 3) {
		printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
		return -EINVAL;
	}

	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
		if (src_x < dst_x) {
			ge_cmd |= 0x00008000;
			src_x += width - 1;
			dst_x += width - 1;
		}
		if (src_y < dst_y) {
			ge_cmd |= 0x00004000;
			src_y += height - 1;
			dst_y += height - 1;
		}
	}

	if (op == VIA_BITBLT_FILL) {
		switch (fill_rop) {
		case 0x00: /* blackness */
		case 0x5A: /* pattern inversion */
		case 0xF0: /* pattern copy */
		case 0xFF: /* whiteness */
			break;
		default:
			printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
				"%u\n", fill_rop);
			return -EINVAL;
		}
	}

	ret = viafb_set_bpp(engine, dst_bpp);
	if (ret)
		return ret;

	if (op == VIA_BITBLT_FILL)
		tmp = 0;
	else
		tmp = src_pitch;
	if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
			tmp, dst_pitch);
		return -EINVAL;
	}
	tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
	writel(tmp, engine + 0x08);

	if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
			"%d %d\n", width, height);
		return -EINVAL;
	}
	tmp = (width - 1) | ((height - 1) << 16);
	writel(tmp, engine + 0x0C);

	if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
			"%d %d\n", dst_x, dst_y);
		return -EINVAL;
	}
	tmp = dst_x | (dst_y << 16);
	writel(tmp, engine + 0x10);

	if (dst_addr & 0xE0000007) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
			"address %X\n", dst_addr);
		return -EINVAL;
	}
	tmp = dst_addr >> 3;
	writel(tmp, engine + 0x14);

	if (op != VIA_BITBLT_FILL) {
		if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
			|| src_y & 0xFFFFF000) {
			printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
				"x/y %d %d\n", src_x, src_y);
			return -EINVAL;
		}
		tmp = src_x | (src_y << 16);
		writel(tmp, engine + 0x18);

		tmp = src_mem ? 0 : src_addr;
		if (dst_addr & 0xE0000007) {
			printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
				"address %X\n", tmp);
			return -EINVAL;
		}
		tmp >>= 3;
		writel(tmp, engine + 0x1C);
	}

	if (op != VIA_BITBLT_COLOR)
		writel(fg_color, engine + 0x4C);

	if (op == VIA_BITBLT_MONO)
		writel(bg_color, engine + 0x50);

	if (op == VIA_BITBLT_FILL)
		ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
	else {
		ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
		if (src_mem)
			ge_cmd |= 0x00000040;
		if (op == VIA_BITBLT_MONO)
			ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
		else
			ge_cmd |= 0x00000001;
	}
	writel(ge_cmd, engine);

	if (op == VIA_BITBLT_FILL || !src_mem)
		return 0;

	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
		3) >> 2;

	for (i = 0; i < tmp; i++)
		writel(src_mem[i], engine + VIA_MMIO_BLTBASE);

	return 0;
}

int viafb_init_engine(struct fb_info *info)
{
	struct viafb_par *viapar = info->par;
	void __iomem *engine;
	int highest_reg, i;
	u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
		vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;

	engine = viapar->shared->vdev->engine_mmio;
	if (!engine) {
		printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
			"hardware acceleration disabled\n");
		return -ENOMEM;
	}

	/* Initialize registers to reset the 2D engine */
	switch (viapar->shared->chip_info.twod_engine) {
	case VIA_2D_ENG_M1:
		highest_reg = 0x5c;
		break;
	default:
		highest_reg = 0x40;
		break;
	}
	for (i = 0; i <= highest_reg; i += 4)
		writel(0x0, engine + i);

	switch (chip_name) {
	case UNICHROME_CLE266:
	case UNICHROME_K400:
	case UNICHROME_K800:
	case UNICHROME_PM800:
	case UNICHROME_CN700:
	case UNICHROME_CX700:
	case UNICHROME_CN750:
	case UNICHROME_K8M890:
	case UNICHROME_P4M890:
	case UNICHROME_P4M900:
		viapar->shared->hw_bitblt = hw_bitblt_1;
		break;
	case UNICHROME_VX800:
	case UNICHROME_VX855:
		viapar->shared->hw_bitblt = hw_bitblt_2;
		break;
	default:
		viapar->shared->hw_bitblt = NULL;
	}

	viapar->fbmem_free -= CURSOR_SIZE;
	viapar->shared->cursor_vram_addr = viapar->fbmem_free;
	viapar->fbmem_used += CURSOR_SIZE;

	viapar->fbmem_free -= VQ_SIZE;
	viapar->shared->vq_vram_addr = viapar->fbmem_free;
	viapar->fbmem_used += VQ_SIZE;

#if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)
	/*
	 * Set aside a chunk of framebuffer memory for the camera
	 * driver.  Someday this driver probably needs a proper allocator
	 * for fbmem; for now, we just have to do this before the
	 * framebuffer initializes itself.
	 *
	 * As for the size: the engine can handle three frames,
	 * 16 bits deep, up to VGA resolution.
	 */
	viapar->shared->vdev->camera_fbmem_size = 3*VGA_HEIGHT*VGA_WIDTH*2;
	viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size;
	viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size;
	viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;
#endif

	/* Init AGP and VQ regs */
	switch (chip_name) {
	case UNICHROME_K8M890:
	case UNICHROME_P4M900:
	case UNICHROME_VX800:
	case UNICHROME_VX855:
		writel(0x00100000, engine + VIA_REG_CR_TRANSET);
		writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
		writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
		break;

	default:
		writel(0x00100000, engine + VIA_REG_TRANSET);
		writel(0x00000000, engine + VIA_REG_TRANSPACE);
		writel(0x00333004, engine + VIA_REG_TRANSPACE);
		writel(0x60000000, engine + VIA_REG_TRANSPACE);
		writel(0x61000000, engine + VIA_REG_TRANSPACE);
		writel(0x62000000, engine + VIA_REG_TRANSPACE);
		writel(0x63000000, engine + VIA_REG_TRANSPACE);
		writel(0x64000000, engine + VIA_REG_TRANSPACE);
		writel(0x7D000000, engine + VIA_REG_TRANSPACE);

		writel(0xFE020000, engine + VIA_REG_TRANSET);
		writel(0x00000000, engine + VIA_REG_TRANSPACE);
		break;
	}

	/* Enable VQ */
	vq_start_addr = viapar->shared->vq_vram_addr;
	vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;

	vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
	vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
	vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
		((vq_end_addr & 0xFF000000) >> 16);
	vq_len = 0x53000000 | (VQ_SIZE >> 3);

	switch (chip_name) {
	case UNICHROME_K8M890:
	case UNICHROME_P4M900:
	case UNICHROME_VX800:
	case UNICHROME_VX855:
		vq_start_low |= 0x20000000;
		vq_end_low |= 0x20000000;
		vq_high |= 0x20000000;
		vq_len |= 0x20000000;

		writel(0x00100000, engine + VIA_REG_CR_TRANSET);
		writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
		writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
		writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
		writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
		writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
		writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
		break;
	default:
		writel(0x00FE0000, engine + VIA_REG_TRANSET);
		writel(0x080003FE, engine + VIA_REG_TRANSPACE);
		writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
		writel(0x0B000260, engine + VIA_REG_TRANSPACE);
		writel(0x0C000274, engine + VIA_REG_TRANSPACE);
		writel(0x0D000264, engine + VIA_REG_TRANSPACE);
		writel(0x0E000000, engine + VIA_REG_TRANSPACE);
		writel(0x0F000020, engine + VIA_REG_TRANSPACE);
		writel(0x1000027E, engine + VIA_REG_TRANSPACE);
		writel(0x110002FE, engine + VIA_REG_TRANSPACE);
		writel(0x200F0060, engine + VIA_REG_TRANSPACE);

		writel(0x00000006, engine + VIA_REG_TRANSPACE);
		writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
		writel(0x44000000, engine + VIA_REG_TRANSPACE);
		writel(0x45080C04, engine + VIA_REG_TRANSPACE);
		writel(0x46800408, engine + VIA_REG_TRANSPACE);

		writel(vq_high, engine + VIA_REG_TRANSPACE);
		writel(vq_start_low, engine + VIA_REG_TRANSPACE);
		writel(vq_end_low, engine + VIA_REG_TRANSPACE);
		writel(vq_len, engine + VIA_REG_TRANSPACE);
		break;
	}

	/* Set Cursor Image Base Address */
	writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
	writel(0x0, engine + VIA_REG_CURSOR_POS);
	writel(0x0, engine + VIA_REG_CURSOR_ORG);
	writel(0x0, engine + VIA_REG_CURSOR_BG);
	writel(0x0, engine + VIA_REG_CURSOR_FG);
	return 0;
}

void viafb_show_hw_cursor(struct fb_info *info, int Status)
{
	struct viafb_par *viapar = info->par;
	u32 temp, iga_path = viapar->iga_path;

	temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
	switch (Status) {
	case HW_Cursor_ON:
		temp |= 0x1;
		break;
	case HW_Cursor_OFF:
		temp &= 0xFFFFFFFE;
		break;
	}
	switch (iga_path) {
	case IGA2:
		temp |= 0x80000000;
		break;
	case IGA1:
	default:
		temp &= 0x7FFFFFFF;
	}
	writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
}

void viafb_wait_engine_idle(struct fb_info *info)
{
	struct viafb_par *viapar = info->par;
	int loop = 0;
	u32 mask;
	void __iomem *engine = viapar->shared->vdev->engine_mmio;

	switch (viapar->shared->chip_info.twod_engine) {
	case VIA_2D_ENG_H5:
	case VIA_2D_ENG_M1:
		mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
			      VIA_3D_ENG_BUSY_M1;
		break;
	default:
		while (!(readl(engine + VIA_REG_STATUS) &
				VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
			loop++;
			cpu_relax();
		}
		mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
		break;
	}

	while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
		loop++;
		cpu_relax();
	}

	if (loop >= MAXLOOP)
		printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
}
Commit	Line	Data
801b8a8c JC	1	/*
	2	* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
	3	* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
	4
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public
	7	* License as published by the Free Software Foundation;
	8	* either version 2, or (at your option) any later version.
	9
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
	12	* the implied warranty of MERCHANTABILITY or FITNESS FOR
	13	* A PARTICULAR PURPOSE.See the GNU General Public License
	14	* for more details.
	15
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc.,
	19	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	20	*/
ec66841e	21	#include <linux/via-core.h>
801b8a8c JC	22	#include "global.h"
801b8a8c JC	23
f1b99aa9 JC	24	/*
	25	* Figure out an appropriate bytes-per-pixel setting.
	26	*/
	27	static int viafb_set_bpp(void __iomem *engine, u8 bpp)
	28	{
	29	u32 gemode;
	30
	31	/* Preserve the reserved bits */
	32	/* Lowest 2 bits to zero gives us no rotation */
	33	gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
	34	switch (bpp) {
	35	case 8:
	36	gemode \|= VIA_GEM_8bpp;
	37	break;
	38	case 16:
	39	gemode \|= VIA_GEM_16bpp;
	40	break;
	41	case 32:
	42	gemode \|= VIA_GEM_32bpp;
	43	break;
	44	default:
	45	printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
	46	return -EINVAL;
	47	}
	48	writel(gemode, engine + VIA_REG_GEMODE);
	49	return 0;
	50	}
	51
	52
c3e25673 FTS	53	static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
	54	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	55	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	56	u32 fg_color, u32 bg_color, u8 fill_rop)
801b8a8c	57	{
c3e25673	58	u32 ge_cmd = 0, tmp, i;
f1b99aa9	59	int ret;
c3e25673 FTS	60
	61	if (!op \|\| op > 3) {
	62	printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
	63	return -EINVAL;
	64	}
	65
	66	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
	67	if (src_x < dst_x) {
	68	ge_cmd \|= 0x00008000;
	69	src_x += width - 1;
	70	dst_x += width - 1;
	71	}
	72	if (src_y < dst_y) {
	73	ge_cmd \|= 0x00004000;
	74	src_y += height - 1;
	75	dst_y += height - 1;
	76	}
	77	}
	78
	79	if (op == VIA_BITBLT_FILL) {
	80	switch (fill_rop) {
	81	case 0x00: /* blackness */
	82	case 0x5A: /* pattern inversion */
	83	case 0xF0: /* pattern copy */
	84	case 0xFF: /* whiteness */
	85	break;
	86	default:
	87	printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
	88	"%u\n", fill_rop);
	89	return -EINVAL;
	90	}
	91	}
	92
f1b99aa9 JC	93	ret = viafb_set_bpp(engine, dst_bpp);
	94	if (ret)
	95	return ret;
c3e25673 FTS	96
	97	if (op != VIA_BITBLT_FILL) {
	98	if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
	99	\|\| src_y & 0xFFFFF000) {
	100	printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
	101	"x/y %d %d\n", src_x, src_y);
	102	return -EINVAL;
	103	}
	104	tmp = src_x \| (src_y << 16);
	105	writel(tmp, engine + 0x08);
	106	}
	107
	108	if (dst_x & 0xFFFFF000 \|\| dst_y & 0xFFFFF000) {
	109	printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
	110	"%d %d\n", dst_x, dst_y);
	111	return -EINVAL;
	112	}
	113	tmp = dst_x \| (dst_y << 16);
	114	writel(tmp, engine + 0x0C);
	115
	116	if ((width - 1) & 0xFFFFF000 \|\| (height - 1) & 0xFFFFF000) {
	117	printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
	118	"%d %d\n", width, height);
	119	return -EINVAL;
	120	}
	121	tmp = (width - 1) \| ((height - 1) << 16);
	122	writel(tmp, engine + 0x10);
	123
	124	if (op != VIA_BITBLT_COLOR)
	125	writel(fg_color, engine + 0x18);
	126
	127	if (op == VIA_BITBLT_MONO)
	128	writel(bg_color, engine + 0x1C);
	129
	130	if (op != VIA_BITBLT_FILL) {
	131	tmp = src_mem ? 0 : src_addr;
	132	if (dst_addr & 0xE0000007) {
	133	printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
	134	"address %X\n", tmp);
	135	return -EINVAL;
	136	}
	137	tmp >>= 3;
	138	writel(tmp, engine + 0x30);
	139	}
	140
	141	if (dst_addr & 0xE0000007) {
	142	printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
	143	"address %X\n", dst_addr);
	144	return -EINVAL;
	145	}
	146	tmp = dst_addr >> 3;
	147	writel(tmp, engine + 0x34);
	148
	149	if (op == VIA_BITBLT_FILL)
	150	tmp = 0;
	151	else
	152	tmp = src_pitch;
	153	if (tmp & 0xFFFFC007 \|\| dst_pitch & 0xFFFFC007) {
	154	printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
	155	tmp, dst_pitch);
	156	return -EINVAL;
	157	}
97922b54	158	tmp = VIA_PITCH_ENABLE \| (tmp >> 3) \| (dst_pitch << (16 - 3));
c3e25673 FTS	159	writel(tmp, engine + 0x38);
	160
	161	if (op == VIA_BITBLT_FILL)
	162	ge_cmd \|= fill_rop << 24 \| 0x00002000 \| 0x00000001;
	163	else {
	164	ge_cmd \|= 0xCC000000; /* ROP=SRCCOPY */
	165	if (src_mem)
	166	ge_cmd \|= 0x00000040;
	167	if (op == VIA_BITBLT_MONO)
	168	ge_cmd \|= 0x00000002 \| 0x00000100 \| 0x00020000;
	169	else
	170	ge_cmd \|= 0x00000001;
	171	}
	172	writel(ge_cmd, engine);
	173
	174	if (op == VIA_BITBLT_FILL \|\| !src_mem)
	175	return 0;
	176
	177	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
	178	3) >> 2;
	179
	180	for (i = 0; i < tmp; i++)
	181	writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
	182
	183	return 0;
	184	}
	185
	186	static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
	187	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	188	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	189	u32 fg_color, u32 bg_color, u8 fill_rop)
	190	{
	191	u32 ge_cmd = 0, tmp, i;
9ca43cf4	192	int ret;
c3e25673 FTS	193
	194	if (!op \|\| op > 3) {
	195	printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
	196	return -EINVAL;
	197	}
	198
	199	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
	200	if (src_x < dst_x) {
	201	ge_cmd \|= 0x00008000;
	202	src_x += width - 1;
	203	dst_x += width - 1;
	204	}
	205	if (src_y < dst_y) {
	206	ge_cmd \|= 0x00004000;
	207	src_y += height - 1;
	208	dst_y += height - 1;
	209	}
	210	}
	211
	212	if (op == VIA_BITBLT_FILL) {
	213	switch (fill_rop) {
	214	case 0x00: /* blackness */
	215	case 0x5A: /* pattern inversion */
	216	case 0xF0: /* pattern copy */
	217	case 0xFF: /* whiteness */
	218	break;
	219	default:
	220	printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
	221	"%u\n", fill_rop);
	222	return -EINVAL;
	223	}
	224	}
	225
9ca43cf4 JC	226	ret = viafb_set_bpp(engine, dst_bpp);
	227	if (ret)
	228	return ret;
c3e25673 FTS	229
	230	if (op == VIA_BITBLT_FILL)
	231	tmp = 0;
	232	else
	233	tmp = src_pitch;
	234	if (tmp & 0xFFFFC007 \|\| dst_pitch & 0xFFFFC007) {
	235	printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
	236	tmp, dst_pitch);
	237	return -EINVAL;
	238	}
	239	tmp = (tmp >> 3) \| (dst_pitch << (16 - 3));
	240	writel(tmp, engine + 0x08);
	241
	242	if ((width - 1) & 0xFFFFF000 \|\| (height - 1) & 0xFFFFF000) {
	243	printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
	244	"%d %d\n", width, height);
	245	return -EINVAL;
	246	}
	247	tmp = (width - 1) \| ((height - 1) << 16);
	248	writel(tmp, engine + 0x0C);
	249
	250	if (dst_x & 0xFFFFF000 \|\| dst_y & 0xFFFFF000) {
	251	printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
	252	"%d %d\n", dst_x, dst_y);
	253	return -EINVAL;
	254	}
	255	tmp = dst_x \| (dst_y << 16);
	256	writel(tmp, engine + 0x10);
	257
	258	if (dst_addr & 0xE0000007) {
	259	printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
	260	"address %X\n", dst_addr);
	261	return -EINVAL;
	262	}
	263	tmp = dst_addr >> 3;
	264	writel(tmp, engine + 0x14);
	265
	266	if (op != VIA_BITBLT_FILL) {
	267	if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
	268	\|\| src_y & 0xFFFFF000) {
	269	printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
	270	"x/y %d %d\n", src_x, src_y);
	271	return -EINVAL;
	272	}
	273	tmp = src_x \| (src_y << 16);
	274	writel(tmp, engine + 0x18);
	275
	276	tmp = src_mem ? 0 : src_addr;
	277	if (dst_addr & 0xE0000007) {
	278	printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
	279	"address %X\n", tmp);
	280	return -EINVAL;
	281	}
	282	tmp >>= 3;
	283	writel(tmp, engine + 0x1C);
	284	}
	285
	286	if (op != VIA_BITBLT_COLOR)
	287	writel(fg_color, engine + 0x4C);
	288
	289	if (op == VIA_BITBLT_MONO)
	290	writel(bg_color, engine + 0x50);
	291
	292	if (op == VIA_BITBLT_FILL)
293	ge_cmd \|= fill_rop << 24 \| 0x00002000 \| 0x00000001;
294	else {
295	ge_cmd \|= 0xCC000000; /* ROP=SRCCOPY */
296	if (src_mem)
297	ge_cmd \|= 0x00000040;
298	if (op == VIA_BITBLT_MONO)
299	ge_cmd \|= 0x00000002 \| 0x00000100 \| 0x00020000;
300	else
301	ge_cmd \|= 0x00000001;
302	}
303	writel(ge_cmd, engine);
304
305	if (op == VIA_BITBLT_FILL \|\| !src_mem)
306	return 0;
307
308	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
309	3) >> 2;
310
311	for (i = 0; i < tmp; i++)
312	writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
313
314	return 0;
315	}
316
31de59d5	317	int viafb_init_engine(struct fb_info *info)
c3e25673	318	{
31de59d5 FTS	319	struct viafb_par *viapar = info->par;
31de59d5 FTS	320	void __iomem *engine;
13178243	321	int highest_reg, i;
31de59d5 FTS	322	u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
	323	vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
	324
24b4d82e	325	engine = viapar->shared->vdev->engine_mmio;
31de59d5 FTS	326	if (!engine) {
	327	printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
	328	"hardware acceleration disabled\n");
	329	return -ENOMEM;
	330	}
	331
13178243 JC	332	/* Initialize registers to reset the 2D engine */
	333	switch (viapar->shared->chip_info.twod_engine) {
	334	case VIA_2D_ENG_M1:
	335	highest_reg = 0x5c;
	336	break;
	337	default:
	338	highest_reg = 0x40;
	339	break;
	340	}
	341	for (i = 0; i <= highest_reg; i += 4)
	342	writel(0x0, engine + i);
	343
31de59d5	344	switch (chip_name) {
c3e25673 FTS	345	case UNICHROME_CLE266:
	346	case UNICHROME_K400:
	347	case UNICHROME_K800:
	348	case UNICHROME_PM800:
	349	case UNICHROME_CN700:
	350	case UNICHROME_CX700:
	351	case UNICHROME_CN750:
	352	case UNICHROME_K8M890:
	353	case UNICHROME_P4M890:
	354	case UNICHROME_P4M900:
31de59d5	355	viapar->shared->hw_bitblt = hw_bitblt_1;
c3e25673 FTS	356	break;
c3e25673 FTS	357	case UNICHROME_VX800:
3a324569	358	case UNICHROME_VX855:
31de59d5	359	viapar->shared->hw_bitblt = hw_bitblt_2;
c3e25673 FTS	360	break;
c3e25673 FTS	361	default:
31de59d5	362	viapar->shared->hw_bitblt = NULL;
c3e25673 FTS	363	}
c3e25673 FTS	364
31de59d5 FTS	365	viapar->fbmem_free -= CURSOR_SIZE;
	366	viapar->shared->cursor_vram_addr = viapar->fbmem_free;
	367	viapar->fbmem_used += CURSOR_SIZE;
801b8a8c	368
31de59d5 FTS	369	viapar->fbmem_free -= VQ_SIZE;
	370	viapar->shared->vq_vram_addr = viapar->fbmem_free;
	371	viapar->fbmem_used += VQ_SIZE;
801b8a8c	372
c2b12cd4 JC	373	#if defined(CONFIG_FB_VIA_CAMERA) \|\| defined(CONFIG_FB_VIA_CAMERA_MODULE)
	374	/*
	375	* Set aside a chunk of framebuffer memory for the camera
	376	* driver. Someday this driver probably needs a proper allocator
	377	* for fbmem; for now, we just have to do this before the
	378	* framebuffer initializes itself.
	379	*
	380	* As for the size: the engine can handle three frames,
	381	* 16 bits deep, up to VGA resolution.
	382	*/
	383	viapar->shared->vdev->camera_fbmem_size = 3VGA_HEIGHTVGA_WIDTH*2;
	384	viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size;
	385	viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size;
	386	viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;
	387	#endif
	388
801b8a8c	389	/* Init AGP and VQ regs */
31de59d5	390	switch (chip_name) {
801b8a8c JC	391	case UNICHROME_K8M890:
801b8a8c JC	392	case UNICHROME_P4M900:
13178243 JC	393	case UNICHROME_VX800:
13178243 JC	394	case UNICHROME_VX855:
31de59d5 FTS	395	writel(0x00100000, engine + VIA_REG_CR_TRANSET);
	396	writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
	397	writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
801b8a8c JC	398	break;
	399
	400	default:
31de59d5 FTS	401	writel(0x00100000, engine + VIA_REG_TRANSET);
	402	writel(0x00000000, engine + VIA_REG_TRANSPACE);
	403	writel(0x00333004, engine + VIA_REG_TRANSPACE);
	404	writel(0x60000000, engine + VIA_REG_TRANSPACE);
	405	writel(0x61000000, engine + VIA_REG_TRANSPACE);
	406	writel(0x62000000, engine + VIA_REG_TRANSPACE);
	407	writel(0x63000000, engine + VIA_REG_TRANSPACE);
	408	writel(0x64000000, engine + VIA_REG_TRANSPACE);
	409	writel(0x7D000000, engine + VIA_REG_TRANSPACE);
	410
	411	writel(0xFE020000, engine + VIA_REG_TRANSET);
	412	writel(0x00000000, engine + VIA_REG_TRANSPACE);
801b8a8c JC	413	break;
801b8a8c JC	414	}
801b8a8c	415
31de59d5 FTS	416	/* Enable VQ */
	417	vq_start_addr = viapar->shared->vq_vram_addr;
	418	vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
	419
	420	vq_start_low = 0x50000000 \| (vq_start_addr & 0xFFFFFF);
	421	vq_end_low = 0x51000000 \| (vq_end_addr & 0xFFFFFF);
	422	vq_high = 0x52000000 \| ((vq_start_addr & 0xFF000000) >> 24) \|
	423	((vq_end_addr & 0xFF000000) >> 16);
	424	vq_len = 0x53000000 \| (VQ_SIZE >> 3);
	425
	426	switch (chip_name) {
	427	case UNICHROME_K8M890:
	428	case UNICHROME_P4M900:
13178243 JC	429	case UNICHROME_VX800:
13178243 JC	430	case UNICHROME_VX855:
31de59d5 FTS	431	vq_start_low \|= 0x20000000;
	432	vq_end_low \|= 0x20000000;
	433	vq_high \|= 0x20000000;
	434	vq_len \|= 0x20000000;
	435
	436	writel(0x00100000, engine + VIA_REG_CR_TRANSET);
	437	writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
	438	writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
	439	writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
	440	writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
	441	writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
	442	writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
	443	break;
	444	default:
	445	writel(0x00FE0000, engine + VIA_REG_TRANSET);
	446	writel(0x080003FE, engine + VIA_REG_TRANSPACE);
	447	writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
	448	writel(0x0B000260, engine + VIA_REG_TRANSPACE);
	449	writel(0x0C000274, engine + VIA_REG_TRANSPACE);
	450	writel(0x0D000264, engine + VIA_REG_TRANSPACE);
	451	writel(0x0E000000, engine + VIA_REG_TRANSPACE);
	452	writel(0x0F000020, engine + VIA_REG_TRANSPACE);
	453	writel(0x1000027E, engine + VIA_REG_TRANSPACE);
	454	writel(0x110002FE, engine + VIA_REG_TRANSPACE);
	455	writel(0x200F0060, engine + VIA_REG_TRANSPACE);
	456
	457	writel(0x00000006, engine + VIA_REG_TRANSPACE);
	458	writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
	459	writel(0x44000000, engine + VIA_REG_TRANSPACE);
	460	writel(0x45080C04, engine + VIA_REG_TRANSPACE);
	461	writel(0x46800408, engine + VIA_REG_TRANSPACE);
	462
	463	writel(vq_high, engine + VIA_REG_TRANSPACE);
	464	writel(vq_start_low, engine + VIA_REG_TRANSPACE);
	465	writel(vq_end_low, engine + VIA_REG_TRANSPACE);
	466	writel(vq_len, engine + VIA_REG_TRANSPACE);
	467	break;
801b8a8c	468	}
801b8a8c	469
801b8a8c	470	/* Set Cursor Image Base Address */
31de59d5 FTS	471	writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
	472	writel(0x0, engine + VIA_REG_CURSOR_POS);
	473	writel(0x0, engine + VIA_REG_CURSOR_ORG);
	474	writel(0x0, engine + VIA_REG_CURSOR_BG);
	475	writel(0x0, engine + VIA_REG_CURSOR_FG);
	476	return 0;
801b8a8c JC	477	}
	478
	479	void viafb_show_hw_cursor(struct fb_info *info, int Status)
	480	{
31de59d5 FTS	481	struct viafb_par *viapar = info->par;
31de59d5 FTS	482	u32 temp, iga_path = viapar->iga_path;
801b8a8c	483
24b4d82e	484	temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
801b8a8c JC	485	switch (Status) {
	486	case HW_Cursor_ON:
	487	temp \|= 0x1;
	488	break;
	489	case HW_Cursor_OFF:
	490	temp &= 0xFFFFFFFE;
	491	break;
	492	}
	493	switch (iga_path) {
	494	case IGA2:
	495	temp \|= 0x80000000;
	496	break;
	497	case IGA1:
	498	default:
	499	temp &= 0x7FFFFFFF;
	500	}
24b4d82e	501	writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
801b8a8c JC	502	}
801b8a8c JC	503
31de59d5	504	void viafb_wait_engine_idle(struct fb_info *info)
801b8a8c	505	{
31de59d5	506	struct viafb_par *viapar = info->par;
801b8a8c	507	int loop = 0;
13178243	508	u32 mask;
24b4d82e	509	void __iomem *engine = viapar->shared->vdev->engine_mmio;
801b8a8c	510
13178243 JC	511	switch (viapar->shared->chip_info.twod_engine) {
	512	case VIA_2D_ENG_H5:
	513	case VIA_2D_ENG_M1:
	514	mask = VIA_CMD_RGTR_BUSY_M1 \| VIA_2D_ENG_BUSY_M1 \|
	515	VIA_3D_ENG_BUSY_M1;
	516	break;
	517	default:
24b4d82e	518	while (!(readl(engine + VIA_REG_STATUS) &
13178243 JC	519	VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
	520	loop++;
	521	cpu_relax();
	522	}
	523	mask = VIA_CMD_RGTR_BUSY \| VIA_2D_ENG_BUSY \| VIA_3D_ENG_BUSY;
	524	break;
2bd8c475	525	}
801b8a8c	526
24b4d82e	527	while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
2bd8c475	528	loop++;
801b8a8c	529	cpu_relax();
2bd8c475	530	}
801b8a8c	531
31de59d5 FTS	532	if (loop >= MAXLOOP)
31de59d5 FTS	533	printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
801b8a8c	534	}