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CommitLineData
cfb4f5d1
MD
1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
225c9a8d 24#include <video/sh_mobile_lcdc.h>
8564557a 25#include <asm/atomic.h>
cfb4f5d1 26
6de9edd5
GL
27#include "sh_mobile_lcdcfb.h"
28
a6f15ade
PE
29#define SIDE_B_OFFSET 0x1000
30#define MIRROR_OFFSET 0x2000
cfb4f5d1 31
cfb4f5d1
MD
32/* shared registers */
33#define _LDDCKR 0x410
34#define _LDDCKSTPR 0x414
35#define _LDINTR 0x468
36#define _LDSR 0x46c
37#define _LDCNT1R 0x470
38#define _LDCNT2R 0x474
9dd38819 39#define _LDRCNTR 0x478
cfb4f5d1
MD
40#define _LDDDSR 0x47c
41#define _LDDWD0R 0x800
42#define _LDDRDR 0x840
43#define _LDDWAR 0x900
44#define _LDDRAR 0x904
45
0246c471
MD
46/* shared registers and their order for context save/restore */
47static int lcdc_shared_regs[] = {
48 _LDDCKR,
49 _LDDCKSTPR,
50 _LDINTR,
51 _LDDDSR,
52 _LDCNT1R,
53 _LDCNT2R,
54};
55#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
56
0246c471 57static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD
58 [LDDCKPAT1R] = 0x400,
59 [LDDCKPAT2R] = 0x404,
60 [LDMT1R] = 0x418,
61 [LDMT2R] = 0x41c,
62 [LDMT3R] = 0x420,
63 [LDDFR] = 0x424,
64 [LDSM1R] = 0x428,
8564557a 65 [LDSM2R] = 0x42c,
cfb4f5d1
MD
66 [LDSA1R] = 0x430,
67 [LDMLSR] = 0x438,
68 [LDHCNR] = 0x448,
69 [LDHSYNR] = 0x44c,
70 [LDVLNR] = 0x450,
71 [LDVSYNR] = 0x454,
72 [LDPMR] = 0x460,
6011bdea 73 [LDHAJR] = 0x4a0,
cfb4f5d1
MD
74};
75
0246c471 76static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD
77 [LDDCKPAT1R] = 0x408,
78 [LDDCKPAT2R] = 0x40c,
79 [LDMT1R] = 0x600,
80 [LDMT2R] = 0x604,
81 [LDMT3R] = 0x608,
82 [LDDFR] = 0x60c,
83 [LDSM1R] = 0x610,
8564557a 84 [LDSM2R] = 0x614,
cfb4f5d1
MD
85 [LDSA1R] = 0x618,
86 [LDMLSR] = 0x620,
87 [LDHCNR] = 0x624,
88 [LDHSYNR] = 0x628,
89 [LDVLNR] = 0x62c,
90 [LDVSYNR] = 0x630,
91 [LDPMR] = 0x63c,
92};
93
94#define START_LCDC 0x00000001
95#define LCDC_RESET 0x00000100
96#define DISPLAY_BEU 0x00000008
97#define LCDC_ENABLE 0x00000001
8564557a 98#define LDINTR_FE 0x00000400
9dd38819
PE
99#define LDINTR_VSE 0x00000200
100#define LDINTR_VEE 0x00000100
8564557a 101#define LDINTR_FS 0x00000004
9dd38819
PE
102#define LDINTR_VSS 0x00000002
103#define LDINTR_VES 0x00000001
a6f15ade
PE
104#define LDRCNTR_SRS 0x00020000
105#define LDRCNTR_SRC 0x00010000
106#define LDRCNTR_MRS 0x00000002
107#define LDRCNTR_MRC 0x00000001
40331b21 108#define LDSR_MRS 0x00000100
cfb4f5d1 109
0246c471
MD
110struct sh_mobile_lcdc_priv {
111 void __iomem *base;
112 int irq;
113 atomic_t hw_usecnt;
114 struct device *dev;
115 struct clk *dot_clk;
116 unsigned long lddckr;
117 struct sh_mobile_lcdc_chan ch[2];
6011bdea 118 struct notifier_block notifier;
0246c471
MD
119 unsigned long saved_shared_regs[NR_SHARED_REGS];
120 int started;
121};
122
a6f15ade
PE
123static bool banked(int reg_nr)
124{
125 switch (reg_nr) {
126 case LDMT1R:
127 case LDMT2R:
128 case LDMT3R:
129 case LDDFR:
130 case LDSM1R:
131 case LDSA1R:
132 case LDMLSR:
133 case LDHCNR:
134 case LDHSYNR:
135 case LDVLNR:
136 case LDVSYNR:
137 return true;
138 }
139 return false;
140}
141
cfb4f5d1
MD
142static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
143 int reg_nr, unsigned long data)
144{
145 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE
146 if (banked(reg_nr))
147 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
148 SIDE_B_OFFSET);
149}
150
151static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
152 int reg_nr, unsigned long data)
153{
154 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
155 MIRROR_OFFSET);
cfb4f5d1
MD
156}
157
158static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
159 int reg_nr)
160{
161 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
162}
163
164static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
165 unsigned long reg_offs, unsigned long data)
166{
167 iowrite32(data, priv->base + reg_offs);
168}
169
170static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
171 unsigned long reg_offs)
172{
173 return ioread32(priv->base + reg_offs);
174}
175
176static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
177 unsigned long reg_offs,
178 unsigned long mask, unsigned long until)
179{
180 while ((lcdc_read(priv, reg_offs) & mask) != until)
181 cpu_relax();
182}
183
184static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
185{
186 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
187}
188
189static void lcdc_sys_write_index(void *handle, unsigned long data)
190{
191 struct sh_mobile_lcdc_chan *ch = handle;
192
193 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
194 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
195 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 196 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD
197}
198
199static void lcdc_sys_write_data(void *handle, unsigned long data)
200{
201 struct sh_mobile_lcdc_chan *ch = handle;
202
203 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
204 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
205 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 206 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD
207}
208
209static unsigned long lcdc_sys_read_data(void *handle)
210{
211 struct sh_mobile_lcdc_chan *ch = handle;
212
213 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
214 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
215 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
216 udelay(1);
909f10de 217 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 218
ec56b66f 219 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD
220}
221
222struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
223 lcdc_sys_write_index,
224 lcdc_sys_write_data,
225 lcdc_sys_read_data,
226};
227
8564557a
MD
228static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
229{
0246c471
MD
230 if (atomic_inc_and_test(&priv->hw_usecnt)) {
231 pm_runtime_get_sync(priv->dev);
8564557a
MD
232 if (priv->dot_clk)
233 clk_enable(priv->dot_clk);
234 }
235}
236
237static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
238{
0246c471 239 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD
240 if (priv->dot_clk)
241 clk_disable(priv->dot_clk);
0246c471 242 pm_runtime_put(priv->dev);
8564557a
MD
243 }
244}
8564557a 245
1c6a307a
PM
246static int sh_mobile_lcdc_sginit(struct fb_info *info,
247 struct list_head *pagelist)
248{
249 struct sh_mobile_lcdc_chan *ch = info->par;
250 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
251 struct page *page;
252 int nr_pages = 0;
253
254 sg_init_table(ch->sglist, nr_pages_max);
255
256 list_for_each_entry(page, pagelist, lru)
257 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
258
259 return nr_pages;
260}
261
8564557a
MD
262static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
263 struct list_head *pagelist)
264{
265 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 266 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD
267
268 /* enable clocks before accessing hardware */
269 sh_mobile_lcdc_clk_on(ch->lcdc);
270
5c1a56b5
PM
271 /*
272 * It's possible to get here without anything on the pagelist via
273 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
274 * invocation. In the former case, the acceleration routines are
275 * stepped in to when using the framebuffer console causing the
276 * workqueue to be scheduled without any dirty pages on the list.
277 *
278 * Despite this, a panel update is still needed given that the
279 * acceleration routines have their own methods for writing in
280 * that still need to be updated.
281 *
282 * The fsync() and empty pagelist case could be optimized for,
283 * but we don't bother, as any application exhibiting such
284 * behaviour is fundamentally broken anyways.
285 */
286 if (!list_empty(pagelist)) {
287 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
288
289 /* trigger panel update */
290 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD
291 if (bcfg->start_transfer)
292 bcfg->start_transfer(bcfg->board_data, ch,
293 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM
294 lcdc_write_chan(ch, LDSM2R, 1);
295 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD
296 } else {
297 if (bcfg->start_transfer)
298 bcfg->start_transfer(bcfg->board_data, ch,
299 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 300 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 301 }
8564557a
MD
302}
303
304static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
305{
306 struct fb_deferred_io *fbdefio = info->fbdefio;
307
308 if (fbdefio)
309 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
310}
311
312static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
313{
314 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 315 struct sh_mobile_lcdc_chan *ch;
8564557a 316 unsigned long tmp;
9dd38819 317 unsigned long ldintr;
2feb075a
MD
318 int is_sub;
319 int k;
8564557a
MD
320
321 /* acknowledge interrupt */
9dd38819
PE
322 ldintr = tmp = lcdc_read(priv, _LDINTR);
323 /*
324 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
325 * write 0 to bits 0-6 to ack all triggered IRQs.
326 */
327 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD
328 lcdc_write(priv, _LDINTR, tmp);
329
2feb075a
MD
330 /* figure out if this interrupt is for main or sub lcd */
331 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
332
9dd38819 333 /* wake up channel and disable clocks */
2feb075a
MD
334 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
335 ch = &priv->ch[k];
336
337 if (!ch->enabled)
338 continue;
339
9dd38819
PE
340 /* Frame Start */
341 if (ldintr & LDINTR_FS) {
342 if (is_sub == lcdc_chan_is_sublcd(ch)) {
343 ch->frame_end = 1;
344 wake_up(&ch->frame_end_wait);
2feb075a 345
9dd38819
PE
346 sh_mobile_lcdc_clk_off(priv);
347 }
348 }
349
350 /* VSYNC End */
40331b21
PE
351 if (ldintr & LDINTR_VES)
352 complete(&ch->vsync_completion);
2feb075a
MD
353 }
354
8564557a
MD
355 return IRQ_HANDLED;
356}
357
cfb4f5d1
MD
358static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
359 int start)
360{
361 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
362 int k;
363
364 /* start or stop the lcdc */
365 if (start)
366 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
367 else
368 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
369
370 /* wait until power is applied/stopped on all channels */
371 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
372 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
373 while (1) {
374 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
375 if (start && tmp == 3)
376 break;
377 if (!start && tmp == 0)
378 break;
379 cpu_relax();
380 }
381
382 if (!start)
383 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
384}
385
6011bdea
GL
386static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
387{
1c120deb
GL
388 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
389 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL
390 u32 tmp;
391
392 tmp = ch->ldmt1r_value;
393 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
394 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
395 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
396 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
397 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
398 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
399 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
400 lcdc_write_chan(ch, LDMT1R, tmp);
401
402 /* setup SYS bus */
403 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
404 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
405
406 /* horizontal configuration */
1c120deb
GL
407 h_total = display_var->xres + display_var->hsync_len +
408 display_var->left_margin + display_var->right_margin;
6011bdea 409 tmp = h_total / 8; /* HTCN */
1c120deb 410 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL
411 lcdc_write_chan(ch, LDHCNR, tmp);
412
1c120deb 413 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 414 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 415 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL
416 lcdc_write_chan(ch, LDHSYNR, tmp);
417
418 /* vertical configuration */
1c120deb
GL
419 tmp = display_var->yres + display_var->vsync_len +
420 display_var->upper_margin + display_var->lower_margin; /* VTLN */
421 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL
422 lcdc_write_chan(ch, LDVLNR, tmp);
423
1c120deb
GL
424 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
425 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL
426 lcdc_write_chan(ch, LDVSYNR, tmp);
427
428 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL
429 display_h_total = display_var->xres + display_var->hsync_len +
430 display_var->left_margin + display_var->right_margin;
431 tmp = ((display_var->xres & 7) << 24) |
432 ((display_h_total & 7) << 16) |
433 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL
434 hsync_pos;
435 lcdc_write_chan(ch, LDHAJR, tmp);
436}
437
cfb4f5d1
MD
438static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
439{
440 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD
441 struct sh_mobile_lcdc_board_cfg *board_cfg;
442 unsigned long tmp;
443 int k, m;
444 int ret = 0;
445
8564557a
MD
446 /* enable clocks before accessing the hardware */
447 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
448 if (priv->ch[k].enabled)
449 sh_mobile_lcdc_clk_on(priv);
450
cfb4f5d1
MD
451 /* reset */
452 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
453 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
454
455 /* enable LCDC channels */
456 tmp = lcdc_read(priv, _LDCNT2R);
457 tmp |= priv->ch[0].enabled;
458 tmp |= priv->ch[1].enabled;
459 lcdc_write(priv, _LDCNT2R, tmp);
460
461 /* read data from external memory, avoid using the BEU for now */
462 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
463
464 /* stop the lcdc first */
465 sh_mobile_lcdc_start_stop(priv, 0);
466
467 /* configure clocks */
468 tmp = priv->lddckr;
469 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
470 ch = &priv->ch[k];
471
472 if (!priv->ch[k].enabled)
473 continue;
474
475 m = ch->cfg.clock_divider;
476 if (!m)
477 continue;
478
479 if (m == 1)
480 m = 1 << 6;
481 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
482
dd210503 483 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider denominator */
1c120deb 484 lcdc_write_chan(ch, LDDCKPAT1R, 0);
cfb4f5d1
MD
485 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
486 }
487
488 lcdc_write(priv, _LDDCKR, tmp);
489
490 /* start dotclock again */
491 lcdc_write(priv, _LDDCKSTPR, 0);
492 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
493
8564557a 494 /* interrupts are disabled to begin with */
cfb4f5d1
MD
495 lcdc_write(priv, _LDINTR, 0);
496
497 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
498 ch = &priv->ch[k];
cfb4f5d1
MD
499
500 if (!ch->enabled)
501 continue;
502
6011bdea 503 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD
504
505 /* power supply */
506 lcdc_write_chan(ch, LDPMR, 0);
507
cfb4f5d1
MD
508 board_cfg = &ch->cfg.board_cfg;
509 if (board_cfg->setup_sys)
510 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
511 &sh_mobile_lcdc_sys_bus_ops);
512 if (ret)
513 return ret;
514 }
515
cfb4f5d1
MD
516 /* word and long word swap */
517 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
518
519 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
520 ch = &priv->ch[k];
521
522 if (!priv->ch[k].enabled)
523 continue;
524
525 /* set bpp format in PKF[4:0] */
526 tmp = lcdc_read_chan(ch, LDDFR);
1c120deb 527 tmp &= ~0x0001001f;
e33afddc 528 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
cfb4f5d1
MD
529 lcdc_write_chan(ch, LDDFR, tmp);
530
531 /* point out our frame buffer */
e33afddc 532 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
cfb4f5d1
MD
533
534 /* set line size */
e33afddc 535 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
cfb4f5d1 536
8564557a
MD
537 /* setup deferred io if SYS bus */
538 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
539 if (ch->ldmt1r_value & (1 << 12) && tmp) {
540 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
541 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM
542 ch->info->fbdefio = &ch->defio;
543 fb_deferred_io_init(ch->info);
8564557a
MD
544
545 /* one-shot mode */
546 lcdc_write_chan(ch, LDSM1R, 1);
547
548 /* enable "Frame End Interrupt Enable" bit */
549 lcdc_write(priv, _LDINTR, LDINTR_FE);
550
551 } else {
552 /* continuous read mode */
553 lcdc_write_chan(ch, LDSM1R, 0);
554 }
cfb4f5d1
MD
555 }
556
557 /* display output */
558 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
559
560 /* start the lcdc */
561 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 562 priv->started = 1;
cfb4f5d1
MD
563
564 /* tell the board code to enable the panel */
565 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
566 ch = &priv->ch[k];
21bc1f02
MD
567 if (!ch->enabled)
568 continue;
569
cfb4f5d1 570 board_cfg = &ch->cfg.board_cfg;
6de9edd5 571 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
c2439398 572 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL
573 module_put(board_cfg->owner);
574 }
cfb4f5d1
MD
575 }
576
577 return 0;
578}
579
580static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
581{
582 struct sh_mobile_lcdc_chan *ch;
583 struct sh_mobile_lcdc_board_cfg *board_cfg;
584 int k;
585
2feb075a 586 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD
587 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
588 ch = &priv->ch[k];
21bc1f02
MD
589 if (!ch->enabled)
590 continue;
8564557a 591
2feb075a
MD
592 /* deferred io mode:
593 * flush frame, and wait for frame end interrupt
594 * clean up deferred io and enable clock
595 */
5ef6b505 596 if (ch->info && ch->info->fbdefio) {
2feb075a 597 ch->frame_end = 0;
e33afddc 598 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 599 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM
600 fb_deferred_io_cleanup(ch->info);
601 ch->info->fbdefio = NULL;
2feb075a 602 sh_mobile_lcdc_clk_on(priv);
8564557a 603 }
2feb075a
MD
604
605 board_cfg = &ch->cfg.board_cfg;
6de9edd5 606 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
2feb075a 607 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL
608 module_put(board_cfg->owner);
609 }
cfb4f5d1
MD
610 }
611
612 /* stop the lcdc */
8e9bb19e
MD
613 if (priv->started) {
614 sh_mobile_lcdc_start_stop(priv, 0);
615 priv->started = 0;
616 }
b51339ff 617
8564557a
MD
618 /* stop clocks */
619 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
620 if (priv->ch[k].enabled)
621 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD
622}
623
624static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
625{
626 int ifm, miftyp;
627
628 switch (ch->cfg.interface_type) {
629 case RGB8: ifm = 0; miftyp = 0; break;
630 case RGB9: ifm = 0; miftyp = 4; break;
631 case RGB12A: ifm = 0; miftyp = 5; break;
632 case RGB12B: ifm = 0; miftyp = 6; break;
633 case RGB16: ifm = 0; miftyp = 7; break;
634 case RGB18: ifm = 0; miftyp = 10; break;
635 case RGB24: ifm = 0; miftyp = 11; break;
636 case SYS8A: ifm = 1; miftyp = 0; break;
637 case SYS8B: ifm = 1; miftyp = 1; break;
638 case SYS8C: ifm = 1; miftyp = 2; break;
639 case SYS8D: ifm = 1; miftyp = 3; break;
640 case SYS9: ifm = 1; miftyp = 4; break;
641 case SYS12: ifm = 1; miftyp = 5; break;
642 case SYS16A: ifm = 1; miftyp = 7; break;
643 case SYS16B: ifm = 1; miftyp = 8; break;
644 case SYS16C: ifm = 1; miftyp = 9; break;
645 case SYS18: ifm = 1; miftyp = 10; break;
646 case SYS24: ifm = 1; miftyp = 11; break;
647 default: goto bad;
648 }
649
650 /* SUBLCD only supports SYS interface */
651 if (lcdc_chan_is_sublcd(ch)) {
652 if (ifm == 0)
653 goto bad;
654 else
655 ifm = 0;
656 }
657
658 ch->ldmt1r_value = (ifm << 12) | miftyp;
659 return 0;
660 bad:
661 return -EINVAL;
662}
663
b51339ff
MD
664static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
665 int clock_source,
cfb4f5d1
MD
666 struct sh_mobile_lcdc_priv *priv)
667{
668 char *str;
669 int icksel;
670
671 switch (clock_source) {
672 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
673 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
674 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
675 default:
676 return -EINVAL;
677 }
678
679 priv->lddckr = icksel << 16;
680
681 if (str) {
b51339ff
MD
682 priv->dot_clk = clk_get(&pdev->dev, str);
683 if (IS_ERR(priv->dot_clk)) {
684 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 685 return PTR_ERR(priv->dot_clk);
cfb4f5d1 686 }
cfb4f5d1 687 }
0246c471
MD
688
689 /* Runtime PM support involves two step for this driver:
690 * 1) Enable Runtime PM
691 * 2) Force Runtime PM Resume since hardware is accessed from probe()
692 */
8bed9055 693 priv->dev = &pdev->dev;
0246c471
MD
694 pm_runtime_enable(priv->dev);
695 pm_runtime_resume(priv->dev);
cfb4f5d1
MD
696 return 0;
697}
698
699static int sh_mobile_lcdc_setcolreg(u_int regno,
700 u_int red, u_int green, u_int blue,
701 u_int transp, struct fb_info *info)
702{
703 u32 *palette = info->pseudo_palette;
704
705 if (regno >= PALETTE_NR)
706 return -EINVAL;
707
708 /* only FB_VISUAL_TRUECOLOR supported */
709
710 red >>= 16 - info->var.red.length;
711 green >>= 16 - info->var.green.length;
712 blue >>= 16 - info->var.blue.length;
713 transp >>= 16 - info->var.transp.length;
714
715 palette[regno] = (red << info->var.red.offset) |
716 (green << info->var.green.offset) |
717 (blue << info->var.blue.offset) |
718 (transp << info->var.transp.offset);
719
720 return 0;
721}
722
723static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
724 .id = "SH Mobile LCDC",
725 .type = FB_TYPE_PACKED_PIXELS,
726 .visual = FB_VISUAL_TRUECOLOR,
727 .accel = FB_ACCEL_NONE,
9dd38819
PE
728 .xpanstep = 0,
729 .ypanstep = 1,
730 .ywrapstep = 0,
cfb4f5d1
MD
731};
732
8564557a
MD
733static void sh_mobile_lcdc_fillrect(struct fb_info *info,
734 const struct fb_fillrect *rect)
735{
736 sys_fillrect(info, rect);
737 sh_mobile_lcdc_deferred_io_touch(info);
738}
739
740static void sh_mobile_lcdc_copyarea(struct fb_info *info,
741 const struct fb_copyarea *area)
742{
743 sys_copyarea(info, area);
744 sh_mobile_lcdc_deferred_io_touch(info);
745}
746
747static void sh_mobile_lcdc_imageblit(struct fb_info *info,
748 const struct fb_image *image)
749{
750 sys_imageblit(info, image);
751 sh_mobile_lcdc_deferred_io_touch(info);
752}
753
9dd38819
PE
754static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
755 struct fb_info *info)
756{
757 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE
758 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
759 unsigned long ldrcntr;
760 unsigned long new_pan_offset;
761
762 new_pan_offset = (var->yoffset * info->fix.line_length) +
763 (var->xoffset * (info->var.bits_per_pixel / 8));
9dd38819 764
92e1f9a7 765 if (new_pan_offset == ch->pan_offset)
9dd38819
PE
766 return 0; /* No change, do nothing */
767
92e1f9a7 768 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 769
92e1f9a7
PE
770 /* Set the source address for the next refresh */
771 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
772 if (lcdc_chan_is_sublcd(ch))
773 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
774 else
775 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
776
777 ch->pan_offset = new_pan_offset;
778
779 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE
780
781 return 0;
782}
783
40331b21
PE
784static int sh_mobile_wait_for_vsync(struct fb_info *info)
785{
786 struct sh_mobile_lcdc_chan *ch = info->par;
787 unsigned long ldintr;
788 int ret;
789
790 /* Enable VSync End interrupt */
791 ldintr = lcdc_read(ch->lcdc, _LDINTR);
792 ldintr |= LDINTR_VEE;
793 lcdc_write(ch->lcdc, _LDINTR, ldintr);
794
795 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
796 msecs_to_jiffies(100));
797 if (!ret)
798 return -ETIMEDOUT;
799
800 return 0;
801}
802
803static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
804 unsigned long arg)
805{
806 int retval;
807
808 switch (cmd) {
809 case FBIO_WAITFORVSYNC:
810 retval = sh_mobile_wait_for_vsync(info);
811 break;
812
813 default:
814 retval = -ENOIOCTLCMD;
815 break;
816 }
817 return retval;
818}
819
dd210503
GL
820static void sh_mobile_fb_reconfig(struct fb_info *info)
821{
822 struct sh_mobile_lcdc_chan *ch = info->par;
823 struct fb_videomode mode1, mode2;
824 struct fb_event event;
825 int evnt = FB_EVENT_MODE_CHANGE_ALL;
826
827 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
828 /* More framebuffer users are active */
829 return;
830
831 fb_var_to_videomode(&mode1, &ch->display_var);
832 fb_var_to_videomode(&mode2, &info->var);
833
834 if (fb_mode_is_equal(&mode1, &mode2))
835 return;
836
837 /* Display has been re-plugged, framebuffer is free now, reconfigure */
838 if (fb_set_var(info, &ch->display_var) < 0)
839 /* Couldn't reconfigure, hopefully, can continue as before */
840 return;
841
842 info->fix.line_length = mode2.xres * (ch->cfg.bpp / 8);
843
844 /*
845 * fb_set_var() calls the notifier change internally, only if
846 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
847 * user event, we have to call the chain ourselves.
848 */
849 event.info = info;
850 event.data = &mode2;
851 fb_notifier_call_chain(evnt, &event);
852}
853
854/*
855 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
856 * user == 1, or with console sem held, if user == 0.
857 */
858static int sh_mobile_release(struct fb_info *info, int user)
859{
860 struct sh_mobile_lcdc_chan *ch = info->par;
861
862 mutex_lock(&ch->open_lock);
863 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
864
865 ch->use_count--;
866
867 /* Nothing to reconfigure, when called from fbcon */
868 if (user) {
869 acquire_console_sem();
870 sh_mobile_fb_reconfig(info);
871 release_console_sem();
872 }
873
874 mutex_unlock(&ch->open_lock);
875
876 return 0;
877}
878
879static int sh_mobile_open(struct fb_info *info, int user)
880{
881 struct sh_mobile_lcdc_chan *ch = info->par;
882
883 mutex_lock(&ch->open_lock);
884 ch->use_count++;
885
886 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
887 mutex_unlock(&ch->open_lock);
888
889 return 0;
890}
891
892static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
893{
894 struct sh_mobile_lcdc_chan *ch = info->par;
895
896 if (var->xres < 160 || var->xres > 1920 ||
897 var->yres < 120 || var->yres > 1080 ||
898 var->left_margin < 32 || var->left_margin > 320 ||
899 var->right_margin < 12 || var->right_margin > 240 ||
900 var->upper_margin < 12 || var->upper_margin > 120 ||
901 var->lower_margin < 1 || var->lower_margin > 64 ||
902 var->hsync_len < 32 || var->hsync_len > 120 ||
903 var->vsync_len < 2 || var->vsync_len > 64 ||
904 var->pixclock < 6000 || var->pixclock > 40000 ||
905 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
906 dev_warn(info->dev, "Invalid info: %u %u %u %u %u %u %u %u %u!\n",
907 var->xres, var->yres,
908 var->left_margin, var->right_margin,
909 var->upper_margin, var->lower_margin,
910 var->hsync_len, var->vsync_len,
911 var->pixclock);
912 return -EINVAL;
913 }
914 return 0;
915}
916
cfb4f5d1 917static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 918 .owner = THIS_MODULE,
cfb4f5d1 919 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD
920 .fb_read = fb_sys_read,
921 .fb_write = fb_sys_write,
8564557a
MD
922 .fb_fillrect = sh_mobile_lcdc_fillrect,
923 .fb_copyarea = sh_mobile_lcdc_copyarea,
924 .fb_imageblit = sh_mobile_lcdc_imageblit,
9dd38819 925 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 926 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL
927 .fb_open = sh_mobile_open,
928 .fb_release = sh_mobile_release,
929 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD
930};
931
932static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
933{
934 switch (bpp) {
935 case 16: /* PKF[4:0] = 00011 - RGB 565 */
936 var->red.offset = 11;
937 var->red.length = 5;
938 var->green.offset = 5;
939 var->green.length = 6;
940 var->blue.offset = 0;
941 var->blue.length = 5;
942 var->transp.offset = 0;
943 var->transp.length = 0;
944 break;
945
946 case 32: /* PKF[4:0] = 00000 - RGB 888
947 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
948 * this may be because LDDDSR has word swap enabled..
949 */
950 var->red.offset = 0;
951 var->red.length = 8;
952 var->green.offset = 24;
953 var->green.length = 8;
954 var->blue.offset = 16;
955 var->blue.length = 8;
956 var->transp.offset = 0;
957 var->transp.length = 0;
958 break;
959 default:
960 return -EINVAL;
961 }
962 var->bits_per_pixel = bpp;
963 var->red.msb_right = 0;
964 var->green.msb_right = 0;
965 var->blue.msb_right = 0;
966 var->transp.msb_right = 0;
967 return 0;
968}
969
2feb075a
MD
970static int sh_mobile_lcdc_suspend(struct device *dev)
971{
972 struct platform_device *pdev = to_platform_device(dev);
973
974 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
975 return 0;
976}
977
978static int sh_mobile_lcdc_resume(struct device *dev)
979{
980 struct platform_device *pdev = to_platform_device(dev);
981
982 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
983}
984
0246c471
MD
985static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
986{
987 struct platform_device *pdev = to_platform_device(dev);
988 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
989 struct sh_mobile_lcdc_chan *ch;
990 int k, n;
991
992 /* save per-channel registers */
993 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
994 ch = &p->ch[k];
995 if (!ch->enabled)
996 continue;
997 for (n = 0; n < NR_CH_REGS; n++)
998 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
999 }
1000
1001 /* save shared registers */
1002 for (n = 0; n < NR_SHARED_REGS; n++)
1003 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1004
1005 /* turn off LCDC hardware */
1006 lcdc_write(p, _LDCNT1R, 0);
1007 return 0;
1008}
1009
1010static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1011{
1012 struct platform_device *pdev = to_platform_device(dev);
1013 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1014 struct sh_mobile_lcdc_chan *ch;
1015 int k, n;
1016
1017 /* restore per-channel registers */
1018 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1019 ch = &p->ch[k];
1020 if (!ch->enabled)
1021 continue;
1022 for (n = 0; n < NR_CH_REGS; n++)
1023 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1024 }
1025
1026 /* restore shared registers */
1027 for (n = 0; n < NR_SHARED_REGS; n++)
1028 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1029
1030 return 0;
1031}
1032
47145210 1033static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD
1034 .suspend = sh_mobile_lcdc_suspend,
1035 .resume = sh_mobile_lcdc_resume,
0246c471
MD
1036 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1037 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD
1038};
1039
6de9edd5 1040/* locking: called with info->lock held */
6011bdea
GL
1041static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1042 unsigned long action, void *data)
1043{
1044 struct fb_event *event = data;
1045 struct fb_info *info = event->info;
1046 struct sh_mobile_lcdc_chan *ch = info->par;
1047 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1048 struct fb_var_screeninfo *var;
afe417c0 1049 int ret;
6011bdea
GL
1050
1051 if (&ch->lcdc->notifier != nb)
baf16374 1052 return NOTIFY_DONE;
6011bdea
GL
1053
1054 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1055 __func__, action, event->data);
1056
1057 switch(action) {
1058 case FB_EVENT_SUSPEND:
6de9edd5 1059 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
6011bdea 1060 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL
1061 module_put(board_cfg->owner);
1062 }
6011bdea 1063 pm_runtime_put(info->device);
afe417c0 1064 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL
1065 break;
1066 case FB_EVENT_RESUME:
1067 var = &info->var;
1068
dd210503
GL
1069 mutex_lock(&ch->open_lock);
1070 sh_mobile_fb_reconfig(info);
1071 mutex_unlock(&ch->open_lock);
1072
6011bdea 1073 /* HDMI must be enabled before LCDC configuration */
6de9edd5 1074 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
dd210503 1075 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5
GL
1076 module_put(board_cfg->owner);
1077 }
6011bdea 1078
afe417c0
GL
1079 ret = sh_mobile_lcdc_start(ch->lcdc);
1080 if (!ret)
1081 pm_runtime_get_sync(info->device);
6011bdea
GL
1082 }
1083
baf16374 1084 return NOTIFY_OK;
6011bdea
GL
1085}
1086
cfb4f5d1
MD
1087static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1088
c2e13037 1089static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD
1090{
1091 struct fb_info *info;
1092 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1093 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD
1094 struct sh_mobile_lcdc_chan_cfg *cfg;
1095 struct resource *res;
1096 int error;
1097 void *buf;
1098 int i, j;
1099
01ac25b5 1100 if (!pdata) {
cfb4f5d1 1101 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1102 return -EINVAL;
cfb4f5d1
MD
1103 }
1104
1105 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD
1106 i = platform_get_irq(pdev, 0);
1107 if (!res || i < 0) {
1108 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1109 return -ENOENT;
cfb4f5d1
MD
1110 }
1111
1112 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1113 if (!priv) {
1114 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1115 return -ENOMEM;
cfb4f5d1
MD
1116 }
1117
8bed9055
GL
1118 platform_set_drvdata(pdev, priv);
1119
8564557a 1120 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1121 dev_name(&pdev->dev), priv);
8564557a
MD
1122 if (error) {
1123 dev_err(&pdev->dev, "unable to request irq\n");
1124 goto err1;
1125 }
1126
1127 priv->irq = i;
5ef6b505 1128 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD
1129
1130 j = 0;
1131 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1132 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1133
01ac25b5
GL
1134 ch->lcdc = priv;
1135 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
1136
1137 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD
1138 if (error) {
1139 dev_err(&pdev->dev, "unsupported interface type\n");
1140 goto err1;
1141 }
01ac25b5
GL
1142 init_waitqueue_head(&ch->frame_end_wait);
1143 init_completion(&ch->vsync_completion);
1144 ch->pan_offset = 0;
cfb4f5d1
MD
1145
1146 switch (pdata->ch[i].chan) {
1147 case LCDC_CHAN_MAINLCD:
01ac25b5
GL
1148 ch->enabled = 1 << 1;
1149 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD
1150 j++;
1151 break;
1152 case LCDC_CHAN_SUBLCD:
01ac25b5
GL
1153 ch->enabled = 1 << 2;
1154 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD
1155 j++;
1156 break;
1157 }
1158 }
1159
1160 if (!j) {
1161 dev_err(&pdev->dev, "no channels defined\n");
1162 error = -EINVAL;
1163 goto err1;
1164 }
1165
dba6f385
GL
1166 priv->base = ioremap_nocache(res->start, resource_size(res));
1167 if (!priv->base)
1168 goto err1;
1169
b51339ff 1170 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD
1171 if (error) {
1172 dev_err(&pdev->dev, "unable to setup clocks\n");
1173 goto err1;
1174 }
1175
cfb4f5d1 1176 for (i = 0; i < j; i++) {
6011bdea 1177 struct fb_var_screeninfo *var;
71d3b0fc 1178 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1179 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
71d3b0fc
GL
1180 unsigned long max_size = 0;
1181 int k;
cfb4f5d1 1182
01ac25b5
GL
1183 cfg = &ch->cfg;
1184
1185 ch->info = framebuffer_alloc(0, &pdev->dev);
1186 if (!ch->info) {
e33afddc
PM
1187 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1188 error = -ENOMEM;
1189 break;
1190 }
1191
01ac25b5 1192 info = ch->info;
6011bdea 1193 var = &info->var;
cfb4f5d1 1194 info->fbops = &sh_mobile_lcdc_ops;
dd210503
GL
1195
1196 mutex_init(&ch->open_lock);
1197
71d3b0fc 1198 fb_videomode_to_var(var, &cfg->lcd_cfg[0]);
9dd38819 1199 /* Default Y virtual resolution is 2x panel size */
6011bdea 1200 var->yres_virtual = var->yres * 2;
dd210503 1201 var->activate = FB_ACTIVATE_NOW;
6011bdea
GL
1202
1203 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
cfb4f5d1
MD
1204 if (error)
1205 break;
1206
71d3b0fc
GL
1207 for (k = 0, lcd_cfg = cfg->lcd_cfg;
1208 k < cfg->num_cfg;
1209 k++, lcd_cfg++) {
1210 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
1211
1212 if (size > max_size) {
1213 max_cfg = lcd_cfg;
1214 max_size = size;
1215 }
1216 }
1217
1218 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1219 max_cfg->xres, max_cfg->yres);
1220
cfb4f5d1 1221 info->fix = sh_mobile_lcdc_fix;
71d3b0fc
GL
1222 info->fix.line_length = cfg->lcd_cfg[0].xres * (cfg->bpp / 8);
1223 info->fix.smem_len = max_size * (cfg->bpp / 8) * 2;
cfb4f5d1
MD
1224
1225 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1226 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD
1227 if (!buf) {
1228 dev_err(&pdev->dev, "unable to allocate buffer\n");
1229 error = -ENOMEM;
1230 break;
1231 }
1232
01ac25b5 1233 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD
1234 info->flags = FBINFO_FLAG_DEFAULT;
1235
1236 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1237 if (error < 0) {
1238 dev_err(&pdev->dev, "unable to allocate cmap\n");
1239 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1240 buf, ch->dma_handle);
cfb4f5d1
MD
1241 break;
1242 }
1243
01ac25b5 1244 info->fix.smem_start = ch->dma_handle;
cfb4f5d1
MD
1245 info->screen_base = buf;
1246 info->device = &pdev->dev;
01ac25b5 1247 info->par = ch;
1c120deb 1248 ch->display_var = *var;
cfb4f5d1
MD
1249 }
1250
1251 if (error)
1252 goto err1;
1253
1254 error = sh_mobile_lcdc_start(priv);
1255 if (error) {
1256 dev_err(&pdev->dev, "unable to start hardware\n");
1257 goto err1;
1258 }
1259
1260 for (i = 0; i < j; i++) {
1c6a307a
PM
1261 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1262
e33afddc 1263 info = ch->info;
1c6a307a
PM
1264
1265 if (info->fbdefio) {
8bed9055 1266 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1267 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1268 if (!ch->sglist) {
1c6a307a
PM
1269 dev_err(&pdev->dev, "cannot allocate sglist\n");
1270 goto err1;
1271 }
1272 }
1273
afe417c0 1274 fb_videomode_to_modelist(ch->cfg.lcd_cfg, ch->cfg.num_cfg, &info->modelist);
1c6a307a 1275 error = register_framebuffer(info);
cfb4f5d1
MD
1276 if (error < 0)
1277 goto err1;
cfb4f5d1 1278
cfb4f5d1
MD
1279 dev_info(info->dev,
1280 "registered %s/%s as %dx%d %dbpp.\n",
1281 pdev->name,
1c6a307a 1282 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1283 "mainlcd" : "sublcd",
44432407
GL
1284 (int) ch->cfg.lcd_cfg[0].xres,
1285 (int) ch->cfg.lcd_cfg[0].yres,
1c6a307a 1286 ch->cfg.bpp);
8564557a
MD
1287
1288 /* deferred io mode: disable clock to save power */
6011bdea 1289 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1290 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD
1291 }
1292
6011bdea
GL
1293 /* Failure ignored */
1294 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1295 fb_register_client(&priv->notifier);
1296
cfb4f5d1 1297 return 0;
8bed9055 1298err1:
cfb4f5d1 1299 sh_mobile_lcdc_remove(pdev);
8bed9055 1300
cfb4f5d1
MD
1301 return error;
1302}
1303
1304static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1305{
1306 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1307 struct fb_info *info;
1308 int i;
1309
6011bdea
GL
1310 fb_unregister_client(&priv->notifier);
1311
cfb4f5d1 1312 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1313 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1314 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD
1315
1316 sh_mobile_lcdc_stop(priv);
1317
1318 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1319 info = priv->ch[i].info;
cfb4f5d1 1320
e33afddc 1321 if (!info || !info->device)
cfb4f5d1
MD
1322 continue;
1323
1c6a307a
PM
1324 if (priv->ch[i].sglist)
1325 vfree(priv->ch[i].sglist);
1326
cfb4f5d1
MD
1327 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1328 info->screen_base, priv->ch[i].dma_handle);
1329 fb_dealloc_cmap(&info->cmap);
e33afddc 1330 framebuffer_release(info);
cfb4f5d1
MD
1331 }
1332
b51339ff
MD
1333 if (priv->dot_clk)
1334 clk_put(priv->dot_clk);
0246c471 1335
8bed9055
GL
1336 if (priv->dev)
1337 pm_runtime_disable(priv->dev);
cfb4f5d1
MD
1338
1339 if (priv->base)
1340 iounmap(priv->base);
1341
8564557a
MD
1342 if (priv->irq)
1343 free_irq(priv->irq, priv);
cfb4f5d1
MD
1344 kfree(priv);
1345 return 0;
1346}
1347
1348static struct platform_driver sh_mobile_lcdc_driver = {
1349 .driver = {
1350 .name = "sh_mobile_lcdc_fb",
1351 .owner = THIS_MODULE,
2feb075a 1352 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD
1353 },
1354 .probe = sh_mobile_lcdc_probe,
1355 .remove = sh_mobile_lcdc_remove,
1356};
1357
1358static int __init sh_mobile_lcdc_init(void)
1359{
1360 return platform_driver_register(&sh_mobile_lcdc_driver);
1361}
1362
1363static void __exit sh_mobile_lcdc_exit(void)
1364{
1365 platform_driver_unregister(&sh_mobile_lcdc_driver);
1366}
1367
1368module_init(sh_mobile_lcdc_init);
1369module_exit(sh_mobile_lcdc_exit);
1370
1371MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1372MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1373MODULE_LICENSE("GPL v2");