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fbdev: sh_mobile_lcdc: make platform videomode table optional
[net-next-2.6.git] / drivers / video / sh_mobile_hdmi.c
CommitLineData
6011bdea
GL		 1/*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/slab.h>
23#include <linux/types.h>
24#include <linux/workqueue.h>
25
26#include <video/sh_mobile_hdmi.h>
27#include <video/sh_mobile_lcdc.h>
28
6de9edd5
GL		 29#include "sh_mobile_lcdcfb.h"
30
6011bdea
GL		 31#define HDMI_SYSTEM_CTRL 0x00 /* System control */
32#define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
33 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
34#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
35#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
36#define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
37 bits 19..16 of Internal CTS */
38#define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
39#define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
40#define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
41#define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
42#define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
43#define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
44#define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
45#define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
46#define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
47#define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
48#define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
49#define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
50#define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
51#define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
52#define HDMI_CATEGORY_CODE 0x13 /* Category code */
53#define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
54#define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
55#define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
56#define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
57
58/* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
59#define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
60
61#define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
62#define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
63#define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
64#define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
65#define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
66#define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
67#define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
68#define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
69#define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
70#define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
71#define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
72#define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
73#define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
74#define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
75#define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
76#define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
77#define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
78#define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
79#define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
80#define HDMI_OUTPUT_OPTION 0x46 /* Output option */
81#define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
82#define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
83#define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
84#define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
85#define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
86#define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
87#define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
88#define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
89#define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
90#define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
91#define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
92#define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
93#define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
94#define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
95#define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
96#define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
97#define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
98#define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
99#define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
100#define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
101#define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
102#define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
103#define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
104#define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
105#define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
106#define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
107#define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
108#define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
109#define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
110#define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
111#define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
112#define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
113#define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
114#define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
115#define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
116#define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
117#define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
118#define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
119#define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
120#define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
121#define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
122#define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
123#define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
124#define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
125#define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
126#define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
127#define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
128#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
129#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
130#define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
131#define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
132#define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
133#define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
134#define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
135#define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
136#define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
137#define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
138#define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
139#define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
140#define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
141#define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
142#define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
143#define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
144#define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
145#define HDMI_SHA0 0xB9 /* sha0 */
146#define HDMI_SHA1 0xBA /* sha1 */
147#define HDMI_SHA2 0xBB /* sha2 */
148#define HDMI_SHA3 0xBC /* sha3 */
149#define HDMI_SHA4 0xBD /* sha4 */
150#define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
151#define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
152#define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
153#define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
154#define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
155#define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
156#define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
157#define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
158#define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
159#define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
160#define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
161#define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
162#define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
163#define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
164#define HDMI_AN_SEED 0xCC /* An seed */
165#define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
166#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
167#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
168#define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
169#define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
170#define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
171#define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
172#define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
173#define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
174#define HDMI_PJ 0xD7 /* Pj */
175#define HDMI_SHA_RD 0xD8 /* sha_rd */
176#define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
177#define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
178#define HDMI_PJ_SAVED 0xDB /* Pj saved */
179#define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
180#define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
181#define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
182#define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
183#define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
184#define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
185#define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
186#define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
187#define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
188#define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
189#define HDMI_AN_7_0 0xE8 /* An[7:0] */
190#define HDMI_AN_15_8 0xE9 /* An [15:8] */
191#define HDMI_AN_23_16 0xEA /* An [23:16] */
192#define HDMI_AN_31_24 0xEB /* An [31:24] */
193#define HDMI_AN_39_32 0xEC /* An [39:32] */
194#define HDMI_AN_47_40 0xED /* An [47:40] */
195#define HDMI_AN_55_48 0xEE /* An [55:48] */
196#define HDMI_AN_63_56 0xEF /* An [63:56] */
197#define HDMI_PRODUCT_ID 0xF0 /* Product ID */
198#define HDMI_REVISION_ID 0xF1 /* Revision ID */
199#define HDMI_TEST_MODE 0xFE /* Test mode */
200
201enum hotplug_state {
202 HDMI_HOTPLUG_DISCONNECTED,
203 HDMI_HOTPLUG_CONNECTED,
204 HDMI_HOTPLUG_EDID_DONE,
205};
206
207struct sh_hdmi {
208 void __iomem *base;
6aa966e6 209 enum hotplug_state hp_state; /* hot-plug status */
89712699 210 bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
6011bdea
GL		 211 struct clk *hdmi_clk;
212 struct device *dev;
213 struct fb_info *info;
6de9edd5 214 struct mutex mutex; /* Protect the info pointer */
6011bdea
GL		 215 struct delayed_work edid_work;
216 struct fb_var_screeninfo var;
afe417c0 217 struct fb_monspecs monspec;
6011bdea
GL		 218};
219
220static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
221{
222 iowrite8(data, hdmi->base + reg);
223}
224
225static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
226{
227 return ioread8(hdmi->base + reg);
228}
229
230/* External video parameter settings */
6aa966e6 231static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
6011bdea
GL		 232{
233 struct fb_var_screeninfo *var = &hdmi->var;
234 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
235 u8 sync = 0;
236
237 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
238
239 hdelay = var->hsync_len + var->left_margin;
240 hblank = var->right_margin + hdelay;
241
242 /*
243 * Vertical timing looks a bit different in Figure 18,
244 * but let's try the same first by setting offset = 0
245 */
246 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
247
248 vdelay = var->vsync_len + var->upper_margin;
249 vblank = var->lower_margin + vdelay;
250 voffset = min(var->upper_margin / 2, 6U);
251
252 /*
253 * [3]: VSYNC polarity: Positive
254 * [2]: HSYNC polarity: Positive
255 * [1]: Interlace/Progressive: Progressive
256 * [0]: External video settings enable: used.
257 */
258 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
259 sync |= 4;
260 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
261 sync |= 8;
262
6aa966e6
GL		 263 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
264 htotal, hblank, hdelay, var->hsync_len,
265 vtotal, vblank, vdelay, var->vsync_len, sync);
6011bdea
GL		 266
267 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
268
269 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
270 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
271
272 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
273 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
274
275 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
276 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
277
278 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
279 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
280
281 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
282 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
283
284 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
285
286 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
287
288 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
289
89712699
GL		 290 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
291 if (!hdmi->preprogrammed_mode)
292 hdmi_write(hdmi, sync | 1 | (voffset << 4),
293 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
6011bdea
GL		 294}
295
296/**
297 * sh_hdmi_video_config()
298 */
299static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
300{
301 /*
302 * [7:4]: Audio sampling frequency: 48kHz
303 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
304 * [0]: Internal/External DE select: internal
305 */
306 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
307
308 /*
309 * [7:6]: Video output format: RGB 4:4:4
310 * [5:4]: Input video data width: 8 bit
311 * [3:1]: EAV/SAV location: channel 1
312 * [0]: Video input color space: RGB
313 */
314 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
315
316 /*
317 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
318 * left at 0 by default, this configures 24bpp and sets the Color Depth
319 * (CD) field in the General Control Packet
320 */
321 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
322}
323
324/**
325 * sh_hdmi_audio_config()
326 */
327static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
328{
329 /*
330 * [7:4] L/R data swap control
331 * [3:0] appropriate N[19:16]
332 */
333 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
334 /* appropriate N[15:8] */
335 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
336 /* appropriate N[7:0] */
337 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
338
339 /* [7:4] 48 kHz SPDIF not used */
340 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
341
342 /*
343 * [6:5] set required down sampling rate if required
344 * [4:3] set required audio source
345 */
346 hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1);
347
348 /* [3:0] set sending channel number for channel status */
349 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
350
351 /*
352 * [5:2] set valid I2S source input pin
353 * [1:0] set input I2S source mode
354 */
355 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
356
357 /* [7:4] set valid DSD source input pin */
358 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
359
360 /* [7:0] set appropriate I2S input pin swap settings if required */
361 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
362
363 /*
364 * [7] set validity bit for channel status
365 * [3:0] set original sample frequency for channel status
366 */
367 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
368
369 /*
370 * [7] set value for channel status
371 * [6] set value for channel status
372 * [5] set copyright bit for channel status
373 * [4:2] set additional information for channel status
374 * [1:0] set clock accuracy for channel status
375 */
376 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
377
378 /* [7:0] set category code for channel status */
379 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
380
381 /*
382 * [7:4] set source number for channel status
383 * [3:0] set word length for channel status
384 */
385 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
386
387 /* [7:4] set sample frequency for channel status */
388 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
389}
390
391/**
6e45746c 392 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
6011bdea
GL		 393 */
394static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
395{
6e45746c
GL		 396 if (hdmi->var.yres > 480) {
397 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
398 /*
399 * [1:0] Speed_A
400 * [3:2] Speed_B
401 * [4] PLLA_Bypass
402 * [6] DRV_TEST_EN
403 * [7] DRV_TEST_IN
404 */
9289c475 405 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
6e45746c
GL		 406 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
407 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
408 /*
409 * [2:0] BGR_I_OFFSET
410 * [6:4] BGR_V_OFFSET
411 */
412 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
413 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
414 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
415 /*
416 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
417 * LPF capacitance, LPF resistance[1]
418 */
419 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
420 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
421 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
422 /*
423 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
424 * LPF capacitance, LPF resistance[1]
425 */
9289c475 426 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
6e45746c
GL		 427 /* DRV_CONFIG, PE_CONFIG */
428 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
429 /*
430 * [2:0] AMON_SEL (4 == LPF voltage)
431 * [4] PLLA_CONFIG[16]
432 * [5] PLLB_CONFIG[16]
433 */
434 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
435 } else {
436 /* for 480p8bit 27MHz */
437 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
438 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
439 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
440 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
441 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
442 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
443 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
444 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
445 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
446 }
6011bdea
GL		 447}
448
449/**
450 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
451 */
452static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
453{
6e45746c
GL		 454 u8 vic;
455
6011bdea
GL		 456 /* AVI InfoFrame */
457 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
458
459 /* Packet Type = 0x82 */
460 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
461
462 /* Version = 0x02 */
463 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
464
465 /* Length = 13 (0x0D) */
466 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
467
468 /* N. A. Checksum */
469 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
470
471 /*
472 * Y = RGB
473 * A0 = No Data
474 * B = Bar Data not valid
475 * S = No Data
476 */
477 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
478
479 /*
6aa966e6
GL		 480 * [7:6] C = Colorimetry: no data
481 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
482 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
6011bdea
GL		 483 */
484 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
485
486 /*
487 * ITC = No Data
488 * EC = xvYCC601
489 * Q = Default (depends on video format)
490 * SC = No Known non_uniform Scaling
491 */
492 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
493
494 /*
495 * VIC = 1280 x 720p: ignored if external config is used
6e45746c 496 * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
6011bdea 497 */
6e45746c
GL		 498 if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
499 vic = 16;
500 else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
501 vic = 2;
502 else
503 vic = 4;
504 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
6011bdea
GL		 505
506 /* PR = No Repetition */
507 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
508
509 /* Line Number of End of Top Bar (lower 8 bits) */
510 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
511
512 /* Line Number of End of Top Bar (upper 8 bits) */
513 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
514
515 /* Line Number of Start of Bottom Bar (lower 8 bits) */
516 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
517
518 /* Line Number of Start of Bottom Bar (upper 8 bits) */
519 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
520
521 /* Pixel Number of End of Left Bar (lower 8 bits) */
522 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
523
524 /* Pixel Number of End of Left Bar (upper 8 bits) */
525 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
526
527 /* Pixel Number of Start of Right Bar (lower 8 bits) */
528 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
529
530 /* Pixel Number of Start of Right Bar (upper 8 bits) */
531 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
532}
533
534/**
535 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
536 */
537static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
538{
539 /* Audio InfoFrame */
540 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
541
542 /* Packet Type = 0x84 */
543 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
544
545 /* Version Number = 0x01 */
546 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
547
548 /* 0 Length = 10 (0x0A) */
549 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
550
551 /* n. a. Checksum */
552 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
553
554 /* Audio Channel Count = Refer to Stream Header */
555 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
556
557 /* Refer to Stream Header */
558 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
559
560 /* Format depends on coding type (i.e. CT0...CT3) */
561 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
562
563 /* Speaker Channel Allocation = Front Right + Front Left */
564 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
565
566 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
567 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
568
569 /* Reserved (0) */
570 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
571 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
572 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
573 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
574 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
575}
576
6011bdea
GL		 577/**
578 * sh_hdmi_configure() - Initialise HDMI for output
579 */
580static void sh_hdmi_configure(struct sh_hdmi *hdmi)
581{
582 /* Configure video format */
583 sh_hdmi_video_config(hdmi);
584
585 /* Configure audio format */
586 sh_hdmi_audio_config(hdmi);
587
588 /* Configure PHY */
589 sh_hdmi_phy_config(hdmi);
590
591 /* Auxiliary Video Information (AVI) InfoFrame */
592 sh_hdmi_avi_infoframe_setup(hdmi);
593
594 /* Audio InfoFrame */
595 sh_hdmi_audio_infoframe_setup(hdmi);
596
6011bdea
GL		 597 /*
598 * Control packet auto send with VSYNC control: auto send
599 * General control, Gamut metadata, ISRC, and ACP packets
600 */
601 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
602
603 /* FIXME */
604 msleep(10);
605
606 /* PS mode b->d, reset PLLA and PLLB */
607 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
608
609 udelay(10);
610
611 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
612}
613
afe417c0 614static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
6011bdea 615{
6ee48452
GL		 616 struct fb_var_screeninfo tmpvar;
617 /* TODO: When we are ready to use EDID, use this to fill &hdmi->var */
618 struct fb_var_screeninfo *var = &tmpvar;
afe417c0 619 const struct fb_videomode *mode, *found = NULL;
6011bdea
GL		 620 int i;
621 u8 edid[128];
622
623 /* Read EDID */
6aa966e6 624 dev_dbg(hdmi->dev, "Read back EDID code:");
6011bdea
GL		 625 for (i = 0; i < 128; i++) {
626 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
627#ifdef DEBUG
628 if ((i % 16) == 0) {
629 printk(KERN_CONT "\n");
630 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
631 } else {
632 printk(KERN_CONT " %02X", edid[i]);
633 }
634#endif
635 }
636#ifdef DEBUG
637 printk(KERN_CONT "\n");
638#endif
afe417c0
GL		 639
640 fb_edid_to_monspecs(edid, &hdmi->monspec);
641
642 /* First look for an exact match */
643 for (i = 0, mode = hdmi->monspec.modedb; i < hdmi->monspec.modedb_len;
644 i++, mode++) {
645 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
646 mode->left_margin, mode->xres,
647 mode->right_margin, mode->hsync_len,
648 mode->upper_margin, mode->yres,
649 mode->lower_margin, mode->vsync_len,
650 PICOS2KHZ(mode->pixclock));
651 if (!found && hdmi->info) {
652 fb_videomode_to_var(var, mode);
653 found = fb_match_mode(var, &hdmi->info->modelist);
654 /*
655 * If an exact match found, we're good to bail out, but
656 * continue to print out all modes
657 */
658 }
659 }
660
661 /*
662 * The monitor might also work with a mode, that is smaller, than one of
663 * its modes, use the first (default) one for this
664 */
665 if (!found && hdmi->info && hdmi->monspec.modedb_len) {
666 struct fb_modelist *modelist;
667 unsigned int min_err = UINT_MAX, err;
668 const struct fb_videomode *mon_mode = hdmi->monspec.modedb;
669
670 list_for_each_entry(modelist, &hdmi->info->modelist, list) {
671 mode = &modelist->mode;
672 dev_dbg(hdmi->dev, "matching %ux%u to %ux%u\n", mode->xres, mode->yres,
673 mon_mode->xres, mon_mode->yres);
674 if (mode->xres <= mon_mode->xres && mode->yres <= mon_mode->yres) {
675 err = mon_mode->xres - mode->xres + mon_mode->yres - mode->yres;
676 if (!err) {
677 found = mode;
678 break;
679 }
680 if (err < min_err) {
681 found = mode;
682 min_err = err;
683 }
684 }
685 }
686 }
687
688 /* Nothing suitable specified by the platform: use monitor's first mode */
689 if (!found && hdmi->monspec.modedb_len)
690 found = hdmi->monspec.modedb;
691
692 /* No valid timing info in EDID - last resort: use platform default mode */
693 if (!found && hdmi->info) {
694 struct fb_modelist *modelist = list_entry(hdmi->info->modelist.next,
695 struct fb_modelist, list);
696 found = &modelist->mode;
697 }
698
699 /* No cookie today */
700 if (!found)
701 return -ENXIO;
702
703 dev_dbg(hdmi->dev, "best \"%s\" %ux%u@%ups\n", found->name,
704 found->xres, found->yres, found->pixclock);
705
706 if ((found->xres == 720 && found->yres == 480) ||
707 (found->xres == 1280 && found->yres == 720) ||
708 (found->xres == 1920 && found->yres == 1080))
89712699
GL		 709 hdmi->preprogrammed_mode = true;
710 else
711 hdmi->preprogrammed_mode = false;
712
afe417c0 713 fb_videomode_to_var(&hdmi->var, found);
6aa966e6 714 sh_hdmi_external_video_param(hdmi);
afe417c0
GL		 715
716 return 0;
6011bdea
GL		 717}
718
719static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
720{
721 struct sh_hdmi *hdmi = dev_id;
722 u8 status1, status2, mask1, mask2;
723
724 /* mode_b and PLLA and PLLB reset */
725 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
726
727 /* How long shall reset be held? */
728 udelay(10);
729
730 /* mode_b and PLLA and PLLB reset release */
731 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
732
733 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
734 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
735
736 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
737 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
738
739 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
740 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
741 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
742
743 if (printk_ratelimit())
6aa966e6
GL		 744 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
745 irq, status1, mask1, status2, mask2);
6011bdea
GL		 746
747 if (!((status1 & mask1) | (status2 & mask2))) {
748 return IRQ_NONE;
749 } else if (status1 & 0xc0) {
750 u8 msens;
751
752 /* Datasheet specifies 10ms... */
753 udelay(500);
754
755 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
6aa966e6 756 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
6011bdea
GL		 757 /* Check, if hot plug & MSENS pin status are both high */
758 if ((msens & 0xC0) == 0xC0) {
759 /* Display plug in */
760 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
761
762 /* Set EDID word address */
763 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
764 /* Set EDID segment pointer */
765 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
766 /* Enable EDID interrupt */
767 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
768 } else if (!(status1 & 0x80)) {
769 /* Display unplug, beware multiple interrupts */
770 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
771 schedule_delayed_work(&hdmi->edid_work, 0);
772
773 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
774 /* display_off will switch back to mode_a */
775 }
776 } else if (status1 & 2) {
777 /* EDID error interrupt: retry */
778 /* Set EDID word address */
779 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
780 /* Set EDID segment pointer */
781 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
782 } else if (status1 & 4) {
783 /* Disable EDID interrupt */
784 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
785 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
786 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
787 }
788
789 return IRQ_HANDLED;
790}
791
6de9edd5 792/* locking: called with info->lock held, or before register_framebuffer() */
6aa966e6 793static void sh_hdmi_display_on(void *arg, struct fb_info *info)
6011bdea 794{
6de9edd5
GL		 795 /*
796 * info is guaranteed to be valid, when we are called, because our
797 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
798 */
6011bdea
GL		 799 struct sh_hdmi *hdmi = arg;
800 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 801 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea 802
6aa966e6
GL		 803 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
804 pdata->lcd_dev, info->state);
6de9edd5
GL		 805
806 /* No need to lock */
6011bdea 807 hdmi->info = info;
6de9edd5 808
6aa966e6
GL		 809 /*
810 * hp_state can be set to
811 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
812 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
813 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
814 */
6011bdea
GL		 815 switch (hdmi->hp_state) {
816 case HDMI_HOTPLUG_EDID_DONE:
817 /* PS mode d->e. All functions are active */
818 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
6aa966e6 819 dev_dbg(hdmi->dev, "HDMI running\n");
6011bdea
GL		 820 break;
821 case HDMI_HOTPLUG_DISCONNECTED:
822 info->state = FBINFO_STATE_SUSPENDED;
823 default:
1c120deb 824 hdmi->var = ch->display_var;
6011bdea
GL		 825 }
826}
827
6de9edd5 828/* locking: called with info->lock held */
6aa966e6 829static void sh_hdmi_display_off(void *arg)
6011bdea
GL		 830{
831 struct sh_hdmi *hdmi = arg;
832 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
833
6aa966e6 834 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
6011bdea
GL		 835 /* PS mode e->a */
836 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
837}
838
afe417c0
GL		 839static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
840{
841 struct fb_info *info = hdmi->info;
842 struct sh_mobile_lcdc_chan *ch = info->par;
843 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
844 struct fb_videomode mode1, mode2;
845
846 fb_var_to_videomode(&mode1, old_var);
847 fb_var_to_videomode(&mode2, new_var);
848
849 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
850 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
851
852 if (fb_mode_is_equal(&mode1, &mode2))
853 return false;
854
855 dev_dbg(info->dev, "Switching %u -> %u lines\n",
856 mode1.yres, mode2.yres);
857 *old_var = *new_var;
858
859 return true;
860}
861
862/**
863 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
864 * @hdmi: driver context
865 * @pixclock: pixel clock period in picoseconds
866 * return: configured positive rate if successful
867 * 0 if couldn't set the rate, but managed to enable the clock
868 * negative error, if couldn't enable the clock
869 */
870static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
871{
872 long rate;
873 int ret;
874
875 rate = PICOS2KHZ(pixclock) * 1000;
876 rate = clk_round_rate(hdmi->hdmi_clk, rate);
877 if (rate > 0) {
878 ret = clk_set_rate(hdmi->hdmi_clk, rate);
879 if (ret < 0) {
880 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
881 rate = 0;
882 } else {
883 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
884 }
885 } else {
886 rate = 0;
887 dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
888 }
889
890 ret = clk_enable(hdmi->hdmi_clk);
891 if (ret < 0) {
892 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
893 return ret;
894 }
895
896 return rate;
897}
898
6011bdea 899/* Hotplug interrupt occurred, read EDID */
6aa966e6 900static void sh_hdmi_edid_work_fn(struct work_struct *work)
6011bdea
GL		 901{
902 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
903 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 904 struct sh_mobile_lcdc_chan *ch;
afe417c0 905 int ret;
6011bdea 906
6aa966e6
GL		 907 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
908 pdata->lcd_dev, hdmi->hp_state);
6011bdea
GL		 909
910 if (!pdata->lcd_dev)
911 return;
912
6de9edd5
GL		 913 mutex_lock(&hdmi->mutex);
914
6011bdea 915 if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
6011bdea 916 /* A device has been plugged in */
afe417c0
GL		 917 pm_runtime_get_sync(hdmi->dev);
918
919 ret = sh_hdmi_read_edid(hdmi);
920 if (ret < 0)
921 goto out;
922
923 /* Reconfigure the clock */
924 clk_disable(hdmi->hdmi_clk);
925 ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
926 if (ret < 0)
927 goto out;
928
6011bdea
GL		 929 msleep(10);
930 sh_hdmi_configure(hdmi);
931 /* Switched to another (d) power-save mode */
932 msleep(10);
933
934 if (!hdmi->info)
6de9edd5 935 goto out;
6011bdea 936
1c120deb
GL		 937 ch = hdmi->info->par;
938
6011bdea
GL		 939 acquire_console_sem();
940
941 /* HDMI plug in */
afe417c0
GL		 942 if (!sh_hdmi_must_reconfigure(hdmi) &&
943 hdmi->info->state == FBINFO_STATE_RUNNING) {
944 /*
945 * First activation with the default monitor - just turn
946 * on, if we run a resume here, the logo disappears
947 */
6de9edd5 948 if (lock_fb_info(hdmi->info)) {
6aa966e6 949 sh_hdmi_display_on(hdmi, hdmi->info);
6de9edd5
GL		 950 unlock_fb_info(hdmi->info);
951 }
afe417c0
GL		 952 } else {
953 /* New monitor or have to wake up */
954 fb_set_suspend(hdmi->info, 0);
6de9edd5 955 }
6011bdea
GL		 956
957 release_console_sem();
958 } else {
afe417c0 959 ret = 0;
6011bdea 960 if (!hdmi->info)
6de9edd5 961 goto out;
6011bdea
GL		 962
963 acquire_console_sem();
964
965 /* HDMI disconnect */
966 fb_set_suspend(hdmi->info, 1);
967
968 release_console_sem();
969 pm_runtime_put(hdmi->dev);
afe417c0 970 fb_destroy_modedb(hdmi->monspec.modedb);
6011bdea
GL		 971 }
972
6de9edd5 973out:
afe417c0
GL		 974 if (ret < 0)
975 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6de9edd5
GL		 976 mutex_unlock(&hdmi->mutex);
977
6aa966e6 978 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
6011bdea
GL		 979}
980
6de9edd5
GL		 981static int sh_hdmi_notify(struct notifier_block *nb,
982 unsigned long action, void *data);
983
984static struct notifier_block sh_hdmi_notifier = {
985 .notifier_call = sh_hdmi_notify,
986};
987
988static int sh_hdmi_notify(struct notifier_block *nb,
989 unsigned long action, void *data)
990{
991 struct fb_event *event = data;
992 struct fb_info *info = event->info;
993 struct sh_mobile_lcdc_chan *ch = info->par;
994 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
995 struct sh_hdmi *hdmi = board_cfg->board_data;
996
997 if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
998 return NOTIFY_DONE;
999
1000 switch(action) {
1001 case FB_EVENT_FB_REGISTERED:
6aa966e6 1002 /* Unneeded, activation taken care by sh_hdmi_display_on() */
6de9edd5
GL		 1003 break;
1004 case FB_EVENT_FB_UNREGISTERED:
1005 /*
1006 * We are called from unregister_framebuffer() with the
1007 * info->lock held. This is bad for us, because we can race with
1008 * the scheduled work, which has to call fb_set_suspend(), which
6aa966e6
GL		 1009 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1010 * cannot take and hold info->lock for the whole function
1011 * duration. Using an additional lock creates a classical AB-BA
1012 * lock up. Therefore, we have to release the info->lock
1013 * temporarily, synchronise with the work queue and re-acquire
1014 * the info->lock.
6de9edd5
GL		 1015 */
1016 unlock_fb_info(hdmi->info);
1017 mutex_lock(&hdmi->mutex);
1018 hdmi->info = NULL;
1019 mutex_unlock(&hdmi->mutex);
1020 lock_fb_info(hdmi->info);
1021 return NOTIFY_OK;
1022 }
1023 return NOTIFY_DONE;
1024}
1025
6011bdea
GL		 1026static int __init sh_hdmi_probe(struct platform_device *pdev)
1027{
1028 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1029 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1030 struct sh_mobile_lcdc_board_cfg *board_cfg;
6011bdea
GL		 1031 int irq = platform_get_irq(pdev, 0), ret;
1032 struct sh_hdmi *hdmi;
1033 long rate;
1034
1035 if (!res || !pdata || irq < 0)
1036 return -ENODEV;
1037
1038 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1039 if (!hdmi) {
1040 dev_err(&pdev->dev, "Cannot allocate device data\n");
1041 return -ENOMEM;
1042 }
1043
6de9edd5 1044 mutex_init(&hdmi->mutex);
6011bdea
GL		 1045 hdmi->dev = &pdev->dev;
1046
1047 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1048 if (IS_ERR(hdmi->hdmi_clk)) {
1049 ret = PTR_ERR(hdmi->hdmi_clk);
1050 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1051 goto egetclk;
1052 }
1053
c44f9f76
GL		 1054 /* Some arbitrary relaxed pixclock just to get things started */
1055 rate = sh_hdmi_clk_configure(hdmi, 37037);
6011bdea
GL		 1056 if (rate < 0) {
1057 ret = rate;
6011bdea
GL		 1058 goto erate;
1059 }
1060
afe417c0 1061 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
6011bdea
GL		 1062
1063 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1064 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1065 ret = -EBUSY;
1066 goto ereqreg;
1067 }
1068
1069 hdmi->base = ioremap(res->start, resource_size(res));
1070 if (!hdmi->base) {
1071 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1072 ret = -ENOMEM;
1073 goto emap;
1074 }
1075
1076 platform_set_drvdata(pdev, hdmi);
1077
6011bdea
GL		 1078 /* Product and revision IDs are 0 in sh-mobile version */
1079 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1080 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
6011bdea
GL		 1081
1082 /* Set up LCDC callbacks */
6de9edd5
GL		 1083 board_cfg = &pdata->lcd_chan->board_cfg;
1084 board_cfg->owner = THIS_MODULE;
1085 board_cfg->board_data = hdmi;
6aa966e6
GL		 1086 board_cfg->display_on = sh_hdmi_display_on;
1087 board_cfg->display_off = sh_hdmi_display_off;
6011bdea 1088
6aa966e6 1089 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
6011bdea
GL		 1090
1091 pm_runtime_enable(&pdev->dev);
1092 pm_runtime_resume(&pdev->dev);
1093
1094 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1095 dev_name(&pdev->dev), hdmi);
1096 if (ret < 0) {
1097 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1098 goto ereqirq;
1099 }
1100
1101 return 0;
1102
1103ereqirq:
1104 pm_runtime_disable(&pdev->dev);
1105 iounmap(hdmi->base);
1106emap:
1107 release_mem_region(res->start, resource_size(res));
1108ereqreg:
1109 clk_disable(hdmi->hdmi_clk);
6011bdea
GL		 1110erate:
1111 clk_put(hdmi->hdmi_clk);
1112egetclk:
6de9edd5 1113 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1114 kfree(hdmi);
1115
1116 return ret;
1117}
1118
1119static int __exit sh_hdmi_remove(struct platform_device *pdev)
1120{
1121 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1122 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1123 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1124 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
6011bdea
GL		 1125 int irq = platform_get_irq(pdev, 0);
1126
6de9edd5
GL		 1127 board_cfg->display_on = NULL;
1128 board_cfg->display_off = NULL;
1129 board_cfg->board_data = NULL;
1130 board_cfg->owner = NULL;
6011bdea 1131
6de9edd5 1132 /* No new work will be scheduled, wait for running ISR */
6011bdea 1133 free_irq(irq, hdmi);
6de9edd5 1134 /* Wait for already scheduled work */
6011bdea 1135 cancel_delayed_work_sync(&hdmi->edid_work);
6de9edd5 1136 pm_runtime_disable(&pdev->dev);
6011bdea
GL		 1137 clk_disable(hdmi->hdmi_clk);
1138 clk_put(hdmi->hdmi_clk);
1139 iounmap(hdmi->base);
1140 release_mem_region(res->start, resource_size(res));
6de9edd5 1141 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1142 kfree(hdmi);
1143
1144 return 0;
1145}
1146
1147static struct platform_driver sh_hdmi_driver = {
1148 .remove = __exit_p(sh_hdmi_remove),
1149 .driver = {
1150 .name = "sh-mobile-hdmi",
1151 },
1152};
1153
1154static int __init sh_hdmi_init(void)
1155{
1156 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1157}
1158module_init(sh_hdmi_init);
1159
1160static void __exit sh_hdmi_exit(void)
1161{
1162 platform_driver_unregister(&sh_hdmi_driver);
1163}
1164module_exit(sh_hdmi_exit);
1165
1166MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1167MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1168MODULE_LICENSE("GPL v2");
Clone of davem's net-next-2.6 tree