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Merge branches 'irq-core-for-linus' and 'core-locking-for-linus' of git://git.kernel...
[net-next-2.6.git] / drivers / video / sh_mobile_hdmi.c
CommitLineData
6011bdea
GL		 1/*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/slab.h>
23#include <linux/types.h>
24#include <linux/workqueue.h>
1d6be338
KM		 25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
6011bdea
GL		 27
28#include <video/sh_mobile_hdmi.h>
29#include <video/sh_mobile_lcdc.h>
30
6de9edd5
GL		 31#include "sh_mobile_lcdcfb.h"
32
6011bdea
GL		 33#define HDMI_SYSTEM_CTRL 0x00 /* System control */
34#define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
35 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
36#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
37#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
38#define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
39 bits 19..16 of Internal CTS */
40#define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
41#define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
42#define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
43#define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
44#define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
45#define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
46#define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
47#define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
48#define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
49#define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
50#define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
51#define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
52#define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
53#define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
54#define HDMI_CATEGORY_CODE 0x13 /* Category code */
55#define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
56#define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
57#define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
58#define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
59
60/* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
61#define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
62
63#define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
64#define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
65#define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
66#define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
67#define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
68#define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
69#define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
70#define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
71#define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
72#define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
73#define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
74#define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
75#define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
76#define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
77#define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
78#define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
79#define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
80#define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
81#define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
82#define HDMI_OUTPUT_OPTION 0x46 /* Output option */
83#define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
84#define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
85#define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
86#define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
87#define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
88#define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
89#define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
90#define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
91#define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
92#define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
93#define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
94#define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
95#define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
96#define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
97#define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
98#define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
99#define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
100#define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
101#define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
102#define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
103#define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
104#define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
105#define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
106#define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
107#define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
108#define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
109#define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
110#define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
111#define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
112#define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
113#define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
114#define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
115#define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
116#define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
117#define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
118#define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
119#define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
120#define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
121#define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
122#define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
123#define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
124#define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
125#define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
126#define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
127#define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
128#define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
129#define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
130#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
131#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
132#define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
133#define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
134#define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
135#define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
136#define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
137#define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
138#define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
139#define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
140#define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
141#define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
142#define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
143#define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
144#define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
145#define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
146#define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
147#define HDMI_SHA0 0xB9 /* sha0 */
148#define HDMI_SHA1 0xBA /* sha1 */
149#define HDMI_SHA2 0xBB /* sha2 */
150#define HDMI_SHA3 0xBC /* sha3 */
151#define HDMI_SHA4 0xBD /* sha4 */
152#define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
153#define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
154#define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
155#define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
156#define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
157#define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
158#define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
159#define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
160#define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
161#define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
162#define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
163#define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
164#define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
165#define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
166#define HDMI_AN_SEED 0xCC /* An seed */
167#define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
168#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
169#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
170#define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
171#define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
172#define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
173#define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
174#define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
175#define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
176#define HDMI_PJ 0xD7 /* Pj */
177#define HDMI_SHA_RD 0xD8 /* sha_rd */
178#define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
179#define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
180#define HDMI_PJ_SAVED 0xDB /* Pj saved */
181#define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
182#define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
183#define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
184#define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
185#define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
186#define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
187#define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
188#define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
189#define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
190#define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
191#define HDMI_AN_7_0 0xE8 /* An[7:0] */
192#define HDMI_AN_15_8 0xE9 /* An [15:8] */
193#define HDMI_AN_23_16 0xEA /* An [23:16] */
194#define HDMI_AN_31_24 0xEB /* An [31:24] */
195#define HDMI_AN_39_32 0xEC /* An [39:32] */
196#define HDMI_AN_47_40 0xED /* An [47:40] */
197#define HDMI_AN_55_48 0xEE /* An [55:48] */
198#define HDMI_AN_63_56 0xEF /* An [63:56] */
199#define HDMI_PRODUCT_ID 0xF0 /* Product ID */
200#define HDMI_REVISION_ID 0xF1 /* Revision ID */
201#define HDMI_TEST_MODE 0xFE /* Test mode */
202
203enum hotplug_state {
204 HDMI_HOTPLUG_DISCONNECTED,
205 HDMI_HOTPLUG_CONNECTED,
206 HDMI_HOTPLUG_EDID_DONE,
207};
208
209struct sh_hdmi {
210 void __iomem *base;
6aa966e6 211 enum hotplug_state hp_state; /* hot-plug status */
89712699 212 bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
6011bdea
GL		 213 struct clk *hdmi_clk;
214 struct device *dev;
215 struct fb_info *info;
6de9edd5 216 struct mutex mutex; /* Protect the info pointer */
6011bdea
GL		 217 struct delayed_work edid_work;
218 struct fb_var_screeninfo var;
afe417c0 219 struct fb_monspecs monspec;
6011bdea
GL		 220};
221
222static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
223{
224 iowrite8(data, hdmi->base + reg);
225}
226
227static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
228{
229 return ioread8(hdmi->base + reg);
230}
231
f4363b7d
KM		 232/*
233 * HDMI sound
234 */
1d6be338
KM		 235static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
236 unsigned int reg)
237{
238 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
239
240 return hdmi_read(hdmi, reg);
241}
242
243static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
244 unsigned int reg,
245 unsigned int value)
246{
247 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
248
249 hdmi_write(hdmi, value, reg);
250 return 0;
251}
252
253static struct snd_soc_dai_driver sh_hdmi_dai = {
254 .name = "sh_mobile_hdmi-hifi",
255 .playback = {
256 .stream_name = "Playback",
17731f8d
KM		 257 .channels_min = 2,
258 .channels_max = 8,
259 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
260 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
261 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
262 SNDRV_PCM_RATE_192000,
1d6be338
KM		 263 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
264 },
265};
266
267static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
268{
269 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
270
271 return 0;
272}
273
274static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
275 .probe = sh_hdmi_snd_probe,
276 .read = sh_hdmi_snd_read,
277 .write = sh_hdmi_snd_write,
278};
279
f4363b7d
KM		 280/*
281 * HDMI video
282 */
1d6be338 283
6011bdea 284/* External video parameter settings */
6aa966e6 285static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
6011bdea
GL		 286{
287 struct fb_var_screeninfo *var = &hdmi->var;
288 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
289 u8 sync = 0;
290
291 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
292
293 hdelay = var->hsync_len + var->left_margin;
294 hblank = var->right_margin + hdelay;
295
296 /*
297 * Vertical timing looks a bit different in Figure 18,
298 * but let's try the same first by setting offset = 0
299 */
300 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
301
302 vdelay = var->vsync_len + var->upper_margin;
303 vblank = var->lower_margin + vdelay;
304 voffset = min(var->upper_margin / 2, 6U);
305
306 /*
307 * [3]: VSYNC polarity: Positive
308 * [2]: HSYNC polarity: Positive
309 * [1]: Interlace/Progressive: Progressive
310 * [0]: External video settings enable: used.
311 */
312 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
313 sync |= 4;
314 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
315 sync |= 8;
316
6aa966e6
GL		 317 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
318 htotal, hblank, hdelay, var->hsync_len,
319 vtotal, vblank, vdelay, var->vsync_len, sync);
6011bdea
GL		 320
321 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
322
323 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
324 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
325
326 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
327 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
328
329 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
330 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
331
332 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
333 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
334
335 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
336 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
337
338 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
339
340 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
341
342 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
343
89712699
GL		 344 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
345 if (!hdmi->preprogrammed_mode)
346 hdmi_write(hdmi, sync | 1 | (voffset << 4),
347 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
6011bdea
GL		 348}
349
350/**
351 * sh_hdmi_video_config()
352 */
353static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
354{
355 /*
356 * [7:4]: Audio sampling frequency: 48kHz
357 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
358 * [0]: Internal/External DE select: internal
359 */
360 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
361
362 /*
363 * [7:6]: Video output format: RGB 4:4:4
364 * [5:4]: Input video data width: 8 bit
365 * [3:1]: EAV/SAV location: channel 1
366 * [0]: Video input color space: RGB
367 */
368 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
369
370 /*
371 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
372 * left at 0 by default, this configures 24bpp and sets the Color Depth
373 * (CD) field in the General Control Packet
374 */
375 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
376}
377
378/**
379 * sh_hdmi_audio_config()
380 */
381static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
382{
6d865771
KM		 383 u8 data;
384 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
385
6011bdea
GL		 386 /*
387 * [7:4] L/R data swap control
388 * [3:0] appropriate N[19:16]
389 */
390 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
391 /* appropriate N[15:8] */
392 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
393 /* appropriate N[7:0] */
394 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
395
396 /* [7:4] 48 kHz SPDIF not used */
397 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
398
399 /*
400 * [6:5] set required down sampling rate if required
401 * [4:3] set required audio source
402 */
dec6aa49 403 switch (pdata->flags & HDMI_SND_SRC_MASK) {
6d865771 404 default:
f4363b7d 405 /* fall through */
dec6aa49
KM		 406 case HDMI_SND_SRC_I2S:
407 data = 0x0 << 3;
6d865771 408 break;
dec6aa49
KM		 409 case HDMI_SND_SRC_SPDIF:
410 data = 0x1 << 3;
6d865771 411 break;
dec6aa49
KM		 412 case HDMI_SND_SRC_DSD:
413 data = 0x2 << 3;
6d865771 414 break;
dec6aa49
KM		 415 case HDMI_SND_SRC_HBR:
416 data = 0x3 << 3;
6d865771
KM		 417 break;
418 }
419 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
6011bdea
GL		 420
421 /* [3:0] set sending channel number for channel status */
422 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
423
424 /*
425 * [5:2] set valid I2S source input pin
426 * [1:0] set input I2S source mode
427 */
428 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
429
430 /* [7:4] set valid DSD source input pin */
431 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
432
433 /* [7:0] set appropriate I2S input pin swap settings if required */
434 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
435
436 /*
437 * [7] set validity bit for channel status
438 * [3:0] set original sample frequency for channel status
439 */
440 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
441
442 /*
443 * [7] set value for channel status
444 * [6] set value for channel status
445 * [5] set copyright bit for channel status
446 * [4:2] set additional information for channel status
447 * [1:0] set clock accuracy for channel status
448 */
449 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
450
451 /* [7:0] set category code for channel status */
452 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
453
454 /*
455 * [7:4] set source number for channel status
456 * [3:0] set word length for channel status
457 */
458 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
459
460 /* [7:4] set sample frequency for channel status */
461 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
462}
463
464/**
6e45746c 465 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
6011bdea
GL		 466 */
467static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
468{
6e45746c
GL		 469 if (hdmi->var.yres > 480) {
470 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
471 /*
472 * [1:0] Speed_A
473 * [3:2] Speed_B
474 * [4] PLLA_Bypass
475 * [6] DRV_TEST_EN
476 * [7] DRV_TEST_IN
477 */
9289c475 478 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
6e45746c
GL		 479 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
480 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
481 /*
482 * [2:0] BGR_I_OFFSET
483 * [6:4] BGR_V_OFFSET
484 */
485 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
486 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
487 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
488 /*
489 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
490 * LPF capacitance, LPF resistance[1]
491 */
492 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
493 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
494 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
495 /*
496 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
497 * LPF capacitance, LPF resistance[1]
498 */
9289c475 499 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
6e45746c
GL		 500 /* DRV_CONFIG, PE_CONFIG */
501 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
502 /*
503 * [2:0] AMON_SEL (4 == LPF voltage)
504 * [4] PLLA_CONFIG[16]
505 * [5] PLLB_CONFIG[16]
506 */
507 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
508 } else {
509 /* for 480p8bit 27MHz */
510 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
511 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
512 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
513 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
514 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
515 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
516 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
517 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
518 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
519 }
6011bdea
GL		 520}
521
522/**
523 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
524 */
525static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
526{
6e45746c
GL		 527 u8 vic;
528
6011bdea
GL		 529 /* AVI InfoFrame */
530 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
531
532 /* Packet Type = 0x82 */
533 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
534
535 /* Version = 0x02 */
536 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
537
538 /* Length = 13 (0x0D) */
539 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
540
541 /* N. A. Checksum */
542 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
543
544 /*
545 * Y = RGB
546 * A0 = No Data
547 * B = Bar Data not valid
548 * S = No Data
549 */
550 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
551
552 /*
6aa966e6
GL		 553 * [7:6] C = Colorimetry: no data
554 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
555 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
6011bdea
GL		 556 */
557 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
558
559 /*
560 * ITC = No Data
561 * EC = xvYCC601
562 * Q = Default (depends on video format)
563 * SC = No Known non_uniform Scaling
564 */
565 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
566
567 /*
568 * VIC = 1280 x 720p: ignored if external config is used
6e45746c 569 * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
6011bdea 570 */
6e45746c
GL		 571 if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
572 vic = 16;
573 else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
574 vic = 2;
575 else
576 vic = 4;
577 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
6011bdea
GL		 578
579 /* PR = No Repetition */
580 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
581
582 /* Line Number of End of Top Bar (lower 8 bits) */
583 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
584
585 /* Line Number of End of Top Bar (upper 8 bits) */
586 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
587
588 /* Line Number of Start of Bottom Bar (lower 8 bits) */
589 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
590
591 /* Line Number of Start of Bottom Bar (upper 8 bits) */
592 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
593
594 /* Pixel Number of End of Left Bar (lower 8 bits) */
595 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
596
597 /* Pixel Number of End of Left Bar (upper 8 bits) */
598 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
599
600 /* Pixel Number of Start of Right Bar (lower 8 bits) */
601 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
602
603 /* Pixel Number of Start of Right Bar (upper 8 bits) */
604 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
605}
606
607/**
608 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
609 */
610static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
611{
612 /* Audio InfoFrame */
613 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
614
615 /* Packet Type = 0x84 */
616 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
617
618 /* Version Number = 0x01 */
619 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
620
621 /* 0 Length = 10 (0x0A) */
622 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
623
624 /* n. a. Checksum */
625 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
626
627 /* Audio Channel Count = Refer to Stream Header */
628 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
629
630 /* Refer to Stream Header */
631 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
632
633 /* Format depends on coding type (i.e. CT0...CT3) */
634 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
635
636 /* Speaker Channel Allocation = Front Right + Front Left */
637 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
638
639 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
640 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
641
642 /* Reserved (0) */
643 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
644 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
645 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
646 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
647 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
648}
649
6011bdea
GL		 650/**
651 * sh_hdmi_configure() - Initialise HDMI for output
652 */
653static void sh_hdmi_configure(struct sh_hdmi *hdmi)
654{
655 /* Configure video format */
656 sh_hdmi_video_config(hdmi);
657
658 /* Configure audio format */
659 sh_hdmi_audio_config(hdmi);
660
661 /* Configure PHY */
662 sh_hdmi_phy_config(hdmi);
663
664 /* Auxiliary Video Information (AVI) InfoFrame */
665 sh_hdmi_avi_infoframe_setup(hdmi);
666
667 /* Audio InfoFrame */
668 sh_hdmi_audio_infoframe_setup(hdmi);
669
6011bdea
GL		 670 /*
671 * Control packet auto send with VSYNC control: auto send
672 * General control, Gamut metadata, ISRC, and ACP packets
673 */
674 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
675
676 /* FIXME */
677 msleep(10);
678
679 /* PS mode b->d, reset PLLA and PLLB */
680 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
681
682 udelay(10);
683
684 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
685}
686
f1198d1e
GL		 687static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
688 const struct fb_videomode *mode)
6011bdea 689{
f1198d1e
GL		 690 long target = PICOS2KHZ(mode->pixclock) * 1000,
691 rate = clk_round_rate(hdmi->hdmi_clk, target);
692 unsigned long rate_error = rate > 0 ? abs(rate - target) : ULONG_MAX;
693
694 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
695 mode->left_margin, mode->xres,
696 mode->right_margin, mode->hsync_len,
697 mode->upper_margin, mode->yres,
698 mode->lower_margin, mode->vsync_len);
699
700 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz\n", target,
701 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
702 mode->refresh);
703
704 return rate_error;
705}
706
afe417c0 707static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
6011bdea 708{
6ee48452 709 struct fb_var_screeninfo tmpvar;
6ee48452 710 struct fb_var_screeninfo *var = &tmpvar;
afe417c0 711 const struct fb_videomode *mode, *found = NULL;
f1198d1e
GL		 712 struct fb_info *info = hdmi->info;
713 struct fb_modelist *modelist = NULL;
714 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
715 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
716 bool exact_match = false;
6011bdea 717 u8 edid[128];
f1198d1e
GL		 718 char *forced;
719 int i;
6011bdea
GL		 720
721 /* Read EDID */
6aa966e6 722 dev_dbg(hdmi->dev, "Read back EDID code:");
6011bdea
GL		 723 for (i = 0; i < 128; i++) {
724 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
725#ifdef DEBUG
726 if ((i % 16) == 0) {
727 printk(KERN_CONT "\n");
728 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
729 } else {
730 printk(KERN_CONT " %02X", edid[i]);
731 }
732#endif
733 }
734#ifdef DEBUG
735 printk(KERN_CONT "\n");
736#endif
afe417c0
GL		 737
738 fb_edid_to_monspecs(edid, &hdmi->monspec);
739
f1198d1e
GL		 740 fb_get_options("sh_mobile_lcdc", &forced);
741 if (forced && *forced) {
742 /* Only primitive parsing so far */
743 i = sscanf(forced, "%ux%u@%u",
744 &f_width, &f_height, &f_refresh);
745 if (i < 2) {
746 f_width = 0;
747 f_height = 0;
748 }
749 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
750 f_width, f_height, f_refresh);
751 }
752
753 /* Walk monitor modes to find the best or the exact match */
754 for (i = 0, mode = hdmi->monspec.modedb;
755 f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
afe417c0 756 i++, mode++) {
f1198d1e
GL		 757 unsigned long rate_error = sh_hdmi_rate_error(hdmi, mode);
758
759 /* No interest in unmatching modes */
760 if (f_width != mode->xres || f_height != mode->yres)
761 continue;
762 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
afe417c0 763 /*
f1198d1e
GL		 764 * Exact match if either the refresh rate matches or it
765 * hasn't been specified and we've found a mode, for
766 * which we can configure the clock precisely
afe417c0 767 */
f1198d1e
GL		 768 exact_match = true;
769 else if (found && found_rate_error <= rate_error)
770 /*
771 * We otherwise search for the closest matching clock
772 * rate - either if no refresh rate has been specified
773 * or we cannot find an exactly matching one
774 */
775 continue;
776
777 /* Check if supported: sufficient fb memory, supported clock-rate */
778 fb_videomode_to_var(var, mode);
779
780 if (info && info->fbops->fb_check_var &&
781 info->fbops->fb_check_var(var, info)) {
782 exact_match = false;
783 continue;
afe417c0 784 }
f1198d1e
GL		 785
786 found = mode;
787 found_rate_error = rate_error;
afe417c0
GL		 788 }
789
790 /*
f1198d1e
GL		 791 * TODO 1: if no ->info is present, postpone running the config until
792 * after ->info first gets registered.
793 * TODO 2: consider registering the HDMI platform device from the LCDC
794 * driver, and passing ->info with HDMI platform data.
afe417c0 795 */
f1198d1e
GL		 796 if (info && !found) {
797 modelist = hdmi->info->modelist.next &&
798 !list_empty(&hdmi->info->modelist) ?
799 list_entry(hdmi->info->modelist.next,
800 struct fb_modelist, list) :
801 NULL;
802
803 if (modelist) {
804 found = &modelist->mode;
805 found_rate_error = sh_hdmi_rate_error(hdmi, found);
afe417c0
GL		 806 }
807 }
808
afe417c0
GL		 809 /* No cookie today */
810 if (!found)
811 return -ENXIO;
812
f1198d1e
GL		 813 dev_info(hdmi->dev, "Using %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
814 modelist ? "default" : "EDID", found->xres, found->yres,
815 found->refresh, PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
afe417c0
GL		 816
817 if ((found->xres == 720 && found->yres == 480) ||
818 (found->xres == 1280 && found->yres == 720) ||
819 (found->xres == 1920 && found->yres == 1080))
89712699
GL		 820 hdmi->preprogrammed_mode = true;
821 else
822 hdmi->preprogrammed_mode = false;
823
afe417c0 824 fb_videomode_to_var(&hdmi->var, found);
6aa966e6 825 sh_hdmi_external_video_param(hdmi);
afe417c0
GL		 826
827 return 0;
6011bdea
GL		 828}
829
830static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
831{
832 struct sh_hdmi *hdmi = dev_id;
833 u8 status1, status2, mask1, mask2;
834
835 /* mode_b and PLLA and PLLB reset */
836 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
837
838 /* How long shall reset be held? */
839 udelay(10);
840
841 /* mode_b and PLLA and PLLB reset release */
842 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
843
844 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
845 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
846
847 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
848 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
849
850 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
851 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
852 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
853
854 if (printk_ratelimit())
6aa966e6
GL		 855 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
856 irq, status1, mask1, status2, mask2);
6011bdea
GL		 857
858 if (!((status1 & mask1) | (status2 & mask2))) {
859 return IRQ_NONE;
860 } else if (status1 & 0xc0) {
861 u8 msens;
862
863 /* Datasheet specifies 10ms... */
864 udelay(500);
865
866 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
6aa966e6 867 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
6011bdea
GL		 868 /* Check, if hot plug & MSENS pin status are both high */
869 if ((msens & 0xC0) == 0xC0) {
870 /* Display plug in */
871 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
872
873 /* Set EDID word address */
874 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
875 /* Set EDID segment pointer */
876 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
877 /* Enable EDID interrupt */
878 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
879 } else if (!(status1 & 0x80)) {
880 /* Display unplug, beware multiple interrupts */
881 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
882 schedule_delayed_work(&hdmi->edid_work, 0);
883
884 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
885 /* display_off will switch back to mode_a */
886 }
887 } else if (status1 & 2) {
888 /* EDID error interrupt: retry */
889 /* Set EDID word address */
890 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
891 /* Set EDID segment pointer */
892 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
893 } else if (status1 & 4) {
894 /* Disable EDID interrupt */
895 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
896 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
897 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
898 }
899
900 return IRQ_HANDLED;
901}
902
6de9edd5 903/* locking: called with info->lock held, or before register_framebuffer() */
6aa966e6 904static void sh_hdmi_display_on(void *arg, struct fb_info *info)
6011bdea 905{
6de9edd5
GL		 906 /*
907 * info is guaranteed to be valid, when we are called, because our
908 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
909 */
6011bdea
GL		 910 struct sh_hdmi *hdmi = arg;
911 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 912 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea 913
6aa966e6
GL		 914 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
915 pdata->lcd_dev, info->state);
6de9edd5
GL		 916
917 /* No need to lock */
6011bdea 918 hdmi->info = info;
6011bdea 919
6011bdea 920 /*
6aa966e6
GL		 921 * hp_state can be set to
922 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
923 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
924 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
6011bdea 925 */
6011bdea
GL		 926 switch (hdmi->hp_state) {
927 case HDMI_HOTPLUG_EDID_DONE:
928 /* PS mode d->e. All functions are active */
929 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
6aa966e6 930 dev_dbg(hdmi->dev, "HDMI running\n");
6011bdea
GL		 931 break;
932 case HDMI_HOTPLUG_DISCONNECTED:
933 info->state = FBINFO_STATE_SUSPENDED;
934 default:
1c120deb 935 hdmi->var = ch->display_var;
6011bdea
GL		 936 }
937}
938
6de9edd5 939/* locking: called with info->lock held */
6aa966e6 940static void sh_hdmi_display_off(void *arg)
6011bdea
GL		 941{
942 struct sh_hdmi *hdmi = arg;
943 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
944
6aa966e6 945 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
6011bdea
GL		 946 /* PS mode e->a */
947 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
948}
949
afe417c0
GL		 950static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
951{
952 struct fb_info *info = hdmi->info;
953 struct sh_mobile_lcdc_chan *ch = info->par;
954 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
955 struct fb_videomode mode1, mode2;
956
957 fb_var_to_videomode(&mode1, old_var);
958 fb_var_to_videomode(&mode2, new_var);
959
960 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
961 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
962
963 if (fb_mode_is_equal(&mode1, &mode2))
964 return false;
965
966 dev_dbg(info->dev, "Switching %u -> %u lines\n",
967 mode1.yres, mode2.yres);
968 *old_var = *new_var;
969
970 return true;
971}
972
973/**
974 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
975 * @hdmi: driver context
976 * @pixclock: pixel clock period in picoseconds
977 * return: configured positive rate if successful
978 * 0 if couldn't set the rate, but managed to enable the clock
979 * negative error, if couldn't enable the clock
980 */
981static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
982{
983 long rate;
984 int ret;
985
986 rate = PICOS2KHZ(pixclock) * 1000;
987 rate = clk_round_rate(hdmi->hdmi_clk, rate);
988 if (rate > 0) {
989 ret = clk_set_rate(hdmi->hdmi_clk, rate);
990 if (ret < 0) {
991 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
992 rate = 0;
993 } else {
994 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
995 }
996 } else {
997 rate = 0;
998 dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
999 }
1000
1001 ret = clk_enable(hdmi->hdmi_clk);
1002 if (ret < 0) {
1003 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1004 return ret;
1005 }
1006
1007 return rate;
1008}
1009
6011bdea 1010/* Hotplug interrupt occurred, read EDID */
6aa966e6 1011static void sh_hdmi_edid_work_fn(struct work_struct *work)
6011bdea
GL		 1012{
1013 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1014 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 1015 struct sh_mobile_lcdc_chan *ch;
afe417c0 1016 int ret;
6011bdea 1017
6aa966e6
GL		 1018 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1019 pdata->lcd_dev, hdmi->hp_state);
6011bdea
GL		 1020
1021 if (!pdata->lcd_dev)
1022 return;
1023
6de9edd5
GL		 1024 mutex_lock(&hdmi->mutex);
1025
6011bdea 1026 if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
6011bdea 1027 /* A device has been plugged in */
afe417c0
GL		 1028 pm_runtime_get_sync(hdmi->dev);
1029
1030 ret = sh_hdmi_read_edid(hdmi);
1031 if (ret < 0)
1032 goto out;
1033
1034 /* Reconfigure the clock */
1035 clk_disable(hdmi->hdmi_clk);
1036 ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
1037 if (ret < 0)
1038 goto out;
1039
6011bdea
GL		 1040 msleep(10);
1041 sh_hdmi_configure(hdmi);
1042 /* Switched to another (d) power-save mode */
1043 msleep(10);
1044
1045 if (!hdmi->info)
6de9edd5 1046 goto out;
6011bdea 1047
1c120deb 1048 ch = hdmi->info->par;
6011bdea
GL		 1049
1050 acquire_console_sem();
1051
1052 /* HDMI plug in */
afe417c0
GL		 1053 if (!sh_hdmi_must_reconfigure(hdmi) &&
1054 hdmi->info->state == FBINFO_STATE_RUNNING) {
1055 /*
1056 * First activation with the default monitor - just turn
1057 * on, if we run a resume here, the logo disappears
1058 */
6de9edd5 1059 if (lock_fb_info(hdmi->info)) {
6aa966e6 1060 sh_hdmi_display_on(hdmi, hdmi->info);
6de9edd5
GL		 1061 unlock_fb_info(hdmi->info);
1062 }
afe417c0
GL		 1063 } else {
1064 /* New monitor or have to wake up */
6011bdea 1065 fb_set_suspend(hdmi->info, 0);
6de9edd5 1066 }
6011bdea
GL		 1067
1068 release_console_sem();
1069 } else {
afe417c0 1070 ret = 0;
6011bdea 1071 if (!hdmi->info)
6de9edd5 1072 goto out;
6011bdea
GL		 1073
1074 acquire_console_sem();
1075
1076 /* HDMI disconnect */
1077 fb_set_suspend(hdmi->info, 1);
1078
1079 release_console_sem();
1080 pm_runtime_put(hdmi->dev);
afe417c0 1081 fb_destroy_modedb(hdmi->monspec.modedb);
6011bdea
GL		 1082 }
1083
6de9edd5 1084out:
afe417c0
GL		 1085 if (ret < 0)
1086 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6de9edd5
GL		 1087 mutex_unlock(&hdmi->mutex);
1088
6aa966e6 1089 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
6011bdea
GL		 1090}
1091
6de9edd5
GL		 1092static int sh_hdmi_notify(struct notifier_block *nb,
1093 unsigned long action, void *data);
1094
1095static struct notifier_block sh_hdmi_notifier = {
1096 .notifier_call = sh_hdmi_notify,
1097};
1098
1099static int sh_hdmi_notify(struct notifier_block *nb,
1100 unsigned long action, void *data)
1101{
1102 struct fb_event *event = data;
1103 struct fb_info *info = event->info;
1104 struct sh_mobile_lcdc_chan *ch = info->par;
1105 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1106 struct sh_hdmi *hdmi = board_cfg->board_data;
1107
1108 if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1109 return NOTIFY_DONE;
1110
1111 switch(action) {
1112 case FB_EVENT_FB_REGISTERED:
6aa966e6 1113 /* Unneeded, activation taken care by sh_hdmi_display_on() */
6de9edd5
GL		 1114 break;
1115 case FB_EVENT_FB_UNREGISTERED:
1116 /*
1117 * We are called from unregister_framebuffer() with the
1118 * info->lock held. This is bad for us, because we can race with
1119 * the scheduled work, which has to call fb_set_suspend(), which
6aa966e6
GL		 1120 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1121 * cannot take and hold info->lock for the whole function
1122 * duration. Using an additional lock creates a classical AB-BA
1123 * lock up. Therefore, we have to release the info->lock
1124 * temporarily, synchronise with the work queue and re-acquire
1125 * the info->lock.
6de9edd5
GL		 1126 */
1127 unlock_fb_info(hdmi->info);
1128 mutex_lock(&hdmi->mutex);
1129 hdmi->info = NULL;
1130 mutex_unlock(&hdmi->mutex);
1131 lock_fb_info(hdmi->info);
1132 return NOTIFY_OK;
1133 }
1134 return NOTIFY_DONE;
6011bdea
GL		 1135}
1136
1137static int __init sh_hdmi_probe(struct platform_device *pdev)
1138{
1139 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1140 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1141 struct sh_mobile_lcdc_board_cfg *board_cfg;
6011bdea
GL		 1142 int irq = platform_get_irq(pdev, 0), ret;
1143 struct sh_hdmi *hdmi;
1144 long rate;
1145
1146 if (!res || !pdata || irq < 0)
1147 return -ENODEV;
1148
1149 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1150 if (!hdmi) {
1151 dev_err(&pdev->dev, "Cannot allocate device data\n");
1152 return -ENOMEM;
1153 }
1154
6de9edd5 1155 mutex_init(&hdmi->mutex);
1d6be338 1156
6011bdea
GL		 1157 hdmi->dev = &pdev->dev;
1158
1159 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1160 if (IS_ERR(hdmi->hdmi_clk)) {
1161 ret = PTR_ERR(hdmi->hdmi_clk);
1162 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1163 goto egetclk;
1164 }
1165
c44f9f76
GL		 1166 /* Some arbitrary relaxed pixclock just to get things started */
1167 rate = sh_hdmi_clk_configure(hdmi, 37037);
6011bdea
GL		 1168 if (rate < 0) {
1169 ret = rate;
6011bdea
GL		 1170 goto erate;
1171 }
1172
afe417c0 1173 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
6011bdea
GL		 1174
1175 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1176 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1177 ret = -EBUSY;
1178 goto ereqreg;
1179 }
1180
1181 hdmi->base = ioremap(res->start, resource_size(res));
1182 if (!hdmi->base) {
1183 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1184 ret = -ENOMEM;
1185 goto emap;
1186 }
1187
1188 platform_set_drvdata(pdev, hdmi);
1189
6011bdea
GL		 1190 /* Product and revision IDs are 0 in sh-mobile version */
1191 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1192 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
6011bdea
GL		 1193
1194 /* Set up LCDC callbacks */
6de9edd5
GL		 1195 board_cfg = &pdata->lcd_chan->board_cfg;
1196 board_cfg->owner = THIS_MODULE;
1197 board_cfg->board_data = hdmi;
6aa966e6
GL		 1198 board_cfg->display_on = sh_hdmi_display_on;
1199 board_cfg->display_off = sh_hdmi_display_off;
6011bdea 1200
6aa966e6 1201 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
6011bdea
GL		 1202
1203 pm_runtime_enable(&pdev->dev);
1204 pm_runtime_resume(&pdev->dev);
1205
1206 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1207 dev_name(&pdev->dev), hdmi);
1208 if (ret < 0) {
1209 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1210 goto ereqirq;
1211 }
1212
b3773301
RK		 1213 ret = snd_soc_register_codec(&pdev->dev,
1214 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1215 if (ret < 0) {
1216 dev_err(&pdev->dev, "codec registration failed\n");
1217 goto ecodec;
1218 }
1219
6011bdea
GL		 1220 return 0;
1221
b3773301
RK		 1222ecodec:
1223 free_irq(irq, hdmi);
6011bdea
GL		 1224ereqirq:
1225 pm_runtime_disable(&pdev->dev);
1226 iounmap(hdmi->base);
1227emap:
1228 release_mem_region(res->start, resource_size(res));
1229ereqreg:
1230 clk_disable(hdmi->hdmi_clk);
6011bdea
GL		 1231erate:
1232 clk_put(hdmi->hdmi_clk);
1233egetclk:
6de9edd5 1234 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1235 kfree(hdmi);
1236
1237 return ret;
1238}
1239
1240static int __exit sh_hdmi_remove(struct platform_device *pdev)
1241{
1242 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1243 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1244 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1245 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
6011bdea
GL		 1246 int irq = platform_get_irq(pdev, 0);
1247
1d6be338
KM		 1248 snd_soc_unregister_codec(&pdev->dev);
1249
6de9edd5
GL		 1250 board_cfg->display_on = NULL;
1251 board_cfg->display_off = NULL;
1252 board_cfg->board_data = NULL;
1253 board_cfg->owner = NULL;
6011bdea 1254
6de9edd5 1255 /* No new work will be scheduled, wait for running ISR */
6011bdea 1256 free_irq(irq, hdmi);
6de9edd5 1257 /* Wait for already scheduled work */
6011bdea 1258 cancel_delayed_work_sync(&hdmi->edid_work);
6de9edd5 1259 pm_runtime_disable(&pdev->dev);
6011bdea
GL		 1260 clk_disable(hdmi->hdmi_clk);
1261 clk_put(hdmi->hdmi_clk);
1262 iounmap(hdmi->base);
1263 release_mem_region(res->start, resource_size(res));
6de9edd5 1264 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1265 kfree(hdmi);
1266
1267 return 0;
1268}
1269
1270static struct platform_driver sh_hdmi_driver = {
1271 .remove = __exit_p(sh_hdmi_remove),
1272 .driver = {
1273 .name = "sh-mobile-hdmi",
1274 },
1275};
1276
1277static int __init sh_hdmi_init(void)
1278{
1279 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1280}
1281module_init(sh_hdmi_init);
1282
1283static void __exit sh_hdmi_exit(void)
1284{
1285 platform_driver_unregister(&sh_hdmi_driver);
1286}
1287module_exit(sh_hdmi_exit);
1288
1289MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1290MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1291MODULE_LICENSE("GPL v2");
Clone of davem's net-next-2.6 tree