[net-next-2.6.git] / drivers / video / geode / gxfb_core.c

/*
 * Geode GX framebuffer driver.
 *
 *   Copyright (C) 2006 Arcom Control Systems Ltd.
 *
 *   This program is free software; you can redistribute it and/or modify it
 *   under the terms of the GNU General Public License as published by the
 *   Free Software Foundation; either version 2 of the License, or (at your
 *   option) any later version.
 *
 *
 * This driver assumes that the BIOS has created a virtual PCI device header
 * for the video device. The PCI header is assumed to contain the following
 * BARs:
 *
 *    BAR0 - framebuffer memory
 *    BAR1 - graphics processor registers
 *    BAR2 - display controller registers
 *    BAR3 - video processor and flat panel control registers.
 *
 * 16 MiB of framebuffer memory is assumed to be available.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/geode.h>

#include "gxfb.h"

static char *mode_option;
static int vram;

/* Modes relevant to the GX (taken from modedb.c) */
static const struct fb_videomode gx_modedb[] __initdata = {
	/* 640x480-60 VESA */
	{ NULL, 60, 640, 480, 39682,  48, 16, 33, 10, 96, 2,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 640x480-75 VESA */
	{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 640x480-85 VESA */
	{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 800x600-60 VESA */
	{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 800x600-75 VESA */
	{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 800x600-85 VESA */
	{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1024x768-60 VESA */
	{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1024x768-75 VESA */
	{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1024x768-85 VESA */
	{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x960-60 VESA */
	{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x960-85 VESA */
	{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x1024-60 VESA */
	{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x1024-75 VESA */
	{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x1024-85 VESA */
	{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1600x1200-60 VESA */
	{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1600x1200-75 VESA */
	{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1600x1200-85 VESA */
	{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};

static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
	if (var->xres > 1600 || var->yres > 1200)
		return -EINVAL;
	if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
		return -EINVAL;

	if (var->bits_per_pixel == 32) {
		var->red.offset   = 16; var->red.length   = 8;
		var->green.offset =  8; var->green.length = 8;
		var->blue.offset  =  0; var->blue.length  = 8;
	} else if (var->bits_per_pixel == 16) {
		var->red.offset   = 11; var->red.length   = 5;
		var->green.offset =  5; var->green.length = 6;
		var->blue.offset  =  0; var->blue.length  = 5;
	} else if (var->bits_per_pixel == 8) {
		var->red.offset   = 0; var->red.length   = 8;
		var->green.offset = 0; var->green.length = 8;
		var->blue.offset  = 0; var->blue.length  = 8;
	} else
		return -EINVAL;
	var->transp.offset = 0; var->transp.length = 0;

	/* Enough video memory? */
	if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
		return -EINVAL;

	/* FIXME: Check timing parameters here? */

	return 0;
}

static int gxfb_set_par(struct fb_info *info)
{
	if (info->var.bits_per_pixel > 8) {
		info->fix.visual = FB_VISUAL_TRUECOLOR;
		fb_dealloc_cmap(&info->cmap);
	} else {
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
		fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
	}

	info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);

	gx_set_mode(info);

	return 0;
}

static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
	chan &= 0xffff;
	chan >>= 16 - bf->length;
	return chan << bf->offset;
}

static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
			   unsigned blue, unsigned transp,
			   struct fb_info *info)
{
	if (info->var.grayscale) {
		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
	}

	/* Truecolor has hardware independent palette */
	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
		u32 *pal = info->pseudo_palette;
		u32 v;

		if (regno >= 16)
			return -EINVAL;

		v  = chan_to_field(red, &info->var.red);
		v |= chan_to_field(green, &info->var.green);
		v |= chan_to_field(blue, &info->var.blue);

		pal[regno] = v;
	} else {
		if (regno >= 256)
			return -EINVAL;

		gx_set_hw_palette_reg(info, regno, red, green, blue);
	}

	return 0;
}

static int gxfb_blank(int blank_mode, struct fb_info *info)
{
	return gx_blank_display(info, blank_mode);
}

static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
	struct gxfb_par *par = info->par;
	int ret;

	ret = pci_enable_device(dev);
	if (ret < 0)
		return ret;

	ret = pci_request_region(dev, 3, "gxfb (video processor)");
	if (ret < 0)
		return ret;
	par->vid_regs = ioremap(pci_resource_start(dev, 3),
				pci_resource_len(dev, 3));
	if (!par->vid_regs)
		return -ENOMEM;

	ret = pci_request_region(dev, 2, "gxfb (display controller)");
	if (ret < 0)
		return ret;
	par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
	if (!par->dc_regs)
		return -ENOMEM;

	ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
	if (ret < 0)
		return ret;

	info->fix.smem_start = pci_resource_start(dev, 0);
	info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
	info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
	if (!info->screen_base)
		return -ENOMEM;

	/* Set the 16MiB aligned base address of the graphics memory region
	 * in the display controller */

	write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);

	dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
		 info->fix.smem_len / 1024, info->fix.smem_start);

	return 0;
}

static struct fb_ops gxfb_ops = {
	.owner		= THIS_MODULE,
	.fb_check_var	= gxfb_check_var,
	.fb_set_par	= gxfb_set_par,
	.fb_setcolreg	= gxfb_setcolreg,
	.fb_blank       = gxfb_blank,
	/* No HW acceleration for now. */
	.fb_fillrect	= cfb_fillrect,
	.fb_copyarea	= cfb_copyarea,
	.fb_imageblit	= cfb_imageblit,
};

static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
{
	struct gxfb_par *par;
	struct fb_info *info;

	/* Alloc enough space for the pseudo palette. */
	info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
			dev);
	if (!info)
		return NULL;

	par = info->par;

	strcpy(info->fix.id, "Geode GX");

	info->fix.type		= FB_TYPE_PACKED_PIXELS;
	info->fix.type_aux	= 0;
	info->fix.xpanstep	= 0;
	info->fix.ypanstep	= 0;
	info->fix.ywrapstep	= 0;
	info->fix.accel		= FB_ACCEL_NONE;

	info->var.nonstd	= 0;
	info->var.activate	= FB_ACTIVATE_NOW;
	info->var.height	= -1;
	info->var.width	= -1;
	info->var.accel_flags = 0;
	info->var.vmode	= FB_VMODE_NONINTERLACED;

	info->fbops		= &gxfb_ops;
	info->flags		= FBINFO_DEFAULT;
	info->node		= -1;

	info->pseudo_palette	= (void *)par + sizeof(struct gxfb_par);

	info->var.grayscale	= 0;

	return info;
}

static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	struct gxfb_par *par;
	struct fb_info *info;
	int ret;
	unsigned long val;

	info = gxfb_init_fbinfo(&pdev->dev);
	if (!info)
		return -ENOMEM;
	par = info->par;

	if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
		dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
		goto err;
	}

	/* Figure out if this is a TFT or CRT part */

	rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);

	if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
		par->enable_crt = 0;
	else
		par->enable_crt = 1;

	ret = fb_find_mode(&info->var, info, mode_option,
			   gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
	if (ret == 0 || ret == 4) {
		dev_err(&pdev->dev, "could not find valid video mode\n");
		ret = -EINVAL;
		goto err;
	}


	/* Clear the frame buffer of garbage. */
        memset_io(info->screen_base, 0, info->fix.smem_len);

	gxfb_check_var(&info->var, info);
	gxfb_set_par(info);

	if (register_framebuffer(info) < 0) {
		ret = -EINVAL;
		goto err;
	}
	pci_set_drvdata(pdev, info);
	printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
	return 0;

  err:
	if (info->screen_base) {
		iounmap(info->screen_base);
		pci_release_region(pdev, 0);
	}
	if (par->vid_regs) {
		iounmap(par->vid_regs);
		pci_release_region(pdev, 3);
	}
	if (par->dc_regs) {
		iounmap(par->dc_regs);
		pci_release_region(pdev, 2);
	}

	if (info)
		framebuffer_release(info);
	return ret;
}

static void gxfb_remove(struct pci_dev *pdev)
{
	struct fb_info *info = pci_get_drvdata(pdev);
	struct gxfb_par *par = info->par;

	unregister_framebuffer(info);

	iounmap((void __iomem *)info->screen_base);
	pci_release_region(pdev, 0);

	iounmap(par->vid_regs);
	pci_release_region(pdev, 3);

	iounmap(par->dc_regs);
	pci_release_region(pdev, 2);

	pci_set_drvdata(pdev, NULL);

	framebuffer_release(info);
}

static struct pci_device_id gxfb_id_table[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
	{ 0, }
};

MODULE_DEVICE_TABLE(pci, gxfb_id_table);

static struct pci_driver gxfb_driver = {
	.name		= "gxfb",
	.id_table	= gxfb_id_table,
	.probe		= gxfb_probe,
	.remove		= gxfb_remove,
};

#ifndef MODULE
static int __init gxfb_setup(char *options)
{

	char *opt;

	if (!options || !*options)
		return 0;

	while ((opt = strsep(&options, ",")) != NULL) {
		if (!*opt)
			continue;

		mode_option = opt;
	}

	return 0;
}
#endif

static int __init gxfb_init(void)
{
#ifndef MODULE
	char *option = NULL;

	if (fb_get_options("gxfb", &option))
		return -ENODEV;

	gxfb_setup(option);
#endif
	return pci_register_driver(&gxfb_driver);
}

static void __exit gxfb_cleanup(void)
{
	pci_unregister_driver(&gxfb_driver);
}

module_init(gxfb_init);
module_exit(gxfb_cleanup);

module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");

module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "video memory size");

MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
MODULE_LICENSE("GPL");
Commit	Line	Data
fc4effc7 DV	1	/*
	2	* Geode GX framebuffer driver.
	3	*
	4	* Copyright (C) 2006 Arcom Control Systems Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	*
	12	* This driver assumes that the BIOS has created a virtual PCI device header
	13	* for the video device. The PCI header is assumed to contain the following
	14	* BARs:
	15	*
	16	* BAR0 - framebuffer memory
	17	* BAR1 - graphics processor registers
	18	* BAR2 - display controller registers
	19	* BAR3 - video processor and flat panel control registers.
	20	*
	21	* 16 MiB of framebuffer memory is assumed to be available.
	22	*/
	23	#include <linux/module.h>
	24	#include <linux/kernel.h>
	25	#include <linux/errno.h>
	26	#include <linux/string.h>
	27	#include <linux/mm.h>
fc4effc7 DV	28	#include <linux/slab.h>
	29	#include <linux/delay.h>
	30	#include <linux/fb.h>
	31	#include <linux/init.h>
	32	#include <linux/pci.h>
32bf87e3	33	#include <asm/geode.h>
fc4effc7	34
ab06aaf6	35	#include "gxfb.h"
fc4effc7	36
16ef9870	37	static char *mode_option;
fa20c8a6	38	static int vram;
fc4effc7 DV	39
fc4effc7 DV	40	/* Modes relevant to the GX (taken from modedb.c) */
16ef9870	41	static const struct fb_videomode gx_modedb[] __initdata = {
fc4effc7 DV	42	/* 640x480-60 VESA */
	43	{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
	44	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	45	/* 640x480-75 VESA */
	46	{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
	47	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	48	/* 640x480-85 VESA */
	49	{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
	50	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	51	/* 800x600-60 VESA */
	52	{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
	53	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	54	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	55	/* 800x600-75 VESA */
	56	{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
	57	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	58	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	59	/* 800x600-85 VESA */
	60	{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
	61	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	62	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	63	/* 1024x768-60 VESA */
	64	{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
	65	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	66	/* 1024x768-75 VESA */
	67	{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
	68	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	69	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	70	/* 1024x768-85 VESA */
	71	{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
	72	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	73	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	74	/* 1280x960-60 VESA */
	75	{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
	76	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	77	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	78	/* 1280x960-85 VESA */
	79	{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
	80	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	81	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	82	/* 1280x1024-60 VESA */
	83	{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
	84	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	85	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	86	/* 1280x1024-75 VESA */
	87	{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
	88	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	89	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	90	/* 1280x1024-85 VESA */
	91	{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
	92	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	93	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	94	/* 1600x1200-60 VESA */
	95	{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
	96	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	97	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	98	/* 1600x1200-75 VESA */
	99	{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
	100	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	101	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	102	/* 1600x1200-85 VESA */
	103	{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
	104	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	105	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
106	};
107
108	static int gxfb_check_var(struct fb_var_screeninfo var, struct fb_info info)
109	{
110	if (var->xres > 1600 \|\| var->yres > 1200)
111	return -EINVAL;
112	if ((var->xres > 1280 \|\| var->yres > 1024) && var->bits_per_pixel > 16)
113	return -EINVAL;
114
115	if (var->bits_per_pixel == 32) {
116	var->red.offset = 16; var->red.length = 8;
117	var->green.offset = 8; var->green.length = 8;
118	var->blue.offset = 0; var->blue.length = 8;
119	} else if (var->bits_per_pixel == 16) {
120	var->red.offset = 11; var->red.length = 5;
121	var->green.offset = 5; var->green.length = 6;
122	var->blue.offset = 0; var->blue.length = 5;
123	} else if (var->bits_per_pixel == 8) {
124	var->red.offset = 0; var->red.length = 8;
125	var->green.offset = 0; var->green.length = 8;
126	var->blue.offset = 0; var->blue.length = 8;
127	} else
128	return -EINVAL;
129	var->transp.offset = 0; var->transp.length = 0;
130
131	/* Enough video memory? */
132	if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
133	return -EINVAL;
134
135	/* FIXME: Check timing parameters here? */
136
137	return 0;
138	}
139
140	static int gxfb_set_par(struct fb_info *info)
141	{
fc4effc7 DV	142	if (info->var.bits_per_pixel > 8) {
	143	info->fix.visual = FB_VISUAL_TRUECOLOR;
	144	fb_dealloc_cmap(&info->cmap);
	145	} else {
	146	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
	147	fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
	148	}
	149
	150	info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
	151
d1b4cc3e	152	gx_set_mode(info);
fc4effc7 DV	153
	154	return 0;
	155	}
	156
	157	static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
	158	{
	159	chan &= 0xffff;
	160	chan >>= 16 - bf->length;
	161	return chan << bf->offset;
	162	}
	163
	164	static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
	165	unsigned blue, unsigned transp,
	166	struct fb_info *info)
	167	{
fc4effc7 DV	168	if (info->var.grayscale) {
	169	/* grayscale = 0.30R + 0.59G + 0.11B /
	170	red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
	171	}
	172
	173	/* Truecolor has hardware independent palette */
	174	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
	175	u32 *pal = info->pseudo_palette;
	176	u32 v;
	177
	178	if (regno >= 16)
	179	return -EINVAL;
	180
	181	v = chan_to_field(red, &info->var.red);
	182	v \|= chan_to_field(green, &info->var.green);
	183	v \|= chan_to_field(blue, &info->var.blue);
	184
	185	pal[regno] = v;
	186	} else {
	187	if (regno >= 256)
	188	return -EINVAL;
	189
d1b4cc3e	190	gx_set_hw_palette_reg(info, regno, red, green, blue);
fc4effc7 DV	191	}
	192
	193	return 0;
	194	}
	195
	196	static int gxfb_blank(int blank_mode, struct fb_info *info)
	197	{
d1b4cc3e	198	return gx_blank_display(info, blank_mode);
fc4effc7 DV	199	}
	200
	201	static int __init gxfb_map_video_memory(struct fb_info info, struct pci_dev dev)
	202	{
d1b4cc3e	203	struct gxfb_par *par = info->par;
fc4effc7 DV	204	int ret;
	205
	206	ret = pci_enable_device(dev);
	207	if (ret < 0)
	208	return ret;
	209
	210	ret = pci_request_region(dev, 3, "gxfb (video processor)");
	211	if (ret < 0)
	212	return ret;
	213	par->vid_regs = ioremap(pci_resource_start(dev, 3),
	214	pci_resource_len(dev, 3));
	215	if (!par->vid_regs)
	216	return -ENOMEM;
	217
	218	ret = pci_request_region(dev, 2, "gxfb (display controller)");
	219	if (ret < 0)
	220	return ret;
	221	par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
	222	if (!par->dc_regs)
	223	return -ENOMEM;
	224
	225	ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
	226	if (ret < 0)
	227	return ret;
fa20c8a6	228
fc4effc7	229	info->fix.smem_start = pci_resource_start(dev, 0);
fa20c8a6	230	info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
fc4effc7 DV	231	info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
	232	if (!info->screen_base)
	233	return -ENOMEM;
	234
fa20c8a6	235	/* Set the 16MiB aligned base address of the graphics memory region
f378819a JC	236	* in the display controller */
f378819a JC	237
ab06aaf6	238	write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
f378819a	239
fa20c8a6	240	dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
fc4effc7 DV	241	info->fix.smem_len / 1024, info->fix.smem_start);
	242
	243	return 0;
	244	}
	245
	246	static struct fb_ops gxfb_ops = {
	247	.owner = THIS_MODULE,
	248	.fb_check_var = gxfb_check_var,
	249	.fb_set_par = gxfb_set_par,
	250	.fb_setcolreg = gxfb_setcolreg,
	251	.fb_blank = gxfb_blank,
	252	/* No HW acceleration for now. */
	253	.fb_fillrect = cfb_fillrect,
	254	.fb_copyarea = cfb_copyarea,
	255	.fb_imageblit = cfb_imageblit,
	256	};
	257
	258	static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
	259	{
d1b4cc3e	260	struct gxfb_par *par;
fc4effc7 DV	261	struct fb_info *info;
	262
	263	/* Alloc enough space for the pseudo palette. */
d1b4cc3e AS	264	info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
d1b4cc3e AS	265	dev);
fc4effc7 DV	266	if (!info)
	267	return NULL;
	268
	269	par = info->par;
	270
	271	strcpy(info->fix.id, "Geode GX");
	272
	273	info->fix.type = FB_TYPE_PACKED_PIXELS;
	274	info->fix.type_aux = 0;
	275	info->fix.xpanstep = 0;
	276	info->fix.ypanstep = 0;
	277	info->fix.ywrapstep = 0;
	278	info->fix.accel = FB_ACCEL_NONE;
	279
	280	info->var.nonstd = 0;
	281	info->var.activate = FB_ACTIVATE_NOW;
	282	info->var.height = -1;
	283	info->var.width = -1;
	284	info->var.accel_flags = 0;
	285	info->var.vmode = FB_VMODE_NONINTERLACED;
	286
	287	info->fbops = &gxfb_ops;
	288	info->flags = FBINFO_DEFAULT;
	289	info->node = -1;
	290
d1b4cc3e	291	info->pseudo_palette = (void *)par + sizeof(struct gxfb_par);
fc4effc7 DV	292
	293	info->var.grayscale = 0;
	294
	295	return info;
	296	}
	297
	298	static int __init gxfb_probe(struct pci_dev pdev, const struct pci_device_id id)
	299	{
d1b4cc3e	300	struct gxfb_par *par;
fc4effc7 DV	301	struct fb_info *info;
fc4effc7 DV	302	int ret;
ab1db0cf	303	unsigned long val;
fc4effc7 DV	304
	305	info = gxfb_init_fbinfo(&pdev->dev);
	306	if (!info)
	307	return -ENOMEM;
	308	par = info->par;
	309
fc4effc7 DV	310	if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
	311	dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
	312	goto err;
	313	}
	314
ab1db0cf JC	315	/* Figure out if this is a TFT or CRT part */
ab1db0cf JC	316
32bf87e3	317	rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);
ab1db0cf	318
9f1277bd	319	if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
ab1db0cf JC	320	par->enable_crt = 0;
	321	else
	322	par->enable_crt = 1;
	323
fc4effc7 DV	324	ret = fb_find_mode(&info->var, info, mode_option,
	325	gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
	326	if (ret == 0 \|\| ret == 4) {
	327	dev_err(&pdev->dev, "could not find valid video mode\n");
	328	ret = -EINVAL;
	329	goto err;
	330	}
	331
16ef9870 JC	332
16ef9870 JC	333	/* Clear the frame buffer of garbage. */
fc4effc7 DV	334	memset_io(info->screen_base, 0, info->fix.smem_len);
	335
	336	gxfb_check_var(&info->var, info);
	337	gxfb_set_par(info);
	338
	339	if (register_framebuffer(info) < 0) {
	340	ret = -EINVAL;
	341	goto err;
	342	}
	343	pci_set_drvdata(pdev, info);
	344	printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
	345	return 0;
	346
	347	err:
	348	if (info->screen_base) {
	349	iounmap(info->screen_base);
	350	pci_release_region(pdev, 0);
	351	}
	352	if (par->vid_regs) {
	353	iounmap(par->vid_regs);
	354	pci_release_region(pdev, 3);
	355	}
	356	if (par->dc_regs) {
	357	iounmap(par->dc_regs);
	358	pci_release_region(pdev, 2);
	359	}
	360
fc4effc7 DV	361	if (info)
	362	framebuffer_release(info);
	363	return ret;
	364	}
	365
	366	static void gxfb_remove(struct pci_dev *pdev)
	367	{
	368	struct fb_info *info = pci_get_drvdata(pdev);
d1b4cc3e	369	struct gxfb_par *par = info->par;
fc4effc7 DV	370
	371	unregister_framebuffer(info);
	372
	373	iounmap((void __iomem *)info->screen_base);
	374	pci_release_region(pdev, 0);
	375
	376	iounmap(par->vid_regs);
	377	pci_release_region(pdev, 3);
	378
	379	iounmap(par->dc_regs);
	380	pci_release_region(pdev, 2);
	381
fc4effc7 DV	382	pci_set_drvdata(pdev, NULL);
	383
	384	framebuffer_release(info);
	385	}
	386
	387	static struct pci_device_id gxfb_id_table[] = {
0a5e7909	388	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
fc4effc7 DV	389	{ 0, }
	390	};
	391
	392	MODULE_DEVICE_TABLE(pci, gxfb_id_table);
	393
	394	static struct pci_driver gxfb_driver = {
	395	.name = "gxfb",
	396	.id_table = gxfb_id_table,
	397	.probe = gxfb_probe,
	398	.remove = gxfb_remove,
	399	};
	400
16ef9870 JC	401	#ifndef MODULE
	402	static int __init gxfb_setup(char *options)
	403	{
	404
	405	char *opt;
	406
	407	if (!options \|\| !*options)
	408	return 0;
	409
	410	while ((opt = strsep(&options, ",")) != NULL) {
	411	if (!*opt)
	412	continue;
	413
	414	mode_option = opt;
	415	}
	416
	417	return 0;
	418	}
	419	#endif
	420
fc4effc7 DV	421	static int __init gxfb_init(void)
	422	{
	423	#ifndef MODULE
16ef9870 JC	424	char *option = NULL;
	425
	426	if (fb_get_options("gxfb", &option))
fc4effc7	427	return -ENODEV;
16ef9870 JC	428
16ef9870 JC	429	gxfb_setup(option);
fc4effc7 DV	430	#endif
	431	return pci_register_driver(&gxfb_driver);
	432	}
	433
	434	static void __exit gxfb_cleanup(void)
	435	{
	436	pci_unregister_driver(&gxfb_driver);
	437	}
	438
	439	module_init(gxfb_init);
	440	module_exit(gxfb_cleanup);
	441
16ef9870 JC	442	module_param(mode_option, charp, 0);
16ef9870 JC	443	MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
fc4effc7	444
fa20c8a6 AS	445	module_param(vram, int, 0);
	446	MODULE_PARM_DESC(vram, "video memory size");
	447
fc4effc7 DV	448	MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
fc4effc7 DV	449	MODULE_LICENSE("GPL");