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ab06aaf6 AS |
1 | /* |
2 | * Copyright (C) 2008 Andres Salomon <dilinger@debian.org> | |
3 | * | |
4 | * Geode GX2 register tables | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | #ifndef _GXFB_H_ | |
12 | #define _GXFB_H_ | |
13 | ||
14 | #include <linux/io.h> | |
15 | ||
d255114f AS |
16 | /* Display Controller registers (table 6-38 from the data book) */ |
17 | enum dc_registers { | |
18 | DC_UNLOCK = 0, | |
19 | DC_GENERAL_CFG, | |
20 | DC_DISPLAY_CFG, | |
21 | DC_RSVD_0, | |
22 | ||
23 | DC_FB_ST_OFFSET, | |
24 | DC_CB_ST_OFFSET, | |
25 | DC_CURS_ST_OFFSET, | |
26 | DC_ICON_ST_OFFSET, | |
27 | ||
28 | DC_VID_Y_ST_OFFSET, | |
29 | DC_VID_U_ST_OFFSET, | |
30 | DC_VID_V_ST_OFFSET, | |
31 | DC_RSVD_1, | |
32 | ||
33 | DC_LINE_SIZE, | |
34 | DC_GFX_PITCH, | |
35 | DC_VID_YUV_PITCH, | |
36 | DC_RSVD_2, | |
37 | ||
38 | DC_H_ACTIVE_TIMING, | |
39 | DC_H_BLANK_TIMING, | |
40 | DC_H_SYNC_TIMING, | |
41 | DC_RSVD_3, | |
42 | ||
43 | DC_V_ACTIVE_TIMING, | |
44 | DC_V_BLANK_TIMING, | |
45 | DC_V_SYNC_TIMING, | |
46 | DC_RSVD_4, | |
47 | ||
48 | DC_CURSOR_X, | |
49 | DC_CURSOR_Y, | |
50 | DC_ICON_X, | |
51 | DC_LINE_CNT, | |
52 | ||
53 | DC_PAL_ADDRESS, | |
54 | DC_PAL_DATA, | |
55 | DC_DFIFO_DIAG, | |
56 | DC_CFIFO_DIAG, | |
57 | ||
58 | DC_VID_DS_DELTA, | |
59 | DC_GLIU0_MEM_OFFSET, | |
60 | DC_RSVD_5, | |
61 | DC_DV_ACC, /* 0x8c */ | |
62 | }; | |
63 | ||
64 | #define DC_UNLOCK_LOCK 0x00000000 | |
65 | #define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */ | |
66 | ||
67 | #define DC_GENERAL_CFG_YUVM (1 << 20) | |
68 | #define DC_GENERAL_CFG_VDSE (1 << 19) | |
69 | #define DC_GENERAL_CFG_DFHPEL_SHIFT 12 | |
70 | #define DC_GENERAL_CFG_DFHPSL_SHIFT 8 | |
71 | #define DC_GENERAL_CFG_DECE (1 << 6) | |
72 | #define DC_GENERAL_CFG_CMPE (1 << 5) | |
73 | #define DC_GENERAL_CFG_VIDE (1 << 3) | |
74 | #define DC_GENERAL_CFG_ICNE (1 << 2) | |
75 | #define DC_GENERAL_CFG_CURE (1 << 1) | |
76 | #define DC_GENERAL_CFG_DFLE (1 << 0) | |
77 | ||
78 | #define DC_DISPLAY_CFG_A20M (1 << 31) | |
79 | #define DC_DISPLAY_CFG_A18M (1 << 30) | |
80 | #define DC_DISPLAY_CFG_PALB (1 << 25) | |
81 | #define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9) | |
82 | #define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8) | |
83 | #define DC_DISPLAY_CFG_DISP_MODE_8BPP (0) | |
84 | #define DC_DISPLAY_CFG_VDEN (1 << 4) | |
85 | #define DC_DISPLAY_CFG_GDEN (1 << 3) | |
86 | #define DC_DISPLAY_CFG_TGEN (1 << 0) | |
87 | ||
88 | ||
89 | /* | |
90 | * Video Processor registers (table 6-54). | |
91 | * There is space for 64 bit values, but we never use more than the | |
92 | * lower 32 bits. The actual register save/restore code only bothers | |
93 | * to restore those 32 bits. | |
94 | */ | |
95 | enum vp_registers { | |
96 | VP_VCFG = 0, | |
97 | VP_DCFG, | |
98 | ||
99 | VP_VX, | |
100 | VP_VY, | |
101 | ||
102 | VP_VS, | |
103 | VP_VCK, | |
104 | ||
105 | VP_VCM, | |
106 | VP_GAR, | |
107 | ||
108 | VP_GDR, | |
109 | VP_RSVD_0, | |
110 | ||
111 | VP_MISC, | |
112 | VP_CCS, | |
113 | ||
114 | VP_RSVD_1, | |
115 | VP_RSVD_2, | |
116 | ||
117 | VP_RSVD_3, | |
118 | VP_VDC, | |
119 | ||
120 | VP_VCO, | |
121 | VP_CRC, | |
122 | ||
123 | VP_CRC32, | |
124 | VP_VDE, | |
125 | ||
126 | VP_CCK, | |
127 | VP_CCM, | |
128 | ||
129 | VP_CC1, | |
130 | VP_CC2, | |
131 | ||
132 | VP_A1X, | |
133 | VP_A1Y, | |
134 | ||
135 | VP_A1C, | |
136 | VP_A1T, | |
137 | ||
138 | VP_A2X, | |
139 | VP_A2Y, | |
140 | ||
141 | VP_A2C, | |
142 | VP_A2T, | |
143 | ||
144 | VP_A3X, | |
145 | VP_A3Y, | |
146 | ||
147 | VP_A3C, | |
148 | VP_A3T, | |
149 | ||
150 | VP_VRR, | |
151 | VP_AWT, | |
152 | ||
153 | VP_VTM, /* 0x130 */ | |
154 | }; | |
155 | ||
156 | #define VP_VCFG_VID_EN (1 << 0) | |
157 | ||
158 | #define VP_DCFG_DAC_VREF (1 << 26) | |
159 | #define VP_DCFG_GV_GAM (1 << 21) | |
160 | #define VP_DCFG_VG_CK (1 << 20) | |
161 | #define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16) | |
162 | #define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16)) | |
163 | #define VP_DCFG_CRT_VSYNC_POL (1 << 9) | |
164 | #define VP_DCFG_CRT_HSYNC_POL (1 << 8) | |
165 | #define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */ | |
166 | #define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */ | |
167 | #define VP_DCFG_DAC_BL_EN (1 << 3) | |
168 | #define VP_DCFG_VSYNC_EN (1 << 2) | |
169 | #define VP_DCFG_HSYNC_EN (1 << 1) | |
170 | #define VP_DCFG_CRT_EN (1 << 0) | |
171 | ||
172 | #define VP_MISC_GAM_EN (1 << 0) | |
173 | #define VP_MISC_DACPWRDN (1 << 10) | |
174 | #define VP_MISC_APWRDN (1 << 11) | |
175 | ||
176 | ||
177 | /* | |
178 | * Flat Panel registers (table 6-55). | |
179 | * Also 64 bit registers; see above note about 32-bit handling. | |
180 | */ | |
181 | ||
182 | /* we're actually in the VP register space, starting at address 0x400 */ | |
183 | #define VP_FP_START 0x400 | |
184 | ||
185 | enum fp_registers { | |
186 | FP_PT1 = 0, | |
187 | FP_PT2, | |
188 | ||
189 | FP_PM, | |
190 | FP_DFC, | |
191 | ||
192 | FP_BLFSR, | |
193 | FP_RLFSR, | |
194 | ||
195 | FP_FMI, | |
196 | FP_FMD, | |
197 | ||
198 | FP_RSVD_0, | |
199 | FP_DCA, | |
200 | ||
201 | FP_DMD, | |
202 | FP_CRC, | |
203 | ||
204 | FP_FBB, /* 0x460 */ | |
205 | }; | |
206 | ||
207 | #define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */ | |
208 | #define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */ | |
209 | ||
210 | #define FP_PT2_HSP (1 << 22) | |
211 | #define FP_PT2_VSP (1 << 23) | |
212 | ||
213 | #define FP_PM_P (1 << 24) /* panel power on */ | |
214 | #define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */ | |
215 | #define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */ | |
216 | #define FP_PM_PANEL_OFF (1 << 1) /* r/o */ | |
217 | #define FP_PM_PANEL_ON (1 << 0) /* r/o */ | |
218 | ||
219 | #define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6)) | |
220 | ||
221 | ||
222 | /* register access functions */ | |
223 | ||
ab06aaf6 AS |
224 | static inline uint32_t read_dc(struct geodefb_par *par, int reg) |
225 | { | |
d255114f | 226 | return readl(par->dc_regs + 4*reg); |
ab06aaf6 AS |
227 | } |
228 | ||
229 | static inline void write_dc(struct geodefb_par *par, int reg, uint32_t val) | |
230 | { | |
d255114f | 231 | writel(val, par->dc_regs + 4*reg); |
ab06aaf6 AS |
232 | } |
233 | ||
d255114f | 234 | |
ab06aaf6 AS |
235 | static inline uint32_t read_vp(struct geodefb_par *par, int reg) |
236 | { | |
d255114f | 237 | return readl(par->vid_regs + 8*reg); |
ab06aaf6 AS |
238 | } |
239 | ||
240 | static inline void write_vp(struct geodefb_par *par, int reg, uint32_t val) | |
241 | { | |
d255114f | 242 | writel(val, par->vid_regs + 8*reg); |
ab06aaf6 AS |
243 | } |
244 | ||
245 | static inline uint32_t read_fp(struct geodefb_par *par, int reg) | |
246 | { | |
d255114f | 247 | return readl(par->vid_regs + 8*reg + VP_FP_START); |
ab06aaf6 AS |
248 | } |
249 | ||
250 | static inline void write_fp(struct geodefb_par *par, int reg, uint32_t val) | |
251 | { | |
d255114f | 252 | writel(val, par->vid_regs + 8*reg + VP_FP_START); |
ab06aaf6 AS |
253 | } |
254 | ||
9f1277bd AS |
255 | |
256 | /* MSRs are defined in asm/geode.h; their bitfields are here */ | |
257 | ||
258 | #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3) | |
259 | #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2) | |
260 | #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (1 << 1) | |
261 | ||
262 | #define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */ | |
263 | #define MSR_GLCP_DOTPLL_BYPASS (1 << 15) | |
264 | #define MSR_GLCP_DOTPLL_DOTRESET (1 << 0) | |
265 | ||
266 | #define MSR_GX_MSR_PADSEL_MASK 0x3FFFFFFF /* undocumented? */ | |
267 | #define MSR_GX_MSR_PADSEL_TFT 0x1FFFFFFF /* undocumented? */ | |
268 | ||
269 | #define MSR_GX_GLD_MSR_CONFIG_FP (1 << 3) | |
270 | ||
ab06aaf6 | 271 | #endif |