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[net-next-2.6.git] / drivers / video / bfin-lq035q1-fb.c
CommitLineData
9cfe4a93
MH		 1/*
2 * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
3 *
4 * Copyright 2008-2009 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
6 */
7
8#define DRIVER_NAME "bfin-lq035q1"
9#define pr_fmt(fmt) DRIVER_NAME ": " fmt
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/fb.h>
5a0e3ad6 16#include <linux/slab.h>
9cfe4a93
MH		 17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/device.h>
21#include <linux/backlight.h>
22#include <linux/lcd.h>
23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
9cfe4a93
MH		 26
27#include <asm/blackfin.h>
28#include <asm/irq.h>
29#include <asm/dma.h>
30#include <asm/portmux.h>
31#include <asm/gptimers.h>
32
33#include <asm/bfin-lq035q1.h>
34
35#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
36#define TIMER_HSYNC_id TIMER1_id
37#define TIMER_HSYNCbit TIMER1bit
38#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
39#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
40#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
41
42#define TIMER_VSYNC_id TIMER2_id
43#define TIMER_VSYNCbit TIMER2bit
44#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2
45#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2
46#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2
47#else
48#define TIMER_HSYNC_id TIMER0_id
49#define TIMER_HSYNCbit TIMER0bit
50#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0
51#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0
52#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0
53
54#define TIMER_VSYNC_id TIMER1_id
55#define TIMER_VSYNCbit TIMER1bit
56#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
57#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
58#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
59#endif
60
61#define LCD_X_RES 320 /* Horizontal Resolution */
62#define LCD_Y_RES 240 /* Vertical Resolution */
63#define DMA_BUS_SIZE 16
fbd65e0e 64#define U_LINE 4 /* Blanking Lines */
9cfe4a93 65
9cfe4a93
MH		 66
67/* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD)
68 * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
69 */
70
9cfe4a93
MH		 71
72#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
73
74#define PPI_TX_MODE 0x2
75#define PPI_XFER_TYPE_11 0xC
76#define PPI_PORT_CFG_01 0x10
77#define PPI_POLS_1 0x8000
78
9cfe4a93
MH		 79#define LQ035_INDEX 0x74
80#define LQ035_DATA 0x76
81
82#define LQ035_DRIVER_OUTPUT_CTL 0x1
83#define LQ035_SHUT_CTL 0x11
84
85#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
86#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
87
88#define LQ035_SHUT (1 << 0) /* Shutdown */
89#define LQ035_ON (0 << 0) /* Shutdown */
90
91struct bfin_lq035q1fb_info {
92 struct fb_info *fb;
93 struct device *dev;
94 struct spi_driver spidrv;
95 struct bfin_lq035q1fb_disp_info *disp_info;
96 unsigned char *fb_buffer; /* RGB Buffer */
97 dma_addr_t dma_handle;
98 int lq035_open_cnt;
99 int irq;
100 spinlock_t lock; /* lock */
101 u32 pseudo_pal[16];
fbd65e0e
MH		 102
103 u32 lcd_bpp;
104 u32 h_actpix;
105 u32 h_period;
106 u32 h_pulse;
107 u32 h_start;
108 u32 v_lines;
109 u32 v_pulse;
110 u32 v_period;
9cfe4a93
MH		 111};
112
113static int nocursor;
114module_param(nocursor, int, 0644);
115MODULE_PARM_DESC(nocursor, "cursor enable/disable");
116
117struct spi_control {
118 unsigned short mode;
119};
120
121static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value)
122{
123 int ret;
124 u8 regs[3] = { LQ035_INDEX, 0, 0 };
125 u8 dat[3] = { LQ035_DATA, 0, 0 };
126
127 if (!spi)
128 return -ENODEV;
129
130 regs[2] = reg;
131 dat[1] = value >> 8;
132 dat[2] = value & 0xFF;
133
134 ret = spi_write(spi, regs, ARRAY_SIZE(regs));
135 ret |= spi_write(spi, dat, ARRAY_SIZE(dat));
136 return ret;
137}
138
139static int __devinit lq035q1_spidev_probe(struct spi_device *spi)
140{
141 int ret;
142 struct spi_control *ctl;
143 struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver,
144 struct bfin_lq035q1fb_info,
145 spidrv.driver);
146
147 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
148
149 if (!ctl)
150 return -ENOMEM;
151
152 ctl->mode = (info->disp_info->mode &
153 LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT;
154
155 ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
156 ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
157 if (ret)
158 return ret;
159
160 spi_set_drvdata(spi, ctl);
161
162 return 0;
163}
164
165static int lq035q1_spidev_remove(struct spi_device *spi)
166{
167 return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
168}
169
170#ifdef CONFIG_PM
171static int lq035q1_spidev_suspend(struct spi_device *spi, pm_message_t state)
172{
173 return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
174}
175
176static int lq035q1_spidev_resume(struct spi_device *spi)
177{
178 int ret;
179 struct spi_control *ctl = spi_get_drvdata(spi);
180
181 ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
182 if (ret)
183 return ret;
184
185 return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
186}
187#else
188# define lq035q1_spidev_suspend NULL
189# define lq035q1_spidev_resume NULL
190#endif
191
192/* Power down all displays on reboot, poweroff or halt */
193static void lq035q1_spidev_shutdown(struct spi_device *spi)
194{
195 lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
196}
197
198static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg)
199{
200 if (info->disp_info->use_bl)
201 gpio_set_value(info->disp_info->gpio_bl, arg);
202
203 return 0;
204}
205
fbd65e0e
MH		 206static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi)
207{
208 unsigned long clocks_per_pix, cpld_pipeline_delay_cor;
209
210 /*
211 * Interface 16/18-bit TFT over an 8-bit wide PPI using a small
212 * Programmable Logic Device (CPLD)
213 * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
214 */
215
216 switch (fbi->disp_info->ppi_mode) {
217 case USE_RGB565_16_BIT_PPI:
218 fbi->lcd_bpp = 16;
219 clocks_per_pix = 1;
220 cpld_pipeline_delay_cor = 0;
221 break;
222 case USE_RGB565_8_BIT_PPI:
223 fbi->lcd_bpp = 16;
224 clocks_per_pix = 2;
225 cpld_pipeline_delay_cor = 3;
226 break;
227 case USE_RGB888_8_BIT_PPI:
228 fbi->lcd_bpp = 24;
229 clocks_per_pix = 3;
230 cpld_pipeline_delay_cor = 5;
231 break;
232 default:
233 return -EINVAL;
234 }
235
236 /*
237 * HS and VS timing parameters (all in number of PPI clk ticks)
238 */
239
240 fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */
241 fbi->h_period = (336 * clocks_per_pix); /* HS period */
242 fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */
243 fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */
244
245 fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */
246 fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */
247 fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */
248
249 return 0;
250}
251
9cfe4a93
MH		 252static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi)
253{
fbd65e0e
MH		 254 unsigned ppi_pmode;
255
256 if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI)
257 ppi_pmode = DLEN_16;
258 else
259 ppi_pmode = (DLEN_8 | PACK_EN);
260
261 bfin_write_PPI_DELAY(fbi->h_start);
262 bfin_write_PPI_COUNT(fbi->h_actpix - 1);
263 bfin_write_PPI_FRAME(fbi->v_lines);
9cfe4a93
MH		 264
265 bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
266 PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
267 PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
fbd65e0e 268 ppi_pmode | /* 8/16 bit data length / PACK_EN? */
9cfe4a93
MH		 269 PPI_POLS_1); /* faling edge syncs POLS */
270}
271
272static inline void bfin_lq035q1_disable_ppi(void)
273{
274 bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
275}
276
277static inline void bfin_lq035q1_enable_ppi(void)
278{
279 bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
280}
281
282static void bfin_lq035q1_start_timers(void)
283{
284 enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit);
285}
286
287static void bfin_lq035q1_stop_timers(void)
288{
289 disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit);
290
291 set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN |
292 TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL |
293 TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF);
294
295}
296
fbd65e0e 297static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi)
9cfe4a93
MH		 298{
299
300 bfin_lq035q1_stop_timers();
301
fbd65e0e
MH		 302 set_gptimer_period(TIMER_HSYNC_id, fbi->h_period);
303 set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse);
9cfe4a93
MH		 304 set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
305 TIMER_TIN_SEL | TIMER_CLK_SEL|
306 TIMER_EMU_RUN);
307
fbd65e0e
MH		 308 set_gptimer_period(TIMER_VSYNC_id, fbi->v_period);
309 set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse);
9cfe4a93
MH		 310 set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
311 TIMER_TIN_SEL | TIMER_CLK_SEL |
312 TIMER_EMU_RUN);
313
314}
315
316static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi)
317{
318
fbd65e0e 319
9cfe4a93
MH		 320 set_dma_config(CH_PPI,
321 set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
322 INTR_DISABLE, DIMENSION_2D,
323 DATA_SIZE_16,
324 DMA_NOSYNC_KEEP_DMA_BUF));
fbd65e0e 325 set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE);
9cfe4a93 326 set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
fbd65e0e 327 set_dma_y_count(CH_PPI, fbi->v_lines);
9cfe4a93
MH		 328
329 set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
330 set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
331
332}
333
9cfe4a93
MH		 334static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
335 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
336 P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
337 P_PPI0_D6, P_PPI0_D7, P_PPI0_D8,
338 P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
339 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
340 P_PPI0_D15, 0};
fbd65e0e
MH		 341
342static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
9cfe4a93
MH		 343 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
344 P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
345 P_PPI0_D6, P_PPI0_D7, 0};
9cfe4a93 346
fbd65e0e 347static inline void bfin_lq035q1_free_ports(unsigned ppi16)
9cfe4a93 348{
fbd65e0e
MH		 349 if (ppi16)
350 peripheral_free_list(ppi0_req_16);
351 else
352 peripheral_free_list(ppi0_req_8);
353
9cfe4a93
MH		 354 if (ANOMALY_05000400)
355 gpio_free(P_IDENT(P_PPI0_FS3));
356}
357
fbd65e0e
MH		 358static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev,
359 unsigned ppi16)
9cfe4a93 360{
fbd65e0e 361 int ret;
9cfe4a93
MH		 362 /* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode:
363 * Drive PPI_FS3 Low
364 */
365 if (ANOMALY_05000400) {
366 int ret = gpio_request(P_IDENT(P_PPI0_FS3), "PPI_FS3");
367 if (ret)
368 return ret;
369 gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
370 }
371
fbd65e0e
MH		 372 if (ppi16)
373 ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME);
374 else
375 ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME);
376
377 if (ret) {
9cfe4a93
MH		 378 dev_err(&pdev->dev, "requesting peripherals failed\n");
379 return -EFAULT;
380 }
381
382 return 0;
383}
384
385static int bfin_lq035q1_fb_open(struct fb_info *info, int user)
386{
387 struct bfin_lq035q1fb_info *fbi = info->par;
388
389 spin_lock(&fbi->lock);
390 fbi->lq035_open_cnt++;
391
392 if (fbi->lq035_open_cnt <= 1) {
393
394 bfin_lq035q1_disable_ppi();
395 SSYNC();
396
397 bfin_lq035q1_config_dma(fbi);
398 bfin_lq035q1_config_ppi(fbi);
fbd65e0e 399 bfin_lq035q1_init_timers(fbi);
9cfe4a93
MH		 400
401 /* start dma */
402 enable_dma(CH_PPI);
403 bfin_lq035q1_enable_ppi();
404 bfin_lq035q1_start_timers();
405 lq035q1_backlight(fbi, 1);
406 }
407
408 spin_unlock(&fbi->lock);
409
410 return 0;
411}
412
413static int bfin_lq035q1_fb_release(struct fb_info *info, int user)
414{
415 struct bfin_lq035q1fb_info *fbi = info->par;
416
417 spin_lock(&fbi->lock);
418
419 fbi->lq035_open_cnt--;
420
421 if (fbi->lq035_open_cnt <= 0) {
422 lq035q1_backlight(fbi, 0);
423 bfin_lq035q1_disable_ppi();
424 SSYNC();
425 disable_dma(CH_PPI);
426 bfin_lq035q1_stop_timers();
427 }
428
429 spin_unlock(&fbi->lock);
430
431 return 0;
432}
433
434static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var,
435 struct fb_info *info)
436{
fbd65e0e
MH		 437 struct bfin_lq035q1fb_info *fbi = info->par;
438
439 if (var->bits_per_pixel == fbi->lcd_bpp) {
9cfe4a93
MH		 440 var->red.offset = info->var.red.offset;
441 var->green.offset = info->var.green.offset;
442 var->blue.offset = info->var.blue.offset;
443 var->red.length = info->var.red.length;
444 var->green.length = info->var.green.length;
445 var->blue.length = info->var.blue.length;
446 var->transp.offset = 0;
447 var->transp.length = 0;
448 var->transp.msb_right = 0;
449 var->red.msb_right = 0;
450 var->green.msb_right = 0;
451 var->blue.msb_right = 0;
fbd65e0e 452 } else {
9cfe4a93
MH		 453 pr_debug("%s: depth not supported: %u BPP\n", __func__,
454 var->bits_per_pixel);
455 return -EINVAL;
456 }
457
458 if (info->var.xres != var->xres || info->var.yres != var->yres ||
459 info->var.xres_virtual != var->xres_virtual ||
460 info->var.yres_virtual != var->yres_virtual) {
461 pr_debug("%s: Resolution not supported: X%u x Y%u \n",
462 __func__, var->xres, var->yres);
463 return -EINVAL;
464 }
465
466 /*
467 * Memory limit
468 */
469
470 if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
471 pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
472 __func__, var->yres_virtual);
473 return -ENOMEM;
474 }
475
476
477 return 0;
478}
479
480int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
481{
482 if (nocursor)
483 return 0;
484 else
485 return -EINVAL; /* just to force soft_cursor() call */
486}
487
488static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green,
489 u_int blue, u_int transp,
490 struct fb_info *info)
491{
492 if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
493 return -EINVAL;
494
495 if (info->var.grayscale) {
496 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
497 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
498 }
499
500 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
501
502 u32 value;
503 /* Place color in the pseudopalette */
504 if (regno > 16)
505 return -EINVAL;
506
507 red >>= (16 - info->var.red.length);
508 green >>= (16 - info->var.green.length);
509 blue >>= (16 - info->var.blue.length);
510
511 value = (red << info->var.red.offset) |
512 (green << info->var.green.offset) |
513 (blue << info->var.blue.offset);
514 value &= 0xFFFFFF;
515
516 ((u32 *) (info->pseudo_palette))[regno] = value;
517
518 }
519
520 return 0;
521}
522
523static struct fb_ops bfin_lq035q1_fb_ops = {
524 .owner = THIS_MODULE,
525 .fb_open = bfin_lq035q1_fb_open,
526 .fb_release = bfin_lq035q1_fb_release,
527 .fb_check_var = bfin_lq035q1_fb_check_var,
528 .fb_fillrect = cfb_fillrect,
529 .fb_copyarea = cfb_copyarea,
530 .fb_imageblit = cfb_imageblit,
531 .fb_cursor = bfin_lq035q1_fb_cursor,
532 .fb_setcolreg = bfin_lq035q1_fb_setcolreg,
533};
534
535static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id)
536{
537 /*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/
538
539 u16 status = bfin_read_PPI_STATUS();
540 bfin_write_PPI_STATUS(-1);
541
542 if (status) {
543 bfin_lq035q1_disable_ppi();
544 disable_dma(CH_PPI);
545
546 /* start dma */
547 enable_dma(CH_PPI);
548 bfin_lq035q1_enable_ppi();
549 bfin_write_PPI_STATUS(-1);
550 }
551
552 return IRQ_HANDLED;
553}
554
555static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
556{
557 struct bfin_lq035q1fb_info *info;
558 struct fb_info *fbinfo;
fbd65e0e 559 u32 active_video_mem_offset;
9cfe4a93
MH		 560 int ret;
561
562 ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI");
563 if (ret < 0) {
564 dev_err(&pdev->dev, "PPI DMA unavailable\n");
565 goto out1;
566 }
567
568 fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev);
569 if (!fbinfo) {
570 ret = -ENOMEM;
571 goto out2;
572 }
573
574 info = fbinfo->par;
575 info->fb = fbinfo;
576 info->dev = &pdev->dev;
577
578 info->disp_info = pdev->dev.platform_data;
579
580 platform_set_drvdata(pdev, fbinfo);
581
fbd65e0e
MH		 582 ret = bfin_lq035q1_calc_timing(info);
583 if (ret < 0) {
584 dev_err(&pdev->dev, "Failed PPI Mode\n");
585 goto out3;
586 }
587
9cfe4a93
MH		 588 strcpy(fbinfo->fix.id, DRIVER_NAME);
589
590 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
591 fbinfo->fix.type_aux = 0;
592 fbinfo->fix.xpanstep = 0;
593 fbinfo->fix.ypanstep = 0;
594 fbinfo->fix.ywrapstep = 0;
595 fbinfo->fix.accel = FB_ACCEL_NONE;
596 fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
597
598 fbinfo->var.nonstd = 0;
599 fbinfo->var.activate = FB_ACTIVATE_NOW;
600 fbinfo->var.height = -1;
601 fbinfo->var.width = -1;
602 fbinfo->var.accel_flags = 0;
603 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
604
605 fbinfo->var.xres = LCD_X_RES;
606 fbinfo->var.xres_virtual = LCD_X_RES;
607 fbinfo->var.yres = LCD_Y_RES;
608 fbinfo->var.yres_virtual = LCD_Y_RES;
fbd65e0e 609 fbinfo->var.bits_per_pixel = info->lcd_bpp;
9cfe4a93
MH		 610
611 if (info->disp_info->mode & LQ035_BGR) {
fbd65e0e
MH		 612 if (info->lcd_bpp == 24) {
613 fbinfo->var.red.offset = 0;
614 fbinfo->var.green.offset = 8;
615 fbinfo->var.blue.offset = 16;
616 } else {
617 fbinfo->var.red.offset = 0;
618 fbinfo->var.green.offset = 5;
619 fbinfo->var.blue.offset = 11;
620 }
9cfe4a93 621 } else {
fbd65e0e
MH		 622 if (info->lcd_bpp == 24) {
623 fbinfo->var.red.offset = 16;
624 fbinfo->var.green.offset = 8;
625 fbinfo->var.blue.offset = 0;
626 } else {
627 fbinfo->var.red.offset = 11;
628 fbinfo->var.green.offset = 5;
629 fbinfo->var.blue.offset = 0;
630 }
9cfe4a93
MH		 631 }
632
633 fbinfo->var.transp.offset = 0;
634
fbd65e0e
MH		 635 if (info->lcd_bpp == 24) {
636 fbinfo->var.red.length = 8;
637 fbinfo->var.green.length = 8;
638 fbinfo->var.blue.length = 8;
639 } else {
640 fbinfo->var.red.length = 5;
641 fbinfo->var.green.length = 6;
642 fbinfo->var.blue.length = 5;
643 }
9cfe4a93
MH		 644
645 fbinfo->var.transp.length = 0;
646
fbd65e0e
MH		 647 active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8));
648
649 fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8
650 + active_video_mem_offset;
9cfe4a93
MH		 651
652 fbinfo->fix.line_length = fbinfo->var.xres_virtual *
653 fbinfo->var.bits_per_pixel / 8;
654
655
656 fbinfo->fbops = &bfin_lq035q1_fb_ops;
657 fbinfo->flags = FBINFO_FLAG_DEFAULT;
658
659 info->fb_buffer =
660 dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle,
661 GFP_KERNEL);
662
663 if (NULL == info->fb_buffer) {
664 dev_err(&pdev->dev, "couldn't allocate dma buffer\n");
665 ret = -ENOMEM;
666 goto out3;
667 }
668
fbd65e0e
MH		 669 fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset;
670 fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset;
9cfe4a93
MH		 671
672 fbinfo->fbops = &bfin_lq035q1_fb_ops;
673
674 fbinfo->pseudo_palette = &info->pseudo_pal;
675
676 ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0);
677 if (ret < 0) {
678 dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n",
679 BFIN_LCD_NBR_PALETTE_ENTRIES);
680 goto out4;
681 }
682
fbd65e0e
MH		 683 ret = bfin_lq035q1_request_ports(pdev,
684 info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI);
9cfe4a93
MH		 685 if (ret) {
686 dev_err(&pdev->dev, "couldn't request gpio port\n");
687 goto out6;
688 }
689
690 info->irq = platform_get_irq(pdev, 0);
691 if (info->irq < 0) {
692 ret = -EINVAL;
693 goto out7;
694 }
695
696 ret = request_irq(info->irq, bfin_lq035q1_irq_error, IRQF_DISABLED,
697 DRIVER_NAME" PPI ERROR", info);
698 if (ret < 0) {
699 dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n");
700 goto out7;
701 }
702
703 info->spidrv.driver.name = DRIVER_NAME"-spi";
704 info->spidrv.probe = lq035q1_spidev_probe;
705 info->spidrv.remove = __devexit_p(lq035q1_spidev_remove);
706 info->spidrv.shutdown = lq035q1_spidev_shutdown;
707 info->spidrv.suspend = lq035q1_spidev_suspend;
708 info->spidrv.resume = lq035q1_spidev_resume;
709
710 ret = spi_register_driver(&info->spidrv);
711 if (ret < 0) {
712 dev_err(&pdev->dev, "couldn't register SPI Interface\n");
713 goto out8;
714 }
715
716 if (info->disp_info->use_bl) {
717 ret = gpio_request(info->disp_info->gpio_bl, "LQ035 Backlight");
718
719 if (ret) {
720 dev_err(&pdev->dev, "failed to request GPIO %d\n",
721 info->disp_info->gpio_bl);
722 goto out9;
723 }
724 gpio_direction_output(info->disp_info->gpio_bl, 0);
725 }
726
727 ret = register_framebuffer(fbinfo);
728 if (ret < 0) {
729 dev_err(&pdev->dev, "unable to register framebuffer\n");
730 goto out10;
731 }
732
733 dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n",
fbd65e0e 734 LCD_X_RES, LCD_Y_RES, info->lcd_bpp);
9cfe4a93
MH		 735
736 return 0;
737
738 out10:
739 if (info->disp_info->use_bl)
740 gpio_free(info->disp_info->gpio_bl);
741 out9:
742 spi_unregister_driver(&info->spidrv);
743 out8:
744 free_irq(info->irq, info);
745 out7:
fbd65e0e
MH		 746 bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
747 USE_RGB565_16_BIT_PPI);
9cfe4a93
MH		 748 out6:
749 fb_dealloc_cmap(&fbinfo->cmap);
750 out4:
751 dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
752 info->dma_handle);
753 out3:
754 framebuffer_release(fbinfo);
755 out2:
756 free_dma(CH_PPI);
757 out1:
758 platform_set_drvdata(pdev, NULL);
759
760 return ret;
761}
762
763static int __devexit bfin_lq035q1_remove(struct platform_device *pdev)
764{
765 struct fb_info *fbinfo = platform_get_drvdata(pdev);
766 struct bfin_lq035q1fb_info *info = fbinfo->par;
767
768 if (info->disp_info->use_bl)
769 gpio_free(info->disp_info->gpio_bl);
770
771 spi_unregister_driver(&info->spidrv);
772
773 unregister_framebuffer(fbinfo);
774
775 free_dma(CH_PPI);
776 free_irq(info->irq, info);
777
778 if (info->fb_buffer != NULL)
779 dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
780 info->dma_handle);
781
782 fb_dealloc_cmap(&fbinfo->cmap);
783
fbd65e0e
MH		 784 bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
785 USE_RGB565_16_BIT_PPI);
9cfe4a93
MH		 786
787 platform_set_drvdata(pdev, NULL);
788 framebuffer_release(fbinfo);
789
790 dev_info(&pdev->dev, "unregistered LCD driver\n");
791
792 return 0;
793}
794
795#ifdef CONFIG_PM
796static int bfin_lq035q1_suspend(struct device *dev)
797{
798 struct fb_info *fbinfo = dev_get_drvdata(dev);
799 struct bfin_lq035q1fb_info *info = fbinfo->par;
800
801 if (info->lq035_open_cnt) {
802 lq035q1_backlight(info, 0);
803 bfin_lq035q1_disable_ppi();
804 SSYNC();
805 disable_dma(CH_PPI);
806 bfin_lq035q1_stop_timers();
807 bfin_write_PPI_STATUS(-1);
808 }
809
810 return 0;
811}
812
813static int bfin_lq035q1_resume(struct device *dev)
814{
815 struct fb_info *fbinfo = dev_get_drvdata(dev);
816 struct bfin_lq035q1fb_info *info = fbinfo->par;
817
818 if (info->lq035_open_cnt) {
819 bfin_lq035q1_disable_ppi();
820 SSYNC();
821
822 bfin_lq035q1_config_dma(info);
823 bfin_lq035q1_config_ppi(info);
fbd65e0e 824 bfin_lq035q1_init_timers(info);
9cfe4a93
MH		 825
826 /* start dma */
827 enable_dma(CH_PPI);
828 bfin_lq035q1_enable_ppi();
829 bfin_lq035q1_start_timers();
830 lq035q1_backlight(info, 1);
831 }
832
833 return 0;
834}
835
836static struct dev_pm_ops bfin_lq035q1_dev_pm_ops = {
837 .suspend = bfin_lq035q1_suspend,
838 .resume = bfin_lq035q1_resume,
839};
840#endif
841
842static struct platform_driver bfin_lq035q1_driver = {
843 .probe = bfin_lq035q1_probe,
844 .remove = __devexit_p(bfin_lq035q1_remove),
845 .driver = {
846 .name = DRIVER_NAME,
847#ifdef CONFIG_PM
848 .pm = &bfin_lq035q1_dev_pm_ops,
849#endif
850 },
851};
852
853static int __init bfin_lq035q1_driver_init(void)
854{
855 return platform_driver_register(&bfin_lq035q1_driver);
856}
857module_init(bfin_lq035q1_driver_init);
858
859static void __exit bfin_lq035q1_driver_cleanup(void)
860{
861 platform_driver_unregister(&bfin_lq035q1_driver);
862}
863module_exit(bfin_lq035q1_driver_cleanup);
864
865MODULE_DESCRIPTION("Blackfin TFT LCD Driver");
866MODULE_LICENSE("GPL");
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