[net-next-2.6.git] / drivers / usb / musb / omap2430.c

/*
 * Copyright (C) 2005-2007 by Texas Instruments
 * Some code has been taken from tusb6010.c
 * Copyrights for that are attributable to:
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/mux.h>

#include "musb_core.h"
#include "omap2430.h"

#ifdef CONFIG_ARCH_OMAP3430
#define	get_cpu_rev()	2
#endif


static struct timer_list musb_idle_timer;

static void musb_do_idle(unsigned long _musb)
{
	struct musb	*musb = (void *)_musb;
	unsigned long	flags;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	u8	power;
#endif
	u8	devctl;

	spin_lock_irqsave(&musb->lock, flags);

	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	case OTG_STATE_A_SUSPEND:
		/* finish RESUME signaling? */
		if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
			power = musb_readb(musb->mregs, MUSB_POWER);
			power &= ~MUSB_POWER_RESUME;
			DBG(1, "root port resume stopped, power %02x\n", power);
			musb_writeb(musb->mregs, MUSB_POWER, power);
			musb->is_active = 1;
			musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
						| MUSB_PORT_STAT_RESUME);
			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
			usb_hcd_poll_rh_status(musb_to_hcd(musb));
			/* NOTE: it might really be A_WAIT_BCON ... */
			musb->xceiv->state = OTG_STATE_A_HOST;
		}
		break;
#endif
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	case OTG_STATE_A_HOST:
		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl &  MUSB_DEVCTL_BDEVICE)
			musb->xceiv->state = OTG_STATE_B_IDLE;
		else
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
#endif
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}


void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
{
	unsigned long		default_timeout = jiffies + msecs_to_jiffies(3);
	static unsigned long	last_timer;

	if (timeout == 0)
		timeout = default_timeout;

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || ((musb->a_wait_bcon == 0)
			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
		del_timer(&musb_idle_timer);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout)) {
		if (!timer_pending(&musb_idle_timer))
			last_timer = timeout;
		else {
			DBG(4, "Longer idle timer already pending, ignoring\n");
			return;
		}
	}
	last_timer = timeout;

	DBG(4, "%s inactive, for idle timer for %lu ms\n",
		otg_state_string(musb),
		(unsigned long)jiffies_to_msecs(timeout - jiffies));
	mod_timer(&musb_idle_timer, timeout);
}

void musb_platform_enable(struct musb *musb)
{
}
void musb_platform_disable(struct musb *musb)
{
}
static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
{
}

static void omap_set_vbus(struct musb *musb, int is_on)
{
	u8		devctl;
	/* HDRC controls CPEN, but beware current surges during device
	 * connect.  They can trigger transient overcurrent conditions
	 * that must be ignored.
	 */

	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	if (is_on) {
		musb->is_active = 1;
		musb->xceiv->default_a = 1;
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		devctl |= MUSB_DEVCTL_SESSION;

		MUSB_HST_MODE(musb);
	} else {
		musb->is_active = 0;

		/* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
		 * jumping right to B_IDLE...
		 */

		musb->xceiv->default_a = 0;
		musb->xceiv->state = OTG_STATE_B_IDLE;
		devctl &= ~MUSB_DEVCTL_SESSION;

		MUSB_DEV_MODE(musb);
	}
	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int musb_platform_resume(struct musb *musb);

int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
{
	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	devctl |= MUSB_DEVCTL_SESSION;
	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

	return 0;
}

int __init musb_platform_init(struct musb *musb)
{
	u32 l;

#if defined(CONFIG_ARCH_OMAP2430)
	omap_cfg_reg(AE5_2430_USB0HS_STP);
#endif

	/* We require some kind of external transceiver, hooked
	 * up through ULPI.  TWL4030-family PMICs include one,
	 * which needs a driver, drivers aren't always needed.
	 */
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv) {
		pr_err("HS USB OTG: no transceiver configured\n");
		return -ENODEV;
	}

	musb_platform_resume(musb);

	l = omap_readl(OTG_SYSCONFIG);
	l &= ~ENABLEWAKEUP;	/* disable wakeup */
	l &= ~NOSTDBY;		/* remove possible nostdby */
	l |= SMARTSTDBY;	/* enable smart standby */
	l &= ~AUTOIDLE;		/* disable auto idle */
	l &= ~NOIDLE;		/* remove possible noidle */
	l |= SMARTIDLE;		/* enable smart idle */
	l |= AUTOIDLE;		/* enable auto idle */
	omap_writel(l, OTG_SYSCONFIG);

	l = omap_readl(OTG_INTERFSEL);
	l |= ULPI_12PIN;
	omap_writel(l, OTG_INTERFSEL);

	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
			"sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
			omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
			omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
			omap_readl(OTG_SIMENABLE));

	omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);

	if (is_host_enabled(musb))
		musb->board_set_vbus = omap_set_vbus;

	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);

	return 0;
}

int musb_platform_suspend(struct musb *musb)
{
	u32 l;

	if (!musb->clock)
		return 0;

	/* in any role */
	l = omap_readl(OTG_FORCESTDBY);
	l |= ENABLEFORCE;	/* enable MSTANDBY */
	omap_writel(l, OTG_FORCESTDBY);

	l = omap_readl(OTG_SYSCONFIG);
	l |= ENABLEWAKEUP;	/* enable wakeup */
	omap_writel(l, OTG_SYSCONFIG);

	otg_set_suspend(musb->xceiv, 1);

	if (musb->set_clock)
		musb->set_clock(musb->clock, 0);
	else
		clk_disable(musb->clock);

	return 0;
}

static int musb_platform_resume(struct musb *musb)
{
	u32 l;

	if (!musb->clock)
		return 0;

	otg_set_suspend(musb->xceiv, 0);

	if (musb->set_clock)
		musb->set_clock(musb->clock, 1);
	else
		clk_enable(musb->clock);

	l = omap_readl(OTG_SYSCONFIG);
	l &= ~ENABLEWAKEUP;	/* disable wakeup */
	omap_writel(l, OTG_SYSCONFIG);

	l = omap_readl(OTG_FORCESTDBY);
	l &= ~ENABLEFORCE;	/* disable MSTANDBY */
	omap_writel(l, OTG_FORCESTDBY);

	return 0;
}


int musb_platform_exit(struct musb *musb)
{

	omap_vbus_power(musb, 0 /*off*/, 1);

	musb_platform_suspend(musb);

	clk_put(musb->clock);
	musb->clock = 0;

	return 0;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* Copyright (C) 2005-2007 by Texas Instruments
	3	* Some code has been taken from tusb6010.c
	4	* Copyrights for that are attributable to:
	5	* Copyright (C) 2006 Nokia Corporation
550a7375 FB	6	* Tony Lindgren <tony@atomide.com>
	7	*
	8	* This file is part of the Inventra Controller Driver for Linux.
	9	*
	10	* The Inventra Controller Driver for Linux is free software; you
	11	* can redistribute it and/or modify it under the terms of the GNU
	12	* General Public License version 2 as published by the Free Software
	13	* Foundation.
	14	*
	15	* The Inventra Controller Driver for Linux is distributed in
	16	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	17	* without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	19	* License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with The Inventra Controller Driver for Linux ; if not,
	23	* write to the Free Software Foundation, Inc., 59 Temple Place,
	24	* Suite 330, Boston, MA 02111-1307 USA
	25	*
	26	*/
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/sched.h>
	30	#include <linux/slab.h>
	31	#include <linux/init.h>
	32	#include <linux/list.h>
	33	#include <linux/clk.h>
	34	#include <linux/io.h>
	35
	36	#include <asm/mach-types.h>
0590d587 FB	37	#include <mach/hardware.h>
0590d587 FB	38	#include <mach/mux.h>
550a7375 FB	39
	40	#include "musb_core.h"
	41	#include "omap2430.h"
	42
	43	#ifdef CONFIG_ARCH_OMAP3430
	44	#define get_cpu_rev() 2
	45	#endif
	46
550a7375 FB	47
	48	static struct timer_list musb_idle_timer;
	49
	50	static void musb_do_idle(unsigned long _musb)
	51	{
	52	struct musb musb = (void )_musb;
	53	unsigned long flags;
eef767b7	54	#ifdef CONFIG_USB_MUSB_HDRC_HCD
550a7375	55	u8 power;
eef767b7	56	#endif
550a7375 FB	57	u8 devctl;
550a7375 FB	58
550a7375 FB	59	spin_lock_irqsave(&musb->lock, flags);
550a7375 FB	60
71783e0d DB	61	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
71783e0d DB	62
84e250ff	63	switch (musb->xceiv->state) {
550a7375 FB	64	case OTG_STATE_A_WAIT_BCON:
	65	devctl &= ~MUSB_DEVCTL_SESSION;
	66	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	67
	68	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	69	if (devctl & MUSB_DEVCTL_BDEVICE) {
84e250ff	70	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	71	MUSB_DEV_MODE(musb);
550a7375 FB	72	} else {
84e250ff	73	musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 FB	74	MUSB_HST_MODE(musb);
	75	}
	76	break;
	77	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	78	case OTG_STATE_A_SUSPEND:
	79	/* finish RESUME signaling? */
	80	if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
	81	power = musb_readb(musb->mregs, MUSB_POWER);
	82	power &= ~MUSB_POWER_RESUME;
	83	DBG(1, "root port resume stopped, power %02x\n", power);
	84	musb_writeb(musb->mregs, MUSB_POWER, power);
	85	musb->is_active = 1;
	86	musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
	87	\| MUSB_PORT_STAT_RESUME);
	88	musb->port1_status \|= USB_PORT_STAT_C_SUSPEND << 16;
	89	usb_hcd_poll_rh_status(musb_to_hcd(musb));
	90	/* NOTE: it might really be A_WAIT_BCON ... */
84e250ff	91	musb->xceiv->state = OTG_STATE_A_HOST;
550a7375 FB	92	}
	93	break;
	94	#endif
	95	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	96	case OTG_STATE_A_HOST:
	97	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	98	if (devctl & MUSB_DEVCTL_BDEVICE)
84e250ff	99	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375	100	else
84e250ff	101	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
550a7375 FB	102	#endif
	103	default:
	104	break;
	105	}
	106	spin_unlock_irqrestore(&musb->lock, flags);
	107	}
	108
	109
	110	void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
	111	{
	112	unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
	113	static unsigned long last_timer;
	114
	115	if (timeout == 0)
	116	timeout = default_timeout;
	117
	118	/* Never idle if active, or when VBUS timeout is not set as host */
	119	if (musb->is_active \|\| ((musb->a_wait_bcon == 0)
84e250ff	120	&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
550a7375 FB	121	DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
	122	del_timer(&musb_idle_timer);
	123	last_timer = jiffies;
	124	return;
	125	}
	126
	127	if (time_after(last_timer, timeout)) {
	128	if (!timer_pending(&musb_idle_timer))
	129	last_timer = timeout;
	130	else {
	131	DBG(4, "Longer idle timer already pending, ignoring\n");
	132	return;
	133	}
	134	}
	135	last_timer = timeout;
	136
	137	DBG(4, "%s inactive, for idle timer for %lu ms\n",
	138	otg_state_string(musb),
	139	(unsigned long)jiffies_to_msecs(timeout - jiffies));
	140	mod_timer(&musb_idle_timer, timeout);
	141	}
	142
	143	void musb_platform_enable(struct musb *musb)
	144	{
	145	}
	146	void musb_platform_disable(struct musb *musb)
	147	{
	148	}
	149	static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
	150	{
	151	}
	152
	153	static void omap_set_vbus(struct musb *musb, int is_on)
	154	{
	155	u8 devctl;
	156	/* HDRC controls CPEN, but beware current surges during device
	157	* connect. They can trigger transient overcurrent conditions
	158	* that must be ignored.
	159	*/
	160
	161	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	162
	163	if (is_on) {
	164	musb->is_active = 1;
84e250ff DB	165	musb->xceiv->default_a = 1;
84e250ff DB	166	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	167	devctl \|= MUSB_DEVCTL_SESSION;
	168
	169	MUSB_HST_MODE(musb);
	170	} else {
	171	musb->is_active = 0;
	172
	173	/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
	174	* jumping right to B_IDLE...
	175	*/
	176
84e250ff DB	177	musb->xceiv->default_a = 0;
84e250ff DB	178	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	179	devctl &= ~MUSB_DEVCTL_SESSION;
	180
	181	MUSB_DEV_MODE(musb);
	182	}
	183	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	184
	185	DBG(1, "VBUS %s, devctl %02x "
	186	/* otg %3x conf %08x prcm %08x */ "\n",
	187	otg_state_string(musb),
	188	musb_readb(musb->mregs, MUSB_DEVCTL));
	189	}
550a7375 FB	190
	191	static int musb_platform_resume(struct musb *musb);
	192
96a274d1	193	int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
550a7375 FB	194	{
	195	u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	196
	197	devctl \|= MUSB_DEVCTL_SESSION;
	198	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	199
96a274d1	200	return 0;
550a7375 FB	201	}
	202
	203	int __init musb_platform_init(struct musb *musb)
	204	{
	205	u32 l;
	206
	207	#if defined(CONFIG_ARCH_OMAP2430)
	208	omap_cfg_reg(AE5_2430_USB0HS_STP);
	209	#endif
	210
84e250ff DB	211	/* We require some kind of external transceiver, hooked
	212	* up through ULPI. TWL4030-family PMICs include one,
	213	* which needs a driver, drivers aren't always needed.
	214	*/
	215	musb->xceiv = otg_get_transceiver();
	216	if (!musb->xceiv) {
	217	pr_err("HS USB OTG: no transceiver configured\n");
	218	return -ENODEV;
	219	}
	220
550a7375 FB	221	musb_platform_resume(musb);
	222
	223	l = omap_readl(OTG_SYSCONFIG);
	224	l &= ~ENABLEWAKEUP; /* disable wakeup */
	225	l &= ~NOSTDBY; /* remove possible nostdby */
	226	l \|= SMARTSTDBY; /* enable smart standby */
	227	l &= ~AUTOIDLE; /* disable auto idle */
	228	l &= ~NOIDLE; /* remove possible noidle */
	229	l \|= SMARTIDLE; /* enable smart idle */
	230	l \|= AUTOIDLE; /* enable auto idle */
	231	omap_writel(l, OTG_SYSCONFIG);
	232
	233	l = omap_readl(OTG_INTERFSEL);
	234	l \|= ULPI_12PIN;
	235	omap_writel(l, OTG_INTERFSEL);
	236
	237	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
	238	"sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
	239	omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
	240	omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
	241	omap_readl(OTG_SIMENABLE));
	242
	243	omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
	244
	245	if (is_host_enabled(musb))
	246	musb->board_set_vbus = omap_set_vbus;
550a7375 FB	247
	248	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
	249
	250	return 0;
	251	}
	252
	253	int musb_platform_suspend(struct musb *musb)
	254	{
	255	u32 l;
	256
	257	if (!musb->clock)
	258	return 0;
	259
	260	/* in any role */
	261	l = omap_readl(OTG_FORCESTDBY);
	262	l \|= ENABLEFORCE; /* enable MSTANDBY */
	263	omap_writel(l, OTG_FORCESTDBY);
	264
	265	l = omap_readl(OTG_SYSCONFIG);
	266	l \|= ENABLEWAKEUP; /* enable wakeup */
	267	omap_writel(l, OTG_SYSCONFIG);
	268
84e250ff	269	otg_set_suspend(musb->xceiv, 1);
550a7375 FB	270
	271	if (musb->set_clock)
	272	musb->set_clock(musb->clock, 0);
	273	else
	274	clk_disable(musb->clock);
	275
	276	return 0;
	277	}
	278
	279	static int musb_platform_resume(struct musb *musb)
	280	{
	281	u32 l;
	282
	283	if (!musb->clock)
	284	return 0;
	285
84e250ff	286	otg_set_suspend(musb->xceiv, 0);
550a7375 FB	287
	288	if (musb->set_clock)
	289	musb->set_clock(musb->clock, 1);
	290	else
	291	clk_enable(musb->clock);
	292
	293	l = omap_readl(OTG_SYSCONFIG);
	294	l &= ~ENABLEWAKEUP; /* disable wakeup */
	295	omap_writel(l, OTG_SYSCONFIG);
	296
	297	l = omap_readl(OTG_FORCESTDBY);
	298	l &= ~ENABLEFORCE; /* disable MSTANDBY */
	299	omap_writel(l, OTG_FORCESTDBY);
	300
	301	return 0;
	302	}
	303
	304
	305	int musb_platform_exit(struct musb *musb)
	306	{
	307
	308	omap_vbus_power(musb, 0 /off/, 1);
	309
	310	musb_platform_suspend(musb);
	311
	312	clk_put(musb->clock);
	313	musb->clock = 0;
	314
	315	return 0;
	316	}