[net-next-2.6.git] / drivers / usb / musb / musbhsdma.c

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "musb_core.h"
#include "musbhsdma.h"

static int dma_controller_start(struct dma_controller *c)
{
	/* nothing to do */
	return 0;
}

static void dma_channel_release(struct dma_channel *channel);

static int dma_controller_stop(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb *musb = controller->private_data;
	struct dma_channel *channel;
	u8 bit;

	if (controller->used_channels != 0) {
		dev_err(musb->controller,
			"Stopping DMA controller while channel active\n");

		for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
			if (controller->used_channels & (1 << bit)) {
				channel = &controller->channel[bit].channel;
				dma_channel_release(channel);

				if (!controller->used_channels)
					break;
			}
		}
	}

	return 0;
}

static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 transmit)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb_dma_channel *musb_channel = NULL;
	struct dma_channel *channel = NULL;
	u8 bit;

	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
		if (!(controller->used_channels & (1 << bit))) {
			controller->used_channels |= (1 << bit);
			musb_channel = &(controller->channel[bit]);
			musb_channel->controller = controller;
			musb_channel->idx = bit;
			musb_channel->epnum = hw_ep->epnum;
			musb_channel->transmit = transmit;
			channel = &(musb_channel->channel);
			channel->private_data = musb_channel;
			channel->status = MUSB_DMA_STATUS_FREE;
			channel->max_len = 0x100000;
			/* Tx => mode 1; Rx => mode 0 */
			channel->desired_mode = transmit;
			channel->actual_len = 0;
			break;
		}
	}

	return channel;
}

static void dma_channel_release(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	channel->actual_len = 0;
	musb_channel->start_addr = 0;
	musb_channel->len = 0;

	musb_channel->controller->used_channels &=
		~(1 << musb_channel->idx);

	channel->status = MUSB_DMA_STATUS_UNKNOWN;
}

static void configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	void __iomem *mbase = controller->base;
	u8 bchannel = musb_channel->idx;
	u16 csr = 0;

	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
			channel, packet_sz, dma_addr, len, mode);

	if (mode) {
		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
		BUG_ON(len < packet_sz);
	}
	csr |= MUSB_HSDMA_BURSTMODE_INCR16
				<< MUSB_HSDMA_BURSTMODE_SHIFT;

	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
		| (musb_channel->transmit
				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
				: 0);

	/* address/count */
	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
	musb_write_hsdma_count(mbase, bchannel, len);

	/* control (this should start things) */
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
		csr);
}

static int dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	struct musb *musb = controller->private_data;

	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
		musb_channel->epnum,
		musb_channel->transmit ? "Tx" : "Rx",
		packet_sz, dma_addr, len, mode);

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	/*
	 * The DMA engine in RTL1.8 and above cannot handle
	 * DMA addresses that are not aligned to a 4 byte boundary.
	 * It ends up masking the last two bits of the address
	 * programmed in DMA_ADDR.
	 *
	 * Fail such DMA transfers, so that the backup PIO mode
	 * can carry out the transfer
	 */
	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
		return false;

	channel->actual_len = 0;
	musb_channel->start_addr = dma_addr;
	musb_channel->len = len;
	musb_channel->max_packet_sz = packet_sz;
	channel->status = MUSB_DMA_STATUS_BUSY;

	configure_channel(channel, packet_sz, mode, dma_addr, len);

	return true;
}

static int dma_channel_abort(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	void __iomem *mbase = musb_channel->controller->base;

	u8 bchannel = musb_channel->idx;
	int offset;
	u16 csr;

	if (channel->status == MUSB_DMA_STATUS_BUSY) {
		if (musb_channel->transmit) {
			offset = MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_TXCSR);

			/*
			 * The programming guide says that we must clear
			 * the DMAENAB bit before the DMAMODE bit...
			 */
			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
			musb_writew(mbase, offset, csr);
			csr &= ~MUSB_TXCSR_DMAMODE;
			musb_writew(mbase, offset, csr);
		} else {
			offset = MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_RXCSR);

			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(mbase, offset, csr);
		}

		musb_writew(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
			0);
		musb_write_hsdma_addr(mbase, bchannel, 0);
		musb_write_hsdma_count(mbase, bchannel, 0);
		channel->status = MUSB_DMA_STATUS_FREE;
	}

	return 0;
}

static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
	struct musb_dma_controller *controller = private_data;
	struct musb *musb = controller->private_data;
	struct musb_dma_channel *musb_channel;
	struct dma_channel *channel;

	void __iomem *mbase = controller->base;

	irqreturn_t retval = IRQ_NONE;

	unsigned long flags;

	u8 bchannel;
	u8 int_hsdma;

	u32 addr, count;
	u16 csr;

	spin_lock_irqsave(&musb->lock, flags);

	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);

#ifdef CONFIG_BLACKFIN
	/* Clear DMA interrupt flags */
	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
#endif

	if (!int_hsdma) {
		DBG(2, "spurious DMA irq\n");

		for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;
			if (channel->status == MUSB_DMA_STATUS_BUSY) {
				count = musb_read_hsdma_count(mbase, bchannel);

				if (count == 0)
					int_hsdma |= (1 << bchannel);
			}
		}

		DBG(2, "int_hsdma = 0x%x\n", int_hsdma);

		if (!int_hsdma)
			goto done;
	}

	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
		if (int_hsdma & (1 << bchannel)) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;

			csr = musb_readw(mbase,
					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
							MUSB_HSDMA_CONTROL));

			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
				musb_channel->channel.status =
					MUSB_DMA_STATUS_BUS_ABORT;
			} else {
				u8 devctl;

				addr = musb_read_hsdma_addr(mbase,
						bchannel);
				channel->actual_len = addr
					- musb_channel->start_addr;

				DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
					channel, musb_channel->start_addr,
					addr, channel->actual_len,
					musb_channel->len,
					(channel->actual_len
						< musb_channel->len) ?
					"=> reconfig 0" : "=> complete");

				devctl = musb_readb(mbase, MUSB_DEVCTL);

				channel->status = MUSB_DMA_STATUS_FREE;

				/* completed */
				if ((devctl & MUSB_DEVCTL_HM)
					&& (musb_channel->transmit)
					&& ((channel->desired_mode == 0)
					    || (channel->actual_len &
					    (musb_channel->max_packet_sz - 1)))
				    ) {
					u8  epnum  = musb_channel->epnum;
					int offset = MUSB_EP_OFFSET(epnum,
								    MUSB_TXCSR);
					u16 txcsr;

					/*
					 * The programming guide says that we
					 * must clear DMAENAB before DMAMODE.
					 */
					musb_ep_select(mbase, epnum);
					txcsr = musb_readw(mbase, offset);
					txcsr &= ~(MUSB_TXCSR_DMAENAB
							| MUSB_TXCSR_AUTOSET);
					musb_writew(mbase, offset, txcsr);
					/* Send out the packet */
					txcsr &= ~MUSB_TXCSR_DMAMODE;
					txcsr |=  MUSB_TXCSR_TXPKTRDY;
					musb_writew(mbase, offset, txcsr);
				}
				musb_dma_completion(musb, musb_channel->epnum,
						    musb_channel->transmit);
			}
		}
	}

	retval = IRQ_HANDLED;
done:
	spin_unlock_irqrestore(&musb->lock, flags);
	return retval;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);

	if (!controller)
		return;

	if (controller->irq)
		free_irq(controller->irq, c);

	kfree(controller);
}

struct dma_controller *__init
dma_controller_create(struct musb *musb, void __iomem *base)
{
	struct musb_dma_controller *controller;
	struct device *dev = musb->controller;
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq(pdev, 1);

	if (irq == 0) {
		dev_err(dev, "No DMA interrupt line!\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		return NULL;

	controller->channel_count = MUSB_HSDMA_CHANNELS;
	controller->private_data = musb;
	controller->base = base;

	controller->controller.start = dma_controller_start;
	controller->controller.stop = dma_controller_stop;
	controller->controller.channel_alloc = dma_channel_allocate;
	controller->controller.channel_release = dma_channel_release;
	controller->controller.channel_program = dma_channel_program;
	controller->controller.channel_abort = dma_channel_abort;

	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
			dev_name(musb->controller), &controller->controller)) {
		dev_err(dev, "request_irq %d failed!\n", irq);
		dma_controller_destroy(&controller->controller);

		return NULL;
	}

	controller->irq = irq;

	return &controller->controller;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33	#include <linux/device.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/platform_device.h>
5a0e3ad6	36	#include <linux/slab.h>
550a7375	37	#include "musb_core.h"
6995eb68	38	#include "musbhsdma.h"
550a7375 FB	39
	40	static int dma_controller_start(struct dma_controller *c)
	41	{
	42	/* nothing to do */
	43	return 0;
	44	}
	45
458e6a51	46	static void dma_channel_release(struct dma_channel *channel);
550a7375 FB	47
	48	static int dma_controller_stop(struct dma_controller *c)
	49	{
458e6a51 FB	50	struct musb_dma_controller *controller = container_of(c,
	51	struct musb_dma_controller, controller);
	52	struct musb *musb = controller->private_data;
	53	struct dma_channel *channel;
	54	u8 bit;
550a7375	55
458e6a51	56	if (controller->used_channels != 0) {
550a7375 FB	57	dev_err(musb->controller,
	58	"Stopping DMA controller while channel active\n");
	59
458e6a51 FB	60	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	61	if (controller->used_channels & (1 << bit)) {
	62	channel = &controller->channel[bit].channel;
	63	dma_channel_release(channel);
550a7375	64
458e6a51	65	if (!controller->used_channels)
550a7375 FB	66	break;
	67	}
	68	}
	69	}
458e6a51	70
550a7375 FB	71	return 0;
	72	}
	73
	74	static struct dma_channel dma_channel_allocate(struct dma_controller c,
	75	struct musb_hw_ep *hw_ep, u8 transmit)
	76	{
458e6a51 FB	77	struct musb_dma_controller *controller = container_of(c,
	78	struct musb_dma_controller, controller);
	79	struct musb_dma_channel *musb_channel = NULL;
	80	struct dma_channel *channel = NULL;
	81	u8 bit;
	82
	83	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	84	if (!(controller->used_channels & (1 << bit))) {
	85	controller->used_channels \|= (1 << bit);
	86	musb_channel = &(controller->channel[bit]);
	87	musb_channel->controller = controller;
	88	musb_channel->idx = bit;
	89	musb_channel->epnum = hw_ep->epnum;
	90	musb_channel->transmit = transmit;
	91	channel = &(musb_channel->channel);
	92	channel->private_data = musb_channel;
	93	channel->status = MUSB_DMA_STATUS_FREE;
6587cc0f	94	channel->max_len = 0x100000;
550a7375	95	/* Tx => mode 1; Rx => mode 0 */
458e6a51 FB	96	channel->desired_mode = transmit;
458e6a51 FB	97	channel->actual_len = 0;
550a7375 FB	98	break;
	99	}
	100	}
458e6a51 FB	101
458e6a51 FB	102	return channel;
550a7375 FB	103	}
550a7375 FB	104
458e6a51	105	static void dma_channel_release(struct dma_channel *channel)
550a7375	106	{
458e6a51	107	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375	108
458e6a51 FB	109	channel->actual_len = 0;
	110	musb_channel->start_addr = 0;
	111	musb_channel->len = 0;
550a7375	112
458e6a51 FB	113	musb_channel->controller->used_channels &=
458e6a51 FB	114	~(1 << musb_channel->idx);
550a7375	115
458e6a51	116	channel->status = MUSB_DMA_STATUS_UNKNOWN;
550a7375 FB	117	}
550a7375 FB	118
458e6a51	119	static void configure_channel(struct dma_channel *channel,
550a7375 FB	120	u16 packet_sz, u8 mode,
	121	dma_addr_t dma_addr, u32 len)
	122	{
458e6a51 FB	123	struct musb_dma_channel *musb_channel = channel->private_data;
	124	struct musb_dma_controller *controller = musb_channel->controller;
	125	void __iomem *mbase = controller->base;
	126	u8 bchannel = musb_channel->idx;
550a7375 FB	127	u16 csr = 0;
	128
	129	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
458e6a51	130	channel, packet_sz, dma_addr, len, mode);
550a7375 FB	131
	132	if (mode) {
	133	csr \|= 1 << MUSB_HSDMA_MODE1_SHIFT;
	134	BUG_ON(len < packet_sz);
550a7375	135	}
c0f1f8e3 HH	136	csr \|= MUSB_HSDMA_BURSTMODE_INCR16
c0f1f8e3 HH	137	<< MUSB_HSDMA_BURSTMODE_SHIFT;
550a7375	138
458e6a51	139	csr \|= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
550a7375 FB	140	\| (1 << MUSB_HSDMA_ENABLE_SHIFT)
550a7375 FB	141	\| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
458e6a51	142	\| (musb_channel->transmit
550a7375 FB	143	? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
	144	: 0);
	145
	146	/* address/count */
6995eb68 BW	147	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
6995eb68 BW	148	musb_write_hsdma_count(mbase, bchannel, len);
550a7375 FB	149
	150	/* control (this should start things) */
	151	musb_writew(mbase,
458e6a51	152	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375 FB	153	csr);
	154	}
	155
458e6a51	156	static int dma_channel_program(struct dma_channel *channel,
550a7375 FB	157	u16 packet_sz, u8 mode,
	158	dma_addr_t dma_addr, u32 len)
	159	{
458e6a51	160	struct musb_dma_channel *musb_channel = channel->private_data;
6e16edfe AG	161	struct musb_dma_controller *controller = musb_channel->controller;
6e16edfe AG	162	struct musb *musb = controller->private_data;
550a7375 FB	163
550a7375 FB	164	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
458e6a51 FB	165	musb_channel->epnum,
458e6a51 FB	166	musb_channel->transmit ? "Tx" : "Rx",
550a7375 FB	167	packet_sz, dma_addr, len, mode);
550a7375 FB	168
458e6a51 FB	169	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
458e6a51 FB	170	channel->status == MUSB_DMA_STATUS_BUSY);
550a7375	171
6e16edfe AG	172	/*
	173	* The DMA engine in RTL1.8 and above cannot handle
	174	* DMA addresses that are not aligned to a 4 byte boundary.
	175	* It ends up masking the last two bits of the address
	176	* programmed in DMA_ADDR.
	177	*
	178	* Fail such DMA transfers, so that the backup PIO mode
	179	* can carry out the transfer
	180	*/
	181	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
	182	return false;
	183
458e6a51 FB	184	channel->actual_len = 0;
	185	musb_channel->start_addr = dma_addr;
	186	musb_channel->len = len;
	187	musb_channel->max_packet_sz = packet_sz;
	188	channel->status = MUSB_DMA_STATUS_BUSY;
550a7375	189
8ca47c8a	190	configure_channel(channel, packet_sz, mode, dma_addr, len);
550a7375 FB	191
	192	return true;
	193	}
	194
458e6a51	195	static int dma_channel_abort(struct dma_channel *channel)
550a7375	196	{
458e6a51 FB	197	struct musb_dma_channel *musb_channel = channel->private_data;
	198	void __iomem *mbase = musb_channel->controller->base;
	199
	200	u8 bchannel = musb_channel->idx;
b6e434a5	201	int offset;
550a7375 FB	202	u16 csr;
550a7375 FB	203
458e6a51 FB	204	if (channel->status == MUSB_DMA_STATUS_BUSY) {
458e6a51 FB	205	if (musb_channel->transmit) {
b6e434a5 SS	206	offset = MUSB_EP_OFFSET(musb_channel->epnum,
	207	MUSB_TXCSR);
	208
	209	/*
	210	* The programming guide says that we must clear
	211	* the DMAENAB bit before the DMAMODE bit...
	212	*/
	213	csr = musb_readw(mbase, offset);
	214	csr &= ~(MUSB_TXCSR_AUTOSET \| MUSB_TXCSR_DMAENAB);
	215	musb_writew(mbase, offset, csr);
	216	csr &= ~MUSB_TXCSR_DMAMODE;
	217	musb_writew(mbase, offset, csr);
550a7375	218	} else {
b6e434a5 SS	219	offset = MUSB_EP_OFFSET(musb_channel->epnum,
	220	MUSB_RXCSR);
	221
	222	csr = musb_readw(mbase, offset);
550a7375 FB	223	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
	224	MUSB_RXCSR_DMAENAB \|
	225	MUSB_RXCSR_DMAMODE);
b6e434a5	226	musb_writew(mbase, offset, csr);
550a7375 FB	227	}
	228
	229	musb_writew(mbase,
458e6a51	230	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375	231	0);
6995eb68 BW	232	musb_write_hsdma_addr(mbase, bchannel, 0);
6995eb68 BW	233	musb_write_hsdma_count(mbase, bchannel, 0);
458e6a51	234	channel->status = MUSB_DMA_STATUS_FREE;
550a7375	235	}
458e6a51	236
550a7375 FB	237	return 0;
	238	}
	239
	240	static irqreturn_t dma_controller_irq(int irq, void *private_data)
	241	{
458e6a51 FB	242	struct musb_dma_controller *controller = private_data;
	243	struct musb *musb = controller->private_data;
	244	struct musb_dma_channel *musb_channel;
	245	struct dma_channel *channel;
	246
	247	void __iomem *mbase = controller->base;
	248
550a7375	249	irqreturn_t retval = IRQ_NONE;
458e6a51	250
550a7375 FB	251	unsigned long flags;
550a7375 FB	252
458e6a51 FB	253	u8 bchannel;
	254	u8 int_hsdma;
	255
f933a0c0	256	u32 addr, count;
458e6a51 FB	257	u16 csr;
458e6a51 FB	258
550a7375 FB	259	spin_lock_irqsave(&musb->lock, flags);
	260
	261	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
550a7375	262
6bd03e7b CC	263	#ifdef CONFIG_BLACKFIN
	264	/* Clear DMA interrupt flags */
	265	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
	266	#endif
	267
f933a0c0 AG	268	if (!int_hsdma) {
	269	DBG(2, "spurious DMA irq\n");
	270
	271	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	272	musb_channel = (struct musb_dma_channel *)
	273	&(controller->channel[bchannel]);
	274	channel = &musb_channel->channel;
	275	if (channel->status == MUSB_DMA_STATUS_BUSY) {
	276	count = musb_read_hsdma_count(mbase, bchannel);
	277
	278	if (count == 0)
	279	int_hsdma \|= (1 << bchannel);
	280	}
	281	}
	282
	283	DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
	284
	285	if (!int_hsdma)
	286	goto done;
	287	}
	288
458e6a51 FB	289	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	290	if (int_hsdma & (1 << bchannel)) {
	291	musb_channel = (struct musb_dma_channel *)
	292	&(controller->channel[bchannel]);
	293	channel = &musb_channel->channel;
550a7375 FB	294
550a7375 FB	295	csr = musb_readw(mbase,
458e6a51	296	MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
550a7375 FB	297	MUSB_HSDMA_CONTROL));
550a7375 FB	298
458e6a51 FB	299	if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
458e6a51 FB	300	musb_channel->channel.status =
550a7375	301	MUSB_DMA_STATUS_BUS_ABORT;
458e6a51	302	} else {
550a7375 FB	303	u8 devctl;
550a7375 FB	304
6995eb68 BW	305	addr = musb_read_hsdma_addr(mbase,
6995eb68 BW	306	bchannel);
458e6a51 FB	307	channel->actual_len = addr
458e6a51 FB	308	- musb_channel->start_addr;
550a7375	309
32340d3f	310	DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
458e6a51 FB	311	channel, musb_channel->start_addr,
	312	addr, channel->actual_len,
	313	musb_channel->len,
	314	(channel->actual_len
	315	< musb_channel->len) ?
550a7375 FB	316	"=> reconfig 0" : "=> complete");
	317
	318	devctl = musb_readb(mbase, MUSB_DEVCTL);
	319
458e6a51	320	channel->status = MUSB_DMA_STATUS_FREE;
550a7375 FB	321
	322	/* completed */
	323	if ((devctl & MUSB_DEVCTL_HM)
458e6a51 FB	324	&& (musb_channel->transmit)
	325	&& ((channel->desired_mode == 0)
	326	\|\| (channel->actual_len &
	327	(musb_channel->max_packet_sz - 1)))
b6e434a5 SS	328	) {
	329	u8 epnum = musb_channel->epnum;
	330	int offset = MUSB_EP_OFFSET(epnum,
	331	MUSB_TXCSR);
	332	u16 txcsr;
	333
	334	/*
	335	* The programming guide says that we
	336	* must clear DMAENAB before DMAMODE.
	337	*/
	338	musb_ep_select(mbase, epnum);
	339	txcsr = musb_readw(mbase, offset);
	340	txcsr &= ~(MUSB_TXCSR_DMAENAB
	341	\| MUSB_TXCSR_AUTOSET);
	342	musb_writew(mbase, offset, txcsr);
550a7375	343	/* Send out the packet */
b6e434a5 SS	344	txcsr &= ~MUSB_TXCSR_DMAMODE;
	345	txcsr \|= MUSB_TXCSR_TXPKTRDY;
	346	musb_writew(mbase, offset, txcsr);
458e6a51	347	}
c7bbc056 SS	348	musb_dma_completion(musb, musb_channel->epnum,
c7bbc056 SS	349	musb_channel->transmit);
550a7375 FB	350	}
	351	}
	352	}
6995eb68	353
550a7375 FB	354	retval = IRQ_HANDLED;
	355	done:
	356	spin_unlock_irqrestore(&musb->lock, flags);
	357	return retval;
	358	}
	359
	360	void dma_controller_destroy(struct dma_controller *c)
	361	{
458e6a51 FB	362	struct musb_dma_controller *controller = container_of(c,
458e6a51 FB	363	struct musb_dma_controller, controller);
550a7375	364
550a7375 FB	365	if (!controller)
	366	return;
	367
	368	if (controller->irq)
	369	free_irq(controller->irq, c);
	370
	371	kfree(controller);
	372	}
	373
	374	struct dma_controller *__init
458e6a51	375	dma_controller_create(struct musb musb, void __iomem base)
550a7375 FB	376	{
	377	struct musb_dma_controller *controller;
	378	struct device *dev = musb->controller;
	379	struct platform_device *pdev = to_platform_device(dev);
	380	int irq = platform_get_irq(pdev, 1);
	381
	382	if (irq == 0) {
	383	dev_err(dev, "No DMA interrupt line!\n");
	384	return NULL;
	385	}
	386
458e6a51	387	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
550a7375 FB	388	if (!controller)
	389	return NULL;
	390
458e6a51 FB	391	controller->channel_count = MUSB_HSDMA_CHANNELS;
	392	controller->private_data = musb;
	393	controller->base = base;
550a7375	394
458e6a51 FB	395	controller->controller.start = dma_controller_start;
	396	controller->controller.stop = dma_controller_stop;
	397	controller->controller.channel_alloc = dma_channel_allocate;
	398	controller->controller.channel_release = dma_channel_release;
	399	controller->controller.channel_program = dma_channel_program;
	400	controller->controller.channel_abort = dma_channel_abort;
550a7375 FB	401
550a7375 FB	402	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
427c4f33	403	dev_name(musb->controller), &controller->controller)) {
550a7375	404	dev_err(dev, "request_irq %d failed!\n", irq);
458e6a51 FB	405	dma_controller_destroy(&controller->controller);
458e6a51 FB	406
550a7375 FB	407	return NULL;
	408	}
	409
	410	controller->irq = irq;
	411
458e6a51	412	return &controller->controller;
550a7375	413	}