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Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver - support for Mentor's DMA controller | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2007 by Texas Instruments | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
22 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
23 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
24 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
27 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | * | |
32 | */ | |
33 | #include <linux/device.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include "musb_core.h" | |
6995eb68 | 37 | #include "musbhsdma.h" |
550a7375 FB |
38 | |
39 | static int dma_controller_start(struct dma_controller *c) | |
40 | { | |
41 | /* nothing to do */ | |
42 | return 0; | |
43 | } | |
44 | ||
458e6a51 | 45 | static void dma_channel_release(struct dma_channel *channel); |
550a7375 FB |
46 | |
47 | static int dma_controller_stop(struct dma_controller *c) | |
48 | { | |
458e6a51 FB |
49 | struct musb_dma_controller *controller = container_of(c, |
50 | struct musb_dma_controller, controller); | |
51 | struct musb *musb = controller->private_data; | |
52 | struct dma_channel *channel; | |
53 | u8 bit; | |
550a7375 | 54 | |
458e6a51 | 55 | if (controller->used_channels != 0) { |
550a7375 FB |
56 | dev_err(musb->controller, |
57 | "Stopping DMA controller while channel active\n"); | |
58 | ||
458e6a51 FB |
59 | for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { |
60 | if (controller->used_channels & (1 << bit)) { | |
61 | channel = &controller->channel[bit].channel; | |
62 | dma_channel_release(channel); | |
550a7375 | 63 | |
458e6a51 | 64 | if (!controller->used_channels) |
550a7375 FB |
65 | break; |
66 | } | |
67 | } | |
68 | } | |
458e6a51 | 69 | |
550a7375 FB |
70 | return 0; |
71 | } | |
72 | ||
73 | static struct dma_channel *dma_channel_allocate(struct dma_controller *c, | |
74 | struct musb_hw_ep *hw_ep, u8 transmit) | |
75 | { | |
458e6a51 FB |
76 | struct musb_dma_controller *controller = container_of(c, |
77 | struct musb_dma_controller, controller); | |
78 | struct musb_dma_channel *musb_channel = NULL; | |
79 | struct dma_channel *channel = NULL; | |
80 | u8 bit; | |
81 | ||
82 | for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { | |
83 | if (!(controller->used_channels & (1 << bit))) { | |
84 | controller->used_channels |= (1 << bit); | |
85 | musb_channel = &(controller->channel[bit]); | |
86 | musb_channel->controller = controller; | |
87 | musb_channel->idx = bit; | |
88 | musb_channel->epnum = hw_ep->epnum; | |
89 | musb_channel->transmit = transmit; | |
90 | channel = &(musb_channel->channel); | |
91 | channel->private_data = musb_channel; | |
92 | channel->status = MUSB_DMA_STATUS_FREE; | |
93 | channel->max_len = 0x10000; | |
550a7375 | 94 | /* Tx => mode 1; Rx => mode 0 */ |
458e6a51 FB |
95 | channel->desired_mode = transmit; |
96 | channel->actual_len = 0; | |
550a7375 FB |
97 | break; |
98 | } | |
99 | } | |
458e6a51 FB |
100 | |
101 | return channel; | |
550a7375 FB |
102 | } |
103 | ||
458e6a51 | 104 | static void dma_channel_release(struct dma_channel *channel) |
550a7375 | 105 | { |
458e6a51 | 106 | struct musb_dma_channel *musb_channel = channel->private_data; |
550a7375 | 107 | |
458e6a51 FB |
108 | channel->actual_len = 0; |
109 | musb_channel->start_addr = 0; | |
110 | musb_channel->len = 0; | |
550a7375 | 111 | |
458e6a51 FB |
112 | musb_channel->controller->used_channels &= |
113 | ~(1 << musb_channel->idx); | |
550a7375 | 114 | |
458e6a51 | 115 | channel->status = MUSB_DMA_STATUS_UNKNOWN; |
550a7375 FB |
116 | } |
117 | ||
458e6a51 | 118 | static void configure_channel(struct dma_channel *channel, |
550a7375 FB |
119 | u16 packet_sz, u8 mode, |
120 | dma_addr_t dma_addr, u32 len) | |
121 | { | |
458e6a51 FB |
122 | struct musb_dma_channel *musb_channel = channel->private_data; |
123 | struct musb_dma_controller *controller = musb_channel->controller; | |
124 | void __iomem *mbase = controller->base; | |
125 | u8 bchannel = musb_channel->idx; | |
550a7375 FB |
126 | u16 csr = 0; |
127 | ||
128 | DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", | |
458e6a51 | 129 | channel, packet_sz, dma_addr, len, mode); |
550a7375 FB |
130 | |
131 | if (mode) { | |
132 | csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; | |
133 | BUG_ON(len < packet_sz); | |
134 | ||
135 | if (packet_sz >= 64) { | |
136 | csr |= MUSB_HSDMA_BURSTMODE_INCR16 | |
137 | << MUSB_HSDMA_BURSTMODE_SHIFT; | |
138 | } else if (packet_sz >= 32) { | |
139 | csr |= MUSB_HSDMA_BURSTMODE_INCR8 | |
140 | << MUSB_HSDMA_BURSTMODE_SHIFT; | |
141 | } else if (packet_sz >= 16) { | |
142 | csr |= MUSB_HSDMA_BURSTMODE_INCR4 | |
143 | << MUSB_HSDMA_BURSTMODE_SHIFT; | |
144 | } | |
145 | } | |
146 | ||
458e6a51 | 147 | csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) |
550a7375 FB |
148 | | (1 << MUSB_HSDMA_ENABLE_SHIFT) |
149 | | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) | |
458e6a51 | 150 | | (musb_channel->transmit |
550a7375 FB |
151 | ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) |
152 | : 0); | |
153 | ||
154 | /* address/count */ | |
6995eb68 BW |
155 | musb_write_hsdma_addr(mbase, bchannel, dma_addr); |
156 | musb_write_hsdma_count(mbase, bchannel, len); | |
550a7375 FB |
157 | |
158 | /* control (this should start things) */ | |
159 | musb_writew(mbase, | |
458e6a51 | 160 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), |
550a7375 FB |
161 | csr); |
162 | } | |
163 | ||
458e6a51 | 164 | static int dma_channel_program(struct dma_channel *channel, |
550a7375 FB |
165 | u16 packet_sz, u8 mode, |
166 | dma_addr_t dma_addr, u32 len) | |
167 | { | |
458e6a51 | 168 | struct musb_dma_channel *musb_channel = channel->private_data; |
550a7375 FB |
169 | |
170 | DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", | |
458e6a51 FB |
171 | musb_channel->epnum, |
172 | musb_channel->transmit ? "Tx" : "Rx", | |
550a7375 FB |
173 | packet_sz, dma_addr, len, mode); |
174 | ||
458e6a51 FB |
175 | BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || |
176 | channel->status == MUSB_DMA_STATUS_BUSY); | |
550a7375 | 177 | |
458e6a51 FB |
178 | channel->actual_len = 0; |
179 | musb_channel->start_addr = dma_addr; | |
180 | musb_channel->len = len; | |
181 | musb_channel->max_packet_sz = packet_sz; | |
182 | channel->status = MUSB_DMA_STATUS_BUSY; | |
550a7375 FB |
183 | |
184 | if ((mode == 1) && (len >= packet_sz)) | |
458e6a51 | 185 | configure_channel(channel, packet_sz, 1, dma_addr, len); |
550a7375 | 186 | else |
458e6a51 | 187 | configure_channel(channel, packet_sz, 0, dma_addr, len); |
550a7375 FB |
188 | |
189 | return true; | |
190 | } | |
191 | ||
458e6a51 | 192 | static int dma_channel_abort(struct dma_channel *channel) |
550a7375 | 193 | { |
458e6a51 FB |
194 | struct musb_dma_channel *musb_channel = channel->private_data; |
195 | void __iomem *mbase = musb_channel->controller->base; | |
196 | ||
197 | u8 bchannel = musb_channel->idx; | |
b6e434a5 | 198 | int offset; |
550a7375 FB |
199 | u16 csr; |
200 | ||
458e6a51 FB |
201 | if (channel->status == MUSB_DMA_STATUS_BUSY) { |
202 | if (musb_channel->transmit) { | |
b6e434a5 SS |
203 | offset = MUSB_EP_OFFSET(musb_channel->epnum, |
204 | MUSB_TXCSR); | |
205 | ||
206 | /* | |
207 | * The programming guide says that we must clear | |
208 | * the DMAENAB bit before the DMAMODE bit... | |
209 | */ | |
210 | csr = musb_readw(mbase, offset); | |
211 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); | |
212 | musb_writew(mbase, offset, csr); | |
213 | csr &= ~MUSB_TXCSR_DMAMODE; | |
214 | musb_writew(mbase, offset, csr); | |
550a7375 | 215 | } else { |
b6e434a5 SS |
216 | offset = MUSB_EP_OFFSET(musb_channel->epnum, |
217 | MUSB_RXCSR); | |
218 | ||
219 | csr = musb_readw(mbase, offset); | |
550a7375 FB |
220 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
221 | MUSB_RXCSR_DMAENAB | | |
222 | MUSB_RXCSR_DMAMODE); | |
b6e434a5 | 223 | musb_writew(mbase, offset, csr); |
550a7375 FB |
224 | } |
225 | ||
226 | musb_writew(mbase, | |
458e6a51 | 227 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), |
550a7375 | 228 | 0); |
6995eb68 BW |
229 | musb_write_hsdma_addr(mbase, bchannel, 0); |
230 | musb_write_hsdma_count(mbase, bchannel, 0); | |
458e6a51 | 231 | channel->status = MUSB_DMA_STATUS_FREE; |
550a7375 | 232 | } |
458e6a51 | 233 | |
550a7375 FB |
234 | return 0; |
235 | } | |
236 | ||
237 | static irqreturn_t dma_controller_irq(int irq, void *private_data) | |
238 | { | |
458e6a51 FB |
239 | struct musb_dma_controller *controller = private_data; |
240 | struct musb *musb = controller->private_data; | |
241 | struct musb_dma_channel *musb_channel; | |
242 | struct dma_channel *channel; | |
243 | ||
244 | void __iomem *mbase = controller->base; | |
245 | ||
550a7375 | 246 | irqreturn_t retval = IRQ_NONE; |
458e6a51 | 247 | |
550a7375 FB |
248 | unsigned long flags; |
249 | ||
458e6a51 FB |
250 | u8 bchannel; |
251 | u8 int_hsdma; | |
252 | ||
f933a0c0 | 253 | u32 addr, count; |
458e6a51 FB |
254 | u16 csr; |
255 | ||
550a7375 FB |
256 | spin_lock_irqsave(&musb->lock, flags); |
257 | ||
258 | int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); | |
550a7375 | 259 | |
6bd03e7b CC |
260 | #ifdef CONFIG_BLACKFIN |
261 | /* Clear DMA interrupt flags */ | |
262 | musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); | |
263 | #endif | |
264 | ||
f933a0c0 AG |
265 | if (!int_hsdma) { |
266 | DBG(2, "spurious DMA irq\n"); | |
267 | ||
268 | for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { | |
269 | musb_channel = (struct musb_dma_channel *) | |
270 | &(controller->channel[bchannel]); | |
271 | channel = &musb_channel->channel; | |
272 | if (channel->status == MUSB_DMA_STATUS_BUSY) { | |
273 | count = musb_read_hsdma_count(mbase, bchannel); | |
274 | ||
275 | if (count == 0) | |
276 | int_hsdma |= (1 << bchannel); | |
277 | } | |
278 | } | |
279 | ||
280 | DBG(2, "int_hsdma = 0x%x\n", int_hsdma); | |
281 | ||
282 | if (!int_hsdma) | |
283 | goto done; | |
284 | } | |
285 | ||
458e6a51 FB |
286 | for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { |
287 | if (int_hsdma & (1 << bchannel)) { | |
288 | musb_channel = (struct musb_dma_channel *) | |
289 | &(controller->channel[bchannel]); | |
290 | channel = &musb_channel->channel; | |
550a7375 FB |
291 | |
292 | csr = musb_readw(mbase, | |
458e6a51 | 293 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, |
550a7375 FB |
294 | MUSB_HSDMA_CONTROL)); |
295 | ||
458e6a51 FB |
296 | if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { |
297 | musb_channel->channel.status = | |
550a7375 | 298 | MUSB_DMA_STATUS_BUS_ABORT; |
458e6a51 | 299 | } else { |
550a7375 FB |
300 | u8 devctl; |
301 | ||
6995eb68 BW |
302 | addr = musb_read_hsdma_addr(mbase, |
303 | bchannel); | |
458e6a51 FB |
304 | channel->actual_len = addr |
305 | - musb_channel->start_addr; | |
550a7375 | 306 | |
32340d3f | 307 | DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", |
458e6a51 FB |
308 | channel, musb_channel->start_addr, |
309 | addr, channel->actual_len, | |
310 | musb_channel->len, | |
311 | (channel->actual_len | |
312 | < musb_channel->len) ? | |
550a7375 FB |
313 | "=> reconfig 0" : "=> complete"); |
314 | ||
315 | devctl = musb_readb(mbase, MUSB_DEVCTL); | |
316 | ||
458e6a51 | 317 | channel->status = MUSB_DMA_STATUS_FREE; |
550a7375 FB |
318 | |
319 | /* completed */ | |
320 | if ((devctl & MUSB_DEVCTL_HM) | |
458e6a51 FB |
321 | && (musb_channel->transmit) |
322 | && ((channel->desired_mode == 0) | |
323 | || (channel->actual_len & | |
324 | (musb_channel->max_packet_sz - 1))) | |
b6e434a5 SS |
325 | ) { |
326 | u8 epnum = musb_channel->epnum; | |
327 | int offset = MUSB_EP_OFFSET(epnum, | |
328 | MUSB_TXCSR); | |
329 | u16 txcsr; | |
330 | ||
331 | /* | |
332 | * The programming guide says that we | |
333 | * must clear DMAENAB before DMAMODE. | |
334 | */ | |
335 | musb_ep_select(mbase, epnum); | |
336 | txcsr = musb_readw(mbase, offset); | |
337 | txcsr &= ~(MUSB_TXCSR_DMAENAB | |
338 | | MUSB_TXCSR_AUTOSET); | |
339 | musb_writew(mbase, offset, txcsr); | |
550a7375 | 340 | /* Send out the packet */ |
b6e434a5 SS |
341 | txcsr &= ~MUSB_TXCSR_DMAMODE; |
342 | txcsr |= MUSB_TXCSR_TXPKTRDY; | |
343 | musb_writew(mbase, offset, txcsr); | |
458e6a51 | 344 | } |
c7bbc056 SS |
345 | musb_dma_completion(musb, musb_channel->epnum, |
346 | musb_channel->transmit); | |
550a7375 FB |
347 | } |
348 | } | |
349 | } | |
6995eb68 | 350 | |
550a7375 FB |
351 | retval = IRQ_HANDLED; |
352 | done: | |
353 | spin_unlock_irqrestore(&musb->lock, flags); | |
354 | return retval; | |
355 | } | |
356 | ||
357 | void dma_controller_destroy(struct dma_controller *c) | |
358 | { | |
458e6a51 FB |
359 | struct musb_dma_controller *controller = container_of(c, |
360 | struct musb_dma_controller, controller); | |
550a7375 | 361 | |
550a7375 FB |
362 | if (!controller) |
363 | return; | |
364 | ||
365 | if (controller->irq) | |
366 | free_irq(controller->irq, c); | |
367 | ||
368 | kfree(controller); | |
369 | } | |
370 | ||
371 | struct dma_controller *__init | |
458e6a51 | 372 | dma_controller_create(struct musb *musb, void __iomem *base) |
550a7375 FB |
373 | { |
374 | struct musb_dma_controller *controller; | |
375 | struct device *dev = musb->controller; | |
376 | struct platform_device *pdev = to_platform_device(dev); | |
377 | int irq = platform_get_irq(pdev, 1); | |
378 | ||
379 | if (irq == 0) { | |
380 | dev_err(dev, "No DMA interrupt line!\n"); | |
381 | return NULL; | |
382 | } | |
383 | ||
458e6a51 | 384 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
550a7375 FB |
385 | if (!controller) |
386 | return NULL; | |
387 | ||
458e6a51 FB |
388 | controller->channel_count = MUSB_HSDMA_CHANNELS; |
389 | controller->private_data = musb; | |
390 | controller->base = base; | |
550a7375 | 391 | |
458e6a51 FB |
392 | controller->controller.start = dma_controller_start; |
393 | controller->controller.stop = dma_controller_stop; | |
394 | controller->controller.channel_alloc = dma_channel_allocate; | |
395 | controller->controller.channel_release = dma_channel_release; | |
396 | controller->controller.channel_program = dma_channel_program; | |
397 | controller->controller.channel_abort = dma_channel_abort; | |
550a7375 FB |
398 | |
399 | if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, | |
427c4f33 | 400 | dev_name(musb->controller), &controller->controller)) { |
550a7375 | 401 | dev_err(dev, "request_irq %d failed!\n", irq); |
458e6a51 FB |
402 | dma_controller_destroy(&controller->controller); |
403 | ||
550a7375 FB |
404 | return NULL; |
405 | } | |
406 | ||
407 | controller->irq = irq; | |
408 | ||
458e6a51 | 409 | return &controller->controller; |
550a7375 | 410 | } |