[net-next-2.6.git] / drivers / usb / musb / musbhsdma.c

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include "musb_core.h"

#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
#include "omap2430.h"
#endif

#define MUSB_HSDMA_BASE		0x200
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x4
#define MUSB_HSDMA_ADDRESS		0x8
#define MUSB_HSDMA_COUNT		0xc

#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)

/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT		0
#define MUSB_HSDMA_TRANSMIT_SHIFT		1
#define MUSB_HSDMA_MODE1_SHIFT		2
#define MUSB_HSDMA_IRQENABLE_SHIFT		3
#define MUSB_HSDMA_ENDPOINT_SHIFT		4
#define MUSB_HSDMA_BUSERROR_SHIFT		8
#define MUSB_HSDMA_BURSTMODE_SHIFT		9
#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MUSB_HSDMA_BURSTMODE_UNSPEC	0
#define MUSB_HSDMA_BURSTMODE_INCR4	1
#define MUSB_HSDMA_BURSTMODE_INCR8	2
#define MUSB_HSDMA_BURSTMODE_INCR16	3

#define MUSB_HSDMA_CHANNELS		8

struct musb_dma_controller;

struct musb_dma_channel {
	struct dma_channel		channel;
	struct musb_dma_controller	*controller;
	u32				start_addr;
	u32				len;
	u16				max_packet_sz;
	u8				idx;
	u8				epnum;
	u8				transmit;
};

struct musb_dma_controller {
	struct dma_controller		controller;
	struct musb_dma_channel		channel[MUSB_HSDMA_CHANNELS];
	void				*private_data;
	void __iomem			*base;
	u8				channel_count;
	u8				used_channels;
	u8				irq;
};

static int dma_controller_start(struct dma_controller *c)
{
	/* nothing to do */
	return 0;
}

static void dma_channel_release(struct dma_channel *channel);

static int dma_controller_stop(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb *musb = controller->private_data;
	struct dma_channel *channel;
	u8 bit;

	if (controller->used_channels != 0) {
		dev_err(musb->controller,
			"Stopping DMA controller while channel active\n");

		for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
			if (controller->used_channels & (1 << bit)) {
				channel = &controller->channel[bit].channel;
				dma_channel_release(channel);

				if (!controller->used_channels)
					break;
			}
		}
	}

	return 0;
}

static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 transmit)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb_dma_channel *musb_channel = NULL;
	struct dma_channel *channel = NULL;
	u8 bit;

	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
		if (!(controller->used_channels & (1 << bit))) {
			controller->used_channels |= (1 << bit);
			musb_channel = &(controller->channel[bit]);
			musb_channel->controller = controller;
			musb_channel->idx = bit;
			musb_channel->epnum = hw_ep->epnum;
			musb_channel->transmit = transmit;
			channel = &(musb_channel->channel);
			channel->private_data = musb_channel;
			channel->status = MUSB_DMA_STATUS_FREE;
			channel->max_len = 0x10000;
			/* Tx => mode 1; Rx => mode 0 */
			channel->desired_mode = transmit;
			channel->actual_len = 0;
			break;
		}
	}

	return channel;
}

static void dma_channel_release(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	channel->actual_len = 0;
	musb_channel->start_addr = 0;
	musb_channel->len = 0;

	musb_channel->controller->used_channels &=
		~(1 << musb_channel->idx);

	channel->status = MUSB_DMA_STATUS_UNKNOWN;
}

static void configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	void __iomem *mbase = controller->base;
	u8 bchannel = musb_channel->idx;
	u16 csr = 0;

	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
			channel, packet_sz, dma_addr, len, mode);

	if (mode) {
		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
		BUG_ON(len < packet_sz);

		if (packet_sz >= 64) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR16
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		} else if (packet_sz >= 32) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR8
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		} else if (packet_sz >= 16) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR4
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		}
	}

	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
		| (musb_channel->transmit
				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
				: 0);

	/* address/count */
	musb_writel(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
		dma_addr);
	musb_writel(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
		len);

	/* control (this should start things) */
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
		csr);
}

static int dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
		musb_channel->epnum,
		musb_channel->transmit ? "Tx" : "Rx",
		packet_sz, dma_addr, len, mode);

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	channel->actual_len = 0;
	musb_channel->start_addr = dma_addr;
	musb_channel->len = len;
	musb_channel->max_packet_sz = packet_sz;
	channel->status = MUSB_DMA_STATUS_BUSY;

	if ((mode == 1) && (len >= packet_sz))
		configure_channel(channel, packet_sz, 1, dma_addr, len);
	else
		configure_channel(channel, packet_sz, 0, dma_addr, len);

	return true;
}

static int dma_channel_abort(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	void __iomem *mbase = musb_channel->controller->base;

	u8 bchannel = musb_channel->idx;
	u16 csr;

	if (channel->status == MUSB_DMA_STATUS_BUSY) {
		if (musb_channel->transmit) {

			csr = musb_readw(mbase,
				MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_TXCSR));
			csr &= ~(MUSB_TXCSR_AUTOSET |
				 MUSB_TXCSR_DMAENAB |
				 MUSB_TXCSR_DMAMODE);
			musb_writew(mbase,
				MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
				csr);
		} else {
			csr = musb_readw(mbase,
				MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_RXCSR));
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(mbase,
				MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
				csr);
		}

		musb_writew(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
			0);
		musb_writel(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
			0);
		musb_writel(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
			0);

		channel->status = MUSB_DMA_STATUS_FREE;
	}

	return 0;
}

static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
	struct musb_dma_controller *controller = private_data;
	struct musb *musb = controller->private_data;
	struct musb_dma_channel *musb_channel;
	struct dma_channel *channel;

	void __iomem *mbase = controller->base;

	irqreturn_t retval = IRQ_NONE;

	unsigned long flags;

	u8 bchannel;
	u8 int_hsdma;

	u32 addr;
	u16 csr;

	spin_lock_irqsave(&musb->lock, flags);

	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
	if (!int_hsdma)
		goto done;

	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
		if (int_hsdma & (1 << bchannel)) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;

			csr = musb_readw(mbase,
					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
							MUSB_HSDMA_CONTROL));

			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
				musb_channel->channel.status =
					MUSB_DMA_STATUS_BUS_ABORT;
			} else {
				u8 devctl;

				addr = musb_readl(mbase,
						MUSB_HSDMA_CHANNEL_OFFSET(
							bchannel,
							MUSB_HSDMA_ADDRESS));
				channel->actual_len = addr
					- musb_channel->start_addr;

				DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
					channel, musb_channel->start_addr,
					addr, channel->actual_len,
					musb_channel->len,
					(channel->actual_len
						< musb_channel->len) ?
					"=> reconfig 0" : "=> complete");

				devctl = musb_readb(mbase, MUSB_DEVCTL);

				channel->status = MUSB_DMA_STATUS_FREE;

				/* completed */
				if ((devctl & MUSB_DEVCTL_HM)
					&& (musb_channel->transmit)
					&& ((channel->desired_mode == 0)
					    || (channel->actual_len &
					    (musb_channel->max_packet_sz - 1)))
					 ) {
					/* Send out the packet */
					musb_ep_select(mbase,
						musb_channel->epnum);
					musb_writew(mbase, MUSB_EP_OFFSET(
							musb_channel->epnum,
							MUSB_TXCSR),
						MUSB_TXCSR_TXPKTRDY);
				} else {
					musb_dma_completion(
						musb,
						musb_channel->epnum,
						musb_channel->transmit);
				}
			}
		}
	}
	retval = IRQ_HANDLED;
done:
	spin_unlock_irqrestore(&musb->lock, flags);
	return retval;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);

	if (!controller)
		return;

	if (controller->irq)
		free_irq(controller->irq, c);

	kfree(controller);
}

struct dma_controller *__init
dma_controller_create(struct musb *musb, void __iomem *base)
{
	struct musb_dma_controller *controller;
	struct device *dev = musb->controller;
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq(pdev, 1);

	if (irq == 0) {
		dev_err(dev, "No DMA interrupt line!\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		return NULL;

	controller->channel_count = MUSB_HSDMA_CHANNELS;
	controller->private_data = musb;
	controller->base = base;

	controller->controller.start = dma_controller_start;
	controller->controller.stop = dma_controller_stop;
	controller->controller.channel_alloc = dma_channel_allocate;
	controller->controller.channel_release = dma_channel_release;
	controller->controller.channel_program = dma_channel_program;
	controller->controller.channel_abort = dma_channel_abort;

	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
			musb->controller->bus_id, &controller->controller)) {
		dev_err(dev, "request_irq %d failed!\n", irq);
		dma_controller_destroy(&controller->controller);

		return NULL;
	}

	controller->irq = irq;

	return &controller->controller;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33	#include <linux/device.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/platform_device.h>
	36	#include "musb_core.h"
	37
	38	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP3430)
	39	#include "omap2430.h"
	40	#endif
	41
	42	#define MUSB_HSDMA_BASE 0x200
	43	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	44	#define MUSB_HSDMA_CONTROL 0x4
	45	#define MUSB_HSDMA_ADDRESS 0x8
	46	#define MUSB_HSDMA_COUNT 0xc
	47
458e6a51 FB	48	#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
458e6a51 FB	49	(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
550a7375 FB	50
	51	/* control register (16-bit): */
	52	#define MUSB_HSDMA_ENABLE_SHIFT 0
	53	#define MUSB_HSDMA_TRANSMIT_SHIFT 1
	54	#define MUSB_HSDMA_MODE1_SHIFT 2
	55	#define MUSB_HSDMA_IRQENABLE_SHIFT 3
	56	#define MUSB_HSDMA_ENDPOINT_SHIFT 4
	57	#define MUSB_HSDMA_BUSERROR_SHIFT 8
	58	#define MUSB_HSDMA_BURSTMODE_SHIFT 9
	59	#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
	60	#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
	61	#define MUSB_HSDMA_BURSTMODE_INCR4 1
	62	#define MUSB_HSDMA_BURSTMODE_INCR8 2
	63	#define MUSB_HSDMA_BURSTMODE_INCR16 3
	64
	65	#define MUSB_HSDMA_CHANNELS 8
	66
	67	struct musb_dma_controller;
	68
	69	struct musb_dma_channel {
458e6a51	70	struct dma_channel channel;
550a7375	71	struct musb_dma_controller *controller;
458e6a51	72	u32 start_addr;
550a7375	73	u32 len;
458e6a51 FB	74	u16 max_packet_sz;
458e6a51 FB	75	u8 idx;
550a7375 FB	76	u8 epnum;
	77	u8 transmit;
	78	};
	79
	80	struct musb_dma_controller {
458e6a51 FB	81	struct dma_controller controller;
	82	struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
	83	void *private_data;
	84	void __iomem *base;
	85	u8 channel_count;
	86	u8 used_channels;
550a7375 FB	87	u8 irq;
	88	};
	89
	90	static int dma_controller_start(struct dma_controller *c)
	91	{
	92	/* nothing to do */
	93	return 0;
	94	}
	95
458e6a51	96	static void dma_channel_release(struct dma_channel *channel);
550a7375 FB	97
	98	static int dma_controller_stop(struct dma_controller *c)
	99	{
458e6a51 FB	100	struct musb_dma_controller *controller = container_of(c,
	101	struct musb_dma_controller, controller);
	102	struct musb *musb = controller->private_data;
	103	struct dma_channel *channel;
	104	u8 bit;
550a7375	105
458e6a51	106	if (controller->used_channels != 0) {
550a7375 FB	107	dev_err(musb->controller,
	108	"Stopping DMA controller while channel active\n");
	109
458e6a51 FB	110	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	111	if (controller->used_channels & (1 << bit)) {
	112	channel = &controller->channel[bit].channel;
	113	dma_channel_release(channel);
550a7375	114
458e6a51	115	if (!controller->used_channels)
550a7375 FB	116	break;
	117	}
	118	}
	119	}
458e6a51	120
550a7375 FB	121	return 0;
	122	}
	123
	124	static struct dma_channel dma_channel_allocate(struct dma_controller c,
	125	struct musb_hw_ep *hw_ep, u8 transmit)
	126	{
458e6a51 FB	127	struct musb_dma_controller *controller = container_of(c,
	128	struct musb_dma_controller, controller);
	129	struct musb_dma_channel *musb_channel = NULL;
	130	struct dma_channel *channel = NULL;
	131	u8 bit;
	132
	133	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	134	if (!(controller->used_channels & (1 << bit))) {
	135	controller->used_channels \|= (1 << bit);
	136	musb_channel = &(controller->channel[bit]);
	137	musb_channel->controller = controller;
	138	musb_channel->idx = bit;
	139	musb_channel->epnum = hw_ep->epnum;
	140	musb_channel->transmit = transmit;
	141	channel = &(musb_channel->channel);
	142	channel->private_data = musb_channel;
	143	channel->status = MUSB_DMA_STATUS_FREE;
	144	channel->max_len = 0x10000;
550a7375	145	/* Tx => mode 1; Rx => mode 0 */
458e6a51 FB	146	channel->desired_mode = transmit;
458e6a51 FB	147	channel->actual_len = 0;
550a7375 FB	148	break;
	149	}
	150	}
458e6a51 FB	151
458e6a51 FB	152	return channel;
550a7375 FB	153	}
550a7375 FB	154
458e6a51	155	static void dma_channel_release(struct dma_channel *channel)
550a7375	156	{
458e6a51	157	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375	158
458e6a51 FB	159	channel->actual_len = 0;
	160	musb_channel->start_addr = 0;
	161	musb_channel->len = 0;
550a7375	162
458e6a51 FB	163	musb_channel->controller->used_channels &=
458e6a51 FB	164	~(1 << musb_channel->idx);
550a7375	165
458e6a51	166	channel->status = MUSB_DMA_STATUS_UNKNOWN;
550a7375 FB	167	}
550a7375 FB	168
458e6a51	169	static void configure_channel(struct dma_channel *channel,
550a7375 FB	170	u16 packet_sz, u8 mode,
	171	dma_addr_t dma_addr, u32 len)
	172	{
458e6a51 FB	173	struct musb_dma_channel *musb_channel = channel->private_data;
	174	struct musb_dma_controller *controller = musb_channel->controller;
	175	void __iomem *mbase = controller->base;
	176	u8 bchannel = musb_channel->idx;
550a7375 FB	177	u16 csr = 0;
	178
	179	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
458e6a51	180	channel, packet_sz, dma_addr, len, mode);
550a7375 FB	181
	182	if (mode) {
	183	csr \|= 1 << MUSB_HSDMA_MODE1_SHIFT;
	184	BUG_ON(len < packet_sz);
	185
	186	if (packet_sz >= 64) {
	187	csr \|= MUSB_HSDMA_BURSTMODE_INCR16
	188	<< MUSB_HSDMA_BURSTMODE_SHIFT;
	189	} else if (packet_sz >= 32) {
	190	csr \|= MUSB_HSDMA_BURSTMODE_INCR8
	191	<< MUSB_HSDMA_BURSTMODE_SHIFT;
	192	} else if (packet_sz >= 16) {
	193	csr \|= MUSB_HSDMA_BURSTMODE_INCR4
	194	<< MUSB_HSDMA_BURSTMODE_SHIFT;
	195	}
	196	}
	197
458e6a51	198	csr \|= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
550a7375 FB	199	\| (1 << MUSB_HSDMA_ENABLE_SHIFT)
550a7375 FB	200	\| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
458e6a51	201	\| (musb_channel->transmit
550a7375 FB	202	? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
	203	: 0);
	204
	205	/* address/count */
	206	musb_writel(mbase,
458e6a51	207	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
550a7375 FB	208	dma_addr);
550a7375 FB	209	musb_writel(mbase,
458e6a51	210	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
550a7375 FB	211	len);
	212
	213	/* control (this should start things) */
	214	musb_writew(mbase,
458e6a51	215	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375 FB	216	csr);
	217	}
	218
458e6a51	219	static int dma_channel_program(struct dma_channel *channel,
550a7375 FB	220	u16 packet_sz, u8 mode,
	221	dma_addr_t dma_addr, u32 len)
	222	{
458e6a51	223	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375 FB	224
550a7375 FB	225	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
458e6a51 FB	226	musb_channel->epnum,
458e6a51 FB	227	musb_channel->transmit ? "Tx" : "Rx",
550a7375 FB	228	packet_sz, dma_addr, len, mode);
550a7375 FB	229
458e6a51 FB	230	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
458e6a51 FB	231	channel->status == MUSB_DMA_STATUS_BUSY);
550a7375	232
458e6a51 FB	233	channel->actual_len = 0;
	234	musb_channel->start_addr = dma_addr;
	235	musb_channel->len = len;
	236	musb_channel->max_packet_sz = packet_sz;
	237	channel->status = MUSB_DMA_STATUS_BUSY;
550a7375 FB	238
550a7375 FB	239	if ((mode == 1) && (len >= packet_sz))
458e6a51	240	configure_channel(channel, packet_sz, 1, dma_addr, len);
550a7375	241	else
458e6a51	242	configure_channel(channel, packet_sz, 0, dma_addr, len);
550a7375 FB	243
	244	return true;
	245	}
	246
458e6a51	247	static int dma_channel_abort(struct dma_channel *channel)
550a7375	248	{
458e6a51 FB	249	struct musb_dma_channel *musb_channel = channel->private_data;
	250	void __iomem *mbase = musb_channel->controller->base;
	251
	252	u8 bchannel = musb_channel->idx;
550a7375 FB	253	u16 csr;
550a7375 FB	254
458e6a51 FB	255	if (channel->status == MUSB_DMA_STATUS_BUSY) {
458e6a51 FB	256	if (musb_channel->transmit) {
550a7375 FB	257
550a7375 FB	258	csr = musb_readw(mbase,
458e6a51	259	MUSB_EP_OFFSET(musb_channel->epnum,
550a7375 FB	260	MUSB_TXCSR));
	261	csr &= ~(MUSB_TXCSR_AUTOSET \|
	262	MUSB_TXCSR_DMAENAB \|
	263	MUSB_TXCSR_DMAMODE);
	264	musb_writew(mbase,
458e6a51	265	MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
550a7375 FB	266	csr);
	267	} else {
	268	csr = musb_readw(mbase,
458e6a51	269	MUSB_EP_OFFSET(musb_channel->epnum,
550a7375 FB	270	MUSB_RXCSR));
	271	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
	272	MUSB_RXCSR_DMAENAB \|
	273	MUSB_RXCSR_DMAMODE);
	274	musb_writew(mbase,
458e6a51	275	MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
550a7375 FB	276	csr);
	277	}
	278
	279	musb_writew(mbase,
458e6a51	280	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375 FB	281	0);
550a7375 FB	282	musb_writel(mbase,
458e6a51	283	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
550a7375 FB	284	0);
550a7375 FB	285	musb_writel(mbase,
458e6a51	286	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
550a7375 FB	287	0);
550a7375 FB	288
458e6a51	289	channel->status = MUSB_DMA_STATUS_FREE;
550a7375	290	}
458e6a51	291
550a7375 FB	292	return 0;
	293	}
	294
	295	static irqreturn_t dma_controller_irq(int irq, void *private_data)
	296	{
458e6a51 FB	297	struct musb_dma_controller *controller = private_data;
	298	struct musb *musb = controller->private_data;
	299	struct musb_dma_channel *musb_channel;
	300	struct dma_channel *channel;
	301
	302	void __iomem *mbase = controller->base;
	303
550a7375	304	irqreturn_t retval = IRQ_NONE;
458e6a51	305
550a7375 FB	306	unsigned long flags;
550a7375 FB	307
458e6a51 FB	308	u8 bchannel;
	309	u8 int_hsdma;
	310
	311	u32 addr;
	312	u16 csr;
	313
550a7375 FB	314	spin_lock_irqsave(&musb->lock, flags);
	315
	316	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
	317	if (!int_hsdma)
	318	goto done;
	319
458e6a51 FB	320	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	321	if (int_hsdma & (1 << bchannel)) {
	322	musb_channel = (struct musb_dma_channel *)
	323	&(controller->channel[bchannel]);
	324	channel = &musb_channel->channel;
550a7375 FB	325
550a7375 FB	326	csr = musb_readw(mbase,
458e6a51	327	MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
550a7375 FB	328	MUSB_HSDMA_CONTROL));
550a7375 FB	329
458e6a51 FB	330	if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
458e6a51 FB	331	musb_channel->channel.status =
550a7375	332	MUSB_DMA_STATUS_BUS_ABORT;
458e6a51	333	} else {
550a7375 FB	334	u8 devctl;
550a7375 FB	335
458e6a51	336	addr = musb_readl(mbase,
550a7375	337	MUSB_HSDMA_CHANNEL_OFFSET(
458e6a51	338	bchannel,
550a7375	339	MUSB_HSDMA_ADDRESS));
458e6a51 FB	340	channel->actual_len = addr
458e6a51 FB	341	- musb_channel->start_addr;
550a7375 FB	342
550a7375 FB	343	DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
458e6a51 FB	344	channel, musb_channel->start_addr,
	345	addr, channel->actual_len,
	346	musb_channel->len,
	347	(channel->actual_len
	348	< musb_channel->len) ?
550a7375 FB	349	"=> reconfig 0" : "=> complete");
	350
	351	devctl = musb_readb(mbase, MUSB_DEVCTL);
	352
458e6a51	353	channel->status = MUSB_DMA_STATUS_FREE;
550a7375 FB	354
	355	/* completed */
	356	if ((devctl & MUSB_DEVCTL_HM)
458e6a51 FB	357	&& (musb_channel->transmit)
	358	&& ((channel->desired_mode == 0)
	359	\|\| (channel->actual_len &
	360	(musb_channel->max_packet_sz - 1)))
550a7375 FB	361	) {
	362	/* Send out the packet */
	363	musb_ep_select(mbase,
458e6a51	364	musb_channel->epnum);
550a7375	365	musb_writew(mbase, MUSB_EP_OFFSET(
458e6a51	366	musb_channel->epnum,
550a7375 FB	367	MUSB_TXCSR),
550a7375 FB	368	MUSB_TXCSR_TXPKTRDY);
458e6a51	369	} else {
550a7375 FB	370	musb_dma_completion(
550a7375 FB	371	musb,
458e6a51 FB	372	musb_channel->epnum,
	373	musb_channel->transmit);
	374	}
550a7375 FB	375	}
	376	}
	377	}
	378	retval = IRQ_HANDLED;
	379	done:
	380	spin_unlock_irqrestore(&musb->lock, flags);
	381	return retval;
	382	}
	383
	384	void dma_controller_destroy(struct dma_controller *c)
	385	{
458e6a51 FB	386	struct musb_dma_controller *controller = container_of(c,
458e6a51 FB	387	struct musb_dma_controller, controller);
550a7375	388
550a7375 FB	389	if (!controller)
	390	return;
	391
	392	if (controller->irq)
	393	free_irq(controller->irq, c);
	394
	395	kfree(controller);
	396	}
	397
	398	struct dma_controller *__init
458e6a51	399	dma_controller_create(struct musb musb, void __iomem base)
550a7375 FB	400	{
	401	struct musb_dma_controller *controller;
	402	struct device *dev = musb->controller;
	403	struct platform_device *pdev = to_platform_device(dev);
	404	int irq = platform_get_irq(pdev, 1);
	405
	406	if (irq == 0) {
	407	dev_err(dev, "No DMA interrupt line!\n");
	408	return NULL;
	409	}
	410
458e6a51	411	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
550a7375 FB	412	if (!controller)
	413	return NULL;
	414
458e6a51 FB	415	controller->channel_count = MUSB_HSDMA_CHANNELS;
	416	controller->private_data = musb;
	417	controller->base = base;
550a7375	418
458e6a51 FB	419	controller->controller.start = dma_controller_start;
	420	controller->controller.stop = dma_controller_stop;
	421	controller->controller.channel_alloc = dma_channel_allocate;
	422	controller->controller.channel_release = dma_channel_release;
	423	controller->controller.channel_program = dma_channel_program;
	424	controller->controller.channel_abort = dma_channel_abort;
550a7375 FB	425
550a7375 FB	426	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
458e6a51	427	musb->controller->bus_id, &controller->controller)) {
550a7375	428	dev_err(dev, "request_irq %d failed!\n", irq);
458e6a51 FB	429	dma_controller_destroy(&controller->controller);
458e6a51 FB	430
550a7375 FB	431	return NULL;
	432	}
	433
	434	controller->irq = irq;
	435
458e6a51	436	return &controller->controller;
550a7375	437	}