[net-next-2.6.git] / drivers / usb / musb / musbhsdma.c

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include "musb_core.h"
#include "musbhsdma.h"

static int dma_controller_start(struct dma_controller *c)
{
	/* nothing to do */
	return 0;
}

static void dma_channel_release(struct dma_channel *channel);

static int dma_controller_stop(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb *musb = controller->private_data;
	struct dma_channel *channel;
	u8 bit;

	if (controller->used_channels != 0) {
		dev_err(musb->controller,
			"Stopping DMA controller while channel active\n");

		for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
			if (controller->used_channels & (1 << bit)) {
				channel = &controller->channel[bit].channel;
				dma_channel_release(channel);

				if (!controller->used_channels)
					break;
			}
		}
	}

	return 0;
}

static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 transmit)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb_dma_channel *musb_channel = NULL;
	struct dma_channel *channel = NULL;
	u8 bit;

	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
		if (!(controller->used_channels & (1 << bit))) {
			controller->used_channels |= (1 << bit);
			musb_channel = &(controller->channel[bit]);
			musb_channel->controller = controller;
			musb_channel->idx = bit;
			musb_channel->epnum = hw_ep->epnum;
			musb_channel->transmit = transmit;
			channel = &(musb_channel->channel);
			channel->private_data = musb_channel;
			channel->status = MUSB_DMA_STATUS_FREE;
			channel->max_len = 0x10000;
			/* Tx => mode 1; Rx => mode 0 */
			channel->desired_mode = transmit;
			channel->actual_len = 0;
			break;
		}
	}

	return channel;
}

static void dma_channel_release(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	channel->actual_len = 0;
	musb_channel->start_addr = 0;
	musb_channel->len = 0;

	musb_channel->controller->used_channels &=
		~(1 << musb_channel->idx);

	channel->status = MUSB_DMA_STATUS_UNKNOWN;
}

static void configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	void __iomem *mbase = controller->base;
	u8 bchannel = musb_channel->idx;
	u16 csr = 0;

	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
			channel, packet_sz, dma_addr, len, mode);

	if (mode) {
		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
		BUG_ON(len < packet_sz);

		if (packet_sz >= 64) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR16
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		} else if (packet_sz >= 32) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR8
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		} else if (packet_sz >= 16) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR4
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		}
	}

	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
		| (musb_channel->transmit
				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
				: 0);

	/* address/count */
	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
	musb_write_hsdma_count(mbase, bchannel, len);

	/* control (this should start things) */
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
		csr);
}

static int dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
		musb_channel->epnum,
		musb_channel->transmit ? "Tx" : "Rx",
		packet_sz, dma_addr, len, mode);

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	channel->actual_len = 0;
	musb_channel->start_addr = dma_addr;
	musb_channel->len = len;
	musb_channel->max_packet_sz = packet_sz;
	channel->status = MUSB_DMA_STATUS_BUSY;

	if ((mode == 1) && (len >= packet_sz))
		configure_channel(channel, packet_sz, 1, dma_addr, len);
	else
		configure_channel(channel, packet_sz, 0, dma_addr, len);

	return true;
}

static int dma_channel_abort(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	void __iomem *mbase = musb_channel->controller->base;

	u8 bchannel = musb_channel->idx;
	int offset;
	u16 csr;

	if (channel->status == MUSB_DMA_STATUS_BUSY) {
		if (musb_channel->transmit) {
			offset = MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_TXCSR);

			/*
			 * The programming guide says that we must clear
			 * the DMAENAB bit before the DMAMODE bit...
			 */
			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
			musb_writew(mbase, offset, csr);
			csr &= ~MUSB_TXCSR_DMAMODE;
			musb_writew(mbase, offset, csr);
		} else {
			offset = MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_RXCSR);

			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(mbase, offset, csr);
		}

		musb_writew(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
			0);
		musb_write_hsdma_addr(mbase, bchannel, 0);
		musb_write_hsdma_count(mbase, bchannel, 0);
		channel->status = MUSB_DMA_STATUS_FREE;
	}

	return 0;
}

static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
	struct musb_dma_controller *controller = private_data;
	struct musb *musb = controller->private_data;
	struct musb_dma_channel *musb_channel;
	struct dma_channel *channel;

	void __iomem *mbase = controller->base;

	irqreturn_t retval = IRQ_NONE;

	unsigned long flags;

	u8 bchannel;
	u8 int_hsdma;

	u32 addr;
	u16 csr;

	spin_lock_irqsave(&musb->lock, flags);

	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
	if (!int_hsdma)
		goto done;

	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
		if (int_hsdma & (1 << bchannel)) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;

			csr = musb_readw(mbase,
					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
							MUSB_HSDMA_CONTROL));

			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
				musb_channel->channel.status =
					MUSB_DMA_STATUS_BUS_ABORT;
			} else {
				u8 devctl;

				addr = musb_read_hsdma_addr(mbase,
						bchannel);
				channel->actual_len = addr
					- musb_channel->start_addr;

				DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
					channel, musb_channel->start_addr,
					addr, channel->actual_len,
					musb_channel->len,
					(channel->actual_len
						< musb_channel->len) ?
					"=> reconfig 0" : "=> complete");

				devctl = musb_readb(mbase, MUSB_DEVCTL);

				channel->status = MUSB_DMA_STATUS_FREE;

				/* completed */
				if ((devctl & MUSB_DEVCTL_HM)
					&& (musb_channel->transmit)
					&& ((channel->desired_mode == 0)
					    || (channel->actual_len &
					    (musb_channel->max_packet_sz - 1)))
				    ) {
					u8  epnum  = musb_channel->epnum;
					int offset = MUSB_EP_OFFSET(epnum,
								    MUSB_TXCSR);
					u16 txcsr;

					/*
					 * The programming guide says that we
					 * must clear DMAENAB before DMAMODE.
					 */
					musb_ep_select(mbase, epnum);
					txcsr = musb_readw(mbase, offset);
					txcsr &= ~(MUSB_TXCSR_DMAENAB
							| MUSB_TXCSR_AUTOSET);
					musb_writew(mbase, offset, txcsr);
					/* Send out the packet */
					txcsr &= ~MUSB_TXCSR_DMAMODE;
					txcsr |=  MUSB_TXCSR_TXPKTRDY;
					musb_writew(mbase, offset, txcsr);
				}
				musb_dma_completion(musb, musb_channel->epnum,
						    musb_channel->transmit);
			}
		}
	}

#ifdef CONFIG_BLACKFIN
	/* Clear DMA interrup flags */
	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
#endif

	retval = IRQ_HANDLED;
done:
	spin_unlock_irqrestore(&musb->lock, flags);
	return retval;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);

	if (!controller)
		return;

	if (controller->irq)
		free_irq(controller->irq, c);

	kfree(controller);
}

struct dma_controller *__init
dma_controller_create(struct musb *musb, void __iomem *base)
{
	struct musb_dma_controller *controller;
	struct device *dev = musb->controller;
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq(pdev, 1);

	if (irq == 0) {
		dev_err(dev, "No DMA interrupt line!\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		return NULL;

	controller->channel_count = MUSB_HSDMA_CHANNELS;
	controller->private_data = musb;
	controller->base = base;

	controller->controller.start = dma_controller_start;
	controller->controller.stop = dma_controller_stop;
	controller->controller.channel_alloc = dma_channel_allocate;
	controller->controller.channel_release = dma_channel_release;
	controller->controller.channel_program = dma_channel_program;
	controller->controller.channel_abort = dma_channel_abort;

	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
			dev_name(musb->controller), &controller->controller)) {
		dev_err(dev, "request_irq %d failed!\n", irq);
		dma_controller_destroy(&controller->controller);

		return NULL;
	}

	controller->irq = irq;

	return &controller->controller;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33	#include <linux/device.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/platform_device.h>
	36	#include "musb_core.h"
6995eb68	37	#include "musbhsdma.h"
550a7375 FB	38
	39	static int dma_controller_start(struct dma_controller *c)
	40	{
	41	/* nothing to do */
	42	return 0;
	43	}
	44
458e6a51	45	static void dma_channel_release(struct dma_channel *channel);
550a7375 FB	46
	47	static int dma_controller_stop(struct dma_controller *c)
	48	{
458e6a51 FB	49	struct musb_dma_controller *controller = container_of(c,
	50	struct musb_dma_controller, controller);
	51	struct musb *musb = controller->private_data;
	52	struct dma_channel *channel;
	53	u8 bit;
550a7375	54
458e6a51	55	if (controller->used_channels != 0) {
550a7375 FB	56	dev_err(musb->controller,
	57	"Stopping DMA controller while channel active\n");
	58
458e6a51 FB	59	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	60	if (controller->used_channels & (1 << bit)) {
	61	channel = &controller->channel[bit].channel;
	62	dma_channel_release(channel);
550a7375	63
458e6a51	64	if (!controller->used_channels)
550a7375 FB	65	break;
	66	}
	67	}
	68	}
458e6a51	69
550a7375 FB	70	return 0;
	71	}
	72
	73	static struct dma_channel dma_channel_allocate(struct dma_controller c,
	74	struct musb_hw_ep *hw_ep, u8 transmit)
	75	{
458e6a51 FB	76	struct musb_dma_controller *controller = container_of(c,
	77	struct musb_dma_controller, controller);
	78	struct musb_dma_channel *musb_channel = NULL;
	79	struct dma_channel *channel = NULL;
	80	u8 bit;
	81
	82	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	83	if (!(controller->used_channels & (1 << bit))) {
	84	controller->used_channels \|= (1 << bit);
	85	musb_channel = &(controller->channel[bit]);
	86	musb_channel->controller = controller;
	87	musb_channel->idx = bit;
	88	musb_channel->epnum = hw_ep->epnum;
	89	musb_channel->transmit = transmit;
	90	channel = &(musb_channel->channel);
	91	channel->private_data = musb_channel;
	92	channel->status = MUSB_DMA_STATUS_FREE;
	93	channel->max_len = 0x10000;
550a7375	94	/* Tx => mode 1; Rx => mode 0 */
458e6a51 FB	95	channel->desired_mode = transmit;
458e6a51 FB	96	channel->actual_len = 0;
550a7375 FB	97	break;
	98	}
	99	}
458e6a51 FB	100
458e6a51 FB	101	return channel;
550a7375 FB	102	}
550a7375 FB	103
458e6a51	104	static void dma_channel_release(struct dma_channel *channel)
550a7375	105	{
458e6a51	106	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375	107
458e6a51 FB	108	channel->actual_len = 0;
	109	musb_channel->start_addr = 0;
	110	musb_channel->len = 0;
550a7375	111
458e6a51 FB	112	musb_channel->controller->used_channels &=
458e6a51 FB	113	~(1 << musb_channel->idx);
550a7375	114
458e6a51	115	channel->status = MUSB_DMA_STATUS_UNKNOWN;
550a7375 FB	116	}
550a7375 FB	117
458e6a51	118	static void configure_channel(struct dma_channel *channel,
550a7375 FB	119	u16 packet_sz, u8 mode,
	120	dma_addr_t dma_addr, u32 len)
	121	{
458e6a51 FB	122	struct musb_dma_channel *musb_channel = channel->private_data;
	123	struct musb_dma_controller *controller = musb_channel->controller;
	124	void __iomem *mbase = controller->base;
	125	u8 bchannel = musb_channel->idx;
550a7375 FB	126	u16 csr = 0;
	127
	128	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
458e6a51	129	channel, packet_sz, dma_addr, len, mode);
550a7375 FB	130
	131	if (mode) {
	132	csr \|= 1 << MUSB_HSDMA_MODE1_SHIFT;
	133	BUG_ON(len < packet_sz);
	134
	135	if (packet_sz >= 64) {
	136	csr \|= MUSB_HSDMA_BURSTMODE_INCR16
	137	<< MUSB_HSDMA_BURSTMODE_SHIFT;
	138	} else if (packet_sz >= 32) {
	139	csr \|= MUSB_HSDMA_BURSTMODE_INCR8
	140	<< MUSB_HSDMA_BURSTMODE_SHIFT;
	141	} else if (packet_sz >= 16) {
	142	csr \|= MUSB_HSDMA_BURSTMODE_INCR4
	143	<< MUSB_HSDMA_BURSTMODE_SHIFT;
	144	}
	145	}
	146
458e6a51	147	csr \|= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
550a7375 FB	148	\| (1 << MUSB_HSDMA_ENABLE_SHIFT)
550a7375 FB	149	\| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
458e6a51	150	\| (musb_channel->transmit
550a7375 FB	151	? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
	152	: 0);
	153
	154	/* address/count */
6995eb68 BW	155	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
6995eb68 BW	156	musb_write_hsdma_count(mbase, bchannel, len);
550a7375 FB	157
	158	/* control (this should start things) */
	159	musb_writew(mbase,
458e6a51	160	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375 FB	161	csr);
	162	}
	163
458e6a51	164	static int dma_channel_program(struct dma_channel *channel,
550a7375 FB	165	u16 packet_sz, u8 mode,
	166	dma_addr_t dma_addr, u32 len)
	167	{
458e6a51	168	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375 FB	169
550a7375 FB	170	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
458e6a51 FB	171	musb_channel->epnum,
458e6a51 FB	172	musb_channel->transmit ? "Tx" : "Rx",
550a7375 FB	173	packet_sz, dma_addr, len, mode);
550a7375 FB	174
458e6a51 FB	175	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
458e6a51 FB	176	channel->status == MUSB_DMA_STATUS_BUSY);
550a7375	177
458e6a51 FB	178	channel->actual_len = 0;
	179	musb_channel->start_addr = dma_addr;
	180	musb_channel->len = len;
	181	musb_channel->max_packet_sz = packet_sz;
	182	channel->status = MUSB_DMA_STATUS_BUSY;
550a7375 FB	183
550a7375 FB	184	if ((mode == 1) && (len >= packet_sz))
458e6a51	185	configure_channel(channel, packet_sz, 1, dma_addr, len);
550a7375	186	else
458e6a51	187	configure_channel(channel, packet_sz, 0, dma_addr, len);
550a7375 FB	188
	189	return true;
	190	}
	191
458e6a51	192	static int dma_channel_abort(struct dma_channel *channel)
550a7375	193	{
458e6a51 FB	194	struct musb_dma_channel *musb_channel = channel->private_data;
	195	void __iomem *mbase = musb_channel->controller->base;
	196
	197	u8 bchannel = musb_channel->idx;
b6e434a5	198	int offset;
550a7375 FB	199	u16 csr;
550a7375 FB	200
458e6a51 FB	201	if (channel->status == MUSB_DMA_STATUS_BUSY) {
458e6a51 FB	202	if (musb_channel->transmit) {
b6e434a5 SS	203	offset = MUSB_EP_OFFSET(musb_channel->epnum,
	204	MUSB_TXCSR);
	205
	206	/*
	207	* The programming guide says that we must clear
	208	* the DMAENAB bit before the DMAMODE bit...
	209	*/
	210	csr = musb_readw(mbase, offset);
	211	csr &= ~(MUSB_TXCSR_AUTOSET \| MUSB_TXCSR_DMAENAB);
	212	musb_writew(mbase, offset, csr);
	213	csr &= ~MUSB_TXCSR_DMAMODE;
	214	musb_writew(mbase, offset, csr);
550a7375	215	} else {
b6e434a5 SS	216	offset = MUSB_EP_OFFSET(musb_channel->epnum,
	217	MUSB_RXCSR);
	218
	219	csr = musb_readw(mbase, offset);
550a7375 FB	220	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
	221	MUSB_RXCSR_DMAENAB \|
	222	MUSB_RXCSR_DMAMODE);
b6e434a5	223	musb_writew(mbase, offset, csr);
550a7375 FB	224	}
	225
	226	musb_writew(mbase,
458e6a51	227	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375	228	0);
6995eb68 BW	229	musb_write_hsdma_addr(mbase, bchannel, 0);
6995eb68 BW	230	musb_write_hsdma_count(mbase, bchannel, 0);
458e6a51	231	channel->status = MUSB_DMA_STATUS_FREE;
550a7375	232	}
458e6a51	233
550a7375 FB	234	return 0;
	235	}
	236
	237	static irqreturn_t dma_controller_irq(int irq, void *private_data)
	238	{
458e6a51 FB	239	struct musb_dma_controller *controller = private_data;
	240	struct musb *musb = controller->private_data;
	241	struct musb_dma_channel *musb_channel;
	242	struct dma_channel *channel;
	243
	244	void __iomem *mbase = controller->base;
	245
550a7375	246	irqreturn_t retval = IRQ_NONE;
458e6a51	247
550a7375 FB	248	unsigned long flags;
550a7375 FB	249
458e6a51 FB	250	u8 bchannel;
	251	u8 int_hsdma;
	252
	253	u32 addr;
	254	u16 csr;
	255
550a7375 FB	256	spin_lock_irqsave(&musb->lock, flags);
	257
	258	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
	259	if (!int_hsdma)
	260	goto done;
	261
458e6a51 FB	262	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	263	if (int_hsdma & (1 << bchannel)) {
	264	musb_channel = (struct musb_dma_channel *)
	265	&(controller->channel[bchannel]);
	266	channel = &musb_channel->channel;
550a7375 FB	267
550a7375 FB	268	csr = musb_readw(mbase,
458e6a51	269	MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
550a7375 FB	270	MUSB_HSDMA_CONTROL));
550a7375 FB	271
458e6a51 FB	272	if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
458e6a51 FB	273	musb_channel->channel.status =
550a7375	274	MUSB_DMA_STATUS_BUS_ABORT;
458e6a51	275	} else {
550a7375 FB	276	u8 devctl;
550a7375 FB	277
6995eb68 BW	278	addr = musb_read_hsdma_addr(mbase,
6995eb68 BW	279	bchannel);
458e6a51 FB	280	channel->actual_len = addr
458e6a51 FB	281	- musb_channel->start_addr;
550a7375 FB	282
550a7375 FB	283	DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
458e6a51 FB	284	channel, musb_channel->start_addr,
	285	addr, channel->actual_len,
	286	musb_channel->len,
	287	(channel->actual_len
	288	< musb_channel->len) ?
550a7375 FB	289	"=> reconfig 0" : "=> complete");
	290
	291	devctl = musb_readb(mbase, MUSB_DEVCTL);
	292
458e6a51	293	channel->status = MUSB_DMA_STATUS_FREE;
550a7375 FB	294
	295	/* completed */
	296	if ((devctl & MUSB_DEVCTL_HM)
458e6a51 FB	297	&& (musb_channel->transmit)
	298	&& ((channel->desired_mode == 0)
	299	\|\| (channel->actual_len &
	300	(musb_channel->max_packet_sz - 1)))
b6e434a5 SS	301	) {
	302	u8 epnum = musb_channel->epnum;
	303	int offset = MUSB_EP_OFFSET(epnum,
	304	MUSB_TXCSR);
	305	u16 txcsr;
	306
	307	/*
	308	* The programming guide says that we
	309	* must clear DMAENAB before DMAMODE.
	310	*/
	311	musb_ep_select(mbase, epnum);
	312	txcsr = musb_readw(mbase, offset);
	313	txcsr &= ~(MUSB_TXCSR_DMAENAB
	314	\| MUSB_TXCSR_AUTOSET);
	315	musb_writew(mbase, offset, txcsr);
550a7375	316	/* Send out the packet */
b6e434a5 SS	317	txcsr &= ~MUSB_TXCSR_DMAMODE;
	318	txcsr \|= MUSB_TXCSR_TXPKTRDY;
	319	musb_writew(mbase, offset, txcsr);
458e6a51	320	}
c7bbc056 SS	321	musb_dma_completion(musb, musb_channel->epnum,
c7bbc056 SS	322	musb_channel->transmit);
550a7375 FB	323	}
	324	}
	325	}
6995eb68 BW	326
	327	#ifdef CONFIG_BLACKFIN
	328	/* Clear DMA interrup flags */
	329	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
	330	#endif
	331
550a7375 FB	332	retval = IRQ_HANDLED;
	333	done:
	334	spin_unlock_irqrestore(&musb->lock, flags);
	335	return retval;
	336	}
	337
	338	void dma_controller_destroy(struct dma_controller *c)
	339	{
458e6a51 FB	340	struct musb_dma_controller *controller = container_of(c,
458e6a51 FB	341	struct musb_dma_controller, controller);
550a7375	342
550a7375 FB	343	if (!controller)
	344	return;
	345
	346	if (controller->irq)
	347	free_irq(controller->irq, c);
	348
	349	kfree(controller);
	350	}
	351
	352	struct dma_controller *__init
458e6a51	353	dma_controller_create(struct musb musb, void __iomem base)
550a7375 FB	354	{
	355	struct musb_dma_controller *controller;
	356	struct device *dev = musb->controller;
	357	struct platform_device *pdev = to_platform_device(dev);
	358	int irq = platform_get_irq(pdev, 1);
	359
	360	if (irq == 0) {
	361	dev_err(dev, "No DMA interrupt line!\n");
	362	return NULL;
	363	}
	364
458e6a51	365	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
550a7375 FB	366	if (!controller)
	367	return NULL;
	368
458e6a51 FB	369	controller->channel_count = MUSB_HSDMA_CHANNELS;
	370	controller->private_data = musb;
	371	controller->base = base;
550a7375	372
458e6a51 FB	373	controller->controller.start = dma_controller_start;
	374	controller->controller.stop = dma_controller_stop;
	375	controller->controller.channel_alloc = dma_channel_allocate;
	376	controller->controller.channel_release = dma_channel_release;
	377	controller->controller.channel_program = dma_channel_program;
	378	controller->controller.channel_abort = dma_channel_abort;
550a7375 FB	379
550a7375 FB	380	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
427c4f33	381	dev_name(musb->controller), &controller->controller)) {
550a7375	382	dev_err(dev, "request_irq %d failed!\n", irq);
458e6a51 FB	383	dma_controller_destroy(&controller->controller);
458e6a51 FB	384
550a7375 FB	385	return NULL;
	386	}
	387
	388	controller->irq = irq;
	389
458e6a51	390	return &controller->controller;
550a7375	391	}