[net-next-2.6.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/*-------------------------------------------------------------------------*/

/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
 * off the controller (maybe it can boot from highspeed USB disks).
 */
static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
{
	struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);

	/* always say Linux will own the hardware */
	pci_write_config_byte(pdev, where + 3, 1);

	/* maybe wait a while for BIOS to respond */
	if (cap & (1 << 16)) {
		int msec = 5000;

		do {
			msleep(10);
			msec -= 10;
			pci_read_config_dword(pdev, where, &cap);
		} while ((cap & (1 << 16)) && msec);
		if (cap & (1 << 16)) {
			ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
				where, cap);
			// some BIOS versions seem buggy...
			// return 1;
			ehci_warn(ehci, "continuing after BIOS bug...\n");
			/* disable all SMIs, and clear "BIOS owns" flag */
			pci_write_config_dword(pdev, where + 4, 0);
			pci_write_config_byte(pdev, where + 2, 0);
		} else
			ehci_dbg(ehci, "BIOS handoff succeeded\n");
	}
	return 0;
}

/* called by khubd or root hub init threads */
static int ehci_pci_reset(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32			temp;
	unsigned		count = 256/4;

	spin_lock_init (&ehci->lock);

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
	dbg_hcs_params(ehci, "reset");
	dbg_hcc_params(ehci, "reset");

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = readl(&ehci->caps->hcs_params);

	/* NOTE:  only the parts below this line are PCI-specific */

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
			ehci->is_tdi_rh_tt = 1;
			tdi_reset(ehci);
		}
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			return -EIO;
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_31BIT_MASK) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;
		}
		break;
	}

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, 0x0a);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if ((temp & (3 << 13)) == (1 << 13)) {
			temp &= 0x1fff;
			ehci->debug = hcd->regs + temp;
			temp = readl(&ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				HCS_DEBUG_PORT(ehci->hcs_params),
				(temp & DBGP_ENABLED)
					? " IN USE"
					: "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));

	/* EHCI 0.96 and later may have "extended capabilities" */
	while (temp && count--) {
		u32		cap;

		pci_read_config_dword(to_pci_dev(hcd->self.controller),
				temp, &cap);
		ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
		switch (cap & 0xff) {
		case 1:			/* BIOS/SMM/... handoff */
			if (bios_handoff(ehci, temp, cap) != 0)
				return -EOPNOTSUPP;
			break;
		case 0:			/* illegal reserved capability */
			ehci_warn(ehci, "illegal capability!\n");
			cap = 0;
			/* FALLTHROUGH */
		default:		/* unknown */
			break;
		}
		temp = (cap >> 8) & 0xff;
	}
	if (!count) {
		ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
		return -EIO;
	}
	if (ehci_is_TDI(ehci))
		ehci_reset(ehci);

	ehci_port_power(ehci, 0);

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* force HC to halt state */
	return ehci_halt(ehci);
}

static int ehci_pci_start(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	int			result = 0;
	struct pci_dev		*pdev;
	u16			port_wake;

	pdev = to_pci_dev(hcd->self.controller);

	/* Serial Bus Release Number is at PCI 0x60 offset */
	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* port wake capability, reported by boot firmware */
	pci_read_config_word(pdev, 0x62, &port_wake);
	hcd->can_wakeup = (port_wake & 1) != 0;

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	result = pci_set_mwi(pdev);
	if (!result)
		ehci_dbg(ehci, "MWI active\n");

	return ehci_run(hcd);
}

/* always called by thread; normally rmmod */

static void ehci_pci_stop(struct usb_hcd *hcd)
{
	ehci_stop(hcd);
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);

	if (time_before(jiffies, ehci->next_statechange))
		msleep(10);

	// could save FLADJ in case of Vaux power loss
	// ... we'd only use it to handle clock skew

	return 0;
}

static int ehci_pci_resume(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	unsigned		port;
	struct usb_device	*root = hcd->self.root_hub;
	int			retval = -EINVAL;

	// maybe restore FLADJ

	if (time_before(jiffies, ehci->next_statechange))
		msleep(100);

	/* If CF is clear, we lost PCI Vaux power and need to restart.  */
	if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
		goto restart;

	/* If any port is suspended (or owned by the companion),
	 * we know we can/must resume the HC (and mustn't reset it).
	 * We just defer that to the root hub code.
	 */
	for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
		u32	status;
		port--;
		status = readl(&ehci->regs->port_status [port]);
		if (!(status & PORT_POWER))
			continue;
		if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) {
			usb_hcd_resume_root_hub(hcd);
			return 0;
		}
	}

restart:
	ehci_dbg(ehci, "lost power, restarting\n");
	for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
		port--;
		if (!root->children [port])
			continue;
		usb_set_device_state(root->children[port],
					USB_STATE_NOTATTACHED);
	}

	/* Else reset, to cope with power loss or flush-to-storage
	 * style "resume" having let BIOS kick in during reboot.
	 */
	(void) ehci_halt(ehci);
	(void) ehci_reset(ehci);
	(void) ehci_pci_reset(hcd);

	/* emptying the schedule aborts any urbs */
	spin_lock_irq(&ehci->lock);
	if (ehci->reclaim)
		ehci->reclaim_ready = 1;
	ehci_work(ehci, NULL);
	spin_unlock_irq(&ehci->lock);

	/* restart; khubd will disconnect devices */
	retval = ehci_run(hcd);

	/* here we "know" root ports should always stay powered;
	 * but some controllers may lose all power.
	 */
	ehci_port_power(ehci, 1);

	return retval;
}
#endif

static const struct hc_driver ehci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"EHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ehci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ehci_irq,
	.flags =		HCD_MEMORY | HCD_USB2,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ehci_pci_reset,
	.start =		ehci_pci_start,
#ifdef	CONFIG_PM
	.suspend =		ehci_pci_suspend,
	.resume =		ehci_pci_resume,
#endif
	.stop =			ehci_pci_stop,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ehci_urb_enqueue,
	.urb_dequeue =		ehci_urb_dequeue,
	.endpoint_disable =	ehci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ehci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ehci_hub_status_data,
	.hub_control =		ehci_hub_control,
	.bus_suspend =		ehci_bus_suspend,
	.bus_resume =		ehci_bus_resume,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,

#ifdef	CONFIG_PM
	.suspend =	usb_hcd_pci_suspend,
	.resume =	usb_hcd_pci_resume,
#endif
};

static int __init ehci_hcd_pci_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
		hcd_name,
		sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
		sizeof(struct ehci_itd), sizeof(struct ehci_sitd));

	return pci_register_driver(&ehci_pci_driver);
}
module_init(ehci_hcd_pci_init);

static void __exit ehci_hcd_pci_cleanup(void)
{
	pci_unregister_driver(&ehci_pci_driver);
}
module_exit(ehci_hcd_pci_cleanup);
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef CONFIG_PCI
	22	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	23	#endif
	24
	25	/-------------------------------------------------------------------------/
	26
	27	/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
	28	* off the controller (maybe it can boot from highspeed USB disks).
	29	*/
abcc9448	30	static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
7ff71d6a MP	31	{
	32	struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
	33
	34	/* always say Linux will own the hardware */
	35	pci_write_config_byte(pdev, where + 3, 1);
	36
	37	/* maybe wait a while for BIOS to respond */
	38	if (cap & (1 << 16)) {
	39	int msec = 5000;
	40
	41	do {
	42	msleep(10);
	43	msec -= 10;
	44	pci_read_config_dword(pdev, where, &cap);
	45	} while ((cap & (1 << 16)) && msec);
	46	if (cap & (1 << 16)) {
	47	ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
	48	where, cap);
	49	// some BIOS versions seem buggy...
	50	// return 1;
abcc9448	51	ehci_warn(ehci, "continuing after BIOS bug...\n");
7ff71d6a MP	52	/* disable all SMIs, and clear "BIOS owns" flag */
	53	pci_write_config_dword(pdev, where + 4, 0);
	54	pci_write_config_byte(pdev, where + 2, 0);
	55	} else
	56	ehci_dbg(ehci, "BIOS handoff succeeded\n");
	57	}
	58	return 0;
	59	}
	60
	61	/* called by khubd or root hub init threads */
abcc9448	62	static int ehci_pci_reset(struct usb_hcd *hcd)
7ff71d6a	63	{
abcc9448 DB	64	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	65	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a MP	66	u32 temp;
	67	unsigned count = 256/4;
	68
	69	spin_lock_init (&ehci->lock);
	70
	71	ehci->caps = hcd->regs;
abcc9448 DB	72	ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
	73	dbg_hcs_params(ehci, "reset");
	74	dbg_hcc_params(ehci, "reset");
7ff71d6a MP	75
7ff71d6a MP	76	/* cache this readonly data; minimize chip reads */
abcc9448	77	ehci->hcs_params = readl(&ehci->caps->hcs_params);
7ff71d6a	78
abcc9448	79	/* NOTE: only the parts below this line are PCI-specific */
7ff71d6a	80
abcc9448 DB	81	switch (pdev->vendor) {
	82	case PCI_VENDOR_ID_TDI:
	83	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
	84	ehci->is_tdi_rh_tt = 1;
	85	tdi_reset(ehci);
	86	}
	87	break;
	88	case PCI_VENDOR_ID_AMD:
	89	/* AMD8111 EHCI doesn't work, according to AMD errata */
	90	if (pdev->device == 0x7463) {
	91	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
	92	return -EIO;
	93	}
	94	break;
	95	case PCI_VENDOR_ID_NVIDIA:
	96	/* NVidia reports that certain chips don't handle
	97	* QH, ITD, or SITD addresses above 2GB. (But TD,
	98	* data buffer, and periodic schedule are normal.)
	99	*/
	100	switch (pdev->device) {
	101	case 0x003c: /* MCP04 */
	102	case 0x005b: /* CK804 */
	103	case 0x00d8: /* CK8 */
	104	case 0x00e8: /* CK8S */
	105	if (pci_set_consistent_dma_mask(pdev,
	106	DMA_31BIT_MASK) < 0)
	107	ehci_warn(ehci, "can't enable NVidia "
	108	"workaround for >2GB RAM\n");
7ff71d6a MP	109	break;
7ff71d6a MP	110	}
abcc9448 DB	111	break;
abcc9448 DB	112	}
7ff71d6a	113
abcc9448 DB	114	/* optional debug port, normally in the first BAR */
	115	temp = pci_find_capability(pdev, 0x0a);
	116	if (temp) {
	117	pci_read_config_dword(pdev, temp, &temp);
	118	temp >>= 16;
	119	if ((temp & (3 << 13)) == (1 << 13)) {
	120	temp &= 0x1fff;
	121	ehci->debug = hcd->regs + temp;
	122	temp = readl(&ehci->debug->control);
	123	ehci_info(ehci, "debug port %d%s\n",
	124	HCS_DEBUG_PORT(ehci->hcs_params),
	125	(temp & DBGP_ENABLED)
	126	? " IN USE"
	127	: "");
	128	if (!(temp & DBGP_ENABLED))
	129	ehci->debug = NULL;
7ff71d6a	130	}
abcc9448	131	}
7ff71d6a	132
abcc9448	133	temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
7ff71d6a MP	134
	135	/* EHCI 0.96 and later may have "extended capabilities" */
	136	while (temp && count--) {
	137	u32 cap;
	138
abcc9448	139	pci_read_config_dword(to_pci_dev(hcd->self.controller),
7ff71d6a	140	temp, &cap);
abcc9448	141	ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
7ff71d6a MP	142	switch (cap & 0xff) {
7ff71d6a MP	143	case 1: /* BIOS/SMM/... handoff */
abcc9448	144	if (bios_handoff(ehci, temp, cap) != 0)
7ff71d6a MP	145	return -EOPNOTSUPP;
	146	break;
	147	case 0: /* illegal reserved capability */
abcc9448	148	ehci_warn(ehci, "illegal capability!\n");
7ff71d6a MP	149	cap = 0;
	150	/* FALLTHROUGH */
	151	default: /* unknown */
	152	break;
	153	}
	154	temp = (cap >> 8) & 0xff;
	155	}
	156	if (!count) {
abcc9448	157	ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
7ff71d6a MP	158	return -EIO;
	159	}
	160	if (ehci_is_TDI(ehci))
abcc9448	161	ehci_reset(ehci);
7ff71d6a	162
abcc9448	163	ehci_port_power(ehci, 0);
7ff71d6a MP	164
	165	/* at least the Genesys GL880S needs fixup here */
	166	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	167	temp &= 0x0f;
	168	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	169	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	170	"cc=%d x pcc=%d < ports=%d\n",
	171	HCS_N_CC(ehci->hcs_params),
	172	HCS_N_PCC(ehci->hcs_params),
	173	HCS_N_PORTS(ehci->hcs_params));
	174
abcc9448 DB	175	switch (pdev->vendor) {
	176	case 0x17a0: /* GENESYS */
	177	/* GL880S: should be PORTS=2 */
	178	temp \|= (ehci->hcs_params & ~0xf);
	179	ehci->hcs_params = temp;
	180	break;
	181	case PCI_VENDOR_ID_NVIDIA:
	182	/* NF4: should be PCC=10 */
	183	break;
7ff71d6a MP	184	}
	185	}
	186
	187	/* force HC to halt state */
abcc9448	188	return ehci_halt(ehci);
7ff71d6a MP	189	}
7ff71d6a MP	190
abcc9448	191	static int ehci_pci_start(struct usb_hcd *hcd)
7ff71d6a	192	{
abcc9448 DB	193	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
	194	int result = 0;
	195	struct pci_dev *pdev;
	196	u16 port_wake;
7ff71d6a	197
abcc9448	198	pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	199
abcc9448 DB	200	/* Serial Bus Release Number is at PCI 0x60 offset */
abcc9448 DB	201	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	202
abcc9448 DB	203	/* port wake capability, reported by boot firmware */
	204	pci_read_config_word(pdev, 0x62, &port_wake);
	205	hcd->can_wakeup = (port_wake & 1) != 0;
7ff71d6a	206
abcc9448 DB	207	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	208	result = pci_set_mwi(pdev);
	209	if (!result)
	210	ehci_dbg(ehci, "MWI active\n");
7ff71d6a	211
abcc9448	212	return ehci_run(hcd);
7ff71d6a MP	213	}
	214
	215	/* always called by thread; normally rmmod */
	216
abcc9448	217	static void ehci_pci_stop(struct usb_hcd *hcd)
7ff71d6a	218	{
abcc9448	219	ehci_stop(hcd);
7ff71d6a MP	220	}
	221
	222	/-------------------------------------------------------------------------/
	223
	224	#ifdef CONFIG_PM
	225
	226	/* suspend/resume, section 4.3 */
	227
f03c17fc	228	/* These routines rely on the PCI bus glue
7ff71d6a MP	229	* to handle powerdown and wakeup, and currently also on
	230	* transceivers that don't need any software attention to set up
	231	* the right sort of wakeup.
f03c17fc	232	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	233	*/
7ff71d6a MP	234
abcc9448	235	static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
7ff71d6a	236	{
abcc9448	237	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
7ff71d6a	238
abcc9448 DB	239	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	240	msleep(10);
7ff71d6a	241
f03c17fc	242	// could save FLADJ in case of Vaux power loss
7ff71d6a MP	243	// ... we'd only use it to handle clock skew
	244
	245	return 0;
	246	}
	247
abcc9448	248	static int ehci_pci_resume(struct usb_hcd *hcd)
7ff71d6a	249	{
abcc9448	250	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
7ff71d6a MP	251	unsigned port;
	252	struct usb_device *root = hcd->self.root_hub;
	253	int retval = -EINVAL;
	254
f03c17fc	255	// maybe restore FLADJ
7ff71d6a	256
abcc9448 DB	257	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	258	msleep(100);
7ff71d6a	259
f03c17fc	260	/* If CF is clear, we lost PCI Vaux power and need to restart. */
abcc9448	261	if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
f03c17fc DB	262	goto restart;
f03c17fc DB	263
7ff71d6a MP	264	/* If any port is suspended (or owned by the companion),
7ff71d6a MP	265	* we know we can/must resume the HC (and mustn't reset it).
f03c17fc	266	* We just defer that to the root hub code.
7ff71d6a	267	*/
abcc9448	268	for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
7ff71d6a MP	269	u32 status;
7ff71d6a MP	270	port--;
abcc9448	271	status = readl(&ehci->regs->port_status [port]);
7ff71d6a MP	272	if (!(status & PORT_POWER))
7ff71d6a MP	273	continue;
f03c17fc DB	274	if (status & (PORT_SUSPEND \| PORT_RESUME \| PORT_OWNER)) {
	275	usb_hcd_resume_root_hub(hcd);
	276	return 0;
7ff71d6a	277	}
f03c17fc DB	278	}
	279
	280	restart:
	281	ehci_dbg(ehci, "lost power, restarting\n");
abcc9448	282	for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
f03c17fc	283	port--;
7ff71d6a MP	284	if (!root->children [port])
7ff71d6a MP	285	continue;
abcc9448	286	usb_set_device_state(root->children[port],
7ff71d6a MP	287	USB_STATE_NOTATTACHED);
	288	}
	289
	290	/* Else reset, to cope with power loss or flush-to-storage
f03c17fc	291	* style "resume" having let BIOS kick in during reboot.
7ff71d6a	292	*/
abcc9448 DB	293	(void) ehci_halt(ehci);
	294	(void) ehci_reset(ehci);
	295	(void) ehci_pci_reset(hcd);
f03c17fc DB	296
f03c17fc DB	297	/* emptying the schedule aborts any urbs */
abcc9448	298	spin_lock_irq(&ehci->lock);
f03c17fc DB	299	if (ehci->reclaim)
f03c17fc DB	300	ehci->reclaim_ready = 1;
abcc9448 DB	301	ehci_work(ehci, NULL);
abcc9448 DB	302	spin_unlock_irq(&ehci->lock);
f03c17fc DB	303
f03c17fc DB	304	/* restart; khubd will disconnect devices */
abcc9448	305	retval = ehci_run(hcd);
f03c17fc DB	306
	307	/* here we "know" root ports should always stay powered;
	308	* but some controllers may lose all power.
	309	*/
abcc9448	310	ehci_port_power(ehci, 1);
7ff71d6a MP	311
	312	return retval;
	313	}
	314	#endif
	315
	316	static const struct hc_driver ehci_pci_hc_driver = {
	317	.description = hcd_name,
	318	.product_desc = "EHCI Host Controller",
	319	.hcd_priv_size = sizeof(struct ehci_hcd),
	320
	321	/*
	322	* generic hardware linkage
	323	*/
	324	.irq = ehci_irq,
	325	.flags = HCD_MEMORY \| HCD_USB2,
	326
	327	/*
	328	* basic lifecycle operations
	329	*/
	330	.reset = ehci_pci_reset,
	331	.start = ehci_pci_start,
	332	#ifdef CONFIG_PM
	333	.suspend = ehci_pci_suspend,
	334	.resume = ehci_pci_resume,
	335	#endif
	336	.stop = ehci_pci_stop,
	337
	338	/*
	339	* managing i/o requests and associated device resources
	340	*/
	341	.urb_enqueue = ehci_urb_enqueue,
	342	.urb_dequeue = ehci_urb_dequeue,
	343	.endpoint_disable = ehci_endpoint_disable,
	344
	345	/*
	346	* scheduling support
	347	*/
	348	.get_frame_number = ehci_get_frame,
	349
	350	/*
	351	* root hub support
	352	*/
	353	.hub_status_data = ehci_hub_status_data,
	354	.hub_control = ehci_hub_control,
0c0382e3 AS	355	.bus_suspend = ehci_bus_suspend,
0c0382e3 AS	356	.bus_resume = ehci_bus_resume,
7ff71d6a MP	357	};
	358
	359	/-------------------------------------------------------------------------/
	360
	361	/* PCI driver selection metadata; PCI hotplugging uses this */
	362	static const struct pci_device_id pci_ids [] = { {
	363	/* handle any USB 2.0 EHCI controller */
	364	PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) \| 0x20), ~0),
	365	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	366	},
	367	{ /* end: all zeroes */ }
	368	};
abcc9448	369	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	370
	371	/* pci driver glue; this is a "new style" PCI driver module */
	372	static struct pci_driver ehci_pci_driver = {
	373	.name = (char *) hcd_name,
	374	.id_table = pci_ids,
	375
	376	.probe = usb_hcd_pci_probe,
	377	.remove = usb_hcd_pci_remove,
	378
	379	#ifdef CONFIG_PM
	380	.suspend = usb_hcd_pci_suspend,
	381	.resume = usb_hcd_pci_resume,
	382	#endif
	383	};
	384
abcc9448	385	static int __init ehci_hcd_pci_init(void)
7ff71d6a MP	386	{
	387	if (usb_disabled())
	388	return -ENODEV;
	389
abcc9448	390	pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
7ff71d6a	391	hcd_name,
abcc9448 DB	392	sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
abcc9448 DB	393	sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
7ff71d6a	394
abcc9448	395	return pci_register_driver(&ehci_pci_driver);
7ff71d6a	396	}
abcc9448	397	module_init(ehci_hcd_pci_init);
7ff71d6a	398
abcc9448	399	static void __exit ehci_hcd_pci_cleanup(void)
7ff71d6a	400	{
abcc9448	401	pci_unregister_driver(&ehci_pci_driver);
7ff71d6a	402	}
abcc9448	403	module_exit(ehci_hcd_pci_cleanup);