[net-next-2.6.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/*-------------------------------------------------------------------------*/

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	u32			temp;
	int			retval;

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, 0x0a);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if ((temp & (3 << 13)) == (1 << 13)) {
			temp &= 0x1fff;
			ehci->debug = ehci_to_hcd(ehci)->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				HCS_DEBUG_PORT(ehci->hcs_params),
				(temp & DBGP_ENABLED)
					? " IN USE"
					: "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32			temp;
	int			retval;

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	}

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs +
		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));

	dbg_hcs_params(ehci, "reset");
	dbg_hcc_params(ehci, "reset");

        /* ehci_init() causes memory for DMA transfers to be
         * allocated.  Thus, any vendor-specific workarounds based on
         * limiting the type of memory used for DMA transfers must
         * happen before ehci_init() is called. */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_31BIT_MASK) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;
		}
		break;
	}

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);

	retval = ehci_halt(ehci);
	if (retval)
		return retval;

	/* data structure init */
	retval = ehci_init(hcd);
	if (retval)
		return retval;

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
			ehci->is_tdi_rh_tt = 1;
			hcd->has_tt = 1;
			tdi_reset(ehci);
		}
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	case PCI_VENDOR_ID_VIA:
		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
			u8 tmp;

			/* The VT6212 defaults to a 1 usec EHCI sleep time which
			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
			 * that sleep time use the conventional 10 usec.
			 */
			pci_read_config_byte(pdev, 0x4b, &tmp);
			if (tmp & 0x20)
				break;
			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
		}
		break;
	}

	ehci_reset(ehci);

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Workaround current PCI init glitch:  wakeup bits aren't
	 * being set from PCI PM capability.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001)
			device_init_wakeup(&pdev->dev, 1);
	}

#ifdef	CONFIG_USB_SUSPEND
	/* REVISIT: the controller works fine for wakeup iff the root hub
	 * itself is "globally" suspended, but usbcore currently doesn't
	 * understand such things.
	 *
	 * System suspend currently expects to be able to suspend the entire
	 * device tree, device-at-a-time.  If we failed selective suspend
	 * reports, system suspend would fail; so the root hub code must claim
	 * success.  That's lying to usbcore, and it matters for for runtime
	 * PM scenarios with selective suspend and remote wakeup...
	 */
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	unsigned long		flags;
	int			rc = 0;

	if (time_before(jiffies, ehci->next_statechange))
		msleep(10);

	/* Root hub was already suspended. Disable irq emission and
	 * mark HW unaccessible, bail out if RH has been resumed. Use
	 * the spinlock to properly synchronize with possible pending
	 * RH suspend or resume activity.
	 *
	 * This is still racy as hcd->state is manipulated outside of
	 * any locks =P But that will be a different fix.
	 */
	spin_lock_irqsave (&ehci->lock, flags);
	if (hcd->state != HC_STATE_SUSPENDED) {
		rc = -EINVAL;
		goto bail;
	}
	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
	(void)ehci_readl(ehci, &ehci->regs->intr_enable);

	/* make sure snapshot being resumed re-enumerates everything */
	if (message.event == PM_EVENT_PRETHAW) {
		ehci_halt(ehci);
		ehci_reset(ehci);
	}

	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 bail:
	spin_unlock_irqrestore (&ehci->lock, flags);

	// could save FLADJ in case of Vaux power loss
	// ... we'd only use it to handle clock skew

	return rc;
}

static int ehci_pci_resume(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	// maybe restore FLADJ

	if (time_before(jiffies, ehci->next_statechange))
		msleep(100);

	/* Mark hardware accessible again as we are out of D3 state by now */
	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);

	/* If CF is still set, we maintained PCI Vaux power.
	 * Just undo the effect of ehci_pci_suspend().
	 */
	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
		int	mask = INTR_MASK;

		if (!hcd->self.root_hub->do_remote_wakeup)
			mask &= ~STS_PCD;
		ehci_writel(ehci, mask, &ehci->regs->intr_enable);
		ehci_readl(ehci, &ehci->regs->intr_enable);
		return 0;
	}

	ehci_dbg(ehci, "lost power, restarting\n");
	usb_root_hub_lost_power(hcd->self.root_hub);

	/* Else reset, to cope with power loss or flush-to-storage
	 * style "resume" having let BIOS kick in during reboot.
	 */
	(void) ehci_halt(ehci);
	(void) ehci_reset(ehci);
	(void) ehci_pci_reinit(ehci, pdev);

	/* emptying the schedule aborts any urbs */
	spin_lock_irq(&ehci->lock);
	if (ehci->reclaim)
		end_unlink_async(ehci);
	ehci_work(ehci);
	spin_unlock_irq(&ehci->lock);

	ehci_writel(ehci, ehci->command, &ehci->regs->command);
	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
	ehci_readl(ehci, &ehci->regs->command);	/* unblock posted writes */

	/* here we "know" root ports should always stay powered */
	ehci_port_power(ehci, 1);

	hcd->state = HC_STATE_SUSPENDED;
	return 0;
}
#endif

static const struct hc_driver ehci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"EHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ehci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ehci_irq,
	.flags =		HCD_MEMORY | HCD_USB2,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ehci_pci_setup,
	.start =		ehci_run,
#ifdef	CONFIG_PM
	.pci_suspend =		ehci_pci_suspend,
	.pci_resume =		ehci_pci_resume,
#endif
	.stop =			ehci_stop,
	.shutdown =		ehci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ehci_urb_enqueue,
	.urb_dequeue =		ehci_urb_dequeue,
	.endpoint_disable =	ehci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ehci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ehci_hub_status_data,
	.hub_control =		ehci_hub_control,
	.bus_suspend =		ehci_bus_suspend,
	.bus_resume =		ehci_bus_resume,
	.relinquish_port = 	ehci_relinquish_port,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,

#ifdef	CONFIG_PM
	.suspend =	usb_hcd_pci_suspend,
	.resume =	usb_hcd_pci_resume,
#endif
	.shutdown = 	usb_hcd_pci_shutdown,
};
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef CONFIG_PCI
	22	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	23	#endif
	24
	25	/-------------------------------------------------------------------------/
	26
18807521 DB	27	/* called after powerup, by probe or system-pm "wakeup" */
	28	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	29	{
	30	u32 temp;
	31	int retval;
18807521 DB	32
	33	/* optional debug port, normally in the first BAR */
	34	temp = pci_find_capability(pdev, 0x0a);
	35	if (temp) {
	36	pci_read_config_dword(pdev, temp, &temp);
	37	temp >>= 16;
	38	if ((temp & (3 << 13)) == (1 << 13)) {
	39	temp &= 0x1fff;
	40	ehci->debug = ehci_to_hcd(ehci)->regs + temp;
083522d7	41	temp = ehci_readl(ehci, &ehci->debug->control);
18807521 DB	42	ehci_info(ehci, "debug port %d%s\n",
	43	HCS_DEBUG_PORT(ehci->hcs_params),
	44	(temp & DBGP_ENABLED)
	45	? " IN USE"
	46	: "");
	47	if (!(temp & DBGP_ENABLED))
	48	ehci->debug = NULL;
	49	}
	50	}
	51
401feafa DB	52	/* we expect static quirk code to handle the "extended capabilities"
	53	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	54	*/
18807521 DB	55
	56	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	57	retval = pci_set_mwi(pdev);
	58	if (!retval)
	59	ehci_dbg(ehci, "MWI active\n");
	60
18807521 DB	61	return 0;
	62	}
	63
8926bfa7 DB	64	/* called during probe() after chip reset completes */
8926bfa7 DB	65	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	66	{
abcc9448 DB	67	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	68	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	69	u32 temp;
18807521	70	int retval;
7ff71d6a	71
083522d7 BH	72	switch (pdev->vendor) {
	73	case PCI_VENDOR_ID_TOSHIBA_2:
	74	/* celleb's companion chip */
	75	if (pdev->device == 0x01b5) {
	76	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	77	ehci->big_endian_mmio = 1;
	78	#else
	79	ehci_warn(ehci,
	80	"unsupported big endian Toshiba quirk\n");
	81	#endif
	82	}
	83	break;
	84	}
	85
7ff71d6a	86	ehci->caps = hcd->regs;
083522d7 BH	87	ehci->regs = hcd->regs +
	88	HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
	89
abcc9448 DB	90	dbg_hcs_params(ehci, "reset");
abcc9448 DB	91	dbg_hcc_params(ehci, "reset");
7ff71d6a	92
c32ba30f PS	93	/* ehci_init() causes memory for DMA transfers to be
	94	* allocated. Thus, any vendor-specific workarounds based on
	95	* limiting the type of memory used for DMA transfers must
	96	* happen before ehci_init() is called. */
	97	switch (pdev->vendor) {
	98	case PCI_VENDOR_ID_NVIDIA:
	99	/* NVidia reports that certain chips don't handle
	100	* QH, ITD, or SITD addresses above 2GB. (But TD,
	101	* data buffer, and periodic schedule are normal.)
	102	*/
	103	switch (pdev->device) {
	104	case 0x003c: /* MCP04 */
	105	case 0x005b: /* CK804 */
	106	case 0x00d8: /* CK8 */
	107	case 0x00e8: /* CK8S */
	108	if (pci_set_consistent_dma_mask(pdev,
	109	DMA_31BIT_MASK) < 0)
	110	ehci_warn(ehci, "can't enable NVidia "
	111	"workaround for >2GB RAM\n");
	112	break;
	113	}
	114	break;
	115	}
	116
7ff71d6a	117	/* cache this readonly data; minimize chip reads */
083522d7	118	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
7ff71d6a	119
18807521 DB	120	retval = ehci_halt(ehci);
	121	if (retval)
	122	return retval;
	123
8926bfa7 DB	124	/* data structure init */
	125	retval = ehci_init(hcd);
	126	if (retval)
	127	return retval;
	128
abcc9448 DB	129	switch (pdev->vendor) {
	130	case PCI_VENDOR_ID_TDI:
	131	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
	132	ehci->is_tdi_rh_tt = 1;
7329e211	133	hcd->has_tt = 1;
abcc9448 DB	134	tdi_reset(ehci);
	135	}
	136	break;
	137	case PCI_VENDOR_ID_AMD:
	138	/* AMD8111 EHCI doesn't work, according to AMD errata */
	139	if (pdev->device == 0x7463) {
	140	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	141	retval = -EIO;
8926bfa7 DB	142	goto done;
abcc9448 DB	143	}
	144	break;
	145	case PCI_VENDOR_ID_NVIDIA:
f8aeb3bb	146	switch (pdev->device) {
f8aeb3bb DB	147	/* Some NForce2 chips have problems with selective suspend;
	148	* fixed in newer silicon.
	149	*/
	150	case 0x0068:
44c10138	151	if (pdev->revision < 0xa4)
f8aeb3bb DB	152	ehci->no_selective_suspend = 1;
f8aeb3bb DB	153	break;
7ff71d6a	154	}
abcc9448	155	break;
055b93c9 RH	156	case PCI_VENDOR_ID_VIA:
	157	if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
	158	u8 tmp;
	159
	160	/* The VT6212 defaults to a 1 usec EHCI sleep time which
	161	* hogs the PCI bus badly. Setting bit 5 of 0x4B makes
	162	* that sleep time use the conventional 10 usec.
	163	*/
	164	pci_read_config_byte(pdev, 0x4b, &tmp);
	165	if (tmp & 0x20)
	166	break;
	167	pci_write_config_byte(pdev, 0x4b, tmp \| 0x20);
	168	}
	169	break;
abcc9448	170	}
7ff71d6a	171
af1c51fc	172	ehci_reset(ehci);
7ff71d6a	173
7ff71d6a MP	174	/* at least the Genesys GL880S needs fixup here */
	175	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	176	temp &= 0x0f;
	177	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	178	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	179	"cc=%d x pcc=%d < ports=%d\n",
	180	HCS_N_CC(ehci->hcs_params),
	181	HCS_N_PCC(ehci->hcs_params),
	182	HCS_N_PORTS(ehci->hcs_params));
	183
abcc9448 DB	184	switch (pdev->vendor) {
	185	case 0x17a0: /* GENESYS */
	186	/* GL880S: should be PORTS=2 */
	187	temp \|= (ehci->hcs_params & ~0xf);
	188	ehci->hcs_params = temp;
	189	break;
	190	case PCI_VENDOR_ID_NVIDIA:
	191	/* NF4: should be PCC=10 */
	192	break;
7ff71d6a MP	193	}
	194	}
	195
abcc9448 DB	196	/* Serial Bus Release Number is at PCI 0x60 offset */
abcc9448 DB	197	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	198
2c1c3c4c DB	199	/* Workaround current PCI init glitch: wakeup bits aren't
	200	* being set from PCI PM capability.
	201	*/
	202	if (!device_can_wakeup(&pdev->dev)) {
	203	u16 port_wake;
	204
	205	pci_read_config_word(pdev, 0x62, &port_wake);
	206	if (port_wake & 0x0001)
	207	device_init_wakeup(&pdev->dev, 1);
	208	}
7ff71d6a	209
f8aeb3bb DB	210	#ifdef CONFIG_USB_SUSPEND
	211	/* REVISIT: the controller works fine for wakeup iff the root hub
	212	* itself is "globally" suspended, but usbcore currently doesn't
	213	* understand such things.
	214	*
	215	* System suspend currently expects to be able to suspend the entire
	216	* device tree, device-at-a-time. If we failed selective suspend
	217	* reports, system suspend would fail; so the root hub code must claim
	218	* success. That's lying to usbcore, and it matters for for runtime
	219	* PM scenarios with selective suspend and remote wakeup...
	220	*/
	221	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	222	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	223	#endif
	224
18807521	225	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	226	done:
8926bfa7 DB	227	return retval;
7ff71d6a MP	228	}
	229
	230	/-------------------------------------------------------------------------/
	231
	232	#ifdef CONFIG_PM
	233
	234	/* suspend/resume, section 4.3 */
	235
f03c17fc	236	/* These routines rely on the PCI bus glue
7ff71d6a MP	237	* to handle powerdown and wakeup, and currently also on
	238	* transceivers that don't need any software attention to set up
	239	* the right sort of wakeup.
f03c17fc	240	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	241	*/
7ff71d6a MP	242
abcc9448	243	static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
7ff71d6a	244	{
abcc9448	245	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
8de98402 BH	246	unsigned long flags;
8de98402 BH	247	int rc = 0;
7ff71d6a	248
abcc9448 DB	249	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	250	msleep(10);
7ff71d6a	251
8de98402 BH	252	/* Root hub was already suspended. Disable irq emission and
	253	* mark HW unaccessible, bail out if RH has been resumed. Use
	254	* the spinlock to properly synchronize with possible pending
	255	* RH suspend or resume activity.
	256	*
	257	* This is still racy as hcd->state is manipulated outside of
	258	* any locks =P But that will be a different fix.
	259	*/
	260	spin_lock_irqsave (&ehci->lock, flags);
	261	if (hcd->state != HC_STATE_SUSPENDED) {
	262	rc = -EINVAL;
	263	goto bail;
	264	}
083522d7 BH	265	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
083522d7 BH	266	(void)ehci_readl(ehci, &ehci->regs->intr_enable);
8de98402	267
18584999 DB	268	/* make sure snapshot being resumed re-enumerates everything */
	269	if (message.event == PM_EVENT_PRETHAW) {
	270	ehci_halt(ehci);
	271	ehci_reset(ehci);
	272	}
	273
8de98402 BH	274	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	275	bail:
	276	spin_unlock_irqrestore (&ehci->lock, flags);
	277
f03c17fc	278	// could save FLADJ in case of Vaux power loss
7ff71d6a MP	279	// ... we'd only use it to handle clock skew
7ff71d6a MP	280
8de98402	281	return rc;
7ff71d6a MP	282	}
7ff71d6a MP	283
abcc9448	284	static int ehci_pci_resume(struct usb_hcd *hcd)
7ff71d6a	285	{
abcc9448	286	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	287	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	288
f03c17fc	289	// maybe restore FLADJ
7ff71d6a	290
abcc9448 DB	291	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	292	msleep(100);
7ff71d6a	293
8de98402 BH	294	/* Mark hardware accessible again as we are out of D3 state by now */
	295	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	296
8c03356a AS	297	/* If CF is still set, we maintained PCI Vaux power.
8c03356a AS	298	* Just undo the effect of ehci_pci_suspend().
7ff71d6a	299	*/
083522d7	300	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
8c03356a AS	301	int mask = INTR_MASK;
8c03356a AS	302
58a97ffe	303	if (!hcd->self.root_hub->do_remote_wakeup)
8c03356a	304	mask &= ~STS_PCD;
083522d7 BH	305	ehci_writel(ehci, mask, &ehci->regs->intr_enable);
083522d7 BH	306	ehci_readl(ehci, &ehci->regs->intr_enable);
8c03356a	307	return 0;
f03c17fc DB	308	}
f03c17fc DB	309
f03c17fc	310	ehci_dbg(ehci, "lost power, restarting\n");
1c50c317	311	usb_root_hub_lost_power(hcd->self.root_hub);
7ff71d6a MP	312
7ff71d6a MP	313	/* Else reset, to cope with power loss or flush-to-storage
f03c17fc	314	* style "resume" having let BIOS kick in during reboot.
7ff71d6a	315	*/
abcc9448 DB	316	(void) ehci_halt(ehci);
abcc9448 DB	317	(void) ehci_reset(ehci);
18807521	318	(void) ehci_pci_reinit(ehci, pdev);
f03c17fc DB	319
f03c17fc DB	320	/* emptying the schedule aborts any urbs */
abcc9448	321	spin_lock_irq(&ehci->lock);
f03c17fc	322	if (ehci->reclaim)
07d29b63	323	end_unlink_async(ehci);
7d12e780	324	ehci_work(ehci);
abcc9448	325	spin_unlock_irq(&ehci->lock);
f03c17fc	326
083522d7 BH	327	ehci_writel(ehci, ehci->command, &ehci->regs->command);
	328	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
	329	ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
8c03356a	330
383975d7 AS	331	/* here we "know" root ports should always stay powered */
383975d7 AS	332	ehci_port_power(ehci, 1);
383975d7	333
8c03356a AS	334	hcd->state = HC_STATE_SUSPENDED;
8c03356a AS	335	return 0;
7ff71d6a MP	336	}
	337	#endif
	338
	339	static const struct hc_driver ehci_pci_hc_driver = {
	340	.description = hcd_name,
	341	.product_desc = "EHCI Host Controller",
	342	.hcd_priv_size = sizeof(struct ehci_hcd),
	343
	344	/*
	345	* generic hardware linkage
	346	*/
	347	.irq = ehci_irq,
	348	.flags = HCD_MEMORY \| HCD_USB2,
	349
	350	/*
	351	* basic lifecycle operations
	352	*/
8926bfa7	353	.reset = ehci_pci_setup,
18807521	354	.start = ehci_run,
7ff71d6a	355	#ifdef CONFIG_PM
7be7d741 AS	356	.pci_suspend = ehci_pci_suspend,
7be7d741 AS	357	.pci_resume = ehci_pci_resume,
7ff71d6a	358	#endif
18807521	359	.stop = ehci_stop,
64a21d02	360	.shutdown = ehci_shutdown,
7ff71d6a MP	361
	362	/*
	363	* managing i/o requests and associated device resources
	364	*/
	365	.urb_enqueue = ehci_urb_enqueue,
	366	.urb_dequeue = ehci_urb_dequeue,
	367	.endpoint_disable = ehci_endpoint_disable,
	368
	369	/*
	370	* scheduling support
	371	*/
	372	.get_frame_number = ehci_get_frame,
	373
	374	/*
	375	* root hub support
	376	*/
	377	.hub_status_data = ehci_hub_status_data,
	378	.hub_control = ehci_hub_control,
0c0382e3 AS	379	.bus_suspend = ehci_bus_suspend,
0c0382e3 AS	380	.bus_resume = ehci_bus_resume,
90da096e	381	.relinquish_port = ehci_relinquish_port,
7ff71d6a MP	382	};
	383
	384	/-------------------------------------------------------------------------/
	385
	386	/* PCI driver selection metadata; PCI hotplugging uses this */
	387	static const struct pci_device_id pci_ids [] = { {
	388	/* handle any USB 2.0 EHCI controller */
c67808ee	389	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a MP	390	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	391	},
	392	{ /* end: all zeroes */ }
	393	};
abcc9448	394	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	395
	396	/* pci driver glue; this is a "new style" PCI driver module */
	397	static struct pci_driver ehci_pci_driver = {
	398	.name = (char *) hcd_name,
	399	.id_table = pci_ids,
	400
	401	.probe = usb_hcd_pci_probe,
	402	.remove = usb_hcd_pci_remove,
	403
	404	#ifdef CONFIG_PM
	405	.suspend = usb_hcd_pci_suspend,
	406	.resume = usb_hcd_pci_resume,
	407	#endif
64a21d02	408	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	409	};