[net-next-2.6.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/*-------------------------------------------------------------------------*/

/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
 * off the controller (maybe it can boot from highspeed USB disks).
 */
static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
{
	struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);

	/* always say Linux will own the hardware */
	pci_write_config_byte(pdev, where + 3, 1);

	/* maybe wait a while for BIOS to respond */
	if (cap & (1 << 16)) {
		int msec = 5000;

		do {
			msleep(10);
			msec -= 10;
			pci_read_config_dword(pdev, where, &cap);
		} while ((cap & (1 << 16)) && msec);
		if (cap & (1 << 16)) {
			ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
				where, cap);
			// some BIOS versions seem buggy...
			// return 1;
			ehci_warn(ehci, "continuing after BIOS bug...\n");
			/* disable all SMIs, and clear "BIOS owns" flag */
			pci_write_config_dword(pdev, where + 4, 0);
			pci_write_config_byte(pdev, where + 2, 0);
		} else
			ehci_dbg(ehci, "BIOS handoff succeeded\n");
	}
	return 0;
}

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	u32			temp;
	int			retval;
	unsigned		count = 256/4;

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, 0x0a);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if ((temp & (3 << 13)) == (1 << 13)) {
			temp &= 0x1fff;
			ehci->debug = ehci_to_hcd(ehci)->regs + temp;
			temp = readl(&ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				HCS_DEBUG_PORT(ehci->hcs_params),
				(temp & DBGP_ENABLED)
					? " IN USE"
					: "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));

	/* EHCI 0.96 and later may have "extended capabilities" */
	while (temp && count--) {
		u32		cap;

		pci_read_config_dword(pdev, temp, &cap);
		ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
		switch (cap & 0xff) {
		case 1:			/* BIOS/SMM/... handoff */
			if (bios_handoff(ehci, temp, cap) != 0)
				return -EOPNOTSUPP;
			break;
		case 0:			/* illegal reserved capability */
			ehci_dbg(ehci, "illegal capability!\n");
			cap = 0;
			/* FALLTHROUGH */
		default:		/* unknown */
			break;
		}
		temp = (cap >> 8) & 0xff;
	}
	if (!count) {
		ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
		return -EIO;
	}

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	ehci_port_power(ehci, 0);

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32			temp;
	int			retval;

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
	dbg_hcs_params(ehci, "reset");
	dbg_hcc_params(ehci, "reset");

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = readl(&ehci->caps->hcs_params);

	retval = ehci_halt(ehci);
	if (retval)
		return retval;

	/* data structure init */
	retval = ehci_init(hcd);
	if (retval)
		return retval;

	/* NOTE:  only the parts below this line are PCI-specific */

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
			ehci->is_tdi_rh_tt = 1;
			tdi_reset(ehci);
		}
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_31BIT_MASK) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;
		}
		break;
	}

	if (ehci_is_TDI(ehci))
		ehci_reset(ehci);

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Workaround current PCI init glitch:  wakeup bits aren't
	 * being set from PCI PM capability.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001)
			device_init_wakeup(&pdev->dev, 1);
	}

	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	unsigned long		flags;
	int			rc = 0;

	if (time_before(jiffies, ehci->next_statechange))
		msleep(10);

	/* Root hub was already suspended. Disable irq emission and
	 * mark HW unaccessible, bail out if RH has been resumed. Use
	 * the spinlock to properly synchronize with possible pending
	 * RH suspend or resume activity.
	 *
	 * This is still racy as hcd->state is manipulated outside of
	 * any locks =P But that will be a different fix.
	 */
	spin_lock_irqsave (&ehci->lock, flags);
	if (hcd->state != HC_STATE_SUSPENDED) {
		rc = -EINVAL;
		goto bail;
	}
	writel (0, &ehci->regs->intr_enable);
	(void)readl(&ehci->regs->intr_enable);

	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 bail:
	spin_unlock_irqrestore (&ehci->lock, flags);

	// could save FLADJ in case of Vaux power loss
	// ... we'd only use it to handle clock skew

	return rc;
}

static int ehci_pci_resume(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	unsigned		port;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = -EINVAL;

	// maybe restore FLADJ

	if (time_before(jiffies, ehci->next_statechange))
		msleep(100);

	/* Mark hardware accessible again as we are out of D3 state by now */
	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);

	/* If CF is clear, we lost PCI Vaux power and need to restart.  */
	if (readl(&ehci->regs->configured_flag) != FLAG_CF)
		goto restart;

	/* If any port is suspended (or owned by the companion),
	 * we know we can/must resume the HC (and mustn't reset it).
	 * We just defer that to the root hub code.
	 */
	for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
		u32	status;
		port--;
		status = readl(&ehci->regs->port_status [port]);
		if (!(status & PORT_POWER))
			continue;
		if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) {
			usb_hcd_resume_root_hub(hcd);
			return 0;
		}
	}

restart:
	ehci_dbg(ehci, "lost power, restarting\n");
	usb_root_hub_lost_power(hcd->self.root_hub);

	/* Else reset, to cope with power loss or flush-to-storage
	 * style "resume" having let BIOS kick in during reboot.
	 */
	(void) ehci_halt(ehci);
	(void) ehci_reset(ehci);
	(void) ehci_pci_reinit(ehci, pdev);

	/* emptying the schedule aborts any urbs */
	spin_lock_irq(&ehci->lock);
	if (ehci->reclaim)
		ehci->reclaim_ready = 1;
	ehci_work(ehci, NULL);
	spin_unlock_irq(&ehci->lock);

	/* restart; khubd will disconnect devices */
	retval = ehci_run(hcd);

	/* here we "know" root ports should always stay powered */
	ehci_port_power(ehci, 1);

	return retval;
}
#endif

static const struct hc_driver ehci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"EHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ehci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ehci_irq,
	.flags =		HCD_MEMORY | HCD_USB2,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ehci_pci_setup,
	.start =		ehci_run,
#ifdef	CONFIG_PM
	.suspend =		ehci_pci_suspend,
	.resume =		ehci_pci_resume,
#endif
	.stop =			ehci_stop,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ehci_urb_enqueue,
	.urb_dequeue =		ehci_urb_dequeue,
	.endpoint_disable =	ehci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ehci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ehci_hub_status_data,
	.hub_control =		ehci_hub_control,
	.bus_suspend =		ehci_bus_suspend,
	.bus_resume =		ehci_bus_resume,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,

#ifdef	CONFIG_PM
	.suspend =	usb_hcd_pci_suspend,
	.resume =	usb_hcd_pci_resume,
#endif
};

static int __init ehci_hcd_pci_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
		hcd_name,
		sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
		sizeof(struct ehci_itd), sizeof(struct ehci_sitd));

	return pci_register_driver(&ehci_pci_driver);
}
module_init(ehci_hcd_pci_init);

static void __exit ehci_hcd_pci_cleanup(void)
{
	pci_unregister_driver(&ehci_pci_driver);
}
module_exit(ehci_hcd_pci_cleanup);
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef CONFIG_PCI
	22	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	23	#endif
	24
	25	/-------------------------------------------------------------------------/
	26
	27	/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
	28	* off the controller (maybe it can boot from highspeed USB disks).
	29	*/
abcc9448	30	static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
7ff71d6a MP	31	{
	32	struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
	33
	34	/* always say Linux will own the hardware */
	35	pci_write_config_byte(pdev, where + 3, 1);
	36
	37	/* maybe wait a while for BIOS to respond */
	38	if (cap & (1 << 16)) {
	39	int msec = 5000;
	40
	41	do {
	42	msleep(10);
	43	msec -= 10;
	44	pci_read_config_dword(pdev, where, &cap);
	45	} while ((cap & (1 << 16)) && msec);
	46	if (cap & (1 << 16)) {
	47	ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
	48	where, cap);
	49	// some BIOS versions seem buggy...
	50	// return 1;
abcc9448	51	ehci_warn(ehci, "continuing after BIOS bug...\n");
7ff71d6a MP	52	/* disable all SMIs, and clear "BIOS owns" flag */
	53	pci_write_config_dword(pdev, where + 4, 0);
	54	pci_write_config_byte(pdev, where + 2, 0);
	55	} else
	56	ehci_dbg(ehci, "BIOS handoff succeeded\n");
	57	}
	58	return 0;
	59	}
	60
18807521 DB	61	/* called after powerup, by probe or system-pm "wakeup" */
	62	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	63	{
	64	u32 temp;
	65	int retval;
	66	unsigned count = 256/4;
	67
	68	/* optional debug port, normally in the first BAR */
	69	temp = pci_find_capability(pdev, 0x0a);
	70	if (temp) {
	71	pci_read_config_dword(pdev, temp, &temp);
	72	temp >>= 16;
	73	if ((temp & (3 << 13)) == (1 << 13)) {
	74	temp &= 0x1fff;
	75	ehci->debug = ehci_to_hcd(ehci)->regs + temp;
	76	temp = readl(&ehci->debug->control);
	77	ehci_info(ehci, "debug port %d%s\n",
	78	HCS_DEBUG_PORT(ehci->hcs_params),
	79	(temp & DBGP_ENABLED)
	80	? " IN USE"
	81	: "");
	82	if (!(temp & DBGP_ENABLED))
	83	ehci->debug = NULL;
	84	}
	85	}
	86
	87	temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
	88
	89	/* EHCI 0.96 and later may have "extended capabilities" */
	90	while (temp && count--) {
	91	u32 cap;
	92
	93	pci_read_config_dword(pdev, temp, &cap);
	94	ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
	95	switch (cap & 0xff) {
	96	case 1: /* BIOS/SMM/... handoff */
	97	if (bios_handoff(ehci, temp, cap) != 0)
	98	return -EOPNOTSUPP;
	99	break;
	100	case 0: /* illegal reserved capability */
	101	ehci_dbg(ehci, "illegal capability!\n");
	102	cap = 0;
	103	/* FALLTHROUGH */
	104	default: /* unknown */
	105	break;
	106	}
	107	temp = (cap >> 8) & 0xff;
	108	}
	109	if (!count) {
	110	ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
	111	return -EIO;
	112	}
	113
	114	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	115	retval = pci_set_mwi(pdev);
	116	if (!retval)
	117	ehci_dbg(ehci, "MWI active\n");
	118
	119	ehci_port_power(ehci, 0);
	120
	121	return 0;
	122	}
	123
8926bfa7 DB	124	/* called during probe() after chip reset completes */
8926bfa7 DB	125	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	126	{
abcc9448 DB	127	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	128	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	129	u32 temp;
18807521	130	int retval;
7ff71d6a MP	131
7ff71d6a MP	132	ehci->caps = hcd->regs;
abcc9448 DB	133	ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
	134	dbg_hcs_params(ehci, "reset");
	135	dbg_hcc_params(ehci, "reset");
7ff71d6a MP	136
7ff71d6a MP	137	/* cache this readonly data; minimize chip reads */
abcc9448	138	ehci->hcs_params = readl(&ehci->caps->hcs_params);
7ff71d6a	139
18807521 DB	140	retval = ehci_halt(ehci);
	141	if (retval)
	142	return retval;
	143
8926bfa7 DB	144	/* data structure init */
	145	retval = ehci_init(hcd);
	146	if (retval)
	147	return retval;
	148
abcc9448	149	/* NOTE: only the parts below this line are PCI-specific */
7ff71d6a	150
abcc9448 DB	151	switch (pdev->vendor) {
	152	case PCI_VENDOR_ID_TDI:
	153	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
	154	ehci->is_tdi_rh_tt = 1;
	155	tdi_reset(ehci);
	156	}
	157	break;
	158	case PCI_VENDOR_ID_AMD:
	159	/* AMD8111 EHCI doesn't work, according to AMD errata */
	160	if (pdev->device == 0x7463) {
	161	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	162	retval = -EIO;
8926bfa7 DB	163	goto done;
abcc9448 DB	164	}
	165	break;
	166	case PCI_VENDOR_ID_NVIDIA:
	167	/* NVidia reports that certain chips don't handle
	168	* QH, ITD, or SITD addresses above 2GB. (But TD,
	169	* data buffer, and periodic schedule are normal.)
	170	*/
	171	switch (pdev->device) {
	172	case 0x003c: /* MCP04 */
	173	case 0x005b: /* CK804 */
	174	case 0x00d8: /* CK8 */
	175	case 0x00e8: /* CK8S */
	176	if (pci_set_consistent_dma_mask(pdev,
	177	DMA_31BIT_MASK) < 0)
	178	ehci_warn(ehci, "can't enable NVidia "
	179	"workaround for >2GB RAM\n");
7ff71d6a MP	180	break;
7ff71d6a MP	181	}
abcc9448 DB	182	break;
abcc9448 DB	183	}
7ff71d6a	184
7ff71d6a	185	if (ehci_is_TDI(ehci))
abcc9448	186	ehci_reset(ehci);
7ff71d6a	187
7ff71d6a MP	188	/* at least the Genesys GL880S needs fixup here */
	189	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	190	temp &= 0x0f;
	191	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	192	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	193	"cc=%d x pcc=%d < ports=%d\n",
	194	HCS_N_CC(ehci->hcs_params),
	195	HCS_N_PCC(ehci->hcs_params),
	196	HCS_N_PORTS(ehci->hcs_params));
	197
abcc9448 DB	198	switch (pdev->vendor) {
	199	case 0x17a0: /* GENESYS */
	200	/* GL880S: should be PORTS=2 */
	201	temp \|= (ehci->hcs_params & ~0xf);
	202	ehci->hcs_params = temp;
	203	break;
	204	case PCI_VENDOR_ID_NVIDIA:
	205	/* NF4: should be PCC=10 */
	206	break;
7ff71d6a MP	207	}
	208	}
	209
abcc9448 DB	210	/* Serial Bus Release Number is at PCI 0x60 offset */
abcc9448 DB	211	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	212
2c1c3c4c DB	213	/* Workaround current PCI init glitch: wakeup bits aren't
	214	* being set from PCI PM capability.
	215	*/
	216	if (!device_can_wakeup(&pdev->dev)) {
	217	u16 port_wake;
	218
	219	pci_read_config_word(pdev, 0x62, &port_wake);
	220	if (port_wake & 0x0001)
	221	device_init_wakeup(&pdev->dev, 1);
	222	}
7ff71d6a	223
18807521	224	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	225	done:
8926bfa7 DB	226	return retval;
7ff71d6a MP	227	}
	228
	229	/-------------------------------------------------------------------------/
	230
	231	#ifdef CONFIG_PM
	232
	233	/* suspend/resume, section 4.3 */
	234
f03c17fc	235	/* These routines rely on the PCI bus glue
7ff71d6a MP	236	* to handle powerdown and wakeup, and currently also on
	237	* transceivers that don't need any software attention to set up
	238	* the right sort of wakeup.
f03c17fc	239	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	240	*/
7ff71d6a MP	241
abcc9448	242	static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
7ff71d6a	243	{
abcc9448	244	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
8de98402 BH	245	unsigned long flags;
8de98402 BH	246	int rc = 0;
7ff71d6a	247
abcc9448 DB	248	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	249	msleep(10);
7ff71d6a	250
8de98402 BH	251	/* Root hub was already suspended. Disable irq emission and
	252	* mark HW unaccessible, bail out if RH has been resumed. Use
	253	* the spinlock to properly synchronize with possible pending
	254	* RH suspend or resume activity.
	255	*
	256	* This is still racy as hcd->state is manipulated outside of
	257	* any locks =P But that will be a different fix.
	258	*/
	259	spin_lock_irqsave (&ehci->lock, flags);
	260	if (hcd->state != HC_STATE_SUSPENDED) {
	261	rc = -EINVAL;
	262	goto bail;
	263	}
	264	writel (0, &ehci->regs->intr_enable);
	265	(void)readl(&ehci->regs->intr_enable);
	266
	267	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	268	bail:
	269	spin_unlock_irqrestore (&ehci->lock, flags);
	270
f03c17fc	271	// could save FLADJ in case of Vaux power loss
7ff71d6a MP	272	// ... we'd only use it to handle clock skew
7ff71d6a MP	273
8de98402	274	return rc;
7ff71d6a MP	275	}
7ff71d6a MP	276
abcc9448	277	static int ehci_pci_resume(struct usb_hcd *hcd)
7ff71d6a	278	{
abcc9448	279	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
7ff71d6a	280	unsigned port;
18807521	281	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a MP	282	int retval = -EINVAL;
7ff71d6a MP	283
f03c17fc	284	// maybe restore FLADJ
7ff71d6a	285
abcc9448 DB	286	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	287	msleep(100);
7ff71d6a	288
8de98402 BH	289	/* Mark hardware accessible again as we are out of D3 state by now */
	290	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	291
f03c17fc	292	/* If CF is clear, we lost PCI Vaux power and need to restart. */
18807521	293	if (readl(&ehci->regs->configured_flag) != FLAG_CF)
f03c17fc DB	294	goto restart;
f03c17fc DB	295
7ff71d6a MP	296	/* If any port is suspended (or owned by the companion),
7ff71d6a MP	297	* we know we can/must resume the HC (and mustn't reset it).
f03c17fc	298	* We just defer that to the root hub code.
7ff71d6a	299	*/
abcc9448	300	for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
7ff71d6a MP	301	u32 status;
7ff71d6a MP	302	port--;
abcc9448	303	status = readl(&ehci->regs->port_status [port]);
7ff71d6a MP	304	if (!(status & PORT_POWER))
7ff71d6a MP	305	continue;
f03c17fc DB	306	if (status & (PORT_SUSPEND \| PORT_RESUME \| PORT_OWNER)) {
	307	usb_hcd_resume_root_hub(hcd);
	308	return 0;
7ff71d6a	309	}
f03c17fc DB	310	}
	311
	312	restart:
	313	ehci_dbg(ehci, "lost power, restarting\n");
1c50c317	314	usb_root_hub_lost_power(hcd->self.root_hub);
7ff71d6a MP	315
7ff71d6a MP	316	/* Else reset, to cope with power loss or flush-to-storage
f03c17fc	317	* style "resume" having let BIOS kick in during reboot.
7ff71d6a	318	*/
abcc9448 DB	319	(void) ehci_halt(ehci);
abcc9448 DB	320	(void) ehci_reset(ehci);
18807521	321	(void) ehci_pci_reinit(ehci, pdev);
f03c17fc DB	322
f03c17fc DB	323	/* emptying the schedule aborts any urbs */
abcc9448	324	spin_lock_irq(&ehci->lock);
f03c17fc DB	325	if (ehci->reclaim)
f03c17fc DB	326	ehci->reclaim_ready = 1;
abcc9448 DB	327	ehci_work(ehci, NULL);
abcc9448 DB	328	spin_unlock_irq(&ehci->lock);
f03c17fc DB	329
f03c17fc DB	330	/* restart; khubd will disconnect devices */
abcc9448	331	retval = ehci_run(hcd);
f03c17fc	332
18807521	333	/* here we "know" root ports should always stay powered */
abcc9448	334	ehci_port_power(ehci, 1);
7ff71d6a MP	335
	336	return retval;
	337	}
	338	#endif
	339
	340	static const struct hc_driver ehci_pci_hc_driver = {
	341	.description = hcd_name,
	342	.product_desc = "EHCI Host Controller",
	343	.hcd_priv_size = sizeof(struct ehci_hcd),
	344
	345	/*
	346	* generic hardware linkage
	347	*/
	348	.irq = ehci_irq,
	349	.flags = HCD_MEMORY \| HCD_USB2,
	350
	351	/*
	352	* basic lifecycle operations
	353	*/
8926bfa7	354	.reset = ehci_pci_setup,
18807521	355	.start = ehci_run,
7ff71d6a MP	356	#ifdef CONFIG_PM
	357	.suspend = ehci_pci_suspend,
	358	.resume = ehci_pci_resume,
	359	#endif
18807521	360	.stop = ehci_stop,
7ff71d6a MP	361
	362	/*
	363	* managing i/o requests and associated device resources
	364	*/
	365	.urb_enqueue = ehci_urb_enqueue,
	366	.urb_dequeue = ehci_urb_dequeue,
	367	.endpoint_disable = ehci_endpoint_disable,
	368
	369	/*
	370	* scheduling support
	371	*/
	372	.get_frame_number = ehci_get_frame,
	373
	374	/*
	375	* root hub support
	376	*/
	377	.hub_status_data = ehci_hub_status_data,
	378	.hub_control = ehci_hub_control,
0c0382e3 AS	379	.bus_suspend = ehci_bus_suspend,
0c0382e3 AS	380	.bus_resume = ehci_bus_resume,
7ff71d6a MP	381	};
	382
	383	/-------------------------------------------------------------------------/
	384
	385	/* PCI driver selection metadata; PCI hotplugging uses this */
	386	static const struct pci_device_id pci_ids [] = { {
	387	/* handle any USB 2.0 EHCI controller */
	388	PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) \| 0x20), ~0),
	389	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	390	},
	391	{ /* end: all zeroes */ }
	392	};
abcc9448	393	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	394
	395	/* pci driver glue; this is a "new style" PCI driver module */
	396	static struct pci_driver ehci_pci_driver = {
	397	.name = (char *) hcd_name,
	398	.id_table = pci_ids,
	399
	400	.probe = usb_hcd_pci_probe,
	401	.remove = usb_hcd_pci_remove,
	402
	403	#ifdef CONFIG_PM
	404	.suspend = usb_hcd_pci_suspend,
	405	.resume = usb_hcd_pci_resume,
	406	#endif
	407	};
	408
abcc9448	409	static int __init ehci_hcd_pci_init(void)
7ff71d6a MP	410	{
	411	if (usb_disabled())
	412	return -ENODEV;
	413
abcc9448	414	pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
7ff71d6a	415	hcd_name,
abcc9448 DB	416	sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
abcc9448 DB	417	sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
7ff71d6a	418
abcc9448	419	return pci_register_driver(&ehci_pci_driver);
7ff71d6a	420	}
abcc9448	421	module_init(ehci_hcd_pci_init);
7ff71d6a	422
abcc9448	423	static void __exit ehci_hcd_pci_cleanup(void)
7ff71d6a	424	{
abcc9448	425	pci_unregister_driver(&ehci_pci_driver);
7ff71d6a	426	}
abcc9448	427	module_exit(ehci_hcd_pci_cleanup);