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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/slab.h> | |
3c04e20e | 27 | #include <linux/vmalloc.h> |
1da177e4 LT |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/interrupt.h> | |
1da177e4 LT |
33 | #include <linux/usb.h> |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/dma-mapping.h> | |
694cc208 | 36 | #include <linux/debugfs.h> |
1da177e4 LT |
37 | |
38 | #include "../core/hcd.h" | |
39 | ||
40 | #include <asm/byteorder.h> | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/unaligned.h> | |
1da177e4 LT |
45 | |
46 | /*-------------------------------------------------------------------------*/ | |
47 | ||
48 | /* | |
49 | * EHCI hc_driver implementation ... experimental, incomplete. | |
50 | * Based on the final 1.0 register interface specification. | |
51 | * | |
52 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
53 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
54 | * Next comes "CardBay", using USB 2.0 signals. | |
55 | * | |
56 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
57 | * Special thanks to Intel and VIA for providing host controllers to | |
58 | * test this driver on, and Cypress (including In-System Design) for | |
59 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
60 | */ |
61 | ||
1da177e4 LT |
62 | #define DRIVER_AUTHOR "David Brownell" |
63 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
64 | ||
65 | static const char hcd_name [] = "ehci_hcd"; | |
66 | ||
67 | ||
9776afc8 | 68 | #undef VERBOSE_DEBUG |
1da177e4 LT |
69 | #undef EHCI_URB_TRACE |
70 | ||
71 | #ifdef DEBUG | |
72 | #define EHCI_STATS | |
73 | #endif | |
74 | ||
75 | /* magic numbers that can affect system performance */ | |
76 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
77 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
78 | #define EHCI_TUNE_RL_TT 0 | |
79 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
80 | #define EHCI_TUNE_MULT_TT 1 | |
81 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
82 | ||
07d29b63 | 83 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
84 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
85 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
b9638011 | 86 | #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ |
1da177e4 LT |
87 | |
88 | /* Initial IRQ latency: faster than hw default */ | |
89 | static int log2_irq_thresh = 0; // 0 to 6 | |
90 | module_param (log2_irq_thresh, int, S_IRUGO); | |
91 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
92 | ||
93 | /* initial park setting: slower than hw default */ | |
94 | static unsigned park = 0; | |
95 | module_param (park, uint, S_IRUGO); | |
96 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
97 | ||
93f1a47c DB |
98 | /* for flakey hardware, ignore overcurrent indicators */ |
99 | static int ignore_oc = 0; | |
100 | module_param (ignore_oc, bool, S_IRUGO); | |
101 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
102 | ||
1da177e4 LT |
103 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
104 | ||
105 | /*-------------------------------------------------------------------------*/ | |
106 | ||
107 | #include "ehci.h" | |
108 | #include "ehci-dbg.c" | |
109 | ||
110 | /*-------------------------------------------------------------------------*/ | |
111 | ||
bc29847e AS |
112 | static void |
113 | timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) | |
114 | { | |
115 | /* Don't override timeouts which shrink or (later) disable | |
116 | * the async ring; just the I/O watchdog. Note that if a | |
117 | * SHRINK were pending, OFF would never be requested. | |
118 | */ | |
119 | if (timer_pending(&ehci->watchdog) | |
120 | && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) | |
121 | & ehci->actions)) | |
122 | return; | |
123 | ||
124 | if (!test_and_set_bit(action, &ehci->actions)) { | |
125 | unsigned long t; | |
126 | ||
127 | switch (action) { | |
128 | case TIMER_IO_WATCHDOG: | |
403dbd36 AD |
129 | if (!ehci->need_io_watchdog) |
130 | return; | |
bc29847e AS |
131 | t = EHCI_IO_JIFFIES; |
132 | break; | |
133 | case TIMER_ASYNC_OFF: | |
134 | t = EHCI_ASYNC_JIFFIES; | |
135 | break; | |
136 | /* case TIMER_ASYNC_SHRINK: */ | |
137 | default: | |
138 | /* add a jiffie since we synch against the | |
139 | * 8 KHz uframe counter. | |
140 | */ | |
141 | t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; | |
142 | break; | |
143 | } | |
144 | mod_timer(&ehci->watchdog, t + jiffies); | |
145 | } | |
146 | } | |
147 | ||
148 | /*-------------------------------------------------------------------------*/ | |
149 | ||
1da177e4 LT |
150 | /* |
151 | * handshake - spin reading hc until handshake completes or fails | |
152 | * @ptr: address of hc register to be read | |
153 | * @mask: bits to look at in result of read | |
154 | * @done: value of those bits when handshake succeeds | |
155 | * @usec: timeout in microseconds | |
156 | * | |
157 | * Returns negative errno, or zero on success | |
158 | * | |
159 | * Success happens when the "mask" bits have the specified value (hardware | |
160 | * handshake done). There are two failure modes: "usec" have passed (major | |
161 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
162 | * | |
163 | * That last failure should_only happen in cases like physical cardbus eject | |
164 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
165 | * bridge shutdown: shutting down the bridge before the devices using it. | |
166 | */ | |
083522d7 BH |
167 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
168 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
169 | { |
170 | u32 result; | |
171 | ||
172 | do { | |
083522d7 | 173 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
174 | if (result == ~(u32)0) /* card removed */ |
175 | return -ENODEV; | |
176 | result &= mask; | |
177 | if (result == done) | |
178 | return 0; | |
179 | udelay (1); | |
180 | usec--; | |
181 | } while (usec > 0); | |
182 | return -ETIMEDOUT; | |
183 | } | |
184 | ||
185 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ | |
186 | static int ehci_halt (struct ehci_hcd *ehci) | |
187 | { | |
083522d7 | 188 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 189 | |
72f30b6f | 190 | /* disable any irqs left enabled by previous code */ |
083522d7 | 191 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 192 | |
1da177e4 LT |
193 | if ((temp & STS_HALT) != 0) |
194 | return 0; | |
195 | ||
083522d7 | 196 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 197 | temp &= ~CMD_RUN; |
083522d7 BH |
198 | ehci_writel(ehci, temp, &ehci->regs->command); |
199 | return handshake (ehci, &ehci->regs->status, | |
200 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
201 | } |
202 | ||
0bcfeb3e DB |
203 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
204 | u32 mask, u32 done, int usec) | |
205 | { | |
206 | int error; | |
207 | ||
208 | error = handshake(ehci, ptr, mask, done, usec); | |
209 | if (error) { | |
210 | ehci_halt(ehci); | |
211 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
212 | ehci_err(ehci, "force halt; handhake %p %08x %08x -> %d\n", | |
213 | ptr, mask, done, error); | |
214 | } | |
215 | ||
216 | return error; | |
217 | } | |
218 | ||
1da177e4 LT |
219 | /* put TDI/ARC silicon into EHCI mode */ |
220 | static void tdi_reset (struct ehci_hcd *ehci) | |
221 | { | |
222 | u32 __iomem *reg_ptr; | |
223 | u32 tmp; | |
224 | ||
d23a1377 | 225 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 226 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
227 | tmp |= USBMODE_CM_HC; |
228 | /* The default byte access to MMR space is LE after | |
229 | * controller reset. Set the required endian mode | |
230 | * for transfer buffers to match the host microprocessor | |
231 | */ | |
232 | if (ehci_big_endian_mmio(ehci)) | |
233 | tmp |= USBMODE_BE; | |
083522d7 | 234 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
235 | } |
236 | ||
237 | /* reset a non-running (STS_HALT == 1) controller */ | |
238 | static int ehci_reset (struct ehci_hcd *ehci) | |
239 | { | |
240 | int retval; | |
083522d7 | 241 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 242 | |
8d053c79 JW |
243 | /* If the EHCI debug controller is active, special care must be |
244 | * taken before and after a host controller reset */ | |
245 | if (ehci->debug && !dbgp_reset_prep()) | |
246 | ehci->debug = NULL; | |
247 | ||
1da177e4 LT |
248 | command |= CMD_RESET; |
249 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 250 | ehci_writel(ehci, command, &ehci->regs->command); |
1da177e4 LT |
251 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; |
252 | ehci->next_statechange = jiffies; | |
083522d7 BH |
253 | retval = handshake (ehci, &ehci->regs->command, |
254 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 | 255 | |
331ac6b2 AD |
256 | if (ehci->has_hostpc) { |
257 | ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, | |
258 | (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); | |
259 | ehci_writel(ehci, TXFIFO_DEFAULT, | |
260 | (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); | |
261 | } | |
1da177e4 LT |
262 | if (retval) |
263 | return retval; | |
264 | ||
265 | if (ehci_is_TDI(ehci)) | |
266 | tdi_reset (ehci); | |
267 | ||
8d053c79 JW |
268 | if (ehci->debug) |
269 | dbgp_external_startup(); | |
270 | ||
1da177e4 LT |
271 | return retval; |
272 | } | |
273 | ||
274 | /* idle the controller (from running) */ | |
275 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
276 | { | |
277 | u32 temp; | |
278 | ||
279 | #ifdef DEBUG | |
280 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
281 | BUG (); | |
282 | #endif | |
283 | ||
284 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 285 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 286 | temp &= STS_ASS | STS_PSS; |
c765d4ca KW |
287 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
288 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 289 | return; |
1da177e4 LT |
290 | |
291 | /* then disable anything that's still active */ | |
083522d7 | 292 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 293 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 294 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
295 | |
296 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
297 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
298 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
299 | } |
300 | ||
301 | /*-------------------------------------------------------------------------*/ | |
302 | ||
07d29b63 | 303 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 304 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
305 | |
306 | #include "ehci-hub.c" | |
307 | #include "ehci-mem.c" | |
308 | #include "ehci-q.c" | |
309 | #include "ehci-sched.c" | |
310 | ||
311 | /*-------------------------------------------------------------------------*/ | |
312 | ||
07d29b63 | 313 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
314 | { |
315 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
316 | unsigned long flags; | |
317 | ||
318 | spin_lock_irqsave (&ehci->lock, flags); | |
319 | ||
e82cc128 DB |
320 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
321 | * So we need this watchdog, but must protect it against both | |
322 | * (a) SMP races against real IAA firing and retriggering, and | |
323 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
324 | */ | |
325 | if (ehci->reclaim | |
326 | && !timer_pending(&ehci->iaa_watchdog) | |
327 | && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
328 | u32 cmd, status; | |
329 | ||
330 | /* If we get here, IAA is *REALLY* late. It's barely | |
331 | * conceivable that the system is so busy that CMD_IAAD | |
332 | * is still legitimately set, so let's be sure it's | |
333 | * clear before we read STS_IAA. (The HC should clear | |
334 | * CMD_IAAD when it sets STS_IAA.) | |
335 | */ | |
336 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
337 | if (cmd & CMD_IAAD) | |
338 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
339 | &ehci->regs->command); | |
340 | ||
341 | /* If IAA is set here it either legitimately triggered | |
342 | * before we cleared IAAD above (but _way_ late, so we'll | |
343 | * still count it as lost) ... or a silicon erratum: | |
344 | * - VIA seems to set IAA without triggering the IRQ; | |
345 | * - IAAD potentially cleared without setting IAA. | |
346 | */ | |
347 | status = ehci_readl(ehci, &ehci->regs->status); | |
348 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 349 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 350 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 351 | } |
e82cc128 DB |
352 | |
353 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
354 | status, cmd); | |
07d29b63 | 355 | end_unlink_async(ehci); |
1da177e4 LT |
356 | } |
357 | ||
07d29b63 AS |
358 | spin_unlock_irqrestore(&ehci->lock, flags); |
359 | } | |
360 | ||
361 | static void ehci_watchdog(unsigned long param) | |
362 | { | |
363 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
364 | unsigned long flags; | |
365 | ||
366 | spin_lock_irqsave(&ehci->lock, flags); | |
367 | ||
368 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 369 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 370 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
371 | |
372 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 373 | ehci_work (ehci); |
1da177e4 LT |
374 | |
375 | spin_unlock_irqrestore (&ehci->lock, flags); | |
376 | } | |
377 | ||
8903795a AS |
378 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
379 | * The firmware seems to think that powering off is a wakeup event! | |
380 | * This routine turns off remote wakeup and everything else, on all ports. | |
381 | */ | |
382 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
383 | { | |
384 | int port = HCS_N_PORTS(ehci->hcs_params); | |
385 | ||
386 | while (port--) | |
387 | ehci_writel(ehci, PORT_RWC_BITS, | |
388 | &ehci->regs->port_status[port]); | |
389 | } | |
390 | ||
21da84a8 SS |
391 | /* |
392 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
393 | * Should be called with ehci->lock held. | |
72f30b6f | 394 | */ |
21da84a8 | 395 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 396 | { |
21da84a8 | 397 | ehci_halt(ehci); |
8903795a | 398 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
399 | |
400 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 401 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
402 | |
403 | /* unblock posted writes */ | |
404 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
405 | } |
406 | ||
21da84a8 SS |
407 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
408 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
409 | * where the next system software may expect clean state. | |
410 | */ | |
411 | static void ehci_shutdown(struct usb_hcd *hcd) | |
412 | { | |
413 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
414 | ||
415 | del_timer_sync(&ehci->watchdog); | |
416 | del_timer_sync(&ehci->iaa_watchdog); | |
417 | ||
418 | spin_lock_irq(&ehci->lock); | |
419 | ehci_silence_controller(ehci); | |
420 | spin_unlock_irq(&ehci->lock); | |
421 | } | |
422 | ||
56c1e26d DB |
423 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
424 | { | |
425 | unsigned port; | |
426 | ||
427 | if (!HCS_PPC (ehci->hcs_params)) | |
428 | return; | |
429 | ||
430 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
431 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
432 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
433 | is_on ? SetPortFeature : ClearPortFeature, | |
434 | USB_PORT_FEAT_POWER, | |
435 | port--, NULL, 0); | |
383975d7 AS |
436 | /* Flush those writes */ |
437 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
438 | msleep(20); |
439 | } | |
440 | ||
7ff71d6a | 441 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 442 | |
7ff71d6a MP |
443 | /* |
444 | * ehci_work is called from some interrupts, timers, and so on. | |
445 | * it calls driver completion functions, after dropping ehci->lock. | |
446 | */ | |
7d12e780 | 447 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
448 | { |
449 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
450 | |
451 | /* another CPU may drop ehci->lock during a schedule scan while | |
452 | * it reports urb completions. this flag guards against bogus | |
453 | * attempts at re-entrant schedule scanning. | |
454 | */ | |
455 | if (ehci->scanning) | |
456 | return; | |
457 | ehci->scanning = 1; | |
7d12e780 | 458 | scan_async (ehci); |
7ff71d6a | 459 | if (ehci->next_uframe != -1) |
7d12e780 | 460 | scan_periodic (ehci); |
7ff71d6a MP |
461 | ehci->scanning = 0; |
462 | ||
463 | /* the IO watchdog guards against hardware or driver bugs that | |
464 | * misplace IRQs, and should let us run completely without IRQs. | |
465 | * such lossage has been observed on both VT6202 and VT8235. | |
466 | */ | |
467 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
468 | (ehci->async->qh_next.ptr != NULL || | |
469 | ehci->periodic_sched != 0)) | |
470 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
471 | } | |
1da177e4 | 472 | |
21da84a8 SS |
473 | /* |
474 | * Called when the ehci_hcd module is removed. | |
475 | */ | |
7ff71d6a | 476 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
477 | { |
478 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 479 | |
7ff71d6a | 480 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 481 | |
7ff71d6a MP |
482 | /* no more interrupts ... */ |
483 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 484 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 485 | |
7ff71d6a MP |
486 | spin_lock_irq(&ehci->lock); |
487 | if (HC_IS_RUNNING (hcd->state)) | |
488 | ehci_quiesce (ehci); | |
1da177e4 | 489 | |
21da84a8 | 490 | ehci_silence_controller(ehci); |
7ff71d6a | 491 | ehci_reset (ehci); |
7ff71d6a | 492 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 493 | |
57e06c11 | 494 | remove_companion_file(ehci); |
7ff71d6a | 495 | remove_debug_files (ehci); |
1da177e4 | 496 | |
7ff71d6a MP |
497 | /* root hub is shut down separately (first, when possible) */ |
498 | spin_lock_irq (&ehci->lock); | |
499 | if (ehci->async) | |
7d12e780 | 500 | ehci_work (ehci); |
7ff71d6a MP |
501 | spin_unlock_irq (&ehci->lock); |
502 | ehci_mem_cleanup (ehci); | |
1da177e4 | 503 | |
7ff71d6a MP |
504 | #ifdef EHCI_STATS |
505 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
506 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
507 | ehci->stats.lost_iaa); | |
508 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
509 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 510 | #endif |
1da177e4 | 511 | |
083522d7 BH |
512 | dbg_status (ehci, "ehci_stop completed", |
513 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
514 | } |
515 | ||
18807521 DB |
516 | /* one-time init, only for memory state */ |
517 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 518 | { |
18807521 | 519 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 520 | u32 temp; |
1da177e4 LT |
521 | int retval; |
522 | u32 hcc_params; | |
3807e26d | 523 | struct ehci_qh_hw *hw; |
18807521 DB |
524 | |
525 | spin_lock_init(&ehci->lock); | |
526 | ||
403dbd36 AD |
527 | /* |
528 | * keep io watchdog by default, those good HCDs could turn off it later | |
529 | */ | |
530 | ehci->need_io_watchdog = 1; | |
18807521 DB |
531 | init_timer(&ehci->watchdog); |
532 | ehci->watchdog.function = ehci_watchdog; | |
533 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 534 | |
07d29b63 AS |
535 | init_timer(&ehci->iaa_watchdog); |
536 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
537 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
538 | ||
1da177e4 LT |
539 | /* |
540 | * hw default: 1K periodic list heads, one per frame. | |
541 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
542 | */ | |
543 | ehci->periodic_size = DEFAULT_I_TDPS; | |
9aa09d2f | 544 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
18807521 | 545 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
546 | return retval; |
547 | ||
548 | /* controllers may cache some of the periodic schedule ... */ | |
083522d7 | 549 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
53bd6a60 | 550 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
1da177e4 LT |
551 | ehci->i_thresh = 8; |
552 | else // N microframes cached | |
18807521 | 553 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
554 | |
555 | ehci->reclaim = NULL; | |
1da177e4 | 556 | ehci->next_uframe = -1; |
9aa09d2f | 557 | ehci->clock_frame = -1; |
1da177e4 | 558 | |
1da177e4 LT |
559 | /* |
560 | * dedicate a qh for the async ring head, since we couldn't unlink | |
561 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
562 | * as the 'reclamation list head' too. | |
563 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
564 | * from automatically advancing to the next td after short reads. | |
565 | */ | |
18807521 | 566 | ehci->async->qh_next.qh = NULL; |
3807e26d AD |
567 | hw = ehci->async->hw; |
568 | hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); | |
569 | hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
570 | hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); | |
571 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 572 | ehci->async->qh_state = QH_STATE_LINKED; |
3807e26d | 573 | hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
574 | |
575 | /* clear interrupt enables, set irq latency */ | |
576 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
577 | log2_irq_thresh = 0; | |
578 | temp = 1 << (16 + log2_irq_thresh); | |
579 | if (HCC_CANPARK(hcc_params)) { | |
580 | /* HW default park == 3, on hardware that supports it (like | |
581 | * NVidia and ALI silicon), maximizes throughput on the async | |
582 | * schedule by avoiding QH fetches between transfers. | |
583 | * | |
584 | * With fast usb storage devices and NForce2, "park" seems to | |
585 | * make problems: throughput reduction (!), data errors... | |
586 | */ | |
587 | if (park) { | |
18807521 | 588 | park = min(park, (unsigned) 3); |
1da177e4 LT |
589 | temp |= CMD_PARK; |
590 | temp |= park << 8; | |
591 | } | |
18807521 | 592 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 593 | } |
18807521 | 594 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
595 | /* periodic schedule size can be smaller than default */ |
596 | temp &= ~(3 << 2); | |
597 | temp |= (EHCI_TUNE_FLS << 2); | |
598 | switch (EHCI_TUNE_FLS) { | |
599 | case 0: ehci->periodic_size = 1024; break; | |
600 | case 1: ehci->periodic_size = 512; break; | |
601 | case 2: ehci->periodic_size = 256; break; | |
18807521 | 602 | default: BUG(); |
1da177e4 LT |
603 | } |
604 | } | |
18807521 DB |
605 | ehci->command = temp; |
606 | ||
18807521 DB |
607 | return 0; |
608 | } | |
609 | ||
610 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
611 | static int ehci_run (struct usb_hcd *hcd) | |
612 | { | |
613 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
614 | int retval; | |
615 | u32 temp; | |
616 | u32 hcc_params; | |
617 | ||
1d619f12 MT |
618 | hcd->uses_new_polling = 1; |
619 | hcd->poll_rh = 0; | |
620 | ||
18807521 DB |
621 | /* EHCI spec section 4.1 */ |
622 | if ((retval = ehci_reset(ehci)) != 0) { | |
18807521 DB |
623 | ehci_mem_cleanup(ehci); |
624 | return retval; | |
625 | } | |
083522d7 BH |
626 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
627 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
628 | |
629 | /* | |
630 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
631 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
632 | * pci_pool consistent memory always uses segment zero. | |
633 | * streaming mappings for I/O buffers, like pci_map_single(), | |
634 | * can return segments above 4GB, if the device allows. | |
635 | * | |
636 | * NOTE: the dma mask is visible through dma_supported(), so | |
637 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
638 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
639 | * host side drivers though. | |
640 | */ | |
083522d7 | 641 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 642 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 643 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
644 | #if 0 |
645 | // this is deeply broken on almost all architectures | |
6a35528a | 646 | if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) |
18807521 DB |
647 | ehci_info(ehci, "enabled 64bit DMA\n"); |
648 | #endif | |
649 | } | |
650 | ||
651 | ||
1da177e4 LT |
652 | // Philips, Intel, and maybe others need CMD_RUN before the |
653 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
654 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
655 | ehci->command |= CMD_RUN; | |
083522d7 | 656 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 657 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 658 | |
1da177e4 LT |
659 | /* |
660 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
661 | * are explicitly handed to companion controller(s), so no TT is | |
662 | * involved with the root hub. (Except where one is integrated, | |
663 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
664 | * |
665 | * Turning on the CF flag will transfer ownership of all ports | |
666 | * from the companions to the EHCI controller. If any of the | |
667 | * companions are in the middle of a port reset at the time, it | |
668 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
669 | * guarantees that no resets are in progress. After we set CF, |
670 | * a short delay lets the hardware catch up; new resets shouldn't | |
671 | * be started before the port switching actions could complete. | |
1da177e4 | 672 | */ |
32fe0198 | 673 | down_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 674 | hcd->state = HC_STATE_RUNNING; |
083522d7 BH |
675 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
676 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 677 | msleep(5); |
32fe0198 | 678 | up_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 679 | |
083522d7 | 680 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 681 | ehci_info (ehci, |
2b70f073 | 682 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 683 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 684 | temp >> 8, temp & 0xff, |
93f1a47c | 685 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 686 | |
083522d7 BH |
687 | ehci_writel(ehci, INTR_MASK, |
688 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 689 | |
18807521 DB |
690 | /* GRR this is run-once init(), being done every time the HC starts. |
691 | * So long as they're part of class devices, we can't do it init() | |
692 | * since the class device isn't created that early. | |
693 | */ | |
694 | create_debug_files(ehci); | |
57e06c11 | 695 | create_companion_file(ehci); |
1da177e4 LT |
696 | |
697 | return 0; | |
698 | } | |
699 | ||
1da177e4 LT |
700 | /*-------------------------------------------------------------------------*/ |
701 | ||
7d12e780 | 702 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
703 | { |
704 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
67b2e029 | 705 | u32 status, masked_status, pcd_status = 0, cmd; |
1da177e4 LT |
706 | int bh; |
707 | ||
708 | spin_lock (&ehci->lock); | |
709 | ||
083522d7 | 710 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
711 | |
712 | /* e.g. cardbus physical eject */ | |
713 | if (status == ~(u32) 0) { | |
714 | ehci_dbg (ehci, "device removed\n"); | |
715 | goto dead; | |
716 | } | |
717 | ||
67b2e029 AS |
718 | masked_status = status & INTR_MASK; |
719 | if (!masked_status) { /* irq sharing? */ | |
1da177e4 LT |
720 | spin_unlock(&ehci->lock); |
721 | return IRQ_NONE; | |
722 | } | |
723 | ||
724 | /* clear (just) interrupts */ | |
67b2e029 | 725 | ehci_writel(ehci, masked_status, &ehci->regs->status); |
e82cc128 | 726 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
727 | bh = 0; |
728 | ||
9776afc8 | 729 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
730 | /* unrequested/ignored: Frame List Rollover */ |
731 | dbg_status (ehci, "irq", status); | |
732 | #endif | |
733 | ||
734 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
735 | ||
736 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
737 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
738 | if (likely ((status & STS_ERR) == 0)) | |
739 | COUNT (ehci->stats.normal); | |
740 | else | |
741 | COUNT (ehci->stats.error); | |
742 | bh = 1; | |
743 | } | |
744 | ||
745 | /* complete the unlinking of some qh [4.15.2.3] */ | |
746 | if (status & STS_IAA) { | |
e82cc128 DB |
747 | /* guard against (alleged) silicon errata */ |
748 | if (cmd & CMD_IAAD) { | |
749 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
750 | &ehci->regs->command); | |
751 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); | |
752 | } | |
753 | if (ehci->reclaim) { | |
754 | COUNT(ehci->stats.reclaim); | |
755 | end_unlink_async(ehci); | |
756 | } else | |
757 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
758 | } |
759 | ||
760 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 761 | if (status & STS_PCD) { |
1da177e4 | 762 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
d1b1842c DB |
763 | |
764 | /* kick root hub later */ | |
1d619f12 | 765 | pcd_status = status; |
1da177e4 LT |
766 | |
767 | /* resume root hub? */ | |
eafe5b99 | 768 | if (!(cmd & CMD_RUN)) |
8c03356a | 769 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
770 | |
771 | while (i--) { | |
083522d7 BH |
772 | int pstatus = ehci_readl(ehci, |
773 | &ehci->regs->port_status [i]); | |
b972b68c DB |
774 | |
775 | if (pstatus & PORT_OWNER) | |
1da177e4 | 776 | continue; |
eafe5b99 AS |
777 | if (!(test_bit(i, &ehci->suspended_ports) && |
778 | ((pstatus & PORT_RESUME) || | |
779 | !(pstatus & PORT_SUSPEND)) && | |
780 | (pstatus & PORT_PE) && | |
781 | ehci->reset_done[i] == 0)) | |
1da177e4 LT |
782 | continue; |
783 | ||
784 | /* start 20 msec resume signaling from this port, | |
785 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
786 | * stop that signaling. | |
787 | */ | |
788 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
1da177e4 | 789 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 790 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
791 | } |
792 | } | |
793 | ||
794 | /* PCI errors [4.15.2.4] */ | |
795 | if (unlikely ((status & STS_FATAL) != 0)) { | |
67b2e029 | 796 | ehci_err(ehci, "fatal error\n"); |
eafe5b99 AS |
797 | dbg_cmd(ehci, "fatal", cmd); |
798 | dbg_status(ehci, "fatal", status); | |
67b2e029 | 799 | ehci_halt(ehci); |
1da177e4 | 800 | dead: |
67b2e029 AS |
801 | ehci_reset(ehci); |
802 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); | |
803 | /* generic layer kills/unlinks all urbs, then | |
804 | * uses ehci_stop to clean up the rest | |
805 | */ | |
806 | bh = 1; | |
1da177e4 LT |
807 | } |
808 | ||
809 | if (bh) | |
7d12e780 | 810 | ehci_work (ehci); |
1da177e4 | 811 | spin_unlock (&ehci->lock); |
d1b1842c | 812 | if (pcd_status) |
1d619f12 | 813 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
814 | return IRQ_HANDLED; |
815 | } | |
816 | ||
817 | /*-------------------------------------------------------------------------*/ | |
818 | ||
819 | /* | |
820 | * non-error returns are a promise to giveback() the urb later | |
821 | * we drop ownership so next owner (or urb unlink) can get it | |
822 | * | |
823 | * urb + dev is in hcd.self.controller.urb_list | |
824 | * we're queueing TDs onto software and hardware lists | |
825 | * | |
826 | * hcd-specific init for hcpriv hasn't been done yet | |
827 | * | |
828 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
829 | * to a (possibly active) QH, and the same QH scanning code. | |
830 | */ | |
831 | static int ehci_urb_enqueue ( | |
832 | struct usb_hcd *hcd, | |
1da177e4 | 833 | struct urb *urb, |
55016f10 | 834 | gfp_t mem_flags |
1da177e4 LT |
835 | ) { |
836 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
837 | struct list_head qtd_list; | |
838 | ||
839 | INIT_LIST_HEAD (&qtd_list); | |
840 | ||
841 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
842 | case PIPE_CONTROL: |
843 | /* qh_completions() code doesn't handle all the fault cases | |
844 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
845 | */ | |
846 | if (urb->transfer_buffer_length > (16 * 1024)) | |
847 | return -EMSGSIZE; | |
848 | /* FALLTHROUGH */ | |
849 | /* case PIPE_BULK: */ | |
1da177e4 LT |
850 | default: |
851 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
852 | return -ENOMEM; | |
e9df41c5 | 853 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
854 | |
855 | case PIPE_INTERRUPT: | |
856 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
857 | return -ENOMEM; | |
e9df41c5 | 858 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
859 | |
860 | case PIPE_ISOCHRONOUS: | |
861 | if (urb->dev->speed == USB_SPEED_HIGH) | |
862 | return itd_submit (ehci, urb, mem_flags); | |
863 | else | |
864 | return sitd_submit (ehci, urb, mem_flags); | |
865 | } | |
866 | } | |
867 | ||
868 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
869 | { | |
07d29b63 | 870 | /* failfast */ |
e82cc128 | 871 | if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) |
07d29b63 AS |
872 | end_unlink_async(ehci); |
873 | ||
3a44494e AS |
874 | /* If the QH isn't linked then there's nothing we can do |
875 | * unless we were called during a giveback, in which case | |
876 | * qh_completions() has to deal with it. | |
877 | */ | |
878 | if (qh->qh_state != QH_STATE_LINKED) { | |
879 | if (qh->qh_state == QH_STATE_COMPLETING) | |
880 | qh->needs_rescan = 1; | |
881 | return; | |
882 | } | |
07d29b63 AS |
883 | |
884 | /* defer till later if busy */ | |
3a44494e | 885 | if (ehci->reclaim) { |
1da177e4 LT |
886 | struct ehci_qh *last; |
887 | ||
888 | for (last = ehci->reclaim; | |
889 | last->reclaim; | |
890 | last = last->reclaim) | |
891 | continue; | |
892 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
893 | last->reclaim = qh; | |
894 | ||
07d29b63 AS |
895 | /* start IAA cycle */ |
896 | } else | |
1da177e4 LT |
897 | start_unlink_async (ehci, qh); |
898 | } | |
899 | ||
900 | /* remove from hardware lists | |
901 | * completions normally happen asynchronously | |
902 | */ | |
903 | ||
e9df41c5 | 904 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
905 | { |
906 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
907 | struct ehci_qh *qh; | |
908 | unsigned long flags; | |
e9df41c5 | 909 | int rc; |
1da177e4 LT |
910 | |
911 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
912 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
913 | if (rc) | |
914 | goto done; | |
915 | ||
1da177e4 LT |
916 | switch (usb_pipetype (urb->pipe)) { |
917 | // case PIPE_CONTROL: | |
918 | // case PIPE_BULK: | |
919 | default: | |
920 | qh = (struct ehci_qh *) urb->hcpriv; | |
921 | if (!qh) | |
922 | break; | |
07d29b63 AS |
923 | switch (qh->qh_state) { |
924 | case QH_STATE_LINKED: | |
925 | case QH_STATE_COMPLETING: | |
926 | unlink_async(ehci, qh); | |
927 | break; | |
928 | case QH_STATE_UNLINK: | |
929 | case QH_STATE_UNLINK_WAIT: | |
930 | /* already started */ | |
931 | break; | |
932 | case QH_STATE_IDLE: | |
7a0f0d95 AS |
933 | /* QH might be waiting for a Clear-TT-Buffer */ |
934 | qh_completions(ehci, qh); | |
07d29b63 AS |
935 | break; |
936 | } | |
1da177e4 LT |
937 | break; |
938 | ||
939 | case PIPE_INTERRUPT: | |
940 | qh = (struct ehci_qh *) urb->hcpriv; | |
941 | if (!qh) | |
942 | break; | |
943 | switch (qh->qh_state) { | |
944 | case QH_STATE_LINKED: | |
a448c9d8 | 945 | case QH_STATE_COMPLETING: |
1da177e4 | 946 | intr_deschedule (ehci, qh); |
a448c9d8 | 947 | break; |
1da177e4 | 948 | case QH_STATE_IDLE: |
7d12e780 | 949 | qh_completions (ehci, qh); |
1da177e4 LT |
950 | break; |
951 | default: | |
952 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
953 | qh, qh->qh_state); | |
954 | goto done; | |
955 | } | |
1da177e4 LT |
956 | break; |
957 | ||
958 | case PIPE_ISOCHRONOUS: | |
959 | // itd or sitd ... | |
960 | ||
961 | // wait till next completion, do it then. | |
962 | // completion irqs can wait up to 1024 msec, | |
963 | break; | |
964 | } | |
965 | done: | |
966 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 967 | return rc; |
1da177e4 LT |
968 | } |
969 | ||
970 | /*-------------------------------------------------------------------------*/ | |
971 | ||
972 | // bulk qh holds the data toggle | |
973 | ||
974 | static void | |
975 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
976 | { | |
977 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
978 | unsigned long flags; | |
979 | struct ehci_qh *qh, *tmp; | |
980 | ||
981 | /* ASSERT: any requests/urbs are being unlinked */ | |
982 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
983 | ||
984 | rescan: | |
985 | spin_lock_irqsave (&ehci->lock, flags); | |
986 | qh = ep->hcpriv; | |
987 | if (!qh) | |
988 | goto done; | |
989 | ||
990 | /* endpoints can be iso streams. for now, we don't | |
991 | * accelerate iso completions ... so spin a while. | |
992 | */ | |
3807e26d | 993 | if (qh->hw->hw_info1 == 0) { |
1da177e4 LT |
994 | ehci_vdbg (ehci, "iso delay\n"); |
995 | goto idle_timeout; | |
996 | } | |
997 | ||
998 | if (!HC_IS_RUNNING (hcd->state)) | |
999 | qh->qh_state = QH_STATE_IDLE; | |
1000 | switch (qh->qh_state) { | |
1001 | case QH_STATE_LINKED: | |
3a44494e | 1002 | case QH_STATE_COMPLETING: |
1da177e4 LT |
1003 | for (tmp = ehci->async->qh_next.qh; |
1004 | tmp && tmp != qh; | |
1005 | tmp = tmp->qh_next.qh) | |
1006 | continue; | |
1007 | /* periodic qh self-unlinks on empty */ | |
1008 | if (!tmp) | |
1009 | goto nogood; | |
1010 | unlink_async (ehci, qh); | |
1011 | /* FALL THROUGH */ | |
1012 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 1013 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
1014 | idle_timeout: |
1015 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 1016 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
1017 | goto rescan; |
1018 | case QH_STATE_IDLE: /* fully unlinked */ | |
914b7012 AS |
1019 | if (qh->clearing_tt) |
1020 | goto idle_timeout; | |
1da177e4 LT |
1021 | if (list_empty (&qh->qtd_list)) { |
1022 | qh_put (qh); | |
1023 | break; | |
1024 | } | |
1025 | /* else FALL THROUGH */ | |
1026 | default: | |
1027 | nogood: | |
1028 | /* caller was supposed to have unlinked any requests; | |
1029 | * that's not our job. just leak this memory. | |
1030 | */ | |
1031 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1032 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1033 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1034 | break; | |
1035 | } | |
1036 | ep->hcpriv = NULL; | |
1037 | done: | |
1038 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1039 | return; | |
1040 | } | |
1041 | ||
b18ffd49 AS |
1042 | static void |
1043 | ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1044 | { | |
1045 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1046 | struct ehci_qh *qh; | |
1047 | int eptype = usb_endpoint_type(&ep->desc); | |
a455212d AS |
1048 | int epnum = usb_endpoint_num(&ep->desc); |
1049 | int is_out = usb_endpoint_dir_out(&ep->desc); | |
1050 | unsigned long flags; | |
b18ffd49 AS |
1051 | |
1052 | if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) | |
1053 | return; | |
1054 | ||
a455212d | 1055 | spin_lock_irqsave(&ehci->lock, flags); |
b18ffd49 AS |
1056 | qh = ep->hcpriv; |
1057 | ||
1058 | /* For Bulk and Interrupt endpoints we maintain the toggle state | |
1059 | * in the hardware; the toggle bits in udev aren't used at all. | |
1060 | * When an endpoint is reset by usb_clear_halt() we must reset | |
1061 | * the toggle bit in the QH. | |
1062 | */ | |
1063 | if (qh) { | |
a455212d | 1064 | usb_settoggle(qh->dev, epnum, is_out, 0); |
b18ffd49 AS |
1065 | if (!list_empty(&qh->qtd_list)) { |
1066 | WARN_ONCE(1, "clear_halt for a busy endpoint\n"); | |
3a44494e AS |
1067 | } else if (qh->qh_state == QH_STATE_LINKED || |
1068 | qh->qh_state == QH_STATE_COMPLETING) { | |
a455212d AS |
1069 | |
1070 | /* The toggle value in the QH can't be updated | |
1071 | * while the QH is active. Unlink it now; | |
1072 | * re-linking will call qh_refresh(). | |
b18ffd49 | 1073 | */ |
a448c9d8 | 1074 | if (eptype == USB_ENDPOINT_XFER_BULK) |
a455212d | 1075 | unlink_async(ehci, qh); |
a448c9d8 | 1076 | else |
a455212d | 1077 | intr_deschedule(ehci, qh); |
b18ffd49 AS |
1078 | } |
1079 | } | |
a455212d | 1080 | spin_unlock_irqrestore(&ehci->lock, flags); |
b18ffd49 AS |
1081 | } |
1082 | ||
7ff71d6a MP |
1083 | static int ehci_get_frame (struct usb_hcd *hcd) |
1084 | { | |
1085 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
083522d7 BH |
1086 | return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % |
1087 | ehci->periodic_size; | |
7ff71d6a | 1088 | } |
1da177e4 LT |
1089 | |
1090 | /*-------------------------------------------------------------------------*/ | |
1091 | ||
2b70f073 | 1092 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1093 | MODULE_AUTHOR (DRIVER_AUTHOR); |
1094 | MODULE_LICENSE ("GPL"); | |
1095 | ||
7ff71d6a MP |
1096 | #ifdef CONFIG_PCI |
1097 | #include "ehci-pci.c" | |
01cced25 | 1098 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1099 | #endif |
1da177e4 | 1100 | |
ba02978a | 1101 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1102 | #include "ehci-fsl.c" |
01cced25 | 1103 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1104 | #endif |
1105 | ||
dfbaa7d8 | 1106 | #ifdef CONFIG_SOC_AU1200 |
76fa9a24 | 1107 | #include "ehci-au1xxx.c" |
01cced25 | 1108 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1109 | #endif |
1110 | ||
ad75a410 GL |
1111 | #ifdef CONFIG_PPC_PS3 |
1112 | #include "ehci-ps3.c" | |
7a4eb7fd | 1113 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1114 | #endif |
1115 | ||
da0e8fb0 VB |
1116 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1117 | #include "ehci-ppc-of.c" | |
1118 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1119 | #endif | |
1120 | ||
705a7521 | 1121 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1122 | #include "ehci-orion.c" |
1123 | #define PLATFORM_DRIVER ehci_orion_driver | |
1124 | #endif | |
1125 | ||
91bc4d31 VB |
1126 | #ifdef CONFIG_ARCH_IXP4XX |
1127 | #include "ehci-ixp4xx.c" | |
1128 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1129 | #endif | |
1130 | ||
586dfc8c WZ |
1131 | #ifdef CONFIG_USB_W90X900_EHCI |
1132 | #include "ehci-w90x900.c" | |
1133 | #define PLATFORM_DRIVER ehci_hcd_w90x900_driver | |
1134 | #endif | |
1135 | ||
501c9c08 NF |
1136 | #ifdef CONFIG_ARCH_AT91 |
1137 | #include "ehci-atmel.c" | |
1138 | #define PLATFORM_DRIVER ehci_atmel_driver | |
1139 | #endif | |
1140 | ||
ad75a410 | 1141 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
c6dd2e61 | 1142 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) |
7ff71d6a MP |
1143 | #error "missing bus glue for ehci-hcd" |
1144 | #endif | |
01cced25 KG |
1145 | |
1146 | static int __init ehci_hcd_init(void) | |
1147 | { | |
1148 | int retval = 0; | |
1149 | ||
2b70f073 AS |
1150 | if (usb_disabled()) |
1151 | return -ENODEV; | |
1152 | ||
1153 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1154 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1155 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1156 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1157 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1158 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1159 | ||
01cced25 KG |
1160 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1161 | hcd_name, | |
1162 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1163 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1164 | ||
694cc208 | 1165 | #ifdef DEBUG |
08f4e586 | 1166 | ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); |
9beeee65 AS |
1167 | if (!ehci_debug_root) { |
1168 | retval = -ENOENT; | |
1169 | goto err_debug; | |
1170 | } | |
694cc208 TJ |
1171 | #endif |
1172 | ||
01cced25 KG |
1173 | #ifdef PLATFORM_DRIVER |
1174 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1175 | if (retval < 0) |
1176 | goto clean0; | |
01cced25 KG |
1177 | #endif |
1178 | ||
1179 | #ifdef PCI_DRIVER | |
1180 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1181 | if (retval < 0) |
1182 | goto clean1; | |
ad75a410 GL |
1183 | #endif |
1184 | ||
1185 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1186 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1187 | if (retval < 0) |
1188 | goto clean2; | |
694cc208 | 1189 | #endif |
da0e8fb0 VB |
1190 | |
1191 | #ifdef OF_PLATFORM_DRIVER | |
1192 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1193 | if (retval < 0) | |
1194 | goto clean3; | |
1195 | #endif | |
1196 | return retval; | |
1197 | ||
1198 | #ifdef OF_PLATFORM_DRIVER | |
1199 | /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */ | |
1200 | clean3: | |
1201 | #endif | |
1202 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1203 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1204 | clean2: | |
ad75a410 GL |
1205 | #endif |
1206 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1207 | pci_unregister_driver(&PCI_DRIVER); |
1208 | clean1: | |
ad75a410 | 1209 | #endif |
da0e8fb0 VB |
1210 | #ifdef PLATFORM_DRIVER |
1211 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1212 | clean0: | |
1213 | #endif | |
1214 | #ifdef DEBUG | |
1215 | debugfs_remove(ehci_debug_root); | |
1216 | ehci_debug_root = NULL; | |
9beeee65 | 1217 | err_debug: |
a9b6148d | 1218 | #endif |
9beeee65 | 1219 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1220 | return retval; |
1221 | } | |
1222 | module_init(ehci_hcd_init); | |
1223 | ||
1224 | static void __exit ehci_hcd_cleanup(void) | |
1225 | { | |
da0e8fb0 VB |
1226 | #ifdef OF_PLATFORM_DRIVER |
1227 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1228 | #endif | |
01cced25 KG |
1229 | #ifdef PLATFORM_DRIVER |
1230 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1231 | #endif | |
1232 | #ifdef PCI_DRIVER | |
1233 | pci_unregister_driver(&PCI_DRIVER); | |
1234 | #endif | |
ad75a410 | 1235 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1236 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1237 | #endif |
694cc208 TJ |
1238 | #ifdef DEBUG |
1239 | debugfs_remove(ehci_debug_root); | |
1240 | #endif | |
9beeee65 | 1241 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1242 | } |
1243 | module_exit(ehci_hcd_cleanup); | |
1244 |