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drivers/usb: Remove unnecessary return's from void functions
[net-next-2.6.git] / drivers / usb / gadget / pxa27x_udc.c
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1/*
2 * Handles the Intel 27x USB Device Controller (UDC)
3 *
4 * Inspired by original driver by Frank Becker, David Brownell, and others.
5 * Copyright (C) 2008 Robert Jarzmik
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/types.h>
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25#include <linux/errno.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/list.h>
29#include <linux/interrupt.h>
30#include <linux/proc_fs.h>
31#include <linux/clk.h>
32#include <linux/irq.h>
eb507025 33#include <linux/gpio.h>
5a0e3ad6 34#include <linux/slab.h>
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35
36#include <asm/byteorder.h>
a09e64fb 37#include <mach/hardware.h>
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38
39#include <linux/usb.h>
40#include <linux/usb/ch9.h>
41#include <linux/usb/gadget.h>
a09e64fb 42#include <mach/udc.h>
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43
44#include "pxa27x_udc.h"
45
46/*
47 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x
48 * series processors.
49 *
50 * Such controller drivers work with a gadget driver. The gadget driver
51 * returns descriptors, implements configuration and data protocols used
52 * by the host to interact with this device, and allocates endpoints to
53 * the different protocol interfaces. The controller driver virtualizes
54 * usb hardware so that the gadget drivers will be more portable.
55 *
56 * This UDC hardware wants to implement a bit too much USB protocol. The
57 * biggest issues are: that the endpoints have to be set up before the
58 * controller can be enabled (minor, and not uncommon); and each endpoint
59 * can only have one configuration, interface and alternative interface
60 * number (major, and very unusual). Once set up, these cannot be changed
61 * without a controller reset.
62 *
63 * The workaround is to setup all combinations necessary for the gadgets which
64 * will work with this driver. This is done in pxa_udc structure, statically.
65 * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep.
66 * (You could modify this if needed. Some drivers have a "fifo_mode" module
67 * parameter to facilitate such changes.)
68 *
69 * The combinations have been tested with these gadgets :
70 * - zero gadget
71 * - file storage gadget
72 * - ether gadget
73 *
74 * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is
75 * made of UDC's double buffering either. USB "On-The-Go" is not implemented.
76 *
77 * All the requests are handled the same way :
78 * - the drivers tries to handle the request directly to the IO
79 * - if the IO fifo is not big enough, the remaining is send/received in
80 * interrupt handling.
81 */
82
83#define DRIVER_VERSION "2008-04-18"
84#define DRIVER_DESC "PXA 27x USB Device Controller driver"
85
86static const char driver_name[] = "pxa27x_udc";
87static struct pxa_udc *the_controller;
88
89static void handle_ep(struct pxa_ep *ep);
90
91/*
92 * Debug filesystem
93 */
94#ifdef CONFIG_USB_GADGET_DEBUG_FS
95
96#include <linux/debugfs.h>
97#include <linux/uaccess.h>
98#include <linux/seq_file.h>
99
100static int state_dbg_show(struct seq_file *s, void *p)
101{
102 struct pxa_udc *udc = s->private;
103 int pos = 0, ret;
104 u32 tmp;
105
106 ret = -ENODEV;
107 if (!udc->driver)
108 goto out;
109
110 /* basic device status */
111 pos += seq_printf(s, DRIVER_DESC "\n"
112 "%s version: %s\nGadget driver: %s\n",
113 driver_name, DRIVER_VERSION,
114 udc->driver ? udc->driver->driver.name : "(none)");
115
116 tmp = udc_readl(udc, UDCCR);
117 pos += seq_printf(s,
118 "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), "
119 "con=%d,inter=%d,altinter=%d\n", tmp,
120 (tmp & UDCCR_OEN) ? " oen":"",
121 (tmp & UDCCR_AALTHNP) ? " aalthnp":"",
122 (tmp & UDCCR_AHNP) ? " rem" : "",
123 (tmp & UDCCR_BHNP) ? " rstir" : "",
124 (tmp & UDCCR_DWRE) ? " dwre" : "",
125 (tmp & UDCCR_SMAC) ? " smac" : "",
126 (tmp & UDCCR_EMCE) ? " emce" : "",
127 (tmp & UDCCR_UDR) ? " udr" : "",
128 (tmp & UDCCR_UDA) ? " uda" : "",
129 (tmp & UDCCR_UDE) ? " ude" : "",
130 (tmp & UDCCR_ACN) >> UDCCR_ACN_S,
131 (tmp & UDCCR_AIN) >> UDCCR_AIN_S,
132 (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S);
133 /* registers for device and ep0 */
134 pos += seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n",
135 udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1));
136 pos += seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n",
137 udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1));
138 pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR));
139 pos += seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, "
140 "reconfig=%lu\n",
141 udc->stats.irqs_reset, udc->stats.irqs_suspend,
142 udc->stats.irqs_resume, udc->stats.irqs_reconfig);
143
144 ret = 0;
145out:
146 return ret;
147}
148
149static int queues_dbg_show(struct seq_file *s, void *p)
150{
151 struct pxa_udc *udc = s->private;
152 struct pxa_ep *ep;
153 struct pxa27x_request *req;
154 int pos = 0, i, maxpkt, ret;
155
156 ret = -ENODEV;
157 if (!udc->driver)
158 goto out;
159
160 /* dump endpoint queues */
161 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
162 ep = &udc->pxa_ep[i];
163 maxpkt = ep->fifo_size;
164 pos += seq_printf(s, "%-12s max_pkt=%d %s\n",
165 EPNAME(ep), maxpkt, "pio");
166
167 if (list_empty(&ep->queue)) {
168 pos += seq_printf(s, "\t(nothing queued)\n");
169 continue;
170 }
171
172 list_for_each_entry(req, &ep->queue, queue) {
173 pos += seq_printf(s, "\treq %p len %d/%d buf %p\n",
174 &req->req, req->req.actual,
175 req->req.length, req->req.buf);
176 }
177 }
178
179 ret = 0;
180out:
181 return ret;
182}
183
184static int eps_dbg_show(struct seq_file *s, void *p)
185{
186 struct pxa_udc *udc = s->private;
187 struct pxa_ep *ep;
188 int pos = 0, i, ret;
189 u32 tmp;
190
191 ret = -ENODEV;
192 if (!udc->driver)
193 goto out;
194
195 ep = &udc->pxa_ep[0];
196 tmp = udc_ep_readl(ep, UDCCSR);
197 pos += seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp,
198 (tmp & UDCCSR0_SA) ? " sa" : "",
199 (tmp & UDCCSR0_RNE) ? " rne" : "",
200 (tmp & UDCCSR0_FST) ? " fst" : "",
201 (tmp & UDCCSR0_SST) ? " sst" : "",
202 (tmp & UDCCSR0_DME) ? " dme" : "",
203 (tmp & UDCCSR0_IPR) ? " ipr" : "",
204 (tmp & UDCCSR0_OPC) ? " opc" : "");
205 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
206 ep = &udc->pxa_ep[i];
207 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR);
208 pos += seq_printf(s, "%-12s: "
209 "IN %lu(%lu reqs), OUT %lu(%lu reqs), "
210 "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, "
211 "udcbcr=%d\n",
212 EPNAME(ep),
213 ep->stats.in_bytes, ep->stats.in_ops,
214 ep->stats.out_bytes, ep->stats.out_ops,
215 ep->stats.irqs,
216 tmp, udc_ep_readl(ep, UDCCSR),
217 udc_ep_readl(ep, UDCBCR));
218 }
219
220 ret = 0;
221out:
222 return ret;
223}
224
225static int eps_dbg_open(struct inode *inode, struct file *file)
226{
227 return single_open(file, eps_dbg_show, inode->i_private);
228}
229
230static int queues_dbg_open(struct inode *inode, struct file *file)
231{
232 return single_open(file, queues_dbg_show, inode->i_private);
233}
234
235static int state_dbg_open(struct inode *inode, struct file *file)
236{
237 return single_open(file, state_dbg_show, inode->i_private);
238}
239
240static const struct file_operations state_dbg_fops = {
241 .owner = THIS_MODULE,
242 .open = state_dbg_open,
243 .llseek = seq_lseek,
244 .read = seq_read,
245 .release = single_release,
246};
247
248static const struct file_operations queues_dbg_fops = {
249 .owner = THIS_MODULE,
250 .open = queues_dbg_open,
251 .llseek = seq_lseek,
252 .read = seq_read,
253 .release = single_release,
254};
255
256static const struct file_operations eps_dbg_fops = {
257 .owner = THIS_MODULE,
258 .open = eps_dbg_open,
259 .llseek = seq_lseek,
260 .read = seq_read,
261 .release = single_release,
262};
263
264static void pxa_init_debugfs(struct pxa_udc *udc)
265{
266 struct dentry *root, *state, *queues, *eps;
267
268 root = debugfs_create_dir(udc->gadget.name, NULL);
269 if (IS_ERR(root) || !root)
270 goto err_root;
271
272 state = debugfs_create_file("udcstate", 0400, root, udc,
273 &state_dbg_fops);
274 if (!state)
275 goto err_state;
276 queues = debugfs_create_file("queues", 0400, root, udc,
277 &queues_dbg_fops);
278 if (!queues)
279 goto err_queues;
280 eps = debugfs_create_file("epstate", 0400, root, udc,
281 &eps_dbg_fops);
00185a60 282 if (!eps)
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283 goto err_eps;
284
285 udc->debugfs_root = root;
286 udc->debugfs_state = state;
287 udc->debugfs_queues = queues;
288 udc->debugfs_eps = eps;
289 return;
290err_eps:
291 debugfs_remove(eps);
292err_queues:
293 debugfs_remove(queues);
294err_state:
295 debugfs_remove(root);
296err_root:
297 dev_err(udc->dev, "debugfs is not available\n");
298}
299
300static void pxa_cleanup_debugfs(struct pxa_udc *udc)
301{
302 debugfs_remove(udc->debugfs_eps);
303 debugfs_remove(udc->debugfs_queues);
304 debugfs_remove(udc->debugfs_state);
305 debugfs_remove(udc->debugfs_root);
306 udc->debugfs_eps = NULL;
307 udc->debugfs_queues = NULL;
308 udc->debugfs_state = NULL;
309 udc->debugfs_root = NULL;
310}
311
312#else
313static inline void pxa_init_debugfs(struct pxa_udc *udc)
314{
315}
316
317static inline void pxa_cleanup_debugfs(struct pxa_udc *udc)
318{
319}
320#endif
321
322/**
323 * is_match_usb_pxa - check if usb_ep and pxa_ep match
324 * @udc_usb_ep: usb endpoint
325 * @ep: pxa endpoint
326 * @config: configuration required in pxa_ep
327 * @interface: interface required in pxa_ep
328 * @altsetting: altsetting required in pxa_ep
329 *
330 * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise
331 */
332static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep,
333 int config, int interface, int altsetting)
334{
335 if (usb_endpoint_num(&udc_usb_ep->desc) != ep->addr)
336 return 0;
337 if (usb_endpoint_dir_in(&udc_usb_ep->desc) != ep->dir_in)
338 return 0;
339 if (usb_endpoint_type(&udc_usb_ep->desc) != ep->type)
340 return 0;
341 if ((ep->config != config) || (ep->interface != interface)
342 || (ep->alternate != altsetting))
343 return 0;
344 return 1;
345}
346
347/**
348 * find_pxa_ep - find pxa_ep structure matching udc_usb_ep
349 * @udc: pxa udc
350 * @udc_usb_ep: udc_usb_ep structure
351 *
352 * Match udc_usb_ep and all pxa_ep available, to see if one matches.
353 * This is necessary because of the strong pxa hardware restriction requiring
354 * that once pxa endpoints are initialized, their configuration is freezed, and
355 * no change can be made to their address, direction, or in which configuration,
356 * interface or altsetting they are active ... which differs from more usual
357 * models which have endpoints be roughly just addressable fifos, and leave
358 * configuration events up to gadget drivers (like all control messages).
359 *
360 * Note that there is still a blurred point here :
361 * - we rely on UDCCR register "active interface" and "active altsetting".
362 * This is a nonsense in regard of USB spec, where multiple interfaces are
363 * active at the same time.
364 * - if we knew for sure that the pxa can handle multiple interface at the
365 * same time, assuming Intel's Developer Guide is wrong, this function
366 * should be reviewed, and a cache of couples (iface, altsetting) should
367 * be kept in the pxa_udc structure. In this case this function would match
368 * against the cache of couples instead of the "last altsetting" set up.
369 *
370 * Returns the matched pxa_ep structure or NULL if none found
371 */
372static struct pxa_ep *find_pxa_ep(struct pxa_udc *udc,
373 struct udc_usb_ep *udc_usb_ep)
374{
375 int i;
376 struct pxa_ep *ep;
377 int cfg = udc->config;
378 int iface = udc->last_interface;
379 int alt = udc->last_alternate;
380
381 if (udc_usb_ep == &udc->udc_usb_ep[0])
382 return &udc->pxa_ep[0];
383
384 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
385 ep = &udc->pxa_ep[i];
386 if (is_match_usb_pxa(udc_usb_ep, ep, cfg, iface, alt))
387 return ep;
388 }
389 return NULL;
390}
391
392/**
393 * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep
394 * @udc: pxa udc
395 *
396 * Context: in_interrupt()
397 *
398 * Updates all pxa_ep fields in udc_usb_ep structures, if this field was
399 * previously set up (and is not NULL). The update is necessary is a
400 * configuration change or altsetting change was issued by the USB host.
401 */
402static void update_pxa_ep_matches(struct pxa_udc *udc)
403{
404 int i;
405 struct udc_usb_ep *udc_usb_ep;
406
407 for (i = 1; i < NR_USB_ENDPOINTS; i++) {
408 udc_usb_ep = &udc->udc_usb_ep[i];
409 if (udc_usb_ep->pxa_ep)
410 udc_usb_ep->pxa_ep = find_pxa_ep(udc, udc_usb_ep);
411 }
412}
413
414/**
415 * pio_irq_enable - Enables irq generation for one endpoint
416 * @ep: udc endpoint
417 */
418static void pio_irq_enable(struct pxa_ep *ep)
419{
420 struct pxa_udc *udc = ep->dev;
421 int index = EPIDX(ep);
422 u32 udcicr0 = udc_readl(udc, UDCICR0);
423 u32 udcicr1 = udc_readl(udc, UDCICR1);
424
425 if (index < 16)
426 udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2)));
427 else
428 udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2)));
429}
430
431/**
432 * pio_irq_disable - Disables irq generation for one endpoint
433 * @ep: udc endpoint
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434 */
435static void pio_irq_disable(struct pxa_ep *ep)
436{
437 struct pxa_udc *udc = ep->dev;
438 int index = EPIDX(ep);
439 u32 udcicr0 = udc_readl(udc, UDCICR0);
440 u32 udcicr1 = udc_readl(udc, UDCICR1);
441
442 if (index < 16)
443 udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2)));
444 else
445 udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2)));
446}
447
448/**
449 * udc_set_mask_UDCCR - set bits in UDCCR
450 * @udc: udc device
451 * @mask: bits to set in UDCCR
452 *
453 * Sets bits in UDCCR, leaving DME and FST bits as they were.
454 */
455static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask)
456{
457 u32 udccr = udc_readl(udc, UDCCR);
458 udc_writel(udc, UDCCR,
459 (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS));
460}
461
462/**
463 * udc_clear_mask_UDCCR - clears bits in UDCCR
464 * @udc: udc device
465 * @mask: bit to clear in UDCCR
466 *
467 * Clears bits in UDCCR, leaving DME and FST bits as they were.
468 */
469static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask)
470{
471 u32 udccr = udc_readl(udc, UDCCR);
472 udc_writel(udc, UDCCR,
473 (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS));
474}
475
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476/**
477 * ep_write_UDCCSR - set bits in UDCCSR
478 * @udc: udc device
479 * @mask: bits to set in UDCCR
480 *
481 * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*).
482 *
483 * A specific case is applied to ep0 : the ACM bit is always set to 1, for
484 * SET_INTERFACE and SET_CONFIGURATION.
485 */
486static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask)
487{
488 if (is_ep0(ep))
489 mask |= UDCCSR0_ACM;
490 udc_ep_writel(ep, UDCCSR, mask);
491}
492
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493/**
494 * ep_count_bytes_remain - get how many bytes in udc endpoint
495 * @ep: udc endpoint
496 *
497 * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP)
498 */
499static int ep_count_bytes_remain(struct pxa_ep *ep)
500{
501 if (ep->dir_in)
502 return -EOPNOTSUPP;
503 return udc_ep_readl(ep, UDCBCR) & 0x3ff;
504}
505
506/**
507 * ep_is_empty - checks if ep has byte ready for reading
508 * @ep: udc endpoint
509 *
510 * If endpoint is the control endpoint, checks if there are bytes in the
511 * control endpoint fifo. If endpoint is a data endpoint, checks if bytes
512 * are ready for reading on OUT endpoint.
513 *
514 * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint
515 */
516static int ep_is_empty(struct pxa_ep *ep)
517{
518 int ret;
519
520 if (!is_ep0(ep) && ep->dir_in)
521 return -EOPNOTSUPP;
522 if (is_ep0(ep))
523 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE);
524 else
525 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE);
526 return ret;
527}
528
529/**
530 * ep_is_full - checks if ep has place to write bytes
531 * @ep: udc endpoint
532 *
533 * If endpoint is not the control endpoint and is an IN endpoint, checks if
534 * there is place to write bytes into the endpoint.
535 *
536 * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint
537 */
538static int ep_is_full(struct pxa_ep *ep)
539{
540 if (is_ep0(ep))
541 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR);
542 if (!ep->dir_in)
543 return -EOPNOTSUPP;
544 return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF));
545}
546
547/**
548 * epout_has_pkt - checks if OUT endpoint fifo has a packet available
549 * @ep: pxa endpoint
550 *
551 * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep.
552 */
553static int epout_has_pkt(struct pxa_ep *ep)
554{
555 if (!is_ep0(ep) && ep->dir_in)
556 return -EOPNOTSUPP;
557 if (is_ep0(ep))
558 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC);
559 return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC);
560}
561
562/**
563 * set_ep0state - Set ep0 automata state
564 * @dev: udc device
565 * @state: state
566 */
567static void set_ep0state(struct pxa_udc *udc, int state)
568{
569 struct pxa_ep *ep = &udc->pxa_ep[0];
570 char *old_stname = EP0_STNAME(udc);
571
572 udc->ep0state = state;
573 ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname,
574 EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR),
575 udc_ep_readl(ep, UDCBCR));
576}
577
578/**
579 * ep0_idle - Put control endpoint into idle state
580 * @dev: udc device
581 */
582static void ep0_idle(struct pxa_udc *dev)
583{
584 set_ep0state(dev, WAIT_FOR_SETUP);
585}
586
587/**
588 * inc_ep_stats_reqs - Update ep stats counts
589 * @ep: physical endpoint
590 * @req: usb request
591 * @is_in: ep direction (USB_DIR_IN or 0)
592 *
593 */
594static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in)
595{
596 if (is_in)
597 ep->stats.in_ops++;
598 else
599 ep->stats.out_ops++;
600}
601
602/**
603 * inc_ep_stats_bytes - Update ep stats counts
604 * @ep: physical endpoint
605 * @count: bytes transfered on endpoint
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606 * @is_in: ep direction (USB_DIR_IN or 0)
607 */
608static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in)
609{
610 if (is_in)
611 ep->stats.in_bytes += count;
612 else
613 ep->stats.out_bytes += count;
614}
615
616/**
617 * pxa_ep_setup - Sets up an usb physical endpoint
618 * @ep: pxa27x physical endpoint
619 *
620 * Find the physical pxa27x ep, and setup its UDCCR
621 */
622static __init void pxa_ep_setup(struct pxa_ep *ep)
623{
624 u32 new_udccr;
625
626 new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN)
627 | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN)
628 | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN)
629 | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN)
630 | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET)
631 | ((ep->dir_in) ? UDCCONR_ED : 0)
632 | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS)
633 | UDCCONR_EE;
634
635 udc_ep_writel(ep, UDCCR, new_udccr);
636}
637
638/**
639 * pxa_eps_setup - Sets up all usb physical endpoints
640 * @dev: udc device
641 *
642 * Setup all pxa physical endpoints, except ep0
643 */
644static __init void pxa_eps_setup(struct pxa_udc *dev)
645{
646 unsigned int i;
647
648 dev_dbg(dev->dev, "%s: dev=%p\n", __func__, dev);
649
650 for (i = 1; i < NR_PXA_ENDPOINTS; i++)
651 pxa_ep_setup(&dev->pxa_ep[i]);
652}
653
654/**
655 * pxa_ep_alloc_request - Allocate usb request
656 * @_ep: usb endpoint
657 * @gfp_flags:
658 *
659 * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers
660 * must still pass correctly initialized endpoints, since other controller
661 * drivers may care about how it's currently set up (dma issues etc).
662 */
663static struct usb_request *
664pxa_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
665{
666 struct pxa27x_request *req;
667
668 req = kzalloc(sizeof *req, gfp_flags);
3131f7b0 669 if (!req)
d75379a5
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670 return NULL;
671
672 INIT_LIST_HEAD(&req->queue);
673 req->in_use = 0;
674 req->udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
675
676 return &req->req;
677}
678
679/**
680 * pxa_ep_free_request - Free usb request
681 * @_ep: usb endpoint
682 * @_req: usb request
683 *
684 * Wrapper around kfree to free _req
685 */
686static void pxa_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
687{
688 struct pxa27x_request *req;
689
690 req = container_of(_req, struct pxa27x_request, req);
691 WARN_ON(!list_empty(&req->queue));
692 kfree(req);
693}
694
695/**
696 * ep_add_request - add a request to the endpoint's queue
697 * @ep: usb endpoint
698 * @req: usb request
699 *
700 * Context: ep->lock held
701 *
702 * Queues the request in the endpoint's queue, and enables the interrupts
703 * on the endpoint.
704 */
705static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req)
706{
707 if (unlikely(!req))
708 return;
709 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req,
710 req->req.length, udc_ep_readl(ep, UDCCSR));
711
712 req->in_use = 1;
713 list_add_tail(&req->queue, &ep->queue);
714 pio_irq_enable(ep);
715}
716
717/**
718 * ep_del_request - removes a request from the endpoint's queue
719 * @ep: usb endpoint
720 * @req: usb request
721 *
722 * Context: ep->lock held
723 *
724 * Unqueue the request from the endpoint's queue. If there are no more requests
725 * on the endpoint, and if it's not the control endpoint, interrupts are
726 * disabled on the endpoint.
727 */
728static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req)
729{
730 if (unlikely(!req))
731 return;
732 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req,
733 req->req.length, udc_ep_readl(ep, UDCCSR));
734
735 list_del_init(&req->queue);
736 req->in_use = 0;
737 if (!is_ep0(ep) && list_empty(&ep->queue))
738 pio_irq_disable(ep);
739}
740
741/**
742 * req_done - Complete an usb request
743 * @ep: pxa physical endpoint
744 * @req: pxa request
745 * @status: usb request status sent to gadget API
5e23e90f 746 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
d75379a5 747 *
5e23e90f 748 * Context: ep->lock held if flags not NULL, else ep->lock released
d75379a5
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749 *
750 * Retire a pxa27x usb request. Endpoint must be locked.
751 */
5e23e90f
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752static void req_done(struct pxa_ep *ep, struct pxa27x_request *req, int status,
753 unsigned long *pflags)
d75379a5 754{
5e23e90f
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755 unsigned long flags;
756
d75379a5
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757 ep_del_request(ep, req);
758 if (likely(req->req.status == -EINPROGRESS))
759 req->req.status = status;
760 else
761 status = req->req.status;
762
763 if (status && status != -ESHUTDOWN)
764 ep_dbg(ep, "complete req %p stat %d len %u/%u\n",
765 &req->req, status,
766 req->req.actual, req->req.length);
767
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768 if (pflags)
769 spin_unlock_irqrestore(&ep->lock, *pflags);
770 local_irq_save(flags);
d75379a5 771 req->req.complete(&req->udc_usb_ep->usb_ep, &req->req);
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772 local_irq_restore(flags);
773 if (pflags)
774 spin_lock_irqsave(&ep->lock, *pflags);
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775}
776
777/**
4c24b6d0 778 * ep_end_out_req - Ends endpoint OUT request
d75379a5
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779 * @ep: physical endpoint
780 * @req: pxa request
5e23e90f 781 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
d75379a5 782 *
5e23e90f 783 * Context: ep->lock held or released (see req_done())
d75379a5 784 *
4c24b6d0 785 * Ends endpoint OUT request (completes usb request).
d75379a5 786 */
5e23e90f
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787static void ep_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req,
788 unsigned long *pflags)
d75379a5
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789{
790 inc_ep_stats_reqs(ep, !USB_DIR_IN);
5e23e90f 791 req_done(ep, req, 0, pflags);
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792}
793
794/**
4c24b6d0 795 * ep0_end_out_req - Ends control endpoint OUT request (ends data stage)
d75379a5
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796 * @ep: physical endpoint
797 * @req: pxa request
5e23e90f 798 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
d75379a5 799 *
5e23e90f 800 * Context: ep->lock held or released (see req_done())
d75379a5 801 *
4c24b6d0 802 * Ends control endpoint OUT request (completes usb request), and puts
d75379a5
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803 * control endpoint into idle state
804 */
5e23e90f
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805static void ep0_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req,
806 unsigned long *pflags)
d75379a5
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807{
808 set_ep0state(ep->dev, OUT_STATUS_STAGE);
5e23e90f 809 ep_end_out_req(ep, req, pflags);
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810 ep0_idle(ep->dev);
811}
812
813/**
4c24b6d0 814 * ep_end_in_req - Ends endpoint IN request
d75379a5
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815 * @ep: physical endpoint
816 * @req: pxa request
5e23e90f 817 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
d75379a5 818 *
5e23e90f 819 * Context: ep->lock held or released (see req_done())
d75379a5 820 *
4c24b6d0 821 * Ends endpoint IN request (completes usb request).
d75379a5 822 */
5e23e90f
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823static void ep_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req,
824 unsigned long *pflags)
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825{
826 inc_ep_stats_reqs(ep, USB_DIR_IN);
5e23e90f 827 req_done(ep, req, 0, pflags);
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828}
829
830/**
4c24b6d0 831 * ep0_end_in_req - Ends control endpoint IN request (ends data stage)
d75379a5
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832 * @ep: physical endpoint
833 * @req: pxa request
5e23e90f 834 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
d75379a5 835 *
5e23e90f 836 * Context: ep->lock held or released (see req_done())
d75379a5 837 *
4c24b6d0 838 * Ends control endpoint IN request (completes usb request), and puts
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839 * control endpoint into status state
840 */
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841static void ep0_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req,
842 unsigned long *pflags)
d75379a5 843{
4c24b6d0 844 set_ep0state(ep->dev, IN_STATUS_STAGE);
5e23e90f 845 ep_end_in_req(ep, req, pflags);
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846}
847
848/**
849 * nuke - Dequeue all requests
850 * @ep: pxa endpoint
851 * @status: usb request status
852 *
5e23e90f 853 * Context: ep->lock released
d75379a5
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854 *
855 * Dequeues all requests on an endpoint. As a side effect, interrupts will be
856 * disabled on that endpoint (because no more requests).
857 */
858static void nuke(struct pxa_ep *ep, int status)
859{
5e23e90f
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860 struct pxa27x_request *req;
861 unsigned long flags;
d75379a5 862
5e23e90f 863 spin_lock_irqsave(&ep->lock, flags);
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864 while (!list_empty(&ep->queue)) {
865 req = list_entry(ep->queue.next, struct pxa27x_request, queue);
5e23e90f 866 req_done(ep, req, status, &flags);
d75379a5 867 }
5e23e90f 868 spin_unlock_irqrestore(&ep->lock, flags);
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869}
870
871/**
872 * read_packet - transfer 1 packet from an OUT endpoint into request
873 * @ep: pxa physical endpoint
874 * @req: usb request
875 *
876 * Takes bytes from OUT endpoint and transfers them info the usb request.
877 * If there is less space in request than bytes received in OUT endpoint,
878 * bytes are left in the OUT endpoint.
879 *
880 * Returns how many bytes were actually transfered
881 */
882static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req)
883{
884 u32 *buf;
885 int bytes_ep, bufferspace, count, i;
886
887 bytes_ep = ep_count_bytes_remain(ep);
888 bufferspace = req->req.length - req->req.actual;
889
890 buf = (u32 *)(req->req.buf + req->req.actual);
891 prefetchw(buf);
892
893 if (likely(!ep_is_empty(ep)))
894 count = min(bytes_ep, bufferspace);
895 else /* zlp */
896 count = 0;
897
898 for (i = count; i > 0; i -= 4)
899 *buf++ = udc_ep_readl(ep, UDCDR);
900 req->req.actual += count;
901
367815ee 902 ep_write_UDCCSR(ep, UDCCSR_PC);
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903
904 return count;
905}
906
907/**
908 * write_packet - transfer 1 packet from request into an IN endpoint
909 * @ep: pxa physical endpoint
910 * @req: usb request
911 * @max: max bytes that fit into endpoint
912 *
913 * Takes bytes from usb request, and transfers them into the physical
914 * endpoint. If there are no bytes to transfer, doesn't write anything
915 * to physical endpoint.
916 *
917 * Returns how many bytes were actually transfered.
918 */
919static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req,
920 unsigned int max)
921{
922 int length, count, remain, i;
923 u32 *buf;
924 u8 *buf_8;
925
926 buf = (u32 *)(req->req.buf + req->req.actual);
927 prefetch(buf);
928
929 length = min(req->req.length - req->req.actual, max);
930 req->req.actual += length;
931
932 remain = length & 0x3;
933 count = length & ~(0x3);
934 for (i = count; i > 0 ; i -= 4)
935 udc_ep_writel(ep, UDCDR, *buf++);
936
937 buf_8 = (u8 *)buf;
938 for (i = remain; i > 0; i--)
939 udc_ep_writeb(ep, UDCDR, *buf_8++);
940
941 ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain,
942 udc_ep_readl(ep, UDCCSR));
943
944 return length;
945}
946
947/**
948 * read_fifo - Transfer packets from OUT endpoint into usb request
949 * @ep: pxa physical endpoint
950 * @req: usb request
951 *
952 * Context: callable when in_interrupt()
953 *
954 * Unload as many packets as possible from the fifo we use for usb OUT
955 * transfers and put them into the request. Caller should have made sure
956 * there's at least one packet ready.
957 * Doesn't complete the request, that's the caller's job
958 *
959 * Returns 1 if the request completed, 0 otherwise
960 */
961static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
962{
963 int count, is_short, completed = 0;
964
965 while (epout_has_pkt(ep)) {
966 count = read_packet(ep, req);
967 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
968
969 is_short = (count < ep->fifo_size);
970 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
971 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "",
972 &req->req, req->req.actual, req->req.length);
973
974 /* completion */
975 if (is_short || req->req.actual == req->req.length) {
976 completed = 1;
977 break;
978 }
979 /* finished that packet. the next one may be waiting... */
980 }
981 return completed;
982}
983
984/**
985 * write_fifo - transfer packets from usb request into an IN endpoint
986 * @ep: pxa physical endpoint
987 * @req: pxa usb request
988 *
989 * Write to an IN endpoint fifo, as many packets as possible.
990 * irqs will use this to write the rest later.
991 * caller guarantees at least one packet buffer is ready (or a zlp).
992 * Doesn't complete the request, that's the caller's job
993 *
994 * Returns 1 if request fully transfered, 0 if partial transfer
995 */
996static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
997{
998 unsigned max;
999 int count, is_short, is_last = 0, completed = 0, totcount = 0;
1000 u32 udccsr;
1001
1002 max = ep->fifo_size;
1003 do {
1004 is_short = 0;
1005
1006 udccsr = udc_ep_readl(ep, UDCCSR);
1007 if (udccsr & UDCCSR_PC) {
1008 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n",
1009 udccsr);
367815ee 1010 ep_write_UDCCSR(ep, UDCCSR_PC);
d75379a5
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1011 }
1012 if (udccsr & UDCCSR_TRN) {
1013 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n",
1014 udccsr);
367815ee 1015 ep_write_UDCCSR(ep, UDCCSR_TRN);
d75379a5
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1016 }
1017
1018 count = write_packet(ep, req, max);
1019 inc_ep_stats_bytes(ep, count, USB_DIR_IN);
1020 totcount += count;
1021
1022 /* last packet is usually short (or a zlp) */
1023 if (unlikely(count < max)) {
1024 is_last = 1;
1025 is_short = 1;
1026 } else {
1027 if (likely(req->req.length > req->req.actual)
1028 || req->req.zero)
1029 is_last = 0;
1030 else
1031 is_last = 1;
1032 /* interrupt/iso maxpacket may not fill the fifo */
1033 is_short = unlikely(max < ep->fifo_size);
1034 }
1035
1036 if (is_short)
367815ee 1037 ep_write_UDCCSR(ep, UDCCSR_SP);
d75379a5
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1038
1039 /* requests complete when all IN data is in the FIFO */
1040 if (is_last) {
1041 completed = 1;
1042 break;
1043 }
1044 } while (!ep_is_full(ep));
1045
1046 ep_dbg(ep, "wrote count:%d bytes%s%s, left:%d req=%p\n",
1047 totcount, is_last ? "/L" : "", is_short ? "/S" : "",
1048 req->req.length - req->req.actual, &req->req);
1049
1050 return completed;
1051}
1052
1053/**
1054 * read_ep0_fifo - Transfer packets from control endpoint into usb request
1055 * @ep: control endpoint
1056 * @req: pxa usb request
1057 *
1058 * Special ep0 version of the above read_fifo. Reads as many bytes from control
1059 * endpoint as can be read, and stores them into usb request (limited by request
1060 * maximum length).
1061 *
1062 * Returns 0 if usb request only partially filled, 1 if fully filled
1063 */
1064static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1065{
1066 int count, is_short, completed = 0;
1067
1068 while (epout_has_pkt(ep)) {
1069 count = read_packet(ep, req);
367815ee 1070 ep_write_UDCCSR(ep, UDCCSR0_OPC);
d75379a5
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1071 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
1072
1073 is_short = (count < ep->fifo_size);
1074 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
1075 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "",
1076 &req->req, req->req.actual, req->req.length);
1077
1078 if (is_short || req->req.actual >= req->req.length) {
1079 completed = 1;
1080 break;
1081 }
1082 }
1083
1084 return completed;
1085}
1086
1087/**
1088 * write_ep0_fifo - Send a request to control endpoint (ep0 in)
1089 * @ep: control endpoint
1090 * @req: request
1091 *
1092 * Context: callable when in_interrupt()
1093 *
1094 * Sends a request (or a part of the request) to the control endpoint (ep0 in).
1095 * If the request doesn't fit, the remaining part will be sent from irq.
1096 * The request is considered fully written only if either :
1097 * - last write transfered all remaining bytes, but fifo was not fully filled
1098 * - last write was a 0 length write
1099 *
1100 * Returns 1 if request fully written, 0 if request only partially sent
1101 */
1102static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1103{
1104 unsigned count;
1105 int is_last, is_short;
1106
1107 count = write_packet(ep, req, EP0_FIFO_SIZE);
1108 inc_ep_stats_bytes(ep, count, USB_DIR_IN);
1109
1110 is_short = (count < EP0_FIFO_SIZE);
1111 is_last = ((count == 0) || (count < EP0_FIFO_SIZE));
1112
1113 /* Sends either a short packet or a 0 length packet */
1114 if (unlikely(is_short))
367815ee 1115 ep_write_UDCCSR(ep, UDCCSR0_IPR);
d75379a5
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1116
1117 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
1118 count, is_short ? "/S" : "", is_last ? "/L" : "",
1119 req->req.length - req->req.actual,
1120 &req->req, udc_ep_readl(ep, UDCCSR));
1121
1122 return is_last;
1123}
1124
1125/**
1126 * pxa_ep_queue - Queue a request into an IN endpoint
1127 * @_ep: usb endpoint
1128 * @_req: usb request
1129 * @gfp_flags: flags
1130 *
1131 * Context: normally called when !in_interrupt, but callable when in_interrupt()
1132 * in the special case of ep0 setup :
1133 * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue)
1134 *
1135 * Returns 0 if succedeed, error otherwise
1136 */
1137static int pxa_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
1138 gfp_t gfp_flags)
1139{
1140 struct udc_usb_ep *udc_usb_ep;
1141 struct pxa_ep *ep;
1142 struct pxa27x_request *req;
1143 struct pxa_udc *dev;
1144 unsigned long flags;
1145 int rc = 0;
1146 int is_first_req;
1147 unsigned length;
5e23e90f 1148 int recursion_detected;
d75379a5
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1149
1150 req = container_of(_req, struct pxa27x_request, req);
1151 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1152
1153 if (unlikely(!_req || !_req->complete || !_req->buf))
1154 return -EINVAL;
1155
1156 if (unlikely(!_ep))
1157 return -EINVAL;
1158
1159 dev = udc_usb_ep->dev;
1160 ep = udc_usb_ep->pxa_ep;
1161 if (unlikely(!ep))
1162 return -EINVAL;
1163
1164 dev = ep->dev;
1165 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1166 ep_dbg(ep, "bogus device state\n");
1167 return -ESHUTDOWN;
1168 }
1169
1170 /* iso is always one packet per request, that's the only way
1171 * we can report per-packet status. that also helps with dma.
1172 */
1173 if (unlikely(EPXFERTYPE_is_ISO(ep)
1174 && req->req.length > ep->fifo_size))
1175 return -EMSGSIZE;
1176
1177 spin_lock_irqsave(&ep->lock, flags);
5e23e90f 1178 recursion_detected = ep->in_handle_ep;
d75379a5
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1179
1180 is_first_req = list_empty(&ep->queue);
1181 ep_dbg(ep, "queue req %p(first=%s), len %d buf %p\n",
1182 _req, is_first_req ? "yes" : "no",
1183 _req->length, _req->buf);
1184
1185 if (!ep->enabled) {
1186 _req->status = -ESHUTDOWN;
1187 rc = -ESHUTDOWN;
5e23e90f 1188 goto out_locked;
d75379a5
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1189 }
1190
1191 if (req->in_use) {
1192 ep_err(ep, "refusing to queue req %p (already queued)\n", req);
5e23e90f 1193 goto out_locked;
d75379a5
RJ
1194 }
1195
1196 length = _req->length;
1197 _req->status = -EINPROGRESS;
1198 _req->actual = 0;
1199
1200 ep_add_request(ep, req);
5e23e90f 1201 spin_unlock_irqrestore(&ep->lock, flags);
d75379a5
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1202
1203 if (is_ep0(ep)) {
1204 switch (dev->ep0state) {
1205 case WAIT_ACK_SET_CONF_INTERF:
1206 if (length == 0) {
5e23e90f 1207 ep_end_in_req(ep, req, NULL);
d75379a5
RJ
1208 } else {
1209 ep_err(ep, "got a request of %d bytes while"
4c24b6d0 1210 "in state WAIT_ACK_SET_CONF_INTERF\n",
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1211 length);
1212 ep_del_request(ep, req);
1213 rc = -EL2HLT;
1214 }
1215 ep0_idle(ep->dev);
1216 break;
1217 case IN_DATA_STAGE:
1218 if (!ep_is_full(ep))
1219 if (write_ep0_fifo(ep, req))
5e23e90f 1220 ep0_end_in_req(ep, req, NULL);
d75379a5
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1221 break;
1222 case OUT_DATA_STAGE:
1223 if ((length == 0) || !epout_has_pkt(ep))
1224 if (read_ep0_fifo(ep, req))
5e23e90f 1225 ep0_end_out_req(ep, req, NULL);
d75379a5
RJ
1226 break;
1227 default:
1228 ep_err(ep, "odd state %s to send me a request\n",
1229 EP0_STNAME(ep->dev));
1230 ep_del_request(ep, req);
1231 rc = -EL2HLT;
1232 break;
1233 }
1234 } else {
5e23e90f
RJ
1235 if (!recursion_detected)
1236 handle_ep(ep);
d75379a5
RJ
1237 }
1238
1239out:
d75379a5 1240 return rc;
5e23e90f
RJ
1241out_locked:
1242 spin_unlock_irqrestore(&ep->lock, flags);
1243 goto out;
d75379a5
RJ
1244}
1245
1246/**
1247 * pxa_ep_dequeue - Dequeue one request
1248 * @_ep: usb endpoint
1249 * @_req: usb request
1250 *
1251 * Return 0 if no error, -EINVAL or -ECONNRESET otherwise
1252 */
1253static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1254{
1255 struct pxa_ep *ep;
1256 struct udc_usb_ep *udc_usb_ep;
1257 struct pxa27x_request *req;
1258 unsigned long flags;
4c24b6d0 1259 int rc = -EINVAL;
d75379a5
RJ
1260
1261 if (!_ep)
4c24b6d0 1262 return rc;
d75379a5
RJ
1263 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1264 ep = udc_usb_ep->pxa_ep;
1265 if (!ep || is_ep0(ep))
4c24b6d0 1266 return rc;
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RJ
1267
1268 spin_lock_irqsave(&ep->lock, flags);
1269
1270 /* make sure it's actually queued on this endpoint */
1271 list_for_each_entry(req, &ep->queue, queue) {
4c24b6d0 1272 if (&req->req == _req) {
4c24b6d0 1273 rc = 0;
d75379a5 1274 break;
4c24b6d0 1275 }
d75379a5
RJ
1276 }
1277
d75379a5 1278 spin_unlock_irqrestore(&ep->lock, flags);
5e23e90f
RJ
1279 if (!rc)
1280 req_done(ep, req, -ECONNRESET, NULL);
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RJ
1281 return rc;
1282}
1283
1284/**
1285 * pxa_ep_set_halt - Halts operations on one endpoint
1286 * @_ep: usb endpoint
1287 * @value:
1288 *
1289 * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise
1290 */
1291static int pxa_ep_set_halt(struct usb_ep *_ep, int value)
1292{
1293 struct pxa_ep *ep;
1294 struct udc_usb_ep *udc_usb_ep;
1295 unsigned long flags;
1296 int rc;
1297
1298
1299 if (!_ep)
1300 return -EINVAL;
1301 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1302 ep = udc_usb_ep->pxa_ep;
1303 if (!ep || is_ep0(ep))
1304 return -EINVAL;
1305
1306 if (value == 0) {
1307 /*
1308 * This path (reset toggle+halt) is needed to implement
1309 * SET_INTERFACE on normal hardware. but it can't be
1310 * done from software on the PXA UDC, and the hardware
1311 * forgets to do it as part of SET_INTERFACE automagic.
1312 */
1313 ep_dbg(ep, "only host can clear halt\n");
1314 return -EROFS;
1315 }
1316
1317 spin_lock_irqsave(&ep->lock, flags);
1318
1319 rc = -EAGAIN;
1320 if (ep->dir_in && (ep_is_full(ep) || !list_empty(&ep->queue)))
1321 goto out;
1322
1323 /* FST, FEF bits are the same for control and non control endpoints */
1324 rc = 0;
367815ee 1325 ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF);
d75379a5
RJ
1326 if (is_ep0(ep))
1327 set_ep0state(ep->dev, STALL);
1328
1329out:
1330 spin_unlock_irqrestore(&ep->lock, flags);
1331 return rc;
1332}
1333
1334/**
1335 * pxa_ep_fifo_status - Get how many bytes in physical endpoint
1336 * @_ep: usb endpoint
1337 *
1338 * Returns number of bytes in OUT fifos. Broken for IN fifos.
1339 */
1340static int pxa_ep_fifo_status(struct usb_ep *_ep)
1341{
1342 struct pxa_ep *ep;
1343 struct udc_usb_ep *udc_usb_ep;
1344
1345 if (!_ep)
1346 return -ENODEV;
1347 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1348 ep = udc_usb_ep->pxa_ep;
1349 if (!ep || is_ep0(ep))
1350 return -ENODEV;
1351
1352 if (ep->dir_in)
1353 return -EOPNOTSUPP;
1354 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN || ep_is_empty(ep))
1355 return 0;
1356 else
1357 return ep_count_bytes_remain(ep) + 1;
1358}
1359
1360/**
1361 * pxa_ep_fifo_flush - Flushes one endpoint
1362 * @_ep: usb endpoint
1363 *
1364 * Discards all data in one endpoint(IN or OUT), except control endpoint.
1365 */
1366static void pxa_ep_fifo_flush(struct usb_ep *_ep)
1367{
1368 struct pxa_ep *ep;
1369 struct udc_usb_ep *udc_usb_ep;
1370 unsigned long flags;
1371
1372 if (!_ep)
1373 return;
1374 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1375 ep = udc_usb_ep->pxa_ep;
1376 if (!ep || is_ep0(ep))
1377 return;
1378
1379 spin_lock_irqsave(&ep->lock, flags);
1380
1381 if (unlikely(!list_empty(&ep->queue)))
1382 ep_dbg(ep, "called while queue list not empty\n");
1383 ep_dbg(ep, "called\n");
1384
1385 /* for OUT, just read and discard the FIFO contents. */
1386 if (!ep->dir_in) {
1387 while (!ep_is_empty(ep))
1388 udc_ep_readl(ep, UDCDR);
1389 } else {
1390 /* most IN status is the same, but ISO can't stall */
367815ee 1391 ep_write_UDCCSR(ep,
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1392 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN
1393 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST));
1394 }
1395
1396 spin_unlock_irqrestore(&ep->lock, flags);
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1397}
1398
1399/**
1400 * pxa_ep_enable - Enables usb endpoint
1401 * @_ep: usb endpoint
1402 * @desc: usb endpoint descriptor
1403 *
1404 * Nothing much to do here, as ep configuration is done once and for all
1405 * before udc is enabled. After udc enable, no physical endpoint configuration
1406 * can be changed.
1407 * Function makes sanity checks and flushes the endpoint.
1408 */
1409static int pxa_ep_enable(struct usb_ep *_ep,
1410 const struct usb_endpoint_descriptor *desc)
1411{
1412 struct pxa_ep *ep;
1413 struct udc_usb_ep *udc_usb_ep;
1414 struct pxa_udc *udc;
1415
1416 if (!_ep || !desc)
1417 return -EINVAL;
1418
1419 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1420 if (udc_usb_ep->pxa_ep) {
1421 ep = udc_usb_ep->pxa_ep;
1422 ep_warn(ep, "usb_ep %s already enabled, doing nothing\n",
1423 _ep->name);
1424 } else {
1425 ep = find_pxa_ep(udc_usb_ep->dev, udc_usb_ep);
1426 }
1427
1428 if (!ep || is_ep0(ep)) {
1429 dev_err(udc_usb_ep->dev->dev,
1430 "unable to match pxa_ep for ep %s\n",
1431 _ep->name);
1432 return -EINVAL;
1433 }
1434
1435 if ((desc->bDescriptorType != USB_DT_ENDPOINT)
1436 || (ep->type != usb_endpoint_type(desc))) {
1437 ep_err(ep, "type mismatch\n");
1438 return -EINVAL;
1439 }
1440
1441 if (ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
1442 ep_err(ep, "bad maxpacket\n");
1443 return -ERANGE;
1444 }
1445
1446 udc_usb_ep->pxa_ep = ep;
1447 udc = ep->dev;
1448
1449 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1450 ep_err(ep, "bogus device state\n");
1451 return -ESHUTDOWN;
1452 }
1453
1454 ep->enabled = 1;
1455
1456 /* flush fifo (mostly for OUT buffers) */
1457 pxa_ep_fifo_flush(_ep);
1458
1459 ep_dbg(ep, "enabled\n");
1460 return 0;
1461}
1462
1463/**
1464 * pxa_ep_disable - Disable usb endpoint
1465 * @_ep: usb endpoint
1466 *
1467 * Same as for pxa_ep_enable, no physical endpoint configuration can be
1468 * changed.
1469 * Function flushes the endpoint and related requests.
1470 */
1471static int pxa_ep_disable(struct usb_ep *_ep)
1472{
1473 struct pxa_ep *ep;
1474 struct udc_usb_ep *udc_usb_ep;
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1475
1476 if (!_ep)
1477 return -EINVAL;
1478
1479 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1480 ep = udc_usb_ep->pxa_ep;
1481 if (!ep || is_ep0(ep) || !list_empty(&ep->queue))
1482 return -EINVAL;
1483
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RJ
1484 ep->enabled = 0;
1485 nuke(ep, -ESHUTDOWN);
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RJ
1486
1487 pxa_ep_fifo_flush(_ep);
1488 udc_usb_ep->pxa_ep = NULL;
1489
1490 ep_dbg(ep, "disabled\n");
1491 return 0;
1492}
1493
1494static struct usb_ep_ops pxa_ep_ops = {
1495 .enable = pxa_ep_enable,
1496 .disable = pxa_ep_disable,
1497
1498 .alloc_request = pxa_ep_alloc_request,
1499 .free_request = pxa_ep_free_request,
1500
1501 .queue = pxa_ep_queue,
1502 .dequeue = pxa_ep_dequeue,
1503
1504 .set_halt = pxa_ep_set_halt,
1505 .fifo_status = pxa_ep_fifo_status,
1506 .fifo_flush = pxa_ep_fifo_flush,
1507};
1508
eb507025
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1509/**
1510 * dplus_pullup - Connect or disconnect pullup resistor to D+ pin
1511 * @udc: udc device
1512 * @on: 0 if disconnect pullup resistor, 1 otherwise
1513 * Context: any
1514 *
1515 * Handle D+ pullup resistor, make the device visible to the usb bus, and
1516 * declare it as a full speed usb device
1517 */
1518static void dplus_pullup(struct pxa_udc *udc, int on)
1519{
1520 if (on) {
1521 if (gpio_is_valid(udc->mach->gpio_pullup))
1522 gpio_set_value(udc->mach->gpio_pullup,
1523 !udc->mach->gpio_pullup_inverted);
1524 if (udc->mach->udc_command)
1525 udc->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
1526 } else {
1527 if (gpio_is_valid(udc->mach->gpio_pullup))
1528 gpio_set_value(udc->mach->gpio_pullup,
1529 udc->mach->gpio_pullup_inverted);
1530 if (udc->mach->udc_command)
1531 udc->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
1532 }
1533 udc->pullup_on = on;
1534}
d75379a5
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1535
1536/**
1537 * pxa_udc_get_frame - Returns usb frame number
1538 * @_gadget: usb gadget
1539 */
1540static int pxa_udc_get_frame(struct usb_gadget *_gadget)
1541{
1542 struct pxa_udc *udc = to_gadget_udc(_gadget);
1543
1544 return (udc_readl(udc, UDCFNR) & 0x7ff);
1545}
1546
1547/**
1548 * pxa_udc_wakeup - Force udc device out of suspend
1549 * @_gadget: usb gadget
1550 *
af901ca1 1551 * Returns 0 if successfull, error code otherwise
d75379a5
RJ
1552 */
1553static int pxa_udc_wakeup(struct usb_gadget *_gadget)
1554{
1555 struct pxa_udc *udc = to_gadget_udc(_gadget);
1556
1557 /* host may not have enabled remote wakeup */
1558 if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0)
1559 return -EHOSTUNREACH;
1560 udc_set_mask_UDCCR(udc, UDCCR_UDR);
1561 return 0;
1562}
1563
eb507025
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1564static void udc_enable(struct pxa_udc *udc);
1565static void udc_disable(struct pxa_udc *udc);
1566
1567/**
1568 * should_enable_udc - Tells if UDC should be enabled
1569 * @udc: udc device
1570 * Context: any
1571 *
1572 * The UDC should be enabled if :
b799a7eb 1573
eb507025
RJ
1574 * - the pullup resistor is connected
1575 * - and a gadget driver is bound
b799a7eb 1576 * - and vbus is sensed (or no vbus sense is available)
eb507025
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1577 *
1578 * Returns 1 if UDC should be enabled, 0 otherwise
1579 */
1580static int should_enable_udc(struct pxa_udc *udc)
1581{
1582 int put_on;
1583
1584 put_on = ((udc->pullup_on) && (udc->driver));
b799a7eb 1585 put_on &= ((udc->vbus_sensed) || (!udc->transceiver));
eb507025
RJ
1586 return put_on;
1587}
1588
1589/**
1590 * should_disable_udc - Tells if UDC should be disabled
1591 * @udc: udc device
1592 * Context: any
1593 *
1594 * The UDC should be disabled if :
1595 * - the pullup resistor is not connected
1596 * - or no gadget driver is bound
b799a7eb 1597 * - or no vbus is sensed (when vbus sesing is available)
eb507025
RJ
1598 *
1599 * Returns 1 if UDC should be disabled
1600 */
1601static int should_disable_udc(struct pxa_udc *udc)
1602{
1603 int put_off;
1604
1605 put_off = ((!udc->pullup_on) || (!udc->driver));
b799a7eb 1606 put_off |= ((!udc->vbus_sensed) && (udc->transceiver));
eb507025
RJ
1607 return put_off;
1608}
1609
1610/**
1611 * pxa_udc_pullup - Offer manual D+ pullup control
1612 * @_gadget: usb gadget using the control
1613 * @is_active: 0 if disconnect, else connect D+ pullup resistor
1614 * Context: !in_interrupt()
1615 *
1616 * Returns 0 if OK, -EOPNOTSUPP if udc driver doesn't handle D+ pullup
1617 */
1618static int pxa_udc_pullup(struct usb_gadget *_gadget, int is_active)
1619{
1620 struct pxa_udc *udc = to_gadget_udc(_gadget);
1621
1622 if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
1623 return -EOPNOTSUPP;
1624
1625 dplus_pullup(udc, is_active);
1626
1627 if (should_enable_udc(udc))
1628 udc_enable(udc);
1629 if (should_disable_udc(udc))
1630 udc_disable(udc);
1631 return 0;
1632}
1633
b799a7eb
RJ
1634static void udc_enable(struct pxa_udc *udc);
1635static void udc_disable(struct pxa_udc *udc);
1636
1637/**
1638 * pxa_udc_vbus_session - Called by external transceiver to enable/disable udc
1639 * @_gadget: usb gadget
1640 * @is_active: 0 if should disable the udc, 1 if should enable
1641 *
1642 * Enables the udc, and optionnaly activates D+ pullup resistor. Or disables the
1643 * udc, and deactivates D+ pullup resistor.
1644 *
1645 * Returns 0
1646 */
1647static int pxa_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1648{
1649 struct pxa_udc *udc = to_gadget_udc(_gadget);
1650
1651 udc->vbus_sensed = is_active;
1652 if (should_enable_udc(udc))
1653 udc_enable(udc);
1654 if (should_disable_udc(udc))
1655 udc_disable(udc);
1656
1657 return 0;
1658}
1659
ee069fb1
RJ
1660/**
1661 * pxa_udc_vbus_draw - Called by gadget driver after SET_CONFIGURATION completed
1662 * @_gadget: usb gadget
1663 * @mA: current drawn
1664 *
1665 * Context: !in_interrupt()
1666 *
1667 * Called after a configuration was chosen by a USB host, to inform how much
1668 * current can be drawn by the device from VBus line.
1669 *
1670 * Returns 0 or -EOPNOTSUPP if no transceiver is handling the udc
1671 */
1672static int pxa_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1673{
1674 struct pxa_udc *udc;
1675
1676 udc = to_gadget_udc(_gadget);
1677 if (udc->transceiver)
1678 return otg_set_power(udc->transceiver, mA);
1679 return -EOPNOTSUPP;
1680}
1681
d75379a5
RJ
1682static const struct usb_gadget_ops pxa_udc_ops = {
1683 .get_frame = pxa_udc_get_frame,
1684 .wakeup = pxa_udc_wakeup,
eb507025 1685 .pullup = pxa_udc_pullup,
b799a7eb 1686 .vbus_session = pxa_udc_vbus_session,
ee069fb1 1687 .vbus_draw = pxa_udc_vbus_draw,
d75379a5
RJ
1688};
1689
1690/**
1691 * udc_disable - disable udc device controller
1692 * @udc: udc device
eb507025 1693 * Context: any
d75379a5
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1694 *
1695 * Disables the udc device : disables clocks, udc interrupts, control endpoint
1696 * interrupts.
1697 */
1698static void udc_disable(struct pxa_udc *udc)
1699{
eb507025
RJ
1700 if (!udc->enabled)
1701 return;
1702
d75379a5
RJ
1703 udc_writel(udc, UDCICR0, 0);
1704 udc_writel(udc, UDCICR1, 0);
1705
1706 udc_clear_mask_UDCCR(udc, UDCCR_UDE);
1707 clk_disable(udc->clk);
1708
1709 ep0_idle(udc);
1710 udc->gadget.speed = USB_SPEED_UNKNOWN;
eb507025
RJ
1711
1712 udc->enabled = 0;
d75379a5
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1713}
1714
1715/**
1716 * udc_init_data - Initialize udc device data structures
1717 * @dev: udc device
1718 *
1719 * Initializes gadget endpoint list, endpoints locks. No action is taken
1720 * on the hardware.
1721 */
1722static __init void udc_init_data(struct pxa_udc *dev)
1723{
1724 int i;
1725 struct pxa_ep *ep;
1726
1727 /* device/ep0 records init */
1728 INIT_LIST_HEAD(&dev->gadget.ep_list);
1729 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1730 dev->udc_usb_ep[0].pxa_ep = &dev->pxa_ep[0];
1731 ep0_idle(dev);
d75379a5
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1732
1733 /* PXA endpoints init */
1734 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
1735 ep = &dev->pxa_ep[i];
1736
1737 ep->enabled = is_ep0(ep);
1738 INIT_LIST_HEAD(&ep->queue);
1739 spin_lock_init(&ep->lock);
1740 }
1741
1742 /* USB endpoints init */
4c24b6d0
VS
1743 for (i = 1; i < NR_USB_ENDPOINTS; i++)
1744 list_add_tail(&dev->udc_usb_ep[i].usb_ep.ep_list,
1745 &dev->gadget.ep_list);
d75379a5
RJ
1746}
1747
1748/**
1749 * udc_enable - Enables the udc device
1750 * @dev: udc device
1751 *
1752 * Enables the udc device : enables clocks, udc interrupts, control endpoint
1753 * interrupts, sets usb as UDC client and setups endpoints.
1754 */
1755static void udc_enable(struct pxa_udc *udc)
1756{
eb507025
RJ
1757 if (udc->enabled)
1758 return;
1759
d75379a5
RJ
1760 udc_writel(udc, UDCICR0, 0);
1761 udc_writel(udc, UDCICR1, 0);
d75379a5
RJ
1762 udc_clear_mask_UDCCR(udc, UDCCR_UDE);
1763
1764 clk_enable(udc->clk);
1765
1766 ep0_idle(udc);
1767 udc->gadget.speed = USB_SPEED_FULL;
1768 memset(&udc->stats, 0, sizeof(udc->stats));
1769
1770 udc_set_mask_UDCCR(udc, UDCCR_UDE);
367815ee 1771 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM);
d75379a5
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1772 udelay(2);
1773 if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
1774 dev_err(udc->dev, "Configuration errors, udc disabled\n");
1775
1776 /*
1777 * Caller must be able to sleep in order to cope with startup transients
1778 */
1779 msleep(100);
1780
1781 /* enable suspend/resume and reset irqs */
1782 udc_writel(udc, UDCICR1,
1783 UDCICR1_IECC | UDCICR1_IERU
1784 | UDCICR1_IESU | UDCICR1_IERS);
1785
1786 /* enable ep0 irqs */
1787 pio_irq_enable(&udc->pxa_ep[0]);
1788
eb507025 1789 udc->enabled = 1;
d75379a5
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1790}
1791
1792/**
1793 * usb_gadget_register_driver - Register gadget driver
1794 * @driver: gadget driver
1795 *
1796 * When a driver is successfully registered, it will receive control requests
1797 * including set_configuration(), which enables non-control requests. Then
1798 * usb traffic follows until a disconnect is reported. Then a host may connect
1799 * again, or the driver might get unbound.
1800 *
eb507025
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1801 * Note that the udc is not automatically enabled. Check function
1802 * should_enable_udc().
1803 *
d75379a5
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1804 * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise
1805 */
1806int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1807{
1808 struct pxa_udc *udc = the_controller;
1809 int retval;
1810
bf31338b 1811 if (!driver || driver->speed < USB_SPEED_FULL || !driver->bind
d75379a5
RJ
1812 || !driver->disconnect || !driver->setup)
1813 return -EINVAL;
1814 if (!udc)
1815 return -ENODEV;
1816 if (udc->driver)
1817 return -EBUSY;
1818
1819 /* first hook up the driver ... */
1820 udc->driver = driver;
1821 udc->gadget.dev.driver = &driver->driver;
eb507025 1822 dplus_pullup(udc, 1);
d75379a5
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1823
1824 retval = device_add(&udc->gadget.dev);
1825 if (retval) {
1826 dev_err(udc->dev, "device_add error %d\n", retval);
1827 goto add_fail;
1828 }
1829 retval = driver->bind(&udc->gadget);
1830 if (retval) {
1831 dev_err(udc->dev, "bind to driver %s --> error %d\n",
1832 driver->driver.name, retval);
1833 goto bind_fail;
1834 }
1835 dev_dbg(udc->dev, "registered gadget driver '%s'\n",
1836 driver->driver.name);
1837
7fec3c25
RJ
1838 if (udc->transceiver) {
1839 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
1840 if (retval) {
1841 dev_err(udc->dev, "can't bind to transceiver\n");
1842 goto transceiver_fail;
1843 }
1844 }
1845
eb507025
RJ
1846 if (should_enable_udc(udc))
1847 udc_enable(udc);
d75379a5
RJ
1848 return 0;
1849
7fec3c25
RJ
1850transceiver_fail:
1851 if (driver->unbind)
1852 driver->unbind(&udc->gadget);
d75379a5
RJ
1853bind_fail:
1854 device_del(&udc->gadget.dev);
1855add_fail:
1856 udc->driver = NULL;
1857 udc->gadget.dev.driver = NULL;
1858 return retval;
1859}
1860EXPORT_SYMBOL(usb_gadget_register_driver);
1861
1862
1863/**
1864 * stop_activity - Stops udc endpoints
1865 * @udc: udc device
1866 * @driver: gadget driver
1867 *
1868 * Disables all udc endpoints (even control endpoint), report disconnect to
1869 * the gadget user.
1870 */
1871static void stop_activity(struct pxa_udc *udc, struct usb_gadget_driver *driver)
1872{
1873 int i;
1874
1875 /* don't disconnect drivers more than once */
1876 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1877 driver = NULL;
1878 udc->gadget.speed = USB_SPEED_UNKNOWN;
1879
1880 for (i = 0; i < NR_USB_ENDPOINTS; i++)
1881 pxa_ep_disable(&udc->udc_usb_ep[i].usb_ep);
1882
1883 if (driver)
1884 driver->disconnect(&udc->gadget);
1885}
1886
1887/**
1888 * usb_gadget_unregister_driver - Unregister the gadget driver
1889 * @driver: gadget driver
1890 *
1891 * Returns 0 if no error, -ENODEV, -EINVAL otherwise
1892 */
1893int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1894{
1895 struct pxa_udc *udc = the_controller;
1896
1897 if (!udc)
1898 return -ENODEV;
1899 if (!driver || driver != udc->driver || !driver->unbind)
1900 return -EINVAL;
1901
1902 stop_activity(udc, driver);
1903 udc_disable(udc);
eb507025 1904 dplus_pullup(udc, 0);
d75379a5
RJ
1905
1906 driver->unbind(&udc->gadget);
1907 udc->driver = NULL;
1908
1909 device_del(&udc->gadget.dev);
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RJ
1910 dev_info(udc->dev, "unregistered gadget driver '%s'\n",
1911 driver->driver.name);
7fec3c25
RJ
1912
1913 if (udc->transceiver)
1914 return otg_set_peripheral(udc->transceiver, NULL);
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RJ
1915 return 0;
1916}
1917EXPORT_SYMBOL(usb_gadget_unregister_driver);
1918
1919/**
1920 * handle_ep0_ctrl_req - handle control endpoint control request
1921 * @udc: udc device
1922 * @req: control request
1923 */
1924static void handle_ep0_ctrl_req(struct pxa_udc *udc,
1925 struct pxa27x_request *req)
1926{
1927 struct pxa_ep *ep = &udc->pxa_ep[0];
1928 union {
1929 struct usb_ctrlrequest r;
1930 u32 word[2];
1931 } u;
1932 int i;
1933 int have_extrabytes = 0;
5e23e90f 1934 unsigned long flags;
d75379a5
RJ
1935
1936 nuke(ep, -EPROTO);
5e23e90f 1937 spin_lock_irqsave(&ep->lock, flags);
d75379a5 1938
9f5351b7
RJ
1939 /*
1940 * In the PXA320 manual, in the section about Back-to-Back setup
1941 * packets, it describes this situation. The solution is to set OPC to
1942 * get rid of the status packet, and then continue with the setup
1943 * packet. Generalize to pxa27x CPUs.
1944 */
1945 if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0))
367815ee 1946 ep_write_UDCCSR(ep, UDCCSR0_OPC);
9f5351b7 1947
d75379a5
RJ
1948 /* read SETUP packet */
1949 for (i = 0; i < 2; i++) {
1950 if (unlikely(ep_is_empty(ep)))
1951 goto stall;
1952 u.word[i] = udc_ep_readl(ep, UDCDR);
1953 }
1954
1955 have_extrabytes = !ep_is_empty(ep);
1956 while (!ep_is_empty(ep)) {
1957 i = udc_ep_readl(ep, UDCDR);
1958 ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i);
1959 }
1960
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RJ
1961 ep_dbg(ep, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1962 u.r.bRequestType, u.r.bRequest,
5a59bc54
RJ
1963 le16_to_cpu(u.r.wValue), le16_to_cpu(u.r.wIndex),
1964 le16_to_cpu(u.r.wLength));
d75379a5
RJ
1965 if (unlikely(have_extrabytes))
1966 goto stall;
1967
1968 if (u.r.bRequestType & USB_DIR_IN)
1969 set_ep0state(udc, IN_DATA_STAGE);
1970 else
1971 set_ep0state(udc, OUT_DATA_STAGE);
1972
1973 /* Tell UDC to enter Data Stage */
367815ee 1974 ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC);
d75379a5 1975
5e23e90f 1976 spin_unlock_irqrestore(&ep->lock, flags);
d75379a5 1977 i = udc->driver->setup(&udc->gadget, &u.r);
5e23e90f 1978 spin_lock_irqsave(&ep->lock, flags);
d75379a5
RJ
1979 if (i < 0)
1980 goto stall;
1981out:
5e23e90f 1982 spin_unlock_irqrestore(&ep->lock, flags);
d75379a5
RJ
1983 return;
1984stall:
1985 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n",
1986 udc_ep_readl(ep, UDCCSR), i);
367815ee 1987 ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF);
d75379a5
RJ
1988 set_ep0state(udc, STALL);
1989 goto out;
1990}
1991
1992/**
1993 * handle_ep0 - Handle control endpoint data transfers
1994 * @udc: udc device
1995 * @fifo_irq: 1 if triggered by fifo service type irq
1996 * @opc_irq: 1 if triggered by output packet complete type irq
1997 *
1998 * Context : when in_interrupt() or with ep->lock held
1999 *
2000 * Tries to transfer all pending request data into the endpoint and/or
2001 * transfer all pending data in the endpoint into usb requests.
2002 * Handles states of ep0 automata.
2003 *
2004 * PXA27x hardware handles several standard usb control requests without
2005 * driver notification. The requests fully handled by hardware are :
2006 * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE,
2007 * GET_STATUS
2008 * The requests handled by hardware, but with irq notification are :
2009 * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE
2010 * The remaining standard requests really handled by handle_ep0 are :
2011 * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests.
2012 * Requests standardized outside of USB 2.0 chapter 9 are handled more
2013 * uniformly, by gadget drivers.
2014 *
2015 * The control endpoint state machine is _not_ USB spec compliant, it's even
2016 * hardly compliant with Intel PXA270 developers guide.
2017 * The key points which inferred this state machine are :
2018 * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by
2019 * software.
2020 * - on every OUT packet received, UDCCSR0_OPC is raised and held until
2021 * cleared by software.
2022 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
2023 * before reading ep0.
9f5351b7
RJ
2024 * This is true only for PXA27x. This is not true anymore for PXA3xx family
2025 * (check Back-to-Back setup packet in developers guide).
d75379a5
RJ
2026 * - irq can be called on a "packet complete" event (opc_irq=1), while
2027 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
2028 * from experimentation).
2029 * - as UDCCSR0_SA can be activated while in irq handling, and clearing
2030 * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC
2031 * => we never actually read the "status stage" packet of an IN data stage
2032 * => this is not documented in Intel documentation
2033 * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA
2034 * STAGE. The driver add STATUS STAGE to send last zero length packet in
2035 * OUT_STATUS_STAGE.
2036 * - special attention was needed for IN_STATUS_STAGE. If a packet complete
2037 * event is detected, we terminate the status stage without ackowledging the
2038 * packet (not to risk to loose a potential SETUP packet)
2039 */
2040static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
2041{
2042 u32 udccsr0;
2043 struct pxa_ep *ep = &udc->pxa_ep[0];
2044 struct pxa27x_request *req = NULL;
2045 int completed = 0;
2046
4c24b6d0
VS
2047 if (!list_empty(&ep->queue))
2048 req = list_entry(ep->queue.next, struct pxa27x_request, queue);
2049
d75379a5
RJ
2050 udccsr0 = udc_ep_readl(ep, UDCCSR);
2051 ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n",
2052 EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR),
2053 (fifo_irq << 1 | opc_irq));
2054
d75379a5
RJ
2055 if (udccsr0 & UDCCSR0_SST) {
2056 ep_dbg(ep, "clearing stall status\n");
2057 nuke(ep, -EPIPE);
367815ee 2058 ep_write_UDCCSR(ep, UDCCSR0_SST);
d75379a5
RJ
2059 ep0_idle(udc);
2060 }
2061
2062 if (udccsr0 & UDCCSR0_SA) {
2063 nuke(ep, 0);
2064 set_ep0state(udc, SETUP_STAGE);
2065 }
2066
2067 switch (udc->ep0state) {
2068 case WAIT_FOR_SETUP:
2069 /*
2070 * Hardware bug : beware, we cannot clear OPC, since we would
2071 * miss a potential OPC irq for a setup packet.
2072 * So, we only do ... nothing, and hope for a next irq with
2073 * UDCCSR0_SA set.
2074 */
2075 break;
2076 case SETUP_STAGE:
2077 udccsr0 &= UDCCSR0_CTRL_REQ_MASK;
2078 if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK))
2079 handle_ep0_ctrl_req(udc, req);
2080 break;
2081 case IN_DATA_STAGE: /* GET_DESCRIPTOR */
2082 if (epout_has_pkt(ep))
367815ee 2083 ep_write_UDCCSR(ep, UDCCSR0_OPC);
d75379a5
RJ
2084 if (req && !ep_is_full(ep))
2085 completed = write_ep0_fifo(ep, req);
2086 if (completed)
5e23e90f 2087 ep0_end_in_req(ep, req, NULL);
d75379a5
RJ
2088 break;
2089 case OUT_DATA_STAGE: /* SET_DESCRIPTOR */
2090 if (epout_has_pkt(ep) && req)
2091 completed = read_ep0_fifo(ep, req);
2092 if (completed)
5e23e90f 2093 ep0_end_out_req(ep, req, NULL);
d75379a5
RJ
2094 break;
2095 case STALL:
367815ee 2096 ep_write_UDCCSR(ep, UDCCSR0_FST);
d75379a5
RJ
2097 break;
2098 case IN_STATUS_STAGE:
2099 /*
2100 * Hardware bug : beware, we cannot clear OPC, since we would
2101 * miss a potential PC irq for a setup packet.
2102 * So, we only put the ep0 into WAIT_FOR_SETUP state.
2103 */
2104 if (opc_irq)
2105 ep0_idle(udc);
2106 break;
2107 case OUT_STATUS_STAGE:
2108 case WAIT_ACK_SET_CONF_INTERF:
2109 ep_warn(ep, "should never get in %s state here!!!\n",
2110 EP0_STNAME(ep->dev));
2111 ep0_idle(udc);
2112 break;
2113 }
2114}
2115
2116/**
2117 * handle_ep - Handle endpoint data tranfers
2118 * @ep: pxa physical endpoint
2119 *
2120 * Tries to transfer all pending request data into the endpoint and/or
2121 * transfer all pending data in the endpoint into usb requests.
2122 *
5e23e90f 2123 * Is always called when in_interrupt() and with ep->lock released.
d75379a5
RJ
2124 */
2125static void handle_ep(struct pxa_ep *ep)
2126{
2127 struct pxa27x_request *req;
2128 int completed;
2129 u32 udccsr;
2130 int is_in = ep->dir_in;
2131 int loop = 0;
5e23e90f
RJ
2132 unsigned long flags;
2133
2134 spin_lock_irqsave(&ep->lock, flags);
2135 if (ep->in_handle_ep)
2136 goto recursion_detected;
2137 ep->in_handle_ep = 1;
d75379a5
RJ
2138
2139 do {
2140 completed = 0;
2141 udccsr = udc_ep_readl(ep, UDCCSR);
5e23e90f 2142
d75379a5
RJ
2143 if (likely(!list_empty(&ep->queue)))
2144 req = list_entry(ep->queue.next,
2145 struct pxa27x_request, queue);
2146 else
2147 req = NULL;
2148
2149 ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n",
2150 req, udccsr, loop++);
2151
2152 if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN)))
2153 udc_ep_writel(ep, UDCCSR,
2154 udccsr & (UDCCSR_SST | UDCCSR_TRN));
2155 if (!req)
2156 break;
2157
2158 if (unlikely(is_in)) {
2159 if (likely(!ep_is_full(ep)))
2160 completed = write_fifo(ep, req);
d75379a5
RJ
2161 } else {
2162 if (likely(epout_has_pkt(ep)))
2163 completed = read_fifo(ep, req);
5e23e90f
RJ
2164 }
2165
2166 if (completed) {
2167 if (is_in)
2168 ep_end_in_req(ep, req, &flags);
2169 else
2170 ep_end_out_req(ep, req, &flags);
d75379a5
RJ
2171 }
2172 } while (completed);
5e23e90f
RJ
2173
2174 ep->in_handle_ep = 0;
2175recursion_detected:
2176 spin_unlock_irqrestore(&ep->lock, flags);
d75379a5
RJ
2177}
2178
2179/**
2180 * pxa27x_change_configuration - Handle SET_CONF usb request notification
2181 * @udc: udc device
2182 * @config: usb configuration
2183 *
2184 * Post the request to upper level.
2185 * Don't use any pxa specific harware configuration capabilities
2186 */
2187static void pxa27x_change_configuration(struct pxa_udc *udc, int config)
2188{
2189 struct usb_ctrlrequest req ;
2190
2191 dev_dbg(udc->dev, "config=%d\n", config);
2192
2193 udc->config = config;
2194 udc->last_interface = 0;
2195 udc->last_alternate = 0;
2196
2197 req.bRequestType = 0;
2198 req.bRequest = USB_REQ_SET_CONFIGURATION;
2199 req.wValue = config;
2200 req.wIndex = 0;
2201 req.wLength = 0;
2202
2203 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2204 udc->driver->setup(&udc->gadget, &req);
367815ee 2205 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
d75379a5
RJ
2206}
2207
2208/**
2209 * pxa27x_change_interface - Handle SET_INTERF usb request notification
2210 * @udc: udc device
2211 * @iface: interface number
2212 * @alt: alternate setting number
2213 *
2214 * Post the request to upper level.
2215 * Don't use any pxa specific harware configuration capabilities
2216 */
2217static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt)
2218{
2219 struct usb_ctrlrequest req;
2220
2221 dev_dbg(udc->dev, "interface=%d, alternate setting=%d\n", iface, alt);
2222
2223 udc->last_interface = iface;
2224 udc->last_alternate = alt;
2225
2226 req.bRequestType = USB_RECIP_INTERFACE;
2227 req.bRequest = USB_REQ_SET_INTERFACE;
2228 req.wValue = alt;
2229 req.wIndex = iface;
2230 req.wLength = 0;
2231
2232 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2233 udc->driver->setup(&udc->gadget, &req);
367815ee 2234 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
d75379a5
RJ
2235}
2236
2237/*
2238 * irq_handle_data - Handle data transfer
2239 * @irq: irq IRQ number
2240 * @udc: dev pxa_udc device structure
2241 *
2242 * Called from irq handler, transferts data to or from endpoint to queue
2243 */
2244static void irq_handle_data(int irq, struct pxa_udc *udc)
2245{
2246 int i;
2247 struct pxa_ep *ep;
2248 u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK;
2249 u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK;
2250
2251 if (udcisr0 & UDCISR_INT_MASK) {
2252 udc->pxa_ep[0].stats.irqs++;
2253 udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK));
2254 handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR),
2255 !!(udcisr0 & UDCICR_PKTCOMPL));
2256 }
2257
2258 udcisr0 >>= 2;
2259 for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) {
2260 if (!(udcisr0 & UDCISR_INT_MASK))
2261 continue;
2262
2263 udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK));
4fdb31d9
ES
2264
2265 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep));
2266 if (i < ARRAY_SIZE(udc->pxa_ep)) {
2267 ep = &udc->pxa_ep[i];
2268 ep->stats.irqs++;
2269 handle_ep(ep);
2270 }
d75379a5
RJ
2271 }
2272
2273 for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) {
2274 udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK));
2275 if (!(udcisr1 & UDCISR_INT_MASK))
2276 continue;
2277
4fdb31d9
ES
2278 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep));
2279 if (i < ARRAY_SIZE(udc->pxa_ep)) {
2280 ep = &udc->pxa_ep[i];
2281 ep->stats.irqs++;
2282 handle_ep(ep);
2283 }
d75379a5
RJ
2284 }
2285
2286}
2287
2288/**
2289 * irq_udc_suspend - Handle IRQ "UDC Suspend"
2290 * @udc: udc device
2291 */
2292static void irq_udc_suspend(struct pxa_udc *udc)
2293{
2294 udc_writel(udc, UDCISR1, UDCISR1_IRSU);
2295 udc->stats.irqs_suspend++;
2296
2297 if (udc->gadget.speed != USB_SPEED_UNKNOWN
2298 && udc->driver && udc->driver->suspend)
2299 udc->driver->suspend(&udc->gadget);
2300 ep0_idle(udc);
2301}
2302
2303/**
2304 * irq_udc_resume - Handle IRQ "UDC Resume"
2305 * @udc: udc device
2306 */
2307static void irq_udc_resume(struct pxa_udc *udc)
2308{
2309 udc_writel(udc, UDCISR1, UDCISR1_IRRU);
2310 udc->stats.irqs_resume++;
2311
2312 if (udc->gadget.speed != USB_SPEED_UNKNOWN
2313 && udc->driver && udc->driver->resume)
2314 udc->driver->resume(&udc->gadget);
2315}
2316
2317/**
2318 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration"
2319 * @udc: udc device
2320 */
2321static void irq_udc_reconfig(struct pxa_udc *udc)
2322{
2323 unsigned config, interface, alternate, config_change;
2324 u32 udccr = udc_readl(udc, UDCCR);
2325
2326 udc_writel(udc, UDCISR1, UDCISR1_IRCC);
2327 udc->stats.irqs_reconfig++;
2328
2329 config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S;
2330 config_change = (config != udc->config);
2331 pxa27x_change_configuration(udc, config);
2332
2333 interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S;
2334 alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S;
2335 pxa27x_change_interface(udc, interface, alternate);
2336
2337 if (config_change)
2338 update_pxa_ep_matches(udc);
2339 udc_set_mask_UDCCR(udc, UDCCR_SMAC);
2340}
2341
2342/**
2343 * irq_udc_reset - Handle IRQ "UDC Reset"
2344 * @udc: udc device
2345 */
2346static void irq_udc_reset(struct pxa_udc *udc)
2347{
2348 u32 udccr = udc_readl(udc, UDCCR);
2349 struct pxa_ep *ep = &udc->pxa_ep[0];
2350
2351 dev_info(udc->dev, "USB reset\n");
2352 udc_writel(udc, UDCISR1, UDCISR1_IRRS);
2353 udc->stats.irqs_reset++;
2354
2355 if ((udccr & UDCCR_UDA) == 0) {
2356 dev_dbg(udc->dev, "USB reset start\n");
2357 stop_activity(udc, udc->driver);
2358 }
2359 udc->gadget.speed = USB_SPEED_FULL;
2360 memset(&udc->stats, 0, sizeof udc->stats);
2361
2362 nuke(ep, -EPROTO);
367815ee 2363 ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC);
d75379a5
RJ
2364 ep0_idle(udc);
2365}
2366
2367/**
2368 * pxa_udc_irq - Main irq handler
2369 * @irq: irq number
2370 * @_dev: udc device
2371 *
2372 * Handles all udc interrupts
2373 */
2374static irqreturn_t pxa_udc_irq(int irq, void *_dev)
2375{
2376 struct pxa_udc *udc = _dev;
2377 u32 udcisr0 = udc_readl(udc, UDCISR0);
2378 u32 udcisr1 = udc_readl(udc, UDCISR1);
2379 u32 udccr = udc_readl(udc, UDCCR);
2380 u32 udcisr1_spec;
2381
2382 dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
2383 "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr);
2384
2385 udcisr1_spec = udcisr1 & 0xf8000000;
2386 if (unlikely(udcisr1_spec & UDCISR1_IRSU))
2387 irq_udc_suspend(udc);
2388 if (unlikely(udcisr1_spec & UDCISR1_IRRU))
2389 irq_udc_resume(udc);
2390 if (unlikely(udcisr1_spec & UDCISR1_IRCC))
2391 irq_udc_reconfig(udc);
2392 if (unlikely(udcisr1_spec & UDCISR1_IRRS))
2393 irq_udc_reset(udc);
2394
2395 if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK))
2396 irq_handle_data(irq, udc);
2397
2398 return IRQ_HANDLED;
2399}
2400
2401static struct pxa_udc memory = {
2402 .gadget = {
2403 .ops = &pxa_udc_ops,
2404 .ep0 = &memory.udc_usb_ep[0].usb_ep,
2405 .name = driver_name,
2406 .dev = {
c682b170 2407 .init_name = "gadget",
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RJ
2408 },
2409 },
2410
2411 .udc_usb_ep = {
2412 USB_EP_CTRL,
2413 USB_EP_OUT_BULK(1),
2414 USB_EP_IN_BULK(2),
2415 USB_EP_IN_ISO(3),
2416 USB_EP_OUT_ISO(4),
2417 USB_EP_IN_INT(5),
2418 },
2419
2420 .pxa_ep = {
2421 PXA_EP_CTRL,
2422 /* Endpoints for gadget zero */
2423 PXA_EP_OUT_BULK(1, 1, 3, 0, 0),
2424 PXA_EP_IN_BULK(2, 2, 3, 0, 0),
2425 /* Endpoints for ether gadget, file storage gadget */
2426 PXA_EP_OUT_BULK(3, 1, 1, 0, 0),
2427 PXA_EP_IN_BULK(4, 2, 1, 0, 0),
2428 PXA_EP_IN_ISO(5, 3, 1, 0, 0),
2429 PXA_EP_OUT_ISO(6, 4, 1, 0, 0),
2430 PXA_EP_IN_INT(7, 5, 1, 0, 0),
2431 /* Endpoints for RNDIS, serial */
2432 PXA_EP_OUT_BULK(8, 1, 2, 0, 0),
2433 PXA_EP_IN_BULK(9, 2, 2, 0, 0),
2434 PXA_EP_IN_INT(10, 5, 2, 0, 0),
2435 /*
2436 * All the following endpoints are only for completion. They
2437 * won't never work, as multiple interfaces are really broken on
2438 * the pxa.
2439 */
2440 PXA_EP_OUT_BULK(11, 1, 2, 1, 0),
2441 PXA_EP_IN_BULK(12, 2, 2, 1, 0),
2442 /* Endpoint for CDC Ether */
2443 PXA_EP_OUT_BULK(13, 1, 1, 1, 1),
2444 PXA_EP_IN_BULK(14, 2, 1, 1, 1),
2445 }
2446};
2447
2448/**
2449 * pxa_udc_probe - probes the udc device
2450 * @_dev: platform device
2451 *
2452 * Perform basic init : allocates udc clock, creates sysfs files, requests
2453 * irq.
2454 */
2455static int __init pxa_udc_probe(struct platform_device *pdev)
2456{
2457 struct resource *regs;
2458 struct pxa_udc *udc = &memory;
eb507025 2459 int retval = 0, gpio;
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2460
2461 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2462 if (!regs)
2463 return -ENXIO;
2464 udc->irq = platform_get_irq(pdev, 0);
2465 if (udc->irq < 0)
2466 return udc->irq;
2467
2468 udc->dev = &pdev->dev;
2469 udc->mach = pdev->dev.platform_data;
7fec3c25 2470 udc->transceiver = otg_get_transceiver();
d75379a5 2471
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2472 gpio = udc->mach->gpio_pullup;
2473 if (gpio_is_valid(gpio)) {
2474 retval = gpio_request(gpio, "USB D+ pullup");
2475 if (retval == 0)
2476 gpio_direction_output(gpio,
2477 udc->mach->gpio_pullup_inverted);
2478 }
2479 if (retval) {
2480 dev_err(&pdev->dev, "Couldn't request gpio %d : %d\n",
2481 gpio, retval);
2482 return retval;
2483 }
2484
e0d8b13a 2485 udc->clk = clk_get(&pdev->dev, NULL);
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RJ
2486 if (IS_ERR(udc->clk)) {
2487 retval = PTR_ERR(udc->clk);
2488 goto err_clk;
2489 }
2490
2491 retval = -ENOMEM;
5c90e314 2492 udc->regs = ioremap(regs->start, resource_size(regs));
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RJ
2493 if (!udc->regs) {
2494 dev_err(&pdev->dev, "Unable to map UDC I/O memory\n");
2495 goto err_map;
2496 }
2497
2498 device_initialize(&udc->gadget.dev);
2499 udc->gadget.dev.parent = &pdev->dev;
2500 udc->gadget.dev.dma_mask = NULL;
b799a7eb 2501 udc->vbus_sensed = 0;
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RJ
2502
2503 the_controller = udc;
2504 platform_set_drvdata(pdev, udc);
2505 udc_init_data(udc);
2506 pxa_eps_setup(udc);
2507
2508 /* irq setup after old hardware state is cleaned up */
2509 retval = request_irq(udc->irq, pxa_udc_irq,
2510 IRQF_SHARED, driver_name, udc);
2511 if (retval != 0) {
2512 dev_err(udc->dev, "%s: can't get irq %i, err %d\n",
2513 driver_name, IRQ_USB, retval);
2514 goto err_irq;
2515 }
2516
2517 pxa_init_debugfs(udc);
2518 return 0;
2519err_irq:
2520 iounmap(udc->regs);
2521err_map:
2522 clk_put(udc->clk);
2523 udc->clk = NULL;
2524err_clk:
2525 return retval;
2526}
2527
2528/**
2529 * pxa_udc_remove - removes the udc device driver
2530 * @_dev: platform device
2531 */
2532static int __exit pxa_udc_remove(struct platform_device *_dev)
2533{
2534 struct pxa_udc *udc = platform_get_drvdata(_dev);
eb507025 2535 int gpio = udc->mach->gpio_pullup;
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RJ
2536
2537 usb_gadget_unregister_driver(udc->driver);
2538 free_irq(udc->irq, udc);
2539 pxa_cleanup_debugfs(udc);
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RJ
2540 if (gpio_is_valid(gpio))
2541 gpio_free(gpio);
d75379a5 2542
7fec3c25
RJ
2543 otg_put_transceiver(udc->transceiver);
2544
2545 udc->transceiver = NULL;
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RJ
2546 platform_set_drvdata(_dev, NULL);
2547 the_controller = NULL;
2548 clk_put(udc->clk);
4c24b6d0 2549 iounmap(udc->regs);
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2550
2551 return 0;
2552}
2553
2554static void pxa_udc_shutdown(struct platform_device *_dev)
2555{
2556 struct pxa_udc *udc = platform_get_drvdata(_dev);
2557
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RJ
2558 if (udc_readl(udc, UDCCR) & UDCCR_UDE)
2559 udc_disable(udc);
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2560}
2561
59376cc3 2562#ifdef CONFIG_PXA27x
f6d529f9
DB
2563extern void pxa27x_clear_otgph(void);
2564#else
2565#define pxa27x_clear_otgph() do {} while (0)
2566#endif
2567
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2568#ifdef CONFIG_PM
2569/**
2570 * pxa_udc_suspend - Suspend udc device
2571 * @_dev: platform device
2572 * @state: suspend state
2573 *
2574 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc
2575 * device.
2576 */
2577static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state)
2578{
2579 int i;
2580 struct pxa_udc *udc = platform_get_drvdata(_dev);
2581 struct pxa_ep *ep;
2582
2583 ep = &udc->pxa_ep[0];
2584 udc->udccsr0 = udc_ep_readl(ep, UDCCSR);
2585 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
2586 ep = &udc->pxa_ep[i];
2587 ep->udccsr_value = udc_ep_readl(ep, UDCCSR);
2588 ep->udccr_value = udc_ep_readl(ep, UDCCR);
2589 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n",
2590 ep->udccsr_value, ep->udccr_value);
2591 }
2592
2593 udc_disable(udc);
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2594 udc->pullup_resume = udc->pullup_on;
2595 dplus_pullup(udc, 0);
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2596
2597 return 0;
2598}
2599
2600/**
2601 * pxa_udc_resume - Resume udc device
2602 * @_dev: platform device
2603 *
2604 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc
2605 * device.
2606 */
2607static int pxa_udc_resume(struct platform_device *_dev)
2608{
2609 int i;
2610 struct pxa_udc *udc = platform_get_drvdata(_dev);
2611 struct pxa_ep *ep;
2612
2613 ep = &udc->pxa_ep[0];
2614 udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME));
2615 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
2616 ep = &udc->pxa_ep[i];
2617 udc_ep_writel(ep, UDCCSR, ep->udccsr_value);
2618 udc_ep_writel(ep, UDCCR, ep->udccr_value);
2619 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n",
2620 ep->udccsr_value, ep->udccr_value);
2621 }
2622
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2623 dplus_pullup(udc, udc->pullup_resume);
2624 if (should_enable_udc(udc))
2625 udc_enable(udc);
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2626 /*
2627 * We do not handle OTG yet.
2628 *
2629 * OTGPH bit is set when sleep mode is entered.
2630 * it indicates that OTG pad is retaining its state.
2631 * Upon exit from sleep mode and before clearing OTGPH,
2632 * Software must configure the USB OTG pad, UDC, and UHC
2633 * to the state they were in before entering sleep mode.
d75379a5 2634 */
f6d529f9 2635 pxa27x_clear_otgph();
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2636
2637 return 0;
2638}
2639#endif
2640
2641/* work with hotplug and coldplug */
7a857620 2642MODULE_ALIAS("platform:pxa27x-udc");
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RJ
2643
2644static struct platform_driver udc_driver = {
2645 .driver = {
7a857620 2646 .name = "pxa27x-udc",
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RJ
2647 .owner = THIS_MODULE,
2648 },
2649 .remove = __exit_p(pxa_udc_remove),
2650 .shutdown = pxa_udc_shutdown,
2651#ifdef CONFIG_PM
2652 .suspend = pxa_udc_suspend,
2653 .resume = pxa_udc_resume
2654#endif
2655};
2656
2657static int __init udc_init(void)
2658{
9f5351b7 2659 if (!cpu_is_pxa27x() && !cpu_is_pxa3xx())
5a59bc54
RJ
2660 return -ENODEV;
2661
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RJ
2662 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2663 return platform_driver_probe(&udc_driver, pxa_udc_probe);
2664}
2665module_init(udc_init);
2666
2667
2668static void __exit udc_exit(void)
2669{
2670 platform_driver_unregister(&udc_driver);
2671}
2672module_exit(udc_exit);
2673
2674MODULE_DESCRIPTION(DRIVER_DESC);
2675MODULE_AUTHOR("Robert Jarzmik");
2676MODULE_LICENSE("GPL");