| d7636e0b |
1 | #ifndef _XGIFB_MAIN |
| 2 | #define _XGIFB_MAIN |
| 3 | |
| 4 | |
| 5 | /* ------------------- Constant Definitions ------------------------- */ |
| 6 | |
| 7 | |
| 8 | #include "XGIfb.h" |
| 9 | #include "vb_struct.h" |
| 10 | #include "vb_def.h" |
| 11 | |
| 12 | //#define LINUXBIOS /* turn this on when compiling for LINUXBIOS */ |
| 13 | #define AGPOFF /* default is turn off AGP */ |
| 14 | |
| 15 | #define XGIFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0) |
| 16 | |
| 17 | #define VER_MAJOR 0 |
| 18 | #define VER_MINOR 8 |
| 19 | #define VER_LEVEL 1 |
| 20 | |
| 21 | #define DRIVER_DESC "XGI Volari Frame Buffer Module Version 0.8.1" |
| 22 | |
| 23 | #ifndef PCI_VENDOR_ID_XG |
| 24 | #define PCI_VENDOR_ID_XG 0x18CA |
| 25 | #endif |
| 26 | |
| 27 | #ifndef PCI_DEVICE_ID_XG_40 |
| 28 | #define PCI_DEVICE_ID_XG_40 0x040 |
| 29 | #endif |
| 30 | #ifndef PCI_DEVICE_ID_XG_41 |
| 31 | #define PCI_DEVICE_ID_XG_41 0x041 |
| 32 | #endif |
| 33 | #ifndef PCI_DEVICE_ID_XG_42 |
| 34 | #define PCI_DEVICE_ID_XG_42 0x042 |
| 35 | #endif |
| 36 | #ifndef PCI_DEVICE_ID_XG_20 |
| 37 | #define PCI_DEVICE_ID_XG_20 0x020 |
| 38 | #endif |
| 39 | #ifndef PCI_DEVICE_ID_XG_27 |
| 40 | #define PCI_DEVICE_ID_XG_27 0x027 |
| 41 | #endif |
| 42 | |
| 43 | |
| 44 | |
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45 | #define XGI_IOTYPE1 void __iomem |
| 46 | #define XGI_IOTYPE2 __iomem |
| 47 | #define XGIINITSTATIC static |
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48 | |
| d7636e0b |
49 | static struct pci_device_id __devinitdata xgifb_pci_table[] = { |
| 50 | |
| 51 | { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 52 | { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_27, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
| 53 | { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_40, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, |
| 54 | { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, |
| 55 | { 0 } |
| 56 | }; |
| 57 | |
| 58 | MODULE_DEVICE_TABLE(pci, xgifb_pci_table); |
| 23aada9c |
59 | |
| d7636e0b |
60 | /* To be included in fb.h */ |
| 61 | #ifndef FB_ACCEL_XGI_GLAMOUR_2 |
| 62 | #define FB_ACCEL_XGI_GLAMOUR_2 40 /* XGI 315, 650, 740 */ |
| 63 | #endif |
| 64 | #ifndef FB_ACCEL_XGI_XABRE |
| 65 | #define FB_ACCEL_XGI_XABRE 41 /* XGI 330 ("Xabre") */ |
| 66 | #endif |
| 67 | |
| 68 | #define MAX_ROM_SCAN 0x10000 |
| 69 | |
| 70 | #define HW_CURSOR_CAP 0x80 |
| 71 | #define TURBO_QUEUE_CAP 0x40 |
| 72 | #define AGP_CMD_QUEUE_CAP 0x20 |
| 73 | #define VM_CMD_QUEUE_CAP 0x10 |
| 74 | #define MMIO_CMD_QUEUE_CAP 0x08 |
| 75 | |
| 76 | |
| 77 | |
| 78 | /* For 315 series */ |
| 79 | |
| 80 | #define COMMAND_QUEUE_AREA_SIZE 0x80000 /* 512K */ |
| 81 | #define COMMAND_QUEUE_THRESHOLD 0x1F |
| 82 | |
| 83 | |
| 84 | /* TW */ |
| 85 | #define HW_CURSOR_AREA_SIZE_315 0x4000 /* 16K */ |
| 86 | #define HW_CURSOR_AREA_SIZE_300 0x1000 /* 4K */ |
| 87 | |
| 88 | #define OH_ALLOC_SIZE 4000 |
| 89 | #define SENTINEL 0x7fffffff |
| 90 | |
| 91 | #define SEQ_ADR 0x14 |
| 92 | #define SEQ_DATA 0x15 |
| 93 | #define DAC_ADR 0x18 |
| 94 | #define DAC_DATA 0x19 |
| 95 | #define CRTC_ADR 0x24 |
| 96 | #define CRTC_DATA 0x25 |
| 97 | #define DAC2_ADR (0x16-0x30) |
| 98 | #define DAC2_DATA (0x17-0x30) |
| 99 | #define VB_PART1_ADR (0x04-0x30) |
| 100 | #define VB_PART1_DATA (0x05-0x30) |
| 101 | #define VB_PART2_ADR (0x10-0x30) |
| 102 | #define VB_PART2_DATA (0x11-0x30) |
| 103 | #define VB_PART3_ADR (0x12-0x30) |
| 104 | #define VB_PART3_DATA (0x13-0x30) |
| 105 | #define VB_PART4_ADR (0x14-0x30) |
| 106 | #define VB_PART4_DATA (0x15-0x30) |
| 107 | |
| 108 | #define XGISR XGI_Pr.P3c4 |
| 109 | #define XGICR XGI_Pr.P3d4 |
| 110 | #define XGIDACA XGI_Pr.P3c8 |
| 111 | #define XGIDACD XGI_Pr.P3c9 |
| 112 | #define XGIPART1 XGI_Pr.Part1Port |
| 113 | #define XGIPART2 XGI_Pr.Part2Port |
| 114 | #define XGIPART3 XGI_Pr.Part3Port |
| 115 | #define XGIPART4 XGI_Pr.Part4Port |
| 116 | #define XGIPART5 XGI_Pr.Part5Port |
| 117 | #define XGIDAC2A XGIPART5 |
| 118 | #define XGIDAC2D (XGIPART5 + 1) |
| 119 | #define XGIMISCR (XGI_Pr.RelIO + 0x1c) |
| 120 | #define XGIINPSTAT (XGI_Pr.RelIO + 0x2a) |
| 121 | |
| 122 | #define IND_XGI_PASSWORD 0x05 /* SRs */ |
| 123 | #define IND_XGI_COLOR_MODE 0x06 |
| 124 | #define IND_XGI_RAMDAC_CONTROL 0x07 |
| 125 | #define IND_XGI_DRAM_SIZE 0x14 |
| 126 | #define IND_XGI_SCRATCH_REG_16 0x16 |
| 127 | #define IND_XGI_SCRATCH_REG_17 0x17 |
| 128 | #define IND_XGI_SCRATCH_REG_1A 0x1A |
| 129 | #define IND_XGI_MODULE_ENABLE 0x1E |
| 130 | #define IND_XGI_PCI_ADDRESS_SET 0x20 |
| 131 | #define IND_XGI_TURBOQUEUE_ADR 0x26 |
| 132 | #define IND_XGI_TURBOQUEUE_SET 0x27 |
| 133 | #define IND_XGI_POWER_ON_TRAP 0x38 |
| 134 | #define IND_XGI_POWER_ON_TRAP2 0x39 |
| 135 | #define IND_XGI_CMDQUEUE_SET 0x26 |
| 136 | #define IND_XGI_CMDQUEUE_THRESHOLD 0x27 |
| 137 | |
| 138 | #define IND_XGI_SCRATCH_REG_CR30 0x30 /* CRs */ |
| 139 | #define IND_XGI_SCRATCH_REG_CR31 0x31 |
| 140 | #define IND_XGI_SCRATCH_REG_CR32 0x32 |
| 141 | #define IND_XGI_SCRATCH_REG_CR33 0x33 |
| 142 | #define IND_XGI_LCD_PANEL 0x36 |
| 143 | #define IND_XGI_SCRATCH_REG_CR37 0x37 |
| 144 | #define IND_XGI_AGP_IO_PAD 0x48 |
| 145 | |
| 146 | #define IND_BRI_DRAM_STATUS 0x63 /* PCI config memory size offset */ |
| 147 | |
| 148 | #define MMIO_QUEUE_PHYBASE 0x85C0 |
| 149 | #define MMIO_QUEUE_WRITEPORT 0x85C4 |
| 150 | #define MMIO_QUEUE_READPORT 0x85C8 |
| 151 | |
| 152 | #define IND_XGI_CRT2_WRITE_ENABLE_300 0x24 |
| 153 | #define IND_XGI_CRT2_WRITE_ENABLE_315 0x2F |
| 154 | |
| 155 | #define XGI_PASSWORD 0x86 /* SR05 */ |
| 156 | #define XGI_INTERLACED_MODE 0x20 /* SR06 */ |
| 157 | #define XGI_8BPP_COLOR_MODE 0x0 |
| 158 | #define XGI_15BPP_COLOR_MODE 0x1 |
| 159 | #define XGI_16BPP_COLOR_MODE 0x2 |
| 160 | #define XGI_32BPP_COLOR_MODE 0x4 |
| 161 | |
| 162 | #define XGI_DRAM_SIZE_MASK 0xF0 /*SR14 */ |
| 163 | #define XGI_DRAM_SIZE_1MB 0x00 |
| 164 | #define XGI_DRAM_SIZE_2MB 0x01 |
| 165 | #define XGI_DRAM_SIZE_4MB 0x02 |
| 166 | #define XGI_DRAM_SIZE_8MB 0x03 |
| 167 | #define XGI_DRAM_SIZE_16MB 0x04 |
| 168 | #define XGI_DRAM_SIZE_32MB 0x05 |
| 169 | #define XGI_DRAM_SIZE_64MB 0x06 |
| 170 | #define XGI_DRAM_SIZE_128MB 0x07 |
| 171 | #define XGI_DRAM_SIZE_256MB 0x08 |
| 172 | #define XGI_DATA_BUS_MASK 0x02 |
| 173 | #define XGI_DATA_BUS_64 0x00 |
| 174 | #define XGI_DATA_BUS_128 0x01 |
| 175 | #define XGI_DUAL_CHANNEL_MASK 0x0C |
| 176 | #define XGI_SINGLE_CHANNEL_1_RANK 0x0 |
| 177 | #define XGI_SINGLE_CHANNEL_2_RANK 0x1 |
| 178 | #define XGI_ASYM_DDR 0x02 |
| 179 | #define XGI_DUAL_CHANNEL_1_RANK 0x3 |
| 180 | |
| 181 | #define XGI550_DRAM_SIZE_MASK 0x3F /* 550/650/740 SR14 */ |
| 182 | #define XGI550_DRAM_SIZE_4MB 0x00 |
| 183 | #define XGI550_DRAM_SIZE_8MB 0x01 |
| 184 | #define XGI550_DRAM_SIZE_16MB 0x03 |
| 185 | #define XGI550_DRAM_SIZE_24MB 0x05 |
| 186 | #define XGI550_DRAM_SIZE_32MB 0x07 |
| 187 | #define XGI550_DRAM_SIZE_64MB 0x0F |
| 188 | #define XGI550_DRAM_SIZE_96MB 0x17 |
| 189 | #define XGI550_DRAM_SIZE_128MB 0x1F |
| 190 | #define XGI550_DRAM_SIZE_256MB 0x3F |
| 191 | |
| 192 | #define XGI_SCRATCH_REG_1A_MASK 0x10 |
| 193 | |
| 194 | #define XGI_ENABLE_2D 0x40 /* SR1E */ |
| 195 | |
| 196 | #define XGI_MEM_MAP_IO_ENABLE 0x01 /* SR20 */ |
| 197 | #define XGI_PCI_ADDR_ENABLE 0x80 |
| 198 | |
| 199 | #define XGI_AGP_CMDQUEUE_ENABLE 0x80 /* 315/650/740 SR26 */ |
| 200 | #define XGI_VRAM_CMDQUEUE_ENABLE 0x40 |
| 201 | #define XGI_MMIO_CMD_ENABLE 0x20 |
| 202 | #define XGI_CMD_QUEUE_SIZE_512k 0x00 |
| 203 | #define XGI_CMD_QUEUE_SIZE_1M 0x04 |
| 204 | #define XGI_CMD_QUEUE_SIZE_2M 0x08 |
| 205 | #define XGI_CMD_QUEUE_SIZE_4M 0x0C |
| 206 | #define XGI_CMD_QUEUE_RESET 0x01 |
| 207 | #define XGI_CMD_AUTO_CORR 0x02 |
| 208 | |
| 209 | #define XGI_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */ |
| 210 | #define XGI_MODE_SELECT_CRT2 0x02 |
| 211 | #define XGI_VB_OUTPUT_COMPOSITE 0x04 |
| 212 | #define XGI_VB_OUTPUT_SVIDEO 0x08 |
| 213 | #define XGI_VB_OUTPUT_SCART 0x10 |
| 214 | #define XGI_VB_OUTPUT_LCD 0x20 |
| 215 | #define XGI_VB_OUTPUT_CRT2 0x40 |
| 216 | #define XGI_VB_OUTPUT_HIVISION 0x80 |
| 217 | |
| 218 | #define XGI_VB_OUTPUT_DISABLE 0x20 /* CR31 */ |
| 219 | #define XGI_DRIVER_MODE 0x40 |
| 220 | |
| 221 | #define XGI_VB_COMPOSITE 0x01 /* CR32 */ |
| 222 | #define XGI_VB_SVIDEO 0x02 |
| 223 | #define XGI_VB_SCART 0x04 |
| 224 | #define XGI_VB_LCD 0x08 |
| 225 | #define XGI_VB_CRT2 0x10 |
| 226 | #define XGI_CRT1 0x20 |
| 227 | #define XGI_VB_HIVISION 0x40 |
| 228 | #define XGI_VB_YPBPR 0x80 |
| 229 | #define XGI_VB_TV (XGI_VB_COMPOSITE | XGI_VB_SVIDEO | \ |
| 230 | XGI_VB_SCART | XGI_VB_HIVISION|XGI_VB_YPBPR) |
| 231 | |
| 232 | #define XGI_EXTERNAL_CHIP_MASK 0x0E /* CR37 */ |
| 233 | #define XGI_EXTERNAL_CHIP_XGI301 0x01 /* in CR37 << 1 ! */ |
| 234 | #define XGI_EXTERNAL_CHIP_LVDS 0x02 /* in CR37 << 1 ! */ |
| 235 | #define XGI_EXTERNAL_CHIP_TRUMPION 0x03 /* in CR37 << 1 ! */ |
| 236 | #define XGI_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04 /* in CR37 << 1 ! */ |
| 237 | #define XGI_EXTERNAL_CHIP_CHRONTEL 0x05 /* in CR37 << 1 ! */ |
| 238 | #define XGI310_EXTERNAL_CHIP_LVDS 0x02 /* in CR37 << 1 ! */ |
| 239 | #define XGI310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03 /* in CR37 << 1 ! */ |
| 240 | |
| 241 | #define XGI_AGP_2X 0x20 /* CR48 */ |
| 242 | |
| 243 | #define BRI_DRAM_SIZE_MASK 0x70 /* PCI bridge config data */ |
| 244 | #define BRI_DRAM_SIZE_2MB 0x00 |
| 245 | #define BRI_DRAM_SIZE_4MB 0x01 |
| 246 | #define BRI_DRAM_SIZE_8MB 0x02 |
| 247 | #define BRI_DRAM_SIZE_16MB 0x03 |
| 248 | #define BRI_DRAM_SIZE_32MB 0x04 |
| 249 | #define BRI_DRAM_SIZE_64MB 0x05 |
| 250 | |
| 251 | #define HW_DEVICE_EXTENSION XGI_HW_DEVICE_INFO |
| 252 | #define PHW_DEVICE_EXTENSION PXGI_HW_DEVICE_INFO |
| 253 | |
| 254 | #define SR_BUFFER_SIZE 5 |
| 255 | #define CR_BUFFER_SIZE 5 |
| 256 | |
| 257 | /* Useful macros */ |
| 258 | #define inXGIREG(base) inb(base) |
| 259 | #define outXGIREG(base,val) outb(val,base) |
| 260 | #define orXGIREG(base,val) do { \ |
| 261 | unsigned char __Temp = inb(base); \ |
| 262 | outXGIREG(base, __Temp | (val)); \ |
| 263 | } while (0) |
| 264 | #define andXGIREG(base,val) do { \ |
| 265 | unsigned char __Temp = inb(base); \ |
| 266 | outXGIREG(base, __Temp & (val)); \ |
| 267 | } while (0) |
| 268 | #define inXGIIDXREG(base,idx,var) do { \ |
| 269 | outb(idx,base); var=inb((base)+1); \ |
| 270 | } while (0) |
| 271 | #define outXGIIDXREG(base,idx,val) do { \ |
| 272 | outb(idx,base); outb((val),(base)+1); \ |
| 273 | } while (0) |
| 274 | #define orXGIIDXREG(base,idx,val) do { \ |
| 275 | unsigned char __Temp; \ |
| 276 | outb(idx,base); \ |
| 277 | __Temp = inb((base)+1)|(val); \ |
| 278 | outXGIIDXREG(base,idx,__Temp); \ |
| 279 | } while (0) |
| 280 | #define andXGIIDXREG(base,idx,and) do { \ |
| 281 | unsigned char __Temp; \ |
| 282 | outb(idx,base); \ |
| 283 | __Temp = inb((base)+1)&(and); \ |
| 284 | outXGIIDXREG(base,idx,__Temp); \ |
| 285 | } while (0) |
| 286 | #define setXGIIDXREG(base,idx,and,or) do { \ |
| 287 | unsigned char __Temp; \ |
| 288 | outb(idx,base); \ |
| 289 | __Temp = (inb((base)+1)&(and))|(or); \ |
| 290 | outXGIIDXREG(base,idx,__Temp); \ |
| 291 | } while (0) |
| 292 | |
| 293 | /* ------------------- Global Variables ----------------------------- */ |
| 294 | |
| 295 | /* Fbcon variables */ |
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296 | static struct fb_info* fb_info; |
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297 | |
| 298 | |
| 299 | static int video_type = FB_TYPE_PACKED_PIXELS; |
| 300 | |
| 301 | static struct fb_var_screeninfo default_var = { |
| 302 | .xres = 0, |
| 303 | .yres = 0, |
| 304 | .xres_virtual = 0, |
| 305 | .yres_virtual = 0, |
| 306 | .xoffset = 0, |
| 307 | .yoffset = 0, |
| 308 | .bits_per_pixel = 0, |
| 309 | .grayscale = 0, |
| 310 | .red = {0, 8, 0}, |
| 311 | .green = {0, 8, 0}, |
| 312 | .blue = {0, 8, 0}, |
| 313 | .transp = {0, 0, 0}, |
| 314 | .nonstd = 0, |
| 315 | .activate = FB_ACTIVATE_NOW, |
| 316 | .height = -1, |
| 317 | .width = -1, |
| 318 | .accel_flags = 0, |
| 319 | .pixclock = 0, |
| 320 | .left_margin = 0, |
| 321 | .right_margin = 0, |
| 322 | .upper_margin = 0, |
| 323 | .lower_margin = 0, |
| 324 | .hsync_len = 0, |
| 325 | .vsync_len = 0, |
| 326 | .sync = 0, |
| 327 | .vmode = FB_VMODE_NONINTERLACED, |
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328 | }; |
| 329 | |
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330 | static struct fb_fix_screeninfo XGIfb_fix = { |
| 331 | .id = "XGI", |
| 332 | .type = FB_TYPE_PACKED_PIXELS, |
| 333 | .xpanstep = 1, |
| 334 | .ypanstep = 1, |
| 335 | }; |
| 336 | static char myid[20]; |
| 337 | static u32 pseudo_palette[17]; |
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338 | |
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339 | |
| 340 | /* display status */ |
| 341 | static int XGIfb_off = 0; |
| 342 | static int XGIfb_crt1off = 0; |
| 343 | static int XGIfb_forcecrt1 = -1; |
| 344 | static int XGIvga_enabled = 0; |
| 345 | static int XGIfb_userom = 0; |
| 346 | //static int XGIfb_useoem = -1; |
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347 | |
| 348 | /* global flags */ |
| 349 | static int XGIfb_registered; |
| 350 | static int XGIfb_tvmode = 0; |
| 351 | static int XGIfb_mem = 0; |
| 352 | static int XGIfb_pdc = 0; |
| 353 | static int enable_dstn = 0; |
| 354 | static int XGIfb_ypan = -1; |
| 355 | |
| 356 | |
| 357 | int XGIfb_accel = 0; |
| 358 | |
| 359 | |
| 360 | static int XGIfb_hwcursor_size = 0; |
| 361 | static int XGIfb_CRT2_write_enable = 0; |
| 362 | |
| 363 | int XGIfb_crt2type = -1; /* TW: CRT2 type (for overriding autodetection) */ |
| 364 | int XGIfb_tvplug = -1; /* PR: Tv plug type (for overriding autodetection) */ |
| 365 | |
| 366 | int XGIfb_queuemode = -1; /* TW: Use MMIO queue mode by default (310/325 series only) */ |
| 367 | |
| 368 | unsigned char XGIfb_detectedpdc = 0; |
| 369 | |
| 370 | unsigned char XGIfb_detectedlcda = 0xff; |
| 371 | |
| 372 | |
| 373 | |
| 374 | |
| 375 | /* TW: For ioctl XGIFB_GET_INFO */ |
| 376 | /* XGIfb_info XGIfbinfo; */ |
| 377 | |
| 378 | /* TW: Hardware extension; contains data on hardware */ |
| 379 | HW_DEVICE_EXTENSION XGIhw_ext; |
| 380 | |
| 381 | /* TW: XGI private structure */ |
| 382 | VB_DEVICE_INFO XGI_Pr; |
| 383 | |
| 384 | /* card parameters */ |
| 385 | static unsigned long XGIfb_mmio_size = 0; |
| 386 | static u8 XGIfb_caps = 0; |
| 387 | |
| 388 | typedef enum _XGI_CMDTYPE { |
| 389 | MMIO_CMD = 0, |
| 390 | AGP_CMD_QUEUE, |
| 391 | VM_CMD_QUEUE, |
| 392 | } XGI_CMDTYPE; |
| 393 | |
| 394 | #define MD_XGI300 1 |
| 395 | #define MD_XGI315 2 |
| 396 | |
| 397 | /* mode table */ |
| 398 | /* NOT const - will be patched for 1280x960 mode number chaos reasons */ |
| 399 | struct _XGIbios_mode { |
| 400 | char name[15]; |
| 401 | u8 mode_no; |
| 402 | u16 vesa_mode_no_1; /* "XGI defined" VESA mode number */ |
| 403 | u16 vesa_mode_no_2; /* Real VESA mode numbers */ |
| 404 | u16 xres; |
| 405 | u16 yres; |
| 406 | u16 bpp; |
| 407 | u16 rate_idx; |
| 408 | u16 cols; |
| 409 | u16 rows; |
| 410 | u8 chipset; |
| 411 | } XGIbios_mode[] = { |
| 412 | #define MODE_INDEX_NONE 0 /* TW: index for mode=none */ |
| 413 | {"none", 0xFF, 0x0000, 0x0000, 0, 0, 0, 0, 0, 0, MD_XGI300|MD_XGI315}, /* TW: for mode "none" */ |
| 414 | {"320x240x16", 0x56, 0x0000, 0x0000, 320, 240, 16, 1, 40, 15, MD_XGI315}, |
| 415 | {"320x480x8", 0x5A, 0x0000, 0x0000, 320, 480, 8, 1, 40, 30, MD_XGI315}, /* TW: FSTN */ |
| 416 | {"320x480x16", 0x5B, 0x0000, 0x0000, 320, 480, 16, 1, 40, 30, MD_XGI315}, /* TW: FSTN */ |
| 417 | {"640x480x8", 0x2E, 0x0101, 0x0101, 640, 480, 8, 1, 80, 30, MD_XGI300|MD_XGI315}, |
| 418 | {"640x480x16", 0x44, 0x0111, 0x0111, 640, 480, 16, 1, 80, 30, MD_XGI300|MD_XGI315}, |
| 419 | {"640x480x24", 0x62, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30, MD_XGI300|MD_XGI315}, /* TW: That's for people who mix up color- and fb depth */ |
| 420 | {"640x480x32", 0x62, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30, MD_XGI300|MD_XGI315}, |
| 421 | {"720x480x8", 0x31, 0x0000, 0x0000, 720, 480, 8, 1, 90, 30, MD_XGI300|MD_XGI315}, |
| 422 | {"720x480x16", 0x33, 0x0000, 0x0000, 720, 480, 16, 1, 90, 30, MD_XGI300|MD_XGI315}, |
| 423 | {"720x480x24", 0x35, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30, MD_XGI300|MD_XGI315}, |
| 424 | {"720x480x32", 0x35, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30, MD_XGI300|MD_XGI315}, |
| 425 | {"720x576x8", 0x32, 0x0000, 0x0000, 720, 576, 8, 1, 90, 36, MD_XGI300|MD_XGI315}, |
| 426 | {"720x576x16", 0x34, 0x0000, 0x0000, 720, 576, 16, 1, 90, 36, MD_XGI300|MD_XGI315}, |
| 427 | {"720x576x24", 0x36, 0x0000, 0x0000, 720, 576, 32, 1, 90, 36, MD_XGI300|MD_XGI315}, |
| 428 | {"720x576x32", 0x36, 0x0000, 0x0000, 720, 576, 32, 1, 90, 36, MD_XGI300|MD_XGI315}, |
| 429 | {"800x480x8", 0x70, 0x0000, 0x0000, 800, 480, 8, 1, 100, 30, MD_XGI300|MD_XGI315}, |
| 430 | {"800x480x16", 0x7a, 0x0000, 0x0000, 800, 480, 16, 1, 100, 30, MD_XGI300|MD_XGI315}, |
| 431 | {"800x480x24", 0x76, 0x0000, 0x0000, 800, 480, 32, 1, 100, 30, MD_XGI300|MD_XGI315}, |
| 432 | {"800x480x32", 0x76, 0x0000, 0x0000, 800, 480, 32, 1, 100, 30, MD_XGI300|MD_XGI315}, |
| 433 | #define DEFAULT_MODE 21 /* TW: index for 800x600x8 */ |
| 434 | #define DEFAULT_LCDMODE 21 /* TW: index for 800x600x8 */ |
| 435 | #define DEFAULT_TVMODE 21 /* TW: index for 800x600x8 */ |
| 436 | {"800x600x8", 0x30, 0x0103, 0x0103, 800, 600, 8, 1, 100, 37, MD_XGI300|MD_XGI315}, |
| 437 | {"800x600x16", 0x47, 0x0114, 0x0114, 800, 600, 16, 1, 100, 37, MD_XGI300|MD_XGI315}, |
| 438 | {"800x600x24", 0x63, 0x013b, 0x0115, 800, 600, 32, 1, 100, 37, MD_XGI300|MD_XGI315}, |
| 439 | {"800x600x32", 0x63, 0x013b, 0x0115, 800, 600, 32, 1, 100, 37, MD_XGI300|MD_XGI315}, |
| 440 | {"1024x576x8", 0x71, 0x0000, 0x0000, 1024, 576, 8, 1, 128, 36, MD_XGI300|MD_XGI315}, |
| 441 | {"1024x576x16", 0x74, 0x0000, 0x0000, 1024, 576, 16, 1, 128, 36, MD_XGI300|MD_XGI315}, |
| 442 | {"1024x576x24", 0x77, 0x0000, 0x0000, 1024, 576, 32, 1, 128, 36, MD_XGI300|MD_XGI315}, |
| 443 | {"1024x576x32", 0x77, 0x0000, 0x0000, 1024, 576, 32, 1, 128, 36, MD_XGI300|MD_XGI315}, |
| 444 | {"1024x600x8", 0x20, 0x0000, 0x0000, 1024, 600, 8, 1, 128, 37, MD_XGI300 }, /* TW: 300 series only */ |
| 445 | {"1024x600x16", 0x21, 0x0000, 0x0000, 1024, 600, 16, 1, 128, 37, MD_XGI300 }, |
| 446 | {"1024x600x24", 0x22, 0x0000, 0x0000, 1024, 600, 32, 1, 128, 37, MD_XGI300 }, |
| 447 | {"1024x600x32", 0x22, 0x0000, 0x0000, 1024, 600, 32, 1, 128, 37, MD_XGI300 }, |
| 448 | {"1024x768x8", 0x38, 0x0105, 0x0105, 1024, 768, 8, 1, 128, 48, MD_XGI300|MD_XGI315}, |
| 449 | {"1024x768x16", 0x4A, 0x0117, 0x0117, 1024, 768, 16, 1, 128, 48, MD_XGI300|MD_XGI315}, |
| 450 | {"1024x768x24", 0x64, 0x013c, 0x0118, 1024, 768, 32, 1, 128, 48, MD_XGI300|MD_XGI315}, |
| 451 | {"1024x768x32", 0x64, 0x013c, 0x0118, 1024, 768, 32, 1, 128, 48, MD_XGI300|MD_XGI315}, |
| 452 | {"1152x768x8", 0x23, 0x0000, 0x0000, 1152, 768, 8, 1, 144, 48, MD_XGI300 }, /* TW: 300 series only */ |
| 453 | {"1152x768x16", 0x24, 0x0000, 0x0000, 1152, 768, 16, 1, 144, 48, MD_XGI300 }, |
| 454 | {"1152x768x24", 0x25, 0x0000, 0x0000, 1152, 768, 32, 1, 144, 48, MD_XGI300 }, |
| 455 | {"1152x768x32", 0x25, 0x0000, 0x0000, 1152, 768, 32, 1, 144, 48, MD_XGI300 }, |
| 456 | {"1280x720x8", 0x79, 0x0000, 0x0000, 1280, 720, 8, 1, 160, 45, MD_XGI300|MD_XGI315}, |
| 457 | {"1280x720x16", 0x75, 0x0000, 0x0000, 1280, 720, 16, 1, 160, 45, MD_XGI300|MD_XGI315}, |
| 458 | {"1280x720x24", 0x78, 0x0000, 0x0000, 1280, 720, 32, 1, 160, 45, MD_XGI300|MD_XGI315}, |
| 459 | {"1280x720x32", 0x78, 0x0000, 0x0000, 1280, 720, 32, 1, 160, 45, MD_XGI300|MD_XGI315}, |
| 460 | {"1280x768x8", 0x23, 0x0000, 0x0000, 1280, 768, 8, 1, 160, 48, MD_XGI315}, /* TW: 310/325 series only */ |
| 461 | {"1280x768x16", 0x24, 0x0000, 0x0000, 1280, 768, 16, 1, 160, 48, MD_XGI315}, |
| 462 | {"1280x768x24", 0x25, 0x0000, 0x0000, 1280, 768, 32, 1, 160, 48, MD_XGI315}, |
| 463 | {"1280x768x32", 0x25, 0x0000, 0x0000, 1280, 768, 32, 1, 160, 48, MD_XGI315}, |
| 464 | #define MODEINDEX_1280x960 48 |
| 465 | {"1280x960x8", 0x7C, 0x0000, 0x0000, 1280, 960, 8, 1, 160, 60, MD_XGI300|MD_XGI315}, /* TW: Modenumbers being patched */ |
| 466 | {"1280x960x16", 0x7D, 0x0000, 0x0000, 1280, 960, 16, 1, 160, 60, MD_XGI300|MD_XGI315}, |
| 467 | {"1280x960x24", 0x7E, 0x0000, 0x0000, 1280, 960, 32, 1, 160, 60, MD_XGI300|MD_XGI315}, |
| 468 | {"1280x960x32", 0x7E, 0x0000, 0x0000, 1280, 960, 32, 1, 160, 60, MD_XGI300|MD_XGI315}, |
| 469 | {"1280x1024x8", 0x3A, 0x0107, 0x0107, 1280, 1024, 8, 1, 160, 64, MD_XGI300|MD_XGI315}, |
| 470 | {"1280x1024x16", 0x4D, 0x011a, 0x011a, 1280, 1024, 16, 1, 160, 64, MD_XGI300|MD_XGI315}, |
| 471 | {"1280x1024x24", 0x65, 0x013d, 0x011b, 1280, 1024, 32, 1, 160, 64, MD_XGI300|MD_XGI315}, |
| 472 | {"1280x1024x32", 0x65, 0x013d, 0x011b, 1280, 1024, 32, 1, 160, 64, MD_XGI300|MD_XGI315}, |
| 473 | {"1400x1050x8", 0x26, 0x0000, 0x0000, 1400, 1050, 8, 1, 175, 65, MD_XGI315}, /* TW: 310/325 series only */ |
| 474 | {"1400x1050x16", 0x27, 0x0000, 0x0000, 1400, 1050, 16, 1, 175, 65, MD_XGI315}, |
| 475 | {"1400x1050x24", 0x28, 0x0000, 0x0000, 1400, 1050, 32, 1, 175, 65, MD_XGI315}, |
| 476 | {"1400x1050x32", 0x28, 0x0000, 0x0000, 1400, 1050, 32, 1, 175, 65, MD_XGI315}, |
| 477 | {"1600x1200x8", 0x3C, 0x0130, 0x011c, 1600, 1200, 8, 1, 200, 75, MD_XGI300|MD_XGI315}, |
| 478 | {"1600x1200x16", 0x3D, 0x0131, 0x011e, 1600, 1200, 16, 1, 200, 75, MD_XGI300|MD_XGI315}, |
| 479 | {"1600x1200x24", 0x66, 0x013e, 0x011f, 1600, 1200, 32, 1, 200, 75, MD_XGI300|MD_XGI315}, |
| 480 | {"1600x1200x32", 0x66, 0x013e, 0x011f, 1600, 1200, 32, 1, 200, 75, MD_XGI300|MD_XGI315}, |
| 481 | {"1920x1440x8", 0x68, 0x013f, 0x0000, 1920, 1440, 8, 1, 240, 75, MD_XGI300|MD_XGI315}, |
| 482 | {"1920x1440x16", 0x69, 0x0140, 0x0000, 1920, 1440, 16, 1, 240, 75, MD_XGI300|MD_XGI315}, |
| 483 | {"1920x1440x24", 0x6B, 0x0141, 0x0000, 1920, 1440, 32, 1, 240, 75, MD_XGI300|MD_XGI315}, |
| 484 | {"1920x1440x32", 0x6B, 0x0141, 0x0000, 1920, 1440, 32, 1, 240, 75, MD_XGI300|MD_XGI315}, |
| 485 | {"2048x1536x8", 0x6c, 0x0000, 0x0000, 2048, 1536, 8, 1, 256, 96, MD_XGI315}, /* TW: 310/325 series only */ |
| 486 | {"2048x1536x16", 0x6d, 0x0000, 0x0000, 2048, 1536, 16, 1, 256, 96, MD_XGI315}, |
| 487 | {"2048x1536x24", 0x6e, 0x0000, 0x0000, 2048, 1536, 32, 1, 256, 96, MD_XGI315}, |
| 488 | {"2048x1536x32", 0x6e, 0x0000, 0x0000, 2048, 1536, 32, 1, 256, 96, MD_XGI315}, |
| 489 | {"\0", 0x00, 0, 0, 0, 0, 0, 0, 0} |
| 490 | }; |
| 491 | |
| 492 | /* mode-related variables */ |
| 493 | #ifdef MODULE |
| d7636e0b |
494 | static int xgifb_mode_idx = 1; |
| 495 | #else |
| d7636e0b |
496 | static int xgifb_mode_idx = -1; /* Use a default mode if we are inside the kernel */ |
| d7636e0b |
497 | #endif |
| 498 | u8 XGIfb_mode_no = 0; |
| 499 | u8 XGIfb_rate_idx = 0; |
| 500 | |
| 501 | /* TW: CR36 evaluation */ |
| 502 | const USHORT XGI300paneltype[] = |
| 503 | { LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024, |
| 504 | LCD_1280x960, LCD_640x480, LCD_1024x600, LCD_1152x768, |
| 505 | LCD_1024x768, LCD_1024x768, LCD_1024x768, |
| 506 | LCD_1024x768, LCD_1024x768, LCD_1024x768, LCD_1024x768 }; |
| 507 | |
| 508 | const USHORT XGI310paneltype[] = |
| 509 | { LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024, |
| 510 | LCD_640x480, LCD_1024x600, LCD_1152x864, LCD_1280x960, |
| 511 | LCD_1152x768, LCD_1400x1050,LCD_1280x768, LCD_1600x1200, |
| 512 | LCD_1024x768, LCD_1024x768, LCD_1024x768 }; |
| 513 | |
| 514 | static const struct _XGI_crt2type { |
| 515 | char name[10]; |
| 516 | int type_no; |
| 517 | int tvplug_no; |
| 518 | } XGI_crt2type[] = { |
| 519 | {"NONE", 0, -1}, |
| 520 | {"LCD", DISPTYPE_LCD, -1}, |
| 521 | {"TV", DISPTYPE_TV, -1}, |
| 522 | {"VGA", DISPTYPE_CRT2, -1}, |
| 523 | {"SVIDEO", DISPTYPE_TV, TVPLUG_SVIDEO}, |
| 524 | {"COMPOSITE", DISPTYPE_TV, TVPLUG_COMPOSITE}, |
| 525 | {"SCART", DISPTYPE_TV, TVPLUG_SCART}, |
| 526 | {"none", 0, -1}, |
| 527 | {"lcd", DISPTYPE_LCD, -1}, |
| 528 | {"tv", DISPTYPE_TV, -1}, |
| 529 | {"vga", DISPTYPE_CRT2, -1}, |
| 530 | {"svideo", DISPTYPE_TV, TVPLUG_SVIDEO}, |
| 531 | {"composite", DISPTYPE_TV, TVPLUG_COMPOSITE}, |
| 532 | {"scart", DISPTYPE_TV, TVPLUG_SCART}, |
| 533 | {"\0", -1, -1} |
| 534 | }; |
| 535 | |
| 536 | /* Queue mode selection for 310 series */ |
| 537 | static const struct _XGI_queuemode { |
| 538 | char name[6]; |
| 539 | int type_no; |
| 540 | } XGI_queuemode[] = { |
| 541 | {"AGP", AGP_CMD_QUEUE}, |
| 542 | {"VRAM", VM_CMD_QUEUE}, |
| 543 | {"MMIO", MMIO_CMD}, |
| 544 | {"agp", AGP_CMD_QUEUE}, |
| 545 | {"vram", VM_CMD_QUEUE}, |
| 546 | {"mmio", MMIO_CMD}, |
| 547 | {"\0", -1} |
| 548 | }; |
| 549 | |
| 550 | /* TV standard */ |
| 551 | static const struct _XGI_tvtype { |
| 552 | char name[6]; |
| 553 | int type_no; |
| 554 | } XGI_tvtype[] = { |
| 555 | {"PAL", 1}, |
| 556 | {"NTSC", 2}, |
| 557 | {"pal", 1}, |
| 558 | {"ntsc", 2}, |
| 559 | {"\0", -1} |
| 560 | }; |
| 561 | |
| 562 | static const struct _XGI_vrate { |
| 563 | u16 idx; |
| 564 | u16 xres; |
| 565 | u16 yres; |
| 566 | u16 refresh; |
| 567 | } XGIfb_vrate[] = { |
| 568 | {1, 640, 480, 60}, {2, 640, 480, 72}, {3, 640, 480, 75}, {4, 640, 480, 85}, |
| 569 | {5, 640, 480,100}, {6, 640, 480, 120}, {7, 640, 480, 160}, {8, 640, 480, 200}, |
| 570 | {1, 720, 480, 60}, |
| 571 | {1, 720, 576, 58}, |
| 572 | {1, 800, 480, 60}, {2, 800, 480, 75}, {3, 800, 480, 85}, |
| 573 | {1, 800, 600, 60}, {2, 800, 600, 72}, {3, 800, 600, 75}, |
| 574 | {4, 800, 600, 85}, {5, 800, 600, 100}, {6, 800, 600, 120}, {7, 800, 600, 160}, |
| 575 | {1, 1024, 768, 60}, {2, 1024, 768, 70}, {3, 1024, 768, 75}, |
| 576 | {4, 1024, 768, 85}, {5, 1024, 768, 100}, {6, 1024, 768, 120}, |
| 577 | {1, 1024, 576, 60}, {2, 1024, 576, 75}, {3, 1024, 576, 85}, |
| 578 | {1, 1024, 600, 60}, |
| 579 | {1, 1152, 768, 60}, |
| 580 | {1, 1280, 720, 60}, {2, 1280, 720, 75}, {3, 1280, 720, 85}, |
| 581 | {1, 1280, 768, 60}, |
| 582 | {1, 1280, 1024, 60}, {2, 1280, 1024, 75}, {3, 1280, 1024, 85}, |
| 583 | {1, 1280, 960, 70}, |
| 584 | {1, 1400, 1050, 60}, |
| 585 | {1, 1600, 1200, 60}, {2, 1600, 1200, 65}, {3, 1600, 1200, 70}, {4, 1600, 1200, 75}, |
| 586 | {5, 1600, 1200, 85}, {6, 1600, 1200, 100}, {7, 1600, 1200, 120}, |
| 587 | {1, 1920, 1440, 60}, {2, 1920, 1440, 65}, {3, 1920, 1440, 70}, {4, 1920, 1440, 75}, |
| 588 | {5, 1920, 1440, 85}, {6, 1920, 1440, 100}, |
| 589 | {1, 2048, 1536, 60}, {2, 2048, 1536, 65}, {3, 2048, 1536, 70}, {4, 2048, 1536, 75}, |
| 590 | {5, 2048, 1536, 85}, |
| 591 | {0, 0, 0, 0} |
| 592 | }; |
| 593 | |
| 594 | static const struct _chswtable { |
| 595 | int subsysVendor; |
| 596 | int subsysCard; |
| 597 | char *vendorName; |
| 598 | char *cardName; |
| 599 | } mychswtable[] = { |
| 600 | { 0x1631, 0x1002, "Mitachi", "0x1002" }, |
| 601 | { 0, 0, "" , "" } |
| 602 | }; |
| 603 | |
| d7636e0b |
604 | typedef struct _XGI_OH { |
| 605 | struct _XGI_OH *poh_next; |
| 606 | struct _XGI_OH *poh_prev; |
| 607 | unsigned long offset; |
| 608 | unsigned long size; |
| 609 | } XGI_OH; |
| 610 | |
| 611 | typedef struct _XGI_OHALLOC { |
| 612 | struct _XGI_OHALLOC *poha_next; |
| 613 | XGI_OH aoh[1]; |
| 614 | } XGI_OHALLOC; |
| 615 | |
| 616 | typedef struct _XGI_HEAP { |
| 617 | XGI_OH oh_free; |
| 618 | XGI_OH oh_used; |
| 619 | XGI_OH *poh_freelist; |
| 620 | XGI_OHALLOC *poha_chain; |
| 621 | unsigned long max_freesize; |
| 622 | } XGI_HEAP; |
| 623 | |
| 624 | static unsigned long XGIfb_hwcursor_vbase; |
| 625 | |
| 626 | static unsigned long XGIfb_heap_start; |
| 627 | static unsigned long XGIfb_heap_end; |
| 628 | static unsigned long XGIfb_heap_size; |
| 629 | static XGI_HEAP XGIfb_heap; |
| 630 | |
| 631 | // Eden Chen |
| 632 | static const struct _XGI_TV_filter { |
| 633 | u8 filter[9][4]; |
| 634 | } XGI_TV_filter[] = { |
| 635 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_0 */ |
| 636 | {0x00,0xE0,0x10,0x60}, |
| 637 | {0x00,0xEE,0x10,0x44}, |
| 638 | {0x00,0xF4,0x10,0x38}, |
| 639 | {0xF8,0xF4,0x18,0x38}, |
| 640 | {0xFC,0xFB,0x14,0x2A}, |
| 641 | {0x00,0x00,0x10,0x20}, |
| 642 | {0x00,0x04,0x10,0x18}, |
| 643 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 644 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_1 */ |
| 645 | {0x00,0xE0,0x10,0x60}, |
| 646 | {0x00,0xEE,0x10,0x44}, |
| 647 | {0x00,0xF4,0x10,0x38}, |
| 648 | {0xF8,0xF4,0x18,0x38}, |
| 649 | {0xFC,0xFB,0x14,0x2A}, |
| 650 | {0x00,0x00,0x10,0x20}, |
| 651 | {0x00,0x04,0x10,0x18}, |
| 652 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 653 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_2 */ |
| 654 | {0xF5,0xEE,0x1B,0x44}, |
| 655 | {0xF8,0xF4,0x18,0x38}, |
| 656 | {0xEB,0x04,0x25,0x18}, |
| 657 | {0xF1,0x05,0x1F,0x16}, |
| 658 | {0xF6,0x06,0x1A,0x14}, |
| 659 | {0xFA,0x06,0x16,0x14}, |
| 660 | {0x00,0x04,0x10,0x18}, |
| 661 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 662 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_3 */ |
| 663 | {0xF1,0x04,0x1F,0x18}, |
| 664 | {0xEE,0x0D,0x22,0x06}, |
| 665 | {0xF7,0x06,0x19,0x14}, |
| 666 | {0xF4,0x0B,0x1C,0x0A}, |
| 667 | {0xFA,0x07,0x16,0x12}, |
| 668 | {0xF9,0x0A,0x17,0x0C}, |
| 669 | {0x00,0x07,0x10,0x12}, |
| 670 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 671 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_4 */ |
| 672 | {0x00,0xE0,0x10,0x60}, |
| 673 | {0x00,0xEE,0x10,0x44}, |
| 674 | {0x00,0xF4,0x10,0x38}, |
| 675 | {0xF8,0xF4,0x18,0x38}, |
| 676 | {0xFC,0xFB,0x14,0x2A}, |
| 677 | {0x00,0x00,0x10,0x20}, |
| 678 | {0x00,0x04,0x10,0x18}, |
| 679 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 680 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_5 */ |
| 681 | {0xF5,0xEE,0x1B,0x44}, |
| 682 | {0xF8,0xF4,0x18,0x38}, |
| 683 | {0xEB,0x04,0x25,0x18}, |
| 684 | {0xF1,0x05,0x1F,0x16}, |
| 685 | {0xF6,0x06,0x1A,0x14}, |
| 686 | {0xFA,0x06,0x16,0x14}, |
| 687 | {0x00,0x04,0x10,0x18}, |
| 688 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 689 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_6 */ |
| 690 | {0xEB,0x04,0x25,0x18}, |
| 691 | {0xE7,0x0E,0x29,0x04}, |
| 692 | {0xEE,0x0C,0x22,0x08}, |
| 693 | {0xF6,0x0B,0x1A,0x0A}, |
| 694 | {0xF9,0x0A,0x17,0x0C}, |
| 695 | {0xFC,0x0A,0x14,0x0C}, |
| 696 | {0x00,0x08,0x10,0x10}, |
| 697 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 698 | { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_7 */ |
| 699 | {0xEC,0x02,0x24,0x1C}, |
| 700 | {0xF2,0x04,0x1E,0x18}, |
| 701 | {0xEB,0x15,0x25,0xF6}, |
| 702 | {0xF4,0x10,0x1C,0x00}, |
| 703 | {0xF8,0x0F,0x18,0x02}, |
| 704 | {0x00,0x04,0x10,0x18}, |
| 705 | {0x01,0x06,0x0F,0x14}, |
| 706 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 707 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_0 */ |
| 708 | {0x00,0xE0,0x10,0x60}, |
| 709 | {0x00,0xEE,0x10,0x44}, |
| 710 | {0x00,0xF4,0x10,0x38}, |
| 711 | {0xF8,0xF4,0x18,0x38}, |
| 712 | {0xFC,0xFB,0x14,0x2A}, |
| 713 | {0x00,0x00,0x10,0x20}, |
| 714 | {0x00,0x04,0x10,0x18}, |
| 715 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 716 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_1 */ |
| 717 | {0x00,0xE0,0x10,0x60}, |
| 718 | {0x00,0xEE,0x10,0x44}, |
| 719 | {0x00,0xF4,0x10,0x38}, |
| 720 | {0xF8,0xF4,0x18,0x38}, |
| 721 | {0xFC,0xFB,0x14,0x2A}, |
| 722 | {0x00,0x00,0x10,0x20}, |
| 723 | {0x00,0x04,0x10,0x18}, |
| 724 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 725 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_2 */ |
| 726 | {0xF5,0xEE,0x1B,0x44}, |
| 727 | {0xF8,0xF4,0x18,0x38}, |
| 728 | {0xF1,0xF7,0x01,0x32}, |
| 729 | {0xF5,0xFB,0x1B,0x2A}, |
| 730 | {0xF9,0xFF,0x17,0x22}, |
| 731 | {0xFB,0x01,0x15,0x1E}, |
| 732 | {0x00,0x04,0x10,0x18}, |
| 733 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 734 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_3 */ |
| 735 | {0xF5,0xFB,0x1B,0x2A}, |
| 736 | {0xEE,0xFE,0x22,0x24}, |
| 737 | {0xF3,0x00,0x1D,0x20}, |
| 738 | {0xF9,0x03,0x17,0x1A}, |
| 739 | {0xFB,0x02,0x14,0x1E}, |
| 740 | {0xFB,0x04,0x15,0x18}, |
| 741 | {0x00,0x06,0x10,0x14}, |
| 742 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 743 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_4 */ |
| 744 | {0x00,0xE0,0x10,0x60}, |
| 745 | {0x00,0xEE,0x10,0x44}, |
| 746 | {0x00,0xF4,0x10,0x38}, |
| 747 | {0xF8,0xF4,0x18,0x38}, |
| 748 | {0xFC,0xFB,0x14,0x2A}, |
| 749 | {0x00,0x00,0x10,0x20}, |
| 750 | {0x00,0x04,0x10,0x18}, |
| 751 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 752 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_5 */ |
| 753 | {0xF5,0xEE,0x1B,0x44}, |
| 754 | {0xF8,0xF4,0x18,0x38}, |
| 755 | {0xF1,0xF7,0x1F,0x32}, |
| 756 | {0xF5,0xFB,0x1B,0x2A}, |
| 757 | {0xF9,0xFF,0x17,0x22}, |
| 758 | {0xFB,0x01,0x15,0x1E}, |
| 759 | {0x00,0x04,0x10,0x18}, |
| 760 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 761 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_6 */ |
| 762 | {0xF5,0xEE,0x1B,0x2A}, |
| 763 | {0xEE,0xFE,0x22,0x24}, |
| 764 | {0xF3,0x00,0x1D,0x20}, |
| 765 | {0xF9,0x03,0x17,0x1A}, |
| 766 | {0xFB,0x02,0x14,0x1E}, |
| 767 | {0xFB,0x04,0x15,0x18}, |
| 768 | {0x00,0x06,0x10,0x14}, |
| 769 | {0xFF,0xFF,0xFF,0xFF} }}, |
| 770 | { {{0x00,0x00,0x00,0x40}, /* PALFilter_7 */ |
| 771 | {0xF5,0xEE,0x1B,0x44}, |
| 772 | {0xF8,0xF4,0x18,0x38}, |
| 773 | {0xFC,0xFB,0x14,0x2A}, |
| 774 | {0xEB,0x05,0x25,0x16}, |
| 775 | {0xF1,0x05,0x1F,0x16}, |
| 776 | {0xFA,0x07,0x16,0x12}, |
| 777 | {0x00,0x07,0x10,0x12}, |
| 778 | {0xFF,0xFF,0xFF,0xFF} }} |
| 779 | }; |
| 780 | |
| 781 | static int filter = -1; |
| 782 | static unsigned char filter_tb; |
| 783 | |
| 784 | |
| 785 | /* ---------------------- Routine prototypes ------------------------- */ |
| 786 | |
| 787 | /* Interface used by the world */ |
| 788 | #ifndef MODULE |
| 789 | XGIINITSTATIC int __init XGIfb_setup(char *options); |
| 790 | #endif |
| 791 | |
| 792 | /* Interface to the low level console driver */ |
| 793 | |
| 794 | |
| 795 | |
| 796 | /* fbdev routines */ |
| d7636e0b |
797 | XGIINITSTATIC int __init xgifb_init(void); |
| 798 | static int XGIfb_set_par(struct fb_info *info); |
| 799 | static int XGIfb_blank(int blank, |
| 800 | struct fb_info *info); |
| 801 | /*static int XGIfb_mmap(struct fb_info *info, struct file *file, |
| 802 | struct vm_area_struct *vma); |
| 803 | */ |
| 804 | extern void fbcon_XGI_fillrect(struct fb_info *info, |
| 805 | const struct fb_fillrect *rect); |
| 806 | extern void fbcon_XGI_copyarea(struct fb_info *info, |
| 807 | const struct fb_copyarea *area); |
| d7636e0b |
808 | extern int fbcon_XGI_sync(struct fb_info *info); |
| 809 | |
| d7636e0b |
810 | static int XGIfb_ioctl(struct fb_info *info, unsigned int cmd, |
| 811 | unsigned long arg); |
| d7636e0b |
812 | |
| 813 | /* |
| 814 | extern int XGIfb_mode_rate_to_dclock(VB_DEVICE_INFO *XGI_Pr, |
| 815 | PXGI_HW_DEVICE_INFO HwDeviceExtension, |
| 816 | unsigned char modeno, unsigned char rateindex); |
| 817 | extern int XGIfb_mode_rate_to_ddata(VB_DEVICE_INFO *XGI_Pr, PXGI_HW_DEVICE_INFO HwDeviceExtension, |
| 818 | unsigned char modeno, unsigned char rateindex, |
| 819 | unsigned int *left_margin, unsigned int *right_margin, |
| 820 | unsigned int *upper_margin, unsigned int *lower_margin, |
| 821 | unsigned int *hsync_len, unsigned int *vsync_len, |
| 822 | unsigned int *sync, unsigned int *vmode); |
| 823 | */ |
| d7636e0b |
824 | extern BOOLEAN XGI_SearchModeID( USHORT ModeNo,USHORT *ModeIdIndex, PVB_DEVICE_INFO ); |
| 825 | static int XGIfb_get_fix(struct fb_fix_screeninfo *fix, int con, |
| 826 | struct fb_info *info); |
| 827 | |
| 828 | /* Internal 2D accelerator functions */ |
| 829 | extern int XGIfb_initaccel(void); |
| 830 | extern void XGIfb_syncaccel(void); |
| 831 | |
| 832 | /* Internal general routines */ |
| 833 | static void XGIfb_search_mode(const char *name); |
| 834 | static int XGIfb_validate_mode(int modeindex); |
| 835 | static u8 XGIfb_search_refresh_rate(unsigned int rate); |
| 836 | static int XGIfb_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 837 | unsigned blue, unsigned transp, |
| 838 | struct fb_info *fb_info); |
| 839 | static int XGIfb_do_set_var(struct fb_var_screeninfo *var, int isactive, |
| 840 | struct fb_info *info); |
| 841 | static void XGIfb_pre_setmode(void); |
| 842 | static void XGIfb_post_setmode(void); |
| 843 | |
| 844 | static BOOLEAN XGIfb_CheckVBRetrace(void); |
| 845 | static BOOLEAN XGIfbcheckvretracecrt2(void); |
| 846 | static BOOLEAN XGIfbcheckvretracecrt1(void); |
| 847 | static BOOLEAN XGIfb_bridgeisslave(void); |
| 848 | |
| 849 | struct XGI_memreq { |
| 850 | unsigned long offset; |
| 851 | unsigned long size; |
| 852 | }; |
| 853 | |
| 854 | /* XGI-specific Export functions */ |
| 855 | void XGI_dispinfo(struct ap_data *rec); |
| 856 | void XGI_malloc(struct XGI_memreq *req); |
| 857 | void XGI_free(unsigned long base); |
| 858 | |
| 859 | /* Internal hardware access routines */ |
| 860 | void XGIfb_set_reg4(u16 port, unsigned long data); |
| 861 | u32 XGIfb_get_reg3(u16 port); |
| 862 | |
| 863 | /* Chipset-dependent internal routines */ |
| 864 | |
| 865 | |
| 866 | static int XGIfb_get_dram_size(void); |
| 867 | static void XGIfb_detect_VB(void); |
| 868 | static void XGIfb_get_VB_type(void); |
| 869 | static int XGIfb_has_VB(void); |
| 870 | |
| 871 | |
| 872 | /* Internal heap routines */ |
| 873 | static int XGIfb_heap_init(void); |
| 874 | static XGI_OH *XGIfb_poh_new_node(void); |
| 875 | static XGI_OH *XGIfb_poh_allocate(unsigned long size); |
| 876 | static void XGIfb_delete_node(XGI_OH *poh); |
| 877 | static void XGIfb_insert_node(XGI_OH *pohList, XGI_OH *poh); |
| 878 | static XGI_OH *XGIfb_poh_free(unsigned long base); |
| 879 | static void XGIfb_free_node(XGI_OH *poh); |
| 880 | |
| 881 | /* Internal routines to access PCI configuration space */ |
| 882 | BOOLEAN XGIfb_query_VGA_config_space(PXGI_HW_DEVICE_INFO pXGIhw_ext, |
| 883 | unsigned long offset, unsigned long set, unsigned long *value); |
| 884 | //BOOLEAN XGIfb_query_north_bridge_space(PXGI_HW_DEVICE_INFO pXGIhw_ext, |
| 885 | // unsigned long offset, unsigned long set, unsigned long *value); |
| 886 | |
| 887 | |
| 888 | /* Routines from init.c/init301.c */ |
| 889 | extern void InitTo330Pointer(UCHAR,PVB_DEVICE_INFO pVBInfo); |
| 890 | extern BOOLEAN XGIInitNew(PXGI_HW_DEVICE_INFO HwDeviceExtension); |
| 891 | extern BOOLEAN XGISetModeNew(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT ModeNo); |
| 892 | //extern void XGI_SetEnableDstn(VB_DEVICE_INFO *XGI_Pr); |
| 893 | extern void XGI_LongWait(VB_DEVICE_INFO *XGI_Pr); |
| 894 | extern USHORT XGI_GetRatePtrCRT2( PXGI_HW_DEVICE_INFO pXGIHWDE, USHORT ModeNo,USHORT ModeIdIndex,PVB_DEVICE_INFO pVBInfo ); |
| 895 | /* TW: Chrontel TV functions */ |
| 896 | extern USHORT XGI_GetCH700x(VB_DEVICE_INFO *XGI_Pr, USHORT tempbx); |
| 897 | extern void XGI_SetCH700x(VB_DEVICE_INFO *XGI_Pr, USHORT tempbx); |
| 898 | extern USHORT XGI_GetCH701x(VB_DEVICE_INFO *XGI_Pr, USHORT tempbx); |
| 899 | extern void XGI_SetCH701x(VB_DEVICE_INFO *XGI_Pr, USHORT tempbx); |
| 900 | extern void XGI_SetCH70xxANDOR(VB_DEVICE_INFO *XGI_Pr, USHORT tempax,USHORT tempbh); |
| 901 | extern void XGI_DDC2Delay(VB_DEVICE_INFO *XGI_Pr, USHORT delaytime); |
| 902 | |
| 903 | /* TW: Sensing routines */ |
| 904 | void XGI_Sense30x(void); |
| 905 | int XGIDoSense(int tempbl, int tempbh, int tempcl, int tempch); |
| 906 | |
| 907 | extern XGI21_LVDSCapStruct XGI21_LCDCapList[13]; |
| 908 | #endif |
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