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Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6
[net-next-2.6.git] / drivers / staging / tm6000 / tm6000-core.c
CommitLineData
9701dc94 1/*
e28f49b0 2 tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
9701dc94
MCC		 3
4 Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
5
3169c9b2
ML		 6 Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
7 - DVB-T support
8
9701dc94
MCC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation version 2
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
4ef09889 25#include <linux/slab.h>
9701dc94
MCC		 26#include <linux/usb.h>
27#include <linux/i2c.h>
9701dc94
MCC		 28#include "tm6000.h"
29#include "tm6000-regs.h"
30#include <media/v4l2-common.h>
31#include <media/tuner.h>
32
9701dc94
MCC		 33#define USB_TIMEOUT 5*HZ /* ms */
34
35int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
36 u16 value, u16 index, u8 *buf, u16 len)
37{
38 int ret, i;
39 unsigned int pipe;
40 static int ini=0, last=0, n=0;
41 u8 *data=NULL;
42
43 if (len)
44 data = kzalloc(len, GFP_KERNEL);
45
46
47 if (req_type & USB_DIR_IN)
48 pipe=usb_rcvctrlpipe(dev->udev, 0);
49 else {
50 pipe=usb_sndctrlpipe(dev->udev, 0);
51 memcpy(data, buf, len);
52 }
53
edecce0a 54 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94
MCC		 55 if (!ini)
56 last=ini=jiffies;
57
58 printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
59
60 printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
61 (req_type & USB_DIR_IN)?" IN":"OUT",
62 jiffies_to_msecs(jiffies-last),
63 jiffies_to_msecs(jiffies-ini),
64 req_type, req,value&0xff,value>>8, index&0xff, index>>8,
65 len&0xff, len>>8);
66 last=jiffies;
67 n++;
68
69 if ( !(req_type & USB_DIR_IN) ) {
70 printk(">>> ");
71 for (i=0;i<len;i++) {
72 printk(" %02x",buf[i]);
73 }
8ae1fc6e 74 printk("\n");
9701dc94
MCC		 75 }
76 }
77
78 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
79 len, USB_TIMEOUT);
80
81 if (req_type & USB_DIR_IN)
82 memcpy(buf, data, len);
83
edecce0a 84 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94
MCC		 85 if (ret<0) {
86 if (req_type & USB_DIR_IN)
87 printk("<<< (len=%d)\n",len);
88
89 printk("%s: Error #%d\n", __FUNCTION__, ret);
90 } else if (req_type & USB_DIR_IN) {
91 printk("<<< ");
92 for (i=0;i<len;i++) {
93 printk(" %02x",buf[i]);
94 }
95 printk("\n");
96 }
97 }
98
99 kfree(data);
100
a5adfbed
ML		 101 msleep(5);
102
9701dc94
MCC		 103 return ret;
104}
105
106int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
107{
108 return
109 tm6000_read_write_usb (dev, USB_DIR_OUT | USB_TYPE_VENDOR,
110 req, value, index, NULL, 0);
111}
29ec15e9 112EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94
MCC		 113
114int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
115{
116 int rc;
117 u8 buf[1];
118
119 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
120 value, index, buf, 1);
121
122 if (rc<0)
123 return rc;
124
125 return *buf;
126}
29ec15e9 127EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94
MCC		 128
129int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
130{
131 int rc;
132 u8 buf[2];
133
134 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
135 value, index, buf, 2);
136
137 if (rc<0)
138 return rc;
139
140 return buf[1]|buf[0]<<8;
141}
142
2f790884
SR		 143int tm6000_get_reg32 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
144{
145 int rc;
146 u8 buf[4];
147
148 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
149 value, index, buf, 4);
150
151 if (rc<0)
152 return rc;
153
154 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
155}
156
2a15ac7a
DB		 157int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
158{
159 int rc;
160
161 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
162 if (rc < 0)
163 return rc;
164
165 msleep(tsleep);
166
167 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
168 msleep(tsleep);
169
170 return rc;
171}
172
9701dc94
MCC		 173void tm6000_set_fourcc_format(struct tm6000_core *dev)
174{
717ecd2b 175 if (dev->dev_type == TM6010) {
42238713
MCC		 176 int val;
177
178 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0) & 0xfc;
717ecd2b 179 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
42238713 180 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
717ecd2b 181 else
42238713 182 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val | 1);
9701dc94 183 } else {
717ecd2b 184 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493 185 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b 186 else
9afec493 187 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94
MCC		 188 }
189}
190
191int tm6000_init_analog_mode (struct tm6000_core *dev)
192{
29c389be
MCC		 193 if (dev->dev_type == TM6010) {
194 int val;
9701dc94 195
29c389be 196 /* Enable video */
9afec493 197 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
29c389be 198 val |= 0x60;
9afec493 199 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
120756e1
SR		 200 val = tm6000_get_reg(dev,
201 TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
202 val &= ~0x40;
203 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
204
205 /* Init teletext */
206 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
207 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
208 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
209 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
210 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
211 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
212 tm6000_set_reg(dev,
213 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
214 tm6000_set_reg(dev,
215 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
216 tm6000_set_reg(dev,
217 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
218 tm6000_set_reg(dev,
219 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
220 tm6000_set_reg(dev,
221 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
222 tm6000_set_reg(dev,
223 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
224 tm6000_set_reg(dev,
225 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
226 tm6000_set_reg(dev,
227 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
228 tm6000_set_reg(dev,
229 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
230 tm6000_set_reg(dev,
231 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
232 tm6000_set_reg(dev,
233 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
234 tm6000_set_reg(dev,
235 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
236 tm6000_set_reg(dev,
237 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
238 tm6000_set_reg(dev,
239 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
240 tm6000_set_reg(dev,
241 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
242 tm6000_set_reg(dev,
243 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
244 tm6000_set_reg(dev,
245 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
246 tm6000_set_reg(dev,
247 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
248 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
249 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
250 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
251 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
252 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
253 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
254
255
256 /* Init audio */
257 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
258 tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04);
259 tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
260 tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0);
261 tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x05);
262 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x06);
263 tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00);
264 tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00);
265 tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08);
266 tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91);
267 tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20);
268 tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12);
269 tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20);
270 tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0);
271 tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80);
272 tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0);
273 tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80);
274 tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12);
275 tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe);
276 tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20);
277 tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14);
278 tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe);
279 tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01);
280 tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0);
281 tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32);
282 tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64);
283 tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20);
284 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00);
285 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00);
286 tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
287 tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
288 tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
289 tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
290 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
291 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
9701dc94 292
9701dc94 293 } else {
29c389be 294 /* Enables soft reset */
9afec493 295 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be
MCC		 296
297 if (dev->scaler) {
9afec493 298 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
29c389be
MCC		 299 } else {
300 /* Enable Hfilter and disable TS Drop err */
9afec493 301 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
29c389be 302 }
9701dc94 303
9afec493
MCC		 304 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
305 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
306 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
307 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
308 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
309 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
9701dc94 310
29c389be 311 /* AP Software reset */
9afec493
MCC		 312 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
313 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94 314
29c389be 315 tm6000_set_fourcc_format(dev);
9701dc94 316
29c389be 317 /* Disables soft reset */
9afec493 318 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
9701dc94 319
29c389be 320 /* E3: Select input 0 - TV tuner */
9afec493 321 tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
29c389be 322 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94 323
29c389be
MCC		 324 /* This controls input */
325 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
326 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
327 }
9701dc94
MCC		 328 msleep(20);
329
29c389be
MCC		 330 /* Tuner firmware can now be loaded */
331
9701dc94
MCC		 332 /*FIXME: Hack!!! */
333 struct v4l2_frequency f;
334 mutex_lock(&dev->lock);
335 f.frequency=dev->freq;
427f7fac 336 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94
MCC		 337 mutex_unlock(&dev->lock);
338
339 msleep(100);
340 tm6000_set_standard (dev, &dev->norm);
341 tm6000_set_audio_bitrate (dev,48000);
342
f36cc034
SR		 343 /* switch dvb led off */
344 if (dev->gpio.dvb_led) {
345 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
346 dev->gpio.dvb_led, 0x01);
347 }
348
9701dc94
MCC		 349 return 0;
350}
351
3169c9b2
ML		 352int tm6000_init_digital_mode (struct tm6000_core *dev)
353{
c733a4d5
SR		 354 if (dev->dev_type == TM6010) {
355 int val;
356 u8 buf[2];
3169c9b2 357
c733a4d5 358 /* digital init */
9afec493 359 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
c733a4d5 360 val &= ~0x60;
9afec493
MCC		 361 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
362 val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
c733a4d5 363 val |= 0x40;
9afec493
MCC		 364 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
365 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
366 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
367 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
368 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
c733a4d5
SR		 369 tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
370 printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
371
372
373 } else {
9afec493
MCC		 374 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
375 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
376 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
377 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
378 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
379 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5 380 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
9afec493
MCC		 381 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
382 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
383 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
384 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
385 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
386 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
387 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
388
389 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
390 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5
SR		 391 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
392 msleep(50);
393
394 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
395 msleep(50);
396 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
397 msleep(50);
398 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
399 msleep(100);
400 }
f36cc034
SR		 401
402 /* switch dvb led on */
403 if (dev->gpio.dvb_led) {
404 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
405 dev->gpio.dvb_led, 0x00);
406 }
407
3169c9b2
ML		 408 return 0;
409}
9701dc94 410
29c389be
MCC		 411struct reg_init {
412 u8 req;
413 u8 reg;
414 u8 val;
415};
416
9701dc94 417/* The meaning of those initializations are unknown */
29c389be 418struct reg_init tm6000_init_tab[] = {
9701dc94 419 /* REG VALUE */
9afec493
MCC		 420 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
421 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
422 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
423 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
424 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
425 { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
426 { TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
427 { TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
428 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
429 { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
29c389be
MCC		 430 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
431 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
9afec493
MCC		 432 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
433 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
434 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
435 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
436 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
437 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
438 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
439 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
440 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
441 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
442 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
443 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
444 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
445 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
446 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
447 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
448 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
449 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
450 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
451 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
452 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
453 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
454 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
455 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
456 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
457 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
458 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
459 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
460 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
461 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
462 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
463 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
464 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
465 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
466 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
467 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
468 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
469 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
470 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
471 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
472 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
473 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
474 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
475 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
476 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
477 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
478 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
479 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
480 { TM6010_REQ07_RC3_HSTART1, 0x88 },
481 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
2415a2c1 482 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be
MCC		 483};
484
485struct reg_init tm6010_init_tab[] = {
9afec493
MCC		 486 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
487 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
488 { TM6010_REQ07_RC6_HEND0, 0x40 },
489 { TM6010_REQ07_RCA_VEND0, 0x31 },
490 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
491 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
492 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
493
494 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
495 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
496 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
497 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
498 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
499 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
500 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
501 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
502 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
503
504 { TM6010_REQ07_R3F_RESET, 0x01 },
505 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
506 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
507 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
508 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
509 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
510 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
511 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
512 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
513 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
514 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
515 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
516 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
517 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
518 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
519 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
520 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
521 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
522 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
523 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
524 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
525 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
526 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
527 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
528 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
529 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
530 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
531 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
532 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
533 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
534 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
535 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
536 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
537 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
538 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
539 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
540 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
541 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
542 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
543 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
544 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
545 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
546 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
547 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
548 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
549 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
550 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
551 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
552 { TM6010_REQ07_RC3_HSTART1, 0x88 },
553 { TM6010_REQ07_R3F_RESET, 0x00 },
29c389be 554
2415a2c1 555 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be 556
9afec493
MCC		 557 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
558 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
559 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
560 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932 561 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493 562 { TM6010_REQ07_RD8_IR, 0x2f },
d46ca932 563
29c389be 564 /* set remote wakeup key:any key wakeup */
9afec493
MCC		 565 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
566 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94
MCC		 567};
568
569int tm6000_init (struct tm6000_core *dev)
570{
29c389be
MCC		 571 int board, rc=0, i, size;
572 struct reg_init *tab;
573
574 if (dev->dev_type == TM6010) {
575 tab = tm6010_init_tab;
576 size = ARRAY_SIZE(tm6010_init_tab);
577 } else {
578 tab = tm6000_init_tab;
579 size = ARRAY_SIZE(tm6000_init_tab);
580 }
9701dc94 581
9701dc94 582 /* Load board's initialization table */
29c389be
MCC		 583 for (i=0; i< size; i++) {
584 rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
9701dc94 585 if (rc<0) {
29c389be
MCC		 586 printk (KERN_ERR "Error %i while setting req %d, "
587 "reg %d to value %d\n", rc,
588 tab[i].req,tab[i].reg, tab[i].val);
9701dc94
MCC		 589 return rc;
590 }
591 }
592
29c389be
MCC		 593 msleep(5); /* Just to be conservative */
594
9701dc94 595 /* Check board version - maybe 10Moons specific */
2f790884 596 board=tm6000_get_reg32 (dev, REQ_40_GET_VERSION, 0, 0);
9701dc94 597 if (board >=0) {
2f790884 598 printk (KERN_INFO "Board version = 0x%08x\n",board);
9701dc94
MCC		 599 } else {
600 printk (KERN_ERR "Error %i while retrieving board version\n",board);
601 }
602
e3ee9e5e 603 rc = tm6000_cards_setup(dev);
a5adfbed 604
e3ee9e5e 605 return rc;
9701dc94
MCC		 606}
607
44351aa0 608int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94
MCC		 609{
610 int val;
611
612 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
613printk("Original value=%d\n",val);
614 if (val<0)
615 return val;
616
617 val &= 0x0f; /* Preserve the audio input control bits */
618 switch (bitrate) {
619 case 44100:
620 val|=0xd0;
c13dd704 621 dev->audio_bitrate=bitrate;
9701dc94
MCC		 622 break;
623 case 48000:
624 val|=0x60;
c13dd704 625 dev->audio_bitrate=bitrate;
9701dc94
MCC		 626 break;
627 }
628 val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);
629
630 return val;
631}
44351aa0 632EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
0439db75
SR		 633
634static LIST_HEAD(tm6000_devlist);
635static DEFINE_MUTEX(tm6000_devlist_mutex);
636
637/*
638 * tm6000_realease_resource()
639 */
640
641void tm6000_remove_from_devlist(struct tm6000_core *dev)
642{
643 mutex_lock(&tm6000_devlist_mutex);
644 list_del(&dev->devlist);
645 mutex_unlock(&tm6000_devlist_mutex);
646};
647
648void tm6000_add_into_devlist(struct tm6000_core *dev)
649{
650 mutex_lock(&tm6000_devlist_mutex);
651 list_add_tail(&dev->devlist, &tm6000_devlist);
652 mutex_unlock(&tm6000_devlist_mutex);
653};
654
655/*
656 * Extension interface
657 */
658
659static LIST_HEAD(tm6000_extension_devlist);
660static DEFINE_MUTEX(tm6000_extension_devlist_lock);
661
662int tm6000_register_extension(struct tm6000_ops *ops)
663{
664 struct tm6000_core *dev = NULL;
665
666 mutex_lock(&tm6000_devlist_mutex);
667 mutex_lock(&tm6000_extension_devlist_lock);
668 list_add_tail(&ops->next, &tm6000_extension_devlist);
669 list_for_each_entry(dev, &tm6000_devlist, devlist) {
670 if (dev)
671 ops->init(dev);
672 }
673 printk(KERN_INFO "tm6000: Initialized (%s) extension\n", ops->name);
674 mutex_unlock(&tm6000_extension_devlist_lock);
675 mutex_unlock(&tm6000_devlist_mutex);
676 return 0;
677}
678EXPORT_SYMBOL(tm6000_register_extension);
679
680void tm6000_unregister_extension(struct tm6000_ops *ops)
681{
682 struct tm6000_core *dev = NULL;
683
684 mutex_lock(&tm6000_devlist_mutex);
685 list_for_each_entry(dev, &tm6000_devlist, devlist) {
686 if (dev)
687 ops->fini(dev);
688 }
689
690 mutex_lock(&tm6000_extension_devlist_lock);
691 printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
692 list_del(&ops->next);
693 mutex_unlock(&tm6000_extension_devlist_lock);
694 mutex_unlock(&tm6000_devlist_mutex);
695}
696EXPORT_SYMBOL(tm6000_unregister_extension);
697
698void tm6000_init_extension(struct tm6000_core *dev)
699{
700 struct tm6000_ops *ops = NULL;
701
702 mutex_lock(&tm6000_extension_devlist_lock);
703 if (!list_empty(&tm6000_extension_devlist)) {
704 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
705 if (ops->init)
706 ops->init(dev);
707 }
708 }
709 mutex_unlock(&tm6000_extension_devlist_lock);
710}
711
712void tm6000_close_extension(struct tm6000_core *dev)
713{
714 struct tm6000_ops *ops = NULL;
715
716 mutex_lock(&tm6000_extension_devlist_lock);
717 if (!list_empty(&tm6000_extension_devlist)) {
718 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
719 if (ops->fini)
720 ops->fini(dev);
721 }
722 }
723 mutex_unlock(&tm6000_extension_devlist_lock);
724}
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