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V4L/DVB: Fix color format with tm6010
[net-next-2.6.git] / drivers / staging / tm6000 / tm6000-core.c
CommitLineData
9701dc94 1/*
e28f49b0 2 tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
9701dc94
MCC		 3
4 Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
5
3169c9b2
ML		 6 Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
7 - DVB-T support
8
9701dc94
MCC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation version 2
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/usb.h>
26#include <linux/i2c.h>
9701dc94
MCC		 27#include "tm6000.h"
28#include "tm6000-regs.h"
29#include <media/v4l2-common.h>
30#include <media/tuner.h>
31
9701dc94
MCC		 32#define USB_TIMEOUT 5*HZ /* ms */
33
34int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
35 u16 value, u16 index, u8 *buf, u16 len)
36{
37 int ret, i;
38 unsigned int pipe;
39 static int ini=0, last=0, n=0;
40 u8 *data=NULL;
41
42 if (len)
43 data = kzalloc(len, GFP_KERNEL);
44
45
46 if (req_type & USB_DIR_IN)
47 pipe=usb_rcvctrlpipe(dev->udev, 0);
48 else {
49 pipe=usb_sndctrlpipe(dev->udev, 0);
50 memcpy(data, buf, len);
51 }
52
edecce0a 53 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94
MCC		 54 if (!ini)
55 last=ini=jiffies;
56
57 printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
58
59 printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
60 (req_type & USB_DIR_IN)?" IN":"OUT",
61 jiffies_to_msecs(jiffies-last),
62 jiffies_to_msecs(jiffies-ini),
63 req_type, req,value&0xff,value>>8, index&0xff, index>>8,
64 len&0xff, len>>8);
65 last=jiffies;
66 n++;
67
68 if ( !(req_type & USB_DIR_IN) ) {
69 printk(">>> ");
70 for (i=0;i<len;i++) {
71 printk(" %02x",buf[i]);
72 }
8ae1fc6e 73 printk("\n");
9701dc94
MCC		 74 }
75 }
76
77 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
78 len, USB_TIMEOUT);
79
80 if (req_type & USB_DIR_IN)
81 memcpy(buf, data, len);
82
edecce0a 83 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94
MCC		 84 if (ret<0) {
85 if (req_type & USB_DIR_IN)
86 printk("<<< (len=%d)\n",len);
87
88 printk("%s: Error #%d\n", __FUNCTION__, ret);
89 } else if (req_type & USB_DIR_IN) {
90 printk("<<< ");
91 for (i=0;i<len;i++) {
92 printk(" %02x",buf[i]);
93 }
94 printk("\n");
95 }
96 }
97
98 kfree(data);
99
a5adfbed
ML		 100 msleep(5);
101
9701dc94
MCC		 102 return ret;
103}
104
105int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
106{
107 return
108 tm6000_read_write_usb (dev, USB_DIR_OUT | USB_TYPE_VENDOR,
109 req, value, index, NULL, 0);
110}
29ec15e9 111EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94
MCC		 112
113int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
114{
115 int rc;
116 u8 buf[1];
117
118 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
119 value, index, buf, 1);
120
121 if (rc<0)
122 return rc;
123
124 return *buf;
125}
29ec15e9 126EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94
MCC		 127
128int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
129{
130 int rc;
131 u8 buf[2];
132
133 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
134 value, index, buf, 2);
135
136 if (rc<0)
137 return rc;
138
139 return buf[1]|buf[0]<<8;
140}
141
2f790884
SR		 142int tm6000_get_reg32 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
143{
144 int rc;
145 u8 buf[4];
146
147 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
148 value, index, buf, 4);
149
150 if (rc<0)
151 return rc;
152
153 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
154}
155
9701dc94
MCC		 156void tm6000_set_fourcc_format(struct tm6000_core *dev)
157{
717ecd2b 158 if (dev->dev_type == TM6010) {
42238713
MCC		 159 int val;
160
161 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0) & 0xfc;
717ecd2b 162 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
42238713 163 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
717ecd2b 164 else
42238713 165 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val | 1);
9701dc94 166 } else {
717ecd2b 167 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493 168 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b 169 else
9afec493 170 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94
MCC		 171 }
172}
173
174int tm6000_init_analog_mode (struct tm6000_core *dev)
175{
29c389be
MCC		 176 if (dev->dev_type == TM6010) {
177 int val;
9701dc94 178
29c389be 179 /* Enable video */
9afec493 180 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
29c389be 181 val |= 0x60;
9afec493 182 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
120756e1
SR		 183 val = tm6000_get_reg(dev,
184 TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
185 val &= ~0x40;
186 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
187
188 /* Init teletext */
189 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
190 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
191 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
192 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
193 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
194 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
195 tm6000_set_reg(dev,
196 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
197 tm6000_set_reg(dev,
198 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
199 tm6000_set_reg(dev,
200 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
201 tm6000_set_reg(dev,
202 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
203 tm6000_set_reg(dev,
204 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
205 tm6000_set_reg(dev,
206 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
207 tm6000_set_reg(dev,
208 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
209 tm6000_set_reg(dev,
210 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
211 tm6000_set_reg(dev,
212 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
213 tm6000_set_reg(dev,
214 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
215 tm6000_set_reg(dev,
216 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
217 tm6000_set_reg(dev,
218 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
219 tm6000_set_reg(dev,
220 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
221 tm6000_set_reg(dev,
222 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
223 tm6000_set_reg(dev,
224 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
225 tm6000_set_reg(dev,
226 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
227 tm6000_set_reg(dev,
228 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
229 tm6000_set_reg(dev,
230 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
231 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
232 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
233 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
234 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
235 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
236 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
237
238
239 /* Init audio */
240 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
241 tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04);
242 tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
243 tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0);
244 tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x05);
245 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x06);
246 tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00);
247 tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00);
248 tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08);
249 tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91);
250 tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20);
251 tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12);
252 tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20);
253 tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0);
254 tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80);
255 tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0);
256 tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80);
257 tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12);
258 tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe);
259 tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20);
260 tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14);
261 tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe);
262 tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01);
263 tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0);
264 tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32);
265 tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64);
266 tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20);
267 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00);
268 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00);
269 tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
270 tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
271 tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
272 tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
273 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
274 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
9701dc94 275
9701dc94 276 } else {
29c389be 277 /* Enables soft reset */
9afec493 278 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be
MCC		 279
280 if (dev->scaler) {
9afec493 281 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
29c389be
MCC		 282 } else {
283 /* Enable Hfilter and disable TS Drop err */
9afec493 284 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
29c389be 285 }
9701dc94 286
9afec493
MCC		 287 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
288 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
289 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
290 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
291 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
292 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
9701dc94 293
29c389be 294 /* AP Software reset */
9afec493
MCC		 295 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
296 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94 297
29c389be 298 tm6000_set_fourcc_format(dev);
9701dc94 299
29c389be 300 /* Disables soft reset */
9afec493 301 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
9701dc94 302
29c389be 303 /* E3: Select input 0 - TV tuner */
9afec493 304 tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
29c389be 305 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94 306
29c389be
MCC		 307 /* This controls input */
308 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
309 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
310 }
9701dc94
MCC		 311 msleep(20);
312
29c389be
MCC		 313 /* Tuner firmware can now be loaded */
314
9701dc94
MCC		 315 /*FIXME: Hack!!! */
316 struct v4l2_frequency f;
317 mutex_lock(&dev->lock);
318 f.frequency=dev->freq;
427f7fac 319 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94
MCC		 320 mutex_unlock(&dev->lock);
321
322 msleep(100);
323 tm6000_set_standard (dev, &dev->norm);
324 tm6000_set_audio_bitrate (dev,48000);
325
9701dc94
MCC		 326 return 0;
327}
328
3169c9b2
ML		 329int tm6000_init_digital_mode (struct tm6000_core *dev)
330{
c733a4d5
SR		 331 if (dev->dev_type == TM6010) {
332 int val;
333 u8 buf[2];
3169c9b2 334
c733a4d5 335 /* digital init */
9afec493 336 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
c733a4d5 337 val &= ~0x60;
9afec493
MCC		 338 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
339 val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
c733a4d5 340 val |= 0x40;
9afec493
MCC		 341 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
342 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
343 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
344 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
345 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
c733a4d5
SR		 346 tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
347 printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
348
349
350 } else {
9afec493
MCC		 351 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
352 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
353 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
354 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
355 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
356 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5 357 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
9afec493
MCC		 358 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
359 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
360 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
361 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
362 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
363 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
364 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
365
366 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
367 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5
SR		 368 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
369 msleep(50);
370
371 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
372 msleep(50);
373 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
374 msleep(50);
375 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
376 msleep(100);
377 }
3169c9b2
ML		 378 return 0;
379}
9701dc94 380
29c389be
MCC		 381struct reg_init {
382 u8 req;
383 u8 reg;
384 u8 val;
385};
386
9701dc94 387/* The meaning of those initializations are unknown */
29c389be 388struct reg_init tm6000_init_tab[] = {
9701dc94 389 /* REG VALUE */
9afec493
MCC		 390 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
391 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
392 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
393 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
394 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
395 { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
396 { TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
397 { TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
398 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
399 { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
29c389be
MCC		 400 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
401 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
9afec493
MCC		 402 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
403 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
404 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
405 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
406 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
407 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
408 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
409 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
410 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
411 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
412 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
413 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
414 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
415 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
416 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
417 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
418 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
419 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
420 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
421 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
422 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
423 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
424 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
425 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
426 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
427 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
428 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
429 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
430 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
431 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
432 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
433 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
434 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
435 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
436 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
437 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
438 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
439 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
440 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
441 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
442 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
443 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
444 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
445 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
446 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
447 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
448 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
449 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
450 { TM6010_REQ07_RC3_HSTART1, 0x88 },
451 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
2415a2c1 452 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be
MCC		 453};
454
455struct reg_init tm6010_init_tab[] = {
9afec493
MCC		 456 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
457 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
458 { TM6010_REQ07_RC6_HEND0, 0x40 },
459 { TM6010_REQ07_RCA_VEND0, 0x31 },
460 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
461 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
462 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
463
464 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
465 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
466 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
467 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
468 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
469 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
470 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
471 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
472 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
473
474 { TM6010_REQ07_R3F_RESET, 0x01 },
475 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
476 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
477 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
478 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
479 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
480 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
481 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
482 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
483 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
484 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
485 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
486 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
487 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
488 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
489 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
490 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
491 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
492 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
493 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
494 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
495 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
496 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
497 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
498 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
499 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
500 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
501 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
502 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
503 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
504 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
505 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
506 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
507 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
508 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
509 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
510 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
511 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
512 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
513 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
514 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
515 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
516 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
517 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
518 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
519 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
520 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
521 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
522 { TM6010_REQ07_RC3_HSTART1, 0x88 },
523 { TM6010_REQ07_R3F_RESET, 0x00 },
29c389be 524
2415a2c1 525 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be 526
9afec493
MCC		 527 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
528 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
529 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
530 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932 531 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493 532 { TM6010_REQ07_RD8_IR, 0x2f },
d46ca932 533
29c389be 534 /* set remote wakeup key:any key wakeup */
9afec493
MCC		 535 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
536 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94
MCC		 537};
538
539int tm6000_init (struct tm6000_core *dev)
540{
29c389be
MCC		 541 int board, rc=0, i, size;
542 struct reg_init *tab;
543
544 if (dev->dev_type == TM6010) {
545 tab = tm6010_init_tab;
546 size = ARRAY_SIZE(tm6010_init_tab);
547 } else {
548 tab = tm6000_init_tab;
549 size = ARRAY_SIZE(tm6000_init_tab);
550 }
9701dc94 551
9701dc94 552 /* Load board's initialization table */
29c389be
MCC		 553 for (i=0; i< size; i++) {
554 rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
9701dc94 555 if (rc<0) {
29c389be
MCC		 556 printk (KERN_ERR "Error %i while setting req %d, "
557 "reg %d to value %d\n", rc,
558 tab[i].req,tab[i].reg, tab[i].val);
9701dc94
MCC		 559 return rc;
560 }
561 }
562
29c389be
MCC		 563 msleep(5); /* Just to be conservative */
564
9701dc94 565 /* Check board version - maybe 10Moons specific */
2f790884 566 board=tm6000_get_reg32 (dev, REQ_40_GET_VERSION, 0, 0);
9701dc94 567 if (board >=0) {
2f790884 568 printk (KERN_INFO "Board version = 0x%08x\n",board);
9701dc94
MCC		 569 } else {
570 printk (KERN_ERR "Error %i while retrieving board version\n",board);
571 }
572
e3ee9e5e 573 rc = tm6000_cards_setup(dev);
a5adfbed 574
e3ee9e5e 575 return rc;
9701dc94
MCC		 576}
577
44351aa0 578int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94
MCC		 579{
580 int val;
581
582 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
583printk("Original value=%d\n",val);
584 if (val<0)
585 return val;
586
587 val &= 0x0f; /* Preserve the audio input control bits */
588 switch (bitrate) {
589 case 44100:
590 val|=0xd0;
c13dd704 591 dev->audio_bitrate=bitrate;
9701dc94
MCC		 592 break;
593 case 48000:
594 val|=0x60;
c13dd704 595 dev->audio_bitrate=bitrate;
9701dc94
MCC		 596 break;
597 }
598 val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);
599
600 return val;
601}
44351aa0 602EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
Clone of davem's net-next-2.6 tree