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9701dc94 1/*
d0058645
RP		 2 * tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
3 *
4 * Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
5 *
6 * Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
7 * - DVB-T support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation version 2
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
9701dc94
MCC		 21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
4ef09889 25#include <linux/slab.h>
9701dc94
MCC		 26#include <linux/usb.h>
27#include <linux/i2c.h>
9701dc94
MCC		 28#include "tm6000.h"
29#include "tm6000-regs.h"
30#include <media/v4l2-common.h>
31#include <media/tuner.h>
32
4363a0b8 33#define USB_TIMEOUT (5 * HZ) /* ms */
9701dc94 34
52e0a72a
TT		 35int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req,
36 u16 value, u16 index, u8 *buf, u16 len)
9701dc94
MCC		 37{
38 int ret, i;
39 unsigned int pipe;
52e0a72a 40 u8 *data = NULL;
9701dc94
MCC		 41
42 if (len)
43 data = kzalloc(len, GFP_KERNEL);
44
45
46 if (req_type & USB_DIR_IN)
52e0a72a 47 pipe = usb_rcvctrlpipe(dev->udev, 0);
9701dc94 48 else {
52e0a72a 49 pipe = usb_sndctrlpipe(dev->udev, 0);
9701dc94
MCC		 50 memcpy(data, buf, len);
51 }
52
edecce0a 53 if (tm6000_debug & V4L2_DEBUG_I2C) {
638054ab 54 printk("(dev %p, pipe %08x): ", dev->udev, pipe);
9701dc94 55
638054ab 56 printk("%s: %02x %02x %02x %02x %02x %02x %02x %02x ",
52e0a72a 57 (req_type & USB_DIR_IN) ? " IN" : "OUT",
52e0a72a
TT		 58 req_type, req, value&0xff, value>>8, index&0xff,
59 index>>8, len&0xff, len>>8);
9701dc94 60
52e0a72a 61 if (!(req_type & USB_DIR_IN)) {
9701dc94 62 printk(">>> ");
52e0a72a
TT		 63 for (i = 0; i < len; i++)
64 printk(" %02x", buf[i]);
8ae1fc6e 65 printk("\n");
9701dc94
MCC		 66 }
67 }
68
52e0a72a
TT		 69 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index,
70 data, len, USB_TIMEOUT);
9701dc94
MCC		 71
72 if (req_type & USB_DIR_IN)
73 memcpy(buf, data, len);
74
edecce0a 75 if (tm6000_debug & V4L2_DEBUG_I2C) {
52e0a72a 76 if (ret < 0) {
9701dc94 77 if (req_type & USB_DIR_IN)
52e0a72a 78 printk("<<< (len=%d)\n", len);
9701dc94
MCC		 79
80 printk("%s: Error #%d\n", __FUNCTION__, ret);
81 } else if (req_type & USB_DIR_IN) {
82 printk("<<< ");
52e0a72a
TT		 83 for (i = 0; i < len; i++)
84 printk(" %02x", buf[i]);
9701dc94
MCC		 85 printk("\n");
86 }
87 }
88
89 kfree(data);
90
a5adfbed
ML		 91 msleep(5);
92
9701dc94
MCC		 93 return ret;
94}
95
52e0a72a 96int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 97{
98 return
52e0a72a
TT		 99 tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
100 req, value, index, NULL, 0);
9701dc94 101}
29ec15e9 102EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94 103
52e0a72a 104int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 105{
106 int rc;
107 u8 buf[1];
108
52e0a72a
TT		 109 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
110 value, index, buf, 1);
9701dc94 111
52e0a72a 112 if (rc < 0)
9701dc94
MCC		 113 return rc;
114
115 return *buf;
116}
29ec15e9 117EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94 118
52e0a72a 119int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 120{
121 int rc;
122 u8 buf[2];
123
52e0a72a
TT		 124 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
125 value, index, buf, 2);
9701dc94 126
52e0a72a 127 if (rc < 0)
9701dc94
MCC		 128 return rc;
129
130 return buf[1]|buf[0]<<8;
131}
132
52e0a72a 133int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index)
2f790884
SR		 134{
135 int rc;
136 u8 buf[4];
137
52e0a72a
TT		 138 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
139 value, index, buf, 4);
2f790884 140
52e0a72a 141 if (rc < 0)
2f790884
SR		 142 return rc;
143
144 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
145}
146
2a15ac7a
DB		 147int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
148{
149 int rc;
150
151 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
152 if (rc < 0)
153 return rc;
154
155 msleep(tsleep);
156
157 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
158 msleep(tsleep);
159
160 return rc;
161}
162
9701dc94
MCC		 163void tm6000_set_fourcc_format(struct tm6000_core *dev)
164{
717ecd2b 165 if (dev->dev_type == TM6010) {
42238713
MCC		 166 int val;
167
168 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0) & 0xfc;
717ecd2b 169 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
42238713 170 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
717ecd2b 171 else
42238713 172 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val | 1);
9701dc94 173 } else {
717ecd2b 174 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493 175 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b 176 else
9afec493 177 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94
MCC		 178 }
179}
180
589851d5 181static void tm6000_set_vbi(struct tm6000_core *dev)
9701dc94 182{
589851d5
MCC		 183 /*
184 * FIXME:
185 * VBI lines and start/end are different between 60Hz and 50Hz
186 * So, it is very likely that we need to change the config to
187 * something that takes it into account, doing something different
188 * if (dev->norm & V4L2_STD_525_60)
189 */
94d4350c 190
29c389be 191 if (dev->dev_type == TM6010) {
120756e1
SR		 192 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
193 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
194 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
195 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
196 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
197 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
198 tm6000_set_reg(dev,
199 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
200 tm6000_set_reg(dev,
201 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
202 tm6000_set_reg(dev,
203 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
204 tm6000_set_reg(dev,
205 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
206 tm6000_set_reg(dev,
207 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
208 tm6000_set_reg(dev,
209 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
210 tm6000_set_reg(dev,
211 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
212 tm6000_set_reg(dev,
213 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
214 tm6000_set_reg(dev,
215 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
216 tm6000_set_reg(dev,
217 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
218 tm6000_set_reg(dev,
219 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
220 tm6000_set_reg(dev,
221 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
222 tm6000_set_reg(dev,
223 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
224 tm6000_set_reg(dev,
225 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
226 tm6000_set_reg(dev,
227 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
228 tm6000_set_reg(dev,
229 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
230 tm6000_set_reg(dev,
231 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
232 tm6000_set_reg(dev,
233 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
234 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
235 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
236 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
237 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
238 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
239 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
589851d5
MCC		 240 }
241}
242
243int tm6000_init_analog_mode(struct tm6000_core *dev)
244{
245 struct v4l2_frequency f;
246
247 if (dev->dev_type == TM6010) {
248 int val;
249
250 /* Enable video */
251 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
252 val |= 0x60;
253 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
254 val = tm6000_get_reg(dev,
255 TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
256 val &= ~0x40;
257 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
258
259 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc);
260
9701dc94 261 } else {
29c389be 262 /* Enables soft reset */
9afec493 263 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be 264
52e0a72a 265 if (dev->scaler)
9afec493 266 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
52e0a72a 267 else /* Enable Hfilter and disable TS Drop err */
9afec493 268 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
9701dc94 269
9afec493
MCC		 270 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
271 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
272 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
273 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
274 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
275 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
9701dc94 276
29c389be 277 /* AP Software reset */
9afec493
MCC		 278 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
279 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94 280
29c389be 281 tm6000_set_fourcc_format(dev);
9701dc94 282
29c389be 283 /* Disables soft reset */
9afec493 284 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
9701dc94 285
29c389be 286 /* E3: Select input 0 - TV tuner */
9afec493 287 tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
29c389be 288 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94 289
29c389be
MCC		 290 /* This controls input */
291 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
292 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
293 }
9701dc94
MCC		 294 msleep(20);
295
29c389be
MCC		 296 /* Tuner firmware can now be loaded */
297
94d4350c
MCC		 298 /*
299 * FIXME: This is a hack! xc3028 "sleeps" when no channel is detected
300 * for more than a few seconds. Not sure why, as this behavior does
301 * not happen on other devices with xc3028. So, I suspect that it
302 * is yet another bug at tm6000. After start sleeping, decoding
303 * doesn't start automatically. Instead, it requires some
304 * I2C commands to wake it up. As we want to have image at the
305 * beginning, we needed to add this hack. The better would be to
306 * discover some way to make tm6000 to wake up without this hack.
307 */
52e0a72a 308 f.frequency = dev->freq;
427f7fac 309 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94
MCC		 310
311 msleep(100);
52e0a72a 312 tm6000_set_standard(dev, &dev->norm);
589851d5 313 tm6000_set_vbi(dev);
52e0a72a 314 tm6000_set_audio_bitrate(dev, 48000);
9701dc94 315
f36cc034
SR		 316 /* switch dvb led off */
317 if (dev->gpio.dvb_led) {
318 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
319 dev->gpio.dvb_led, 0x01);
320 }
321
9701dc94
MCC		 322 return 0;
323}
324
52e0a72a 325int tm6000_init_digital_mode(struct tm6000_core *dev)
3169c9b2 326{
c733a4d5
SR		 327 if (dev->dev_type == TM6010) {
328 int val;
329 u8 buf[2];
3169c9b2 330
c733a4d5 331 /* digital init */
9afec493 332 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
c733a4d5 333 val &= ~0x60;
9afec493
MCC		 334 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
335 val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
c733a4d5 336 val |= 0x40;
9afec493
MCC		 337 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
338 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
339 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
340 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
52e0a72a
TT		 341 tm6000_read_write_usb(dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
342 printk(KERN_INFO"buf %#x %#x\n", buf[0], buf[1]);
c733a4d5 343 } else {
9afec493
MCC		 344 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
345 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
346 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
347 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
348 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
349 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
52e0a72a 350 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
9afec493
MCC		 351 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
352 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
353 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
354 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
355 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
356 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
357 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
358
359 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
360 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
52e0a72a 361 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
c733a4d5
SR		 362 msleep(50);
363
52e0a72a 364 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
c733a4d5 365 msleep(50);
52e0a72a 366 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
c733a4d5 367 msleep(50);
52e0a72a 368 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
c733a4d5
SR		 369 msleep(100);
370 }
f36cc034
SR		 371
372 /* switch dvb led on */
373 if (dev->gpio.dvb_led) {
374 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
375 dev->gpio.dvb_led, 0x00);
376 }
377
3169c9b2
ML		 378 return 0;
379}
cee3926f 380EXPORT_SYMBOL(tm6000_init_digital_mode);
9701dc94 381
29c389be
MCC		 382struct reg_init {
383 u8 req;
384 u8 reg;
385 u8 val;
386};
387
9701dc94 388/* The meaning of those initializations are unknown */
29c389be 389struct reg_init tm6000_init_tab[] = {
9701dc94 390 /* REG VALUE */
9afec493
MCC		 391 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
392 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
393 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
394 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
395 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
396 { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
397 { TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
398 { TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
399 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
400 { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
29c389be
MCC		 401 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
402 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
9afec493
MCC		 403 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
404 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
405 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
406 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
407 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
408 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
409 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
410 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
411 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
412 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
413 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
414 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
415 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
416 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
417 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
418 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
419 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
420 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
421 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
422 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
423 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
424 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
425 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
426 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
427 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
428 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
429 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
430 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
431 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
432 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
433 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
434 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
435 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
436 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
437 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
438 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
439 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
440 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
441 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
442 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
443 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
444 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
445 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
446 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
447 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
448 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
449 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
450 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
451 { TM6010_REQ07_RC3_HSTART1, 0x88 },
452 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
2415a2c1 453 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be
MCC		 454};
455
456struct reg_init tm6010_init_tab[] = {
9afec493
MCC		 457 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
458 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
459 { TM6010_REQ07_RC6_HEND0, 0x40 },
460 { TM6010_REQ07_RCA_VEND0, 0x31 },
461 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
462 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
463 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
464
465 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
466 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
467 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
468 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
469 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
470 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
471 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
472 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
473 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
474
475 { TM6010_REQ07_R3F_RESET, 0x01 },
476 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
477 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
478 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
479 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
480 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
481 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
482 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
483 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
484 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
485 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
486 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
487 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
488 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
489 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
490 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
491 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
492 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
493 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
494 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
495 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
496 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
497 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
498 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
499 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
500 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
501 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
502 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
503 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
504 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
505 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
506 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
507 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
508 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
509 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
510 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
511 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
512 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
513 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
514 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
515 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
516 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
517 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
518 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
519 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
520 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
521 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
522 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
523 { TM6010_REQ07_RC3_HSTART1, 0x88 },
524 { TM6010_REQ07_R3F_RESET, 0x00 },
29c389be 525
2415a2c1 526 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be 527
9afec493
MCC		 528 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
529 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
530 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
531 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932 532 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493 533 { TM6010_REQ07_RD8_IR, 0x2f },
d46ca932 534
29c389be 535 /* set remote wakeup key:any key wakeup */
9afec493
MCC		 536 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
537 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94
MCC		 538};
539
52e0a72a 540int tm6000_init(struct tm6000_core *dev)
9701dc94 541{
52e0a72a 542 int board, rc = 0, i, size;
29c389be
MCC		 543 struct reg_init *tab;
544
545 if (dev->dev_type == TM6010) {
546 tab = tm6010_init_tab;
547 size = ARRAY_SIZE(tm6010_init_tab);
548 } else {
549 tab = tm6000_init_tab;
550 size = ARRAY_SIZE(tm6000_init_tab);
551 }
9701dc94 552
9701dc94 553 /* Load board's initialization table */
52e0a72a
TT		 554 for (i = 0; i < size; i++) {
555 rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val);
556 if (rc < 0) {
557 printk(KERN_ERR "Error %i while setting req %d, "
558 "reg %d to value %d\n", rc,
559 tab[i].req, tab[i].reg, tab[i].val);
9701dc94
MCC		 560 return rc;
561 }
562 }
563
29c389be
MCC		 564 msleep(5); /* Just to be conservative */
565
9701dc94 566 /* Check board version - maybe 10Moons specific */
52e0a72a
TT		 567 board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0);
568 if (board >= 0)
569 printk(KERN_INFO "Board version = 0x%08x\n", board);
570 else
571 printk(KERN_ERR "Error %i while retrieving board version\n", board);
9701dc94 572
e3ee9e5e 573 rc = tm6000_cards_setup(dev);
a5adfbed 574
e3ee9e5e 575 return rc;
9701dc94
MCC		 576}
577
44351aa0 578int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94
MCC		 579{
580 int val;
581
a59bff37
MCC		 582 if (dev->dev_type == TM6010) {
583 val = tm6000_get_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0);
584 if (val < 0)
585 return val;
586 val = (val & 0xf0) | 0x1; /* 48 kHz, not muted */
587 val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, val);
588 if (val < 0)
589 return val;
590 }
591
52e0a72a 592 val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
52e0a72a 593 if (val < 0)
9701dc94
MCC		 594 return val;
595
596 val &= 0x0f; /* Preserve the audio input control bits */
597 switch (bitrate) {
598 case 44100:
52e0a72a
TT		 599 val |= 0xd0;
600 dev->audio_bitrate = bitrate;
9701dc94
MCC		 601 break;
602 case 48000:
52e0a72a
TT		 603 val |= 0x60;
604 dev->audio_bitrate = bitrate;
9701dc94
MCC		 605 break;
606 }
52e0a72a 607 val = tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, val);
9701dc94
MCC		 608
609 return val;
610}
44351aa0 611EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
0439db75
SR		 612
613static LIST_HEAD(tm6000_devlist);
614static DEFINE_MUTEX(tm6000_devlist_mutex);
615
616/*
617 * tm6000_realease_resource()
618 */
619
620void tm6000_remove_from_devlist(struct tm6000_core *dev)
621{
622 mutex_lock(&tm6000_devlist_mutex);
623 list_del(&dev->devlist);
624 mutex_unlock(&tm6000_devlist_mutex);
625};
626
627void tm6000_add_into_devlist(struct tm6000_core *dev)
628{
629 mutex_lock(&tm6000_devlist_mutex);
630 list_add_tail(&dev->devlist, &tm6000_devlist);
631 mutex_unlock(&tm6000_devlist_mutex);
632};
633
634/*
635 * Extension interface
636 */
637
638static LIST_HEAD(tm6000_extension_devlist);
0439db75 639
b17b8699
MCC		 640int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type,
641 char *buf, int size)
642{
643 struct tm6000_ops *ops = NULL;
644
645 /* FIXME: tm6000_extension_devlist_lock should be a spinlock */
646
647 if (!list_empty(&tm6000_extension_devlist)) {
648 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
649 if (ops->fillbuf && ops->type == type)
650 ops->fillbuf(dev, buf, size);
651 }
652 }
653
654 return 0;
655}
656
0439db75
SR		 657int tm6000_register_extension(struct tm6000_ops *ops)
658{
659 struct tm6000_core *dev = NULL;
660
661 mutex_lock(&tm6000_devlist_mutex);
0439db75
SR		 662 list_add_tail(&ops->next, &tm6000_extension_devlist);
663 list_for_each_entry(dev, &tm6000_devlist, devlist) {
3f23a81a
MCC		 664 ops->init(dev);
665 printk(KERN_INFO "%s: Initialized (%s) extension\n",
666 dev->name, ops->name);
0439db75 667 }
0439db75
SR		 668 mutex_unlock(&tm6000_devlist_mutex);
669 return 0;
670}
671EXPORT_SYMBOL(tm6000_register_extension);
672
673void tm6000_unregister_extension(struct tm6000_ops *ops)
674{
675 struct tm6000_core *dev = NULL;
676
677 mutex_lock(&tm6000_devlist_mutex);
a3d7fc5c
JL		 678 list_for_each_entry(dev, &tm6000_devlist, devlist)
679 ops->fini(dev);
0439db75 680
0439db75
SR		 681 printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
682 list_del(&ops->next);
0439db75
SR		 683 mutex_unlock(&tm6000_devlist_mutex);
684}
685EXPORT_SYMBOL(tm6000_unregister_extension);
686
687void tm6000_init_extension(struct tm6000_core *dev)
688{
689 struct tm6000_ops *ops = NULL;
690
4ae18398 691 mutex_lock(&tm6000_devlist_mutex);
0439db75
SR		 692 if (!list_empty(&tm6000_extension_devlist)) {
693 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
694 if (ops->init)
695 ops->init(dev);
696 }
697 }
4ae18398 698 mutex_unlock(&tm6000_devlist_mutex);
0439db75
SR		 699}
700
701void tm6000_close_extension(struct tm6000_core *dev)
702{
703 struct tm6000_ops *ops = NULL;
704
4ae18398 705 mutex_lock(&tm6000_devlist_mutex);
0439db75
SR		 706 if (!list_empty(&tm6000_extension_devlist)) {
707 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
708 if (ops->fini)
709 ops->fini(dev);
710 }
711 }
4ae18398 712 mutex_lock(&tm6000_devlist_mutex);
0439db75 713}
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