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Staging: rtl8192su: remove RTL8192SE ifdefs
[net-next-2.6.git] / drivers / staging / rtl8192su / r8192U_core.c
CommitLineData
5f53d8ca
JC		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 * Linux device driver for RTL8192U
4 *
5 * Based on the r8187 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Jerry chuang <wlanfae@realtek.com>
25 */
26
27#ifndef CONFIG_FORCE_HARD_FLOAT
28double __floatsidf (int i) { return i; }
29unsigned int __fixunsdfsi (double d) { return d; }
30double __adddf3(double a, double b) { return a+b; }
31double __addsf3(float a, float b) { return a+b; }
32double __subdf3(double a, double b) { return a-b; }
33double __extendsfdf2(float a) {return a;}
34#endif
35
36#undef LOOP_TEST
37#undef DUMP_RX
38#undef DUMP_TX
39#undef DEBUG_TX_DESC2
40#undef RX_DONT_PASS_UL
41#undef DEBUG_EPROM
42#undef DEBUG_RX_VERBOSE
43#undef DUMMY_RX
44#undef DEBUG_ZERO_RX
45#undef DEBUG_RX_SKB
46#undef DEBUG_TX_FRAG
47#undef DEBUG_RX_FRAG
48#undef DEBUG_TX_FILLDESC
49#undef DEBUG_TX
50#undef DEBUG_IRQ
51#undef DEBUG_RX
52#undef DEBUG_RXALLOC
53#undef DEBUG_REGISTERS
54#undef DEBUG_RING
55#undef DEBUG_IRQ_TASKLET
56#undef DEBUG_TX_ALLOC
57#undef DEBUG_TX_DESC
58
59#define CONFIG_RTL8192_IO_MAP
60
61#ifdef RTL8192SU
62#include <asm/uaccess.h>
63#include "r8192U.h"
64//#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
65#include "r8180_93cx6.h" /* Card EEPROM */
66#include "r8192U_wx.h"
67
68#include "r8192S_rtl8225.h"
69#include "r8192S_hw.h"
70#include "r8192S_phy.h"
71#include "r8192S_phyreg.h"
72#include "r8192S_Efuse.h"
73
74#include "r819xU_cmdpkt.h"
75#include "r8192U_dm.h"
76//#include "r8192xU_phyreg.h"
77#include <linux/usb.h>
5f53d8ca 78
5f53d8ca 79#include "r8192U_pm.h"
5f53d8ca 80
2a7d71ad 81#include "ieee80211/dot11d.h"
5f53d8ca
JC		 82
83#else
84
85#include <asm/uaccess.h>
86#include "r8192U_hw.h"
87#include "r8192U.h"
88#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
89#include "r8180_93cx6.h" /* Card EEPROM */
90#include "r8192U_wx.h"
91#include "r819xU_phy.h" //added by WB 4.30.2008
92#include "r819xU_phyreg.h"
93#include "r819xU_cmdpkt.h"
94#include "r8192U_dm.h"
95//#include "r8192xU_phyreg.h"
96#include <linux/usb.h>
5f53d8ca 97
5f53d8ca 98#include "r8192U_pm.h"
5f53d8ca 99
2a7d71ad 100#include "ieee80211/dot11d.h"
5f53d8ca
JC		 101
102#endif
103
104
105#ifdef RTL8192SU
106u32 rt_global_debug_component = \
107// COMP_TRACE |
108// COMP_DBG |
109// COMP_INIT |
110// COMP_RECV |
111// COMP_SEND |
112// COMP_IO |
113 COMP_POWER |
114// COMP_EPROM |
115 COMP_SWBW |
116 COMP_POWER_TRACKING |
117 COMP_TURBO |
118 COMP_QOS |
119// COMP_RATE |
120// COMP_RM |
121 COMP_DIG |
122// COMP_EFUSE |
123// COMP_CH |
124// COMP_TXAGC |
125 COMP_HIPWR |
126// COMP_HALDM |
127 COMP_SEC |
128 COMP_LED |
129// COMP_RF |
130// COMP_RXDESC |
131 COMP_FIRMWARE |
132 COMP_HT |
133 COMP_AMSDU |
134 COMP_SCAN |
135// COMP_CMD |
136 COMP_DOWN |
137 COMP_RESET |
138 COMP_ERR; //always open err flags on
139#else
140//set here to open your trace code. //WB
141u32 rt_global_debug_component = \
142 // COMP_INIT |
143// COMP_DBG |
144 // COMP_EPROM |
145// COMP_PHY |
146 // COMP_RF |
147// COMP_FIRMWARE |
148// COMP_CH |
149 // COMP_POWER_TRACKING |
150// COMP_RATE |
151 // COMP_TXAGC |
152 // COMP_TRACE |
153 COMP_DOWN |
154 // COMP_RECV |
155 // COMP_SWBW |
156 COMP_SEC |
157 // COMP_RESET |
158 // COMP_SEND |
159 // COMP_EVENTS |
160 COMP_ERR ; //always open err flags on
161#endif
162
163#define TOTAL_CAM_ENTRY 32
164#define CAM_CONTENT_COUNT 8
165
166static struct usb_device_id rtl8192_usb_id_tbl[] = {
167 /* Realtek */
168 {USB_DEVICE(0x0bda, 0x8192)},
169 {USB_DEVICE(0x0bda, 0x8709)},
170 /* Corega */
171 {USB_DEVICE(0x07aa, 0x0043)},
172 /* Belkin */
173 {USB_DEVICE(0x050d, 0x805E)},
174 /* Sitecom */
175 {USB_DEVICE(0x0df6, 0x0031)},
176 /* EnGenius */
177 {USB_DEVICE(0x1740, 0x9201)},
178 /* Dlink */
179 {USB_DEVICE(0x2001, 0x3301)},
180 /* Zinwell */
181 {USB_DEVICE(0x5a57, 0x0290)},
182 //92SU
183 {USB_DEVICE(0x0bda, 0x8172)},
184 {}
185};
186
187MODULE_LICENSE("GPL");
5f53d8ca 188MODULE_VERSION("V 1.1");
5f53d8ca
JC		 189MODULE_DEVICE_TABLE(usb, rtl8192_usb_id_tbl);
190MODULE_DESCRIPTION("Linux driver for Realtek RTL8192 USB WiFi cards");
191
192static char* ifname = "wlan%d";
193#if 0
194static int hwseqnum = 0;
195static int hwwep = 0;
196#endif
197static int hwwep = 1; //default use hw. set 0 to use software security
198static int channels = 0x3fff;
199
200
201
5f53d8ca
JC		 202module_param(ifname, charp, S_IRUGO|S_IWUSR );
203//module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
204module_param(hwwep,int, S_IRUGO|S_IWUSR);
205module_param(channels,int, S_IRUGO|S_IWUSR);
5f53d8ca
JC		 206
207MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default");
208//MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
209MODULE_PARM_DESC(hwwep," Try to use hardware security support. ");
210MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
211
5f53d8ca
JC		 212static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
213 const struct usb_device_id *id);
214static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf);
5f53d8ca
JC		 215
216static struct usb_driver rtl8192_usb_driver = {
5f53d8ca
JC		 217 .name = RTL819xU_MODULE_NAME, /* Driver name */
218 .id_table = rtl8192_usb_id_tbl, /* PCI_ID table */
219 .probe = rtl8192_usb_probe, /* probe fn */
220 .disconnect = rtl8192_usb_disconnect, /* remove fn */
5f53d8ca
JC		 221 .suspend = rtl8192U_suspend, /* PM suspend fn */
222 .resume = rtl8192U_resume, /* PM resume fn */
5f53d8ca 223 .reset_resume = rtl8192U_resume, /* PM reset resume fn */
5f53d8ca
JC		 224};
225
226
227#ifdef RTL8192SU
228static void rtl8192SU_read_eeprom_info(struct net_device *dev);
229short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
230void rtl8192SU_rx_nomal(struct sk_buff* skb);
231void rtl8192SU_rx_cmd(struct sk_buff *skb);
232bool rtl8192SU_adapter_start(struct net_device *dev);
233short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
234void rtl8192SU_link_change(struct net_device *dev);
235void InitialGain8192S(struct net_device *dev,u8 Operation);
236void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
237
238struct rtl819x_ops rtl8192su_ops = {
239 .nic_type = NIC_8192SU,
240 .rtl819x_read_eeprom_info = rtl8192SU_read_eeprom_info,
241 .rtl819x_tx = rtl8192SU_tx,
242 .rtl819x_tx_cmd = rtl8192SU_tx_cmd,
243 .rtl819x_rx_nomal = rtl8192SU_rx_nomal,
244 .rtl819x_rx_cmd = rtl8192SU_rx_cmd,
245 .rtl819x_adapter_start = rtl8192SU_adapter_start,
246 .rtl819x_link_change = rtl8192SU_link_change,
247 .rtl819x_initial_gain = InitialGain8192S,
248 .rtl819x_query_rxdesc_status = rtl8192SU_query_rxdesc_status,
249};
250#else
251static void rtl8192_read_eeprom_info(struct net_device *dev);
252short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
253void rtl8192_rx_nomal(struct sk_buff* skb);
254void rtl8192_rx_cmd(struct sk_buff *skb);
255bool rtl8192_adapter_start(struct net_device *dev);
256short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
257void rtl8192_link_change(struct net_device *dev);
258void InitialGain819xUsb(struct net_device *dev,u8 Operation);
259void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
260
261struct rtl819x_ops rtl8192u_ops = {
262 .nic_type = NIC_8192U,
263 .rtl819x_read_eeprom_info = rtl8192_read_eeprom_info,
264 .rtl819x_tx = rtl8192_tx,
265 .rtl819x_tx_cmd = rtl819xU_tx_cmd,
266 .rtl819x_rx_nomal = rtl8192_rx_nomal,
267 .rtl819x_rx_cmd = rtl8192_rx_cmd,
268 .rtl819x_adapter_start = rtl8192_adapter_start,
269 .rtl819x_link_change = rtl8192_link_change,
270 .rtl819x_initial_gain = InitialGain819xUsb,
271 .rtl819x_query_rxdesc_status = query_rxdesc_status,
272};
273#endif
274
5f53d8ca
JC		 275
276typedef struct _CHANNEL_LIST
277{
278 u8 Channel[32];
279 u8 Len;
280}CHANNEL_LIST, *PCHANNEL_LIST;
281
282static CHANNEL_LIST ChannelPlan[] = {
283 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
284 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
285 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
286 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI.
287 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
288 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK
289 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1
290 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel.
291 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC
292 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC
293 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
294};
295
296static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv)
297{
298 int i, max_chan=-1, min_chan=-1;
299 struct ieee80211_device* ieee = priv->ieee80211;
300 switch (channel_plan)
301 {
302 case COUNTRY_CODE_FCC:
303 case COUNTRY_CODE_IC:
304 case COUNTRY_CODE_ETSI:
305 case COUNTRY_CODE_SPAIN:
306 case COUNTRY_CODE_FRANCE:
307 case COUNTRY_CODE_MKK:
308 case COUNTRY_CODE_MKK1:
309 case COUNTRY_CODE_ISRAEL:
310 case COUNTRY_CODE_TELEC:
311 case COUNTRY_CODE_MIC:
312 {
313 Dot11d_Init(ieee);
314 ieee->bGlobalDomain = false;
315 //acturally 8225 & 8256 rf chip only support B,G,24N mode
316 if ((priv->rf_chip == RF_8225) || (priv->rf_chip == RF_8256) || (priv->rf_chip == RF_6052))
317 {
318 min_chan = 1;
319 max_chan = 14;
320 }
321 else
322 {
323 RT_TRACE(COMP_ERR, "unknown rf chip, can't set channel map in function:%s()\n", __FUNCTION__);
324 }
325 if (ChannelPlan[channel_plan].Len != 0){
326 // Clear old channel map
327 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
328 // Set new channel map
329 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
330 {
331 if (ChannelPlan[channel_plan].Channel[i] < min_chan || ChannelPlan[channel_plan].Channel[i] > max_chan)
332 break;
333 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
334 }
335 }
336 break;
337 }
338 case COUNTRY_CODE_GLOBAL_DOMAIN:
339 {
340 GET_DOT11D_INFO(ieee)->bEnabled = 0;//this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain settings.
341 Dot11d_Reset(ieee);
342 ieee->bGlobalDomain = true;
343 break;
344 }
345 default:
346 break;
347 }
348 return;
349}
5f53d8ca
JC		 350
351#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
352
353#ifdef RTL8192SU
354#define rx_hal_is_cck_rate(_pDesc)\
355 ((_pDesc->RxMCS == DESC92S_RATE1M ||\
356 _pDesc->RxMCS == DESC92S_RATE2M ||\
357 _pDesc->RxMCS == DESC92S_RATE5_5M ||\
358 _pDesc->RxMCS == DESC92S_RATE11M) &&\
359 !_pDesc->RxHT)
360
361#define tx_hal_is_cck_rate(_DataRate)\
362 ( _DataRate == MGN_1M ||\
363 _DataRate == MGN_2M ||\
364 _DataRate == MGN_5_5M ||\
365 _DataRate == MGN_11M )
366
367#else
368#define rx_hal_is_cck_rate(_pdrvinfo)\
369 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
370 _pdrvinfo->RxRate == DESC90_RATE2M ||\
371 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
372 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
373 !_pdrvinfo->RxHT)
374#endif
375
376
377
378void CamResetAllEntry(struct net_device *dev)
379{
380#if 1
381 u32 ulcommand = 0;
382 //2004/02/11 In static WEP, OID_ADD_KEY or OID_ADD_WEP are set before STA associate to AP.
383 // However, ResetKey is called on OID_802_11_INFRASTRUCTURE_MODE and MlmeAssociateRequest
384 // In this condition, Cam can not be reset because upper layer will not set this static key again.
385 //if(Adapter->EncAlgorithm == WEP_Encryption)
386 // return;
387//debug
388 //DbgPrint("========================================\n");
389 //DbgPrint(" Call ResetAllEntry \n");
390 //DbgPrint("========================================\n\n");
391 ulcommand |= BIT31|BIT30;
392 write_nic_dword(dev, RWCAM, ulcommand);
393#else
394 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
395 CAM_mark_invalid(dev, ucIndex);
396 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
397 CAM_empty_entry(dev, ucIndex);
398#endif
399
400}
401
402
403void write_cam(struct net_device *dev, u8 addr, u32 data)
404{
405 write_nic_dword(dev, WCAMI, data);
406 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) );
407}
408
409u32 read_cam(struct net_device *dev, u8 addr)
410{
411 write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) );
412 return read_nic_dword(dev, 0xa8);
413}
414
415void write_nic_byte_E(struct net_device *dev, int indx, u8 data)
416{
417 int status;
418 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
419 struct usb_device *udev = priv->udev;
420
421 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
422 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
423 indx|0xfe00, 0, &data, 1, HZ / 2);
424
425 if (status < 0)
426 {
427 printk("write_nic_byte_E TimeOut! status:%d\n", status);
428 }
429}
430
431u8 read_nic_byte_E(struct net_device *dev, int indx)
432{
433 int status;
434 u8 data;
435 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
436 struct usb_device *udev = priv->udev;
437
438 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
439 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
440 indx|0xfe00, 0, &data, 1, HZ / 2);
441
442 if (status < 0)
443 {
444 printk("read_nic_byte_E TimeOut! status:%d\n", status);
445 }
446
447 return data;
448}
449//as 92U has extend page from 4 to 16, so modify functions below.
450void write_nic_byte(struct net_device *dev, int indx, u8 data)
451{
452 int status;
453
454 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
455 struct usb_device *udev = priv->udev;
456
457 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
458 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
459#ifdef RTL8192SU
460 indx, 0, &data, 1, HZ / 2);
461#else
462 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
463#endif
464
465 if (status < 0)
466 {
467 printk("write_nic_byte TimeOut! status:%d\n", status);
468 }
469
470
471}
472
473
474void write_nic_word(struct net_device *dev, int indx, u16 data)
475{
476
477 int status;
478
479 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
480 struct usb_device *udev = priv->udev;
481
482 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
483 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
484#ifdef RTL8192SU
485 indx, 0, &data, 2, HZ / 2);
486#else
487 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2);
488#endif
489
490 if (status < 0)
491 {
492 printk("write_nic_word TimeOut! status:%d\n", status);
493 }
494
495}
496
497
498void write_nic_dword(struct net_device *dev, int indx, u32 data)
499{
500
501 int status;
502
503 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
504 struct usb_device *udev = priv->udev;
505
506 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
507 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
508#ifdef RTL8192SU
509 indx, 0, &data, 4, HZ / 2);
510#else
511 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2);
512#endif
513
514
515 if (status < 0)
516 {
517 printk("write_nic_dword TimeOut! status:%d\n", status);
518 }
519
520}
521
522
523
524u8 read_nic_byte(struct net_device *dev, int indx)
525{
526 u8 data;
527 int status;
528 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
529 struct usb_device *udev = priv->udev;
530
531 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
532 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
533#ifdef RTL8192SU
534 indx, 0, &data, 1, HZ / 2);
535#else
536 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
537#endif
538
539 if (status < 0)
540 {
541 printk("read_nic_byte TimeOut! status:%d\n", status);
542 }
543
544 return data;
545}
546
547
548
549u16 read_nic_word(struct net_device *dev, int indx)
550{
551 u16 data;
552 int status;
553 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
554 struct usb_device *udev = priv->udev;
555
556 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
557 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
558#ifdef RTL8192SU
559 indx, 0, &data, 2, HZ / 2);
560#else
561 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2);
562#endif
563
564 if (status < 0)
565 {
566 printk("read_nic_word TimeOut! status:%d\n", status);
567 }
568
569
570 return data;
571}
572
573u16 read_nic_word_E(struct net_device *dev, int indx)
574{
575 u16 data;
576 int status;
577 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
578 struct usb_device *udev = priv->udev;
579
580 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
581 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
582 indx|0xfe00, 0, &data, 2, HZ / 2);
583
584 if (status < 0)
585 {
586 printk("read_nic_word TimeOut! status:%d\n", status);
587 }
588
589
590 return data;
591}
592
593u32 read_nic_dword(struct net_device *dev, int indx)
594{
595 u32 data;
596 int status;
597// int result;
598
599 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
600 struct usb_device *udev = priv->udev;
601
602 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
603 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
604#ifdef RTL8192SU
605 indx, 0, &data, 4, HZ / 2);
606#else
607 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2);
608#endif
609// if(0 != result) {
610// printk(KERN_WARNING "read size of data = %d\, date = %d\n", result, data);
611// }
612
613 if (status < 0)
614 {
615 printk("read_nic_dword TimeOut! status:%d\n", status);
616 if(status == -ENODEV) {
617 priv->usb_error = true;
618 }
619 }
620
621
622
623 return data;
624}
625
626
627//u8 read_phy_cck(struct net_device *dev, u8 adr);
628//u8 read_phy_ofdm(struct net_device *dev, u8 adr);
629/* this might still called in what was the PHY rtl8185/rtl8192 common code
630 * plans are to possibilty turn it again in one common code...
631 */
632inline void force_pci_posting(struct net_device *dev)
633{
634}
635
636
637static struct net_device_stats *rtl8192_stats(struct net_device *dev);
638void rtl8192_commit(struct net_device *dev);
639//void rtl8192_restart(struct net_device *dev);
5f53d8ca
JC		 640void rtl8192_restart(struct work_struct *work);
641//void rtl8192_rq_tx_ack(struct work_struct *work);
5f53d8ca
JC		 642
643void watch_dog_timer_callback(unsigned long data);
644
645/****************************************************************************
646 -----------------------------PROCFS STUFF-------------------------
647*****************************************************************************/
648
649static struct proc_dir_entry *rtl8192_proc = NULL;
650
651
652
653static int proc_get_stats_ap(char *page, char **start,
654 off_t offset, int count,
655 int *eof, void *data)
656{
657 struct net_device *dev = data;
658 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
659 struct ieee80211_device *ieee = priv->ieee80211;
660 struct ieee80211_network *target;
661
662 int len = 0;
663
664 list_for_each_entry(target, &ieee->network_list, list) {
665
666 len += snprintf(page + len, count - len,
667 "%s ", target->ssid);
668
669 if(target->wpa_ie_len>0 || target->rsn_ie_len>0){
670 len += snprintf(page + len, count - len,
671 "WPA\n");
672 }
673 else{
674 len += snprintf(page + len, count - len,
675 "non_WPA\n");
676 }
677
678 }
679
680 *eof = 1;
681 return len;
682}
683
684#ifdef RTL8192SU
685static int proc_get_registers(char *page, char **start,
686 off_t offset, int count,
687 int *eof, void *data)
688{
689 struct net_device *dev = data;
690// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
691
692 int len = 0;
693 int i,n,page0,page1,page2;
694
695 int max=0xff;
696 page0 = 0x000;
697 page1 = 0x100;
698 page2 = 0x800;
699
700 /* This dump the current register page */
701 if(!IS_BB_REG_OFFSET_92S(page0)){
702 len += snprintf(page + len, count - len,
703 "\n####################page %x##################\n ", (page0>>8));
704 for(n=0;n<=max;)
705 {
706 len += snprintf(page + len, count - len,
707 "\nD: %2x > ",n);
708 for(i=0;i<16 && n<=max;i++,n++)
709 len += snprintf(page + len, count - len,
710 "%2.2x ",read_nic_byte(dev,(page0|n)));
711 }
712 }else{
713 len += snprintf(page + len, count - len,
714 "\n####################page %x##################\n ", (page0>>8));
715 for(n=0;n<=max;)
716 {
717 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
718 for(i=0;i<4 && n<=max;n+=4,i++)
719 len += snprintf(page + len, count - len,
720 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
721 }
722 }
723 len += snprintf(page + len, count - len,"\n");
724 *eof = 1;
725 return len;
726
727}
728static int proc_get_registers_1(char *page, char **start,
729 off_t offset, int count,
730 int *eof, void *data)
731{
732 struct net_device *dev = data;
733// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
734
735 int len = 0;
736 int i,n,page0;
737
738 int max=0xff;
739 page0 = 0x100;
740
741 /* This dump the current register page */
742 len += snprintf(page + len, count - len,
743 "\n####################page %x##################\n ", (page0>>8));
744 for(n=0;n<=max;)
745 {
746 len += snprintf(page + len, count - len,
747 "\nD: %2x > ",n);
748 for(i=0;i<16 && n<=max;i++,n++)
749 len += snprintf(page + len, count - len,
750 "%2.2x ",read_nic_byte(dev,(page0|n)));
751 }
752 len += snprintf(page + len, count - len,"\n");
753 *eof = 1;
754 return len;
755
756}
757static int proc_get_registers_2(char *page, char **start,
758 off_t offset, int count,
759 int *eof, void *data)
760{
761 struct net_device *dev = data;
762// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
763
764 int len = 0;
765 int i,n,page0;
766
767 int max=0xff;
768 page0 = 0x200;
769
770 /* This dump the current register page */
771 len += snprintf(page + len, count - len,
772 "\n####################page %x##################\n ", (page0>>8));
773 for(n=0;n<=max;)
774 {
775 len += snprintf(page + len, count - len,
776 "\nD: %2x > ",n);
777 for(i=0;i<16 && n<=max;i++,n++)
778 len += snprintf(page + len, count - len,
779 "%2.2x ",read_nic_byte(dev,(page0|n)));
780 }
781 len += snprintf(page + len, count - len,"\n");
782 *eof = 1;
783 return len;
784
785}
786static int proc_get_registers_8(char *page, char **start,
787 off_t offset, int count,
788 int *eof, void *data)
789{
790 struct net_device *dev = data;
791
792 int len = 0;
793 int i,n,page0;
794
795 int max=0xff;
796 page0 = 0x800;
797
798 /* This dump the current register page */
799 len += snprintf(page + len, count - len,
800 "\n####################page %x##################\n ", (page0>>8));
801 for(n=0;n<=max;)
802 {
803 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
804 for(i=0;i<4 && n<=max;n+=4,i++)
805 len += snprintf(page + len, count - len,
806 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
807 }
808 len += snprintf(page + len, count - len,"\n");
809 *eof = 1;
810 return len;
811
812 }
813static int proc_get_registers_9(char *page, char **start,
814 off_t offset, int count,
815 int *eof, void *data)
816{
817 struct net_device *dev = data;
818// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
819
820 int len = 0;
821 int i,n,page0;
822
823 int max=0xff;
824 page0 = 0x900;
825
826 /* This dump the current register page */
827 len += snprintf(page + len, count - len,
828 "\n####################page %x##################\n ", (page0>>8));
829 for(n=0;n<=max;)
830 {
831 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
832 for(i=0;i<4 && n<=max;n+=4,i++)
833 len += snprintf(page + len, count - len,
834 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
835 }
836 len += snprintf(page + len, count - len,"\n");
837 *eof = 1;
838 return len;
839}
840static int proc_get_registers_a(char *page, char **start,
841 off_t offset, int count,
842 int *eof, void *data)
843{
844 struct net_device *dev = data;
845// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
846
847 int len = 0;
848 int i,n,page0;
849
850 int max=0xff;
851 page0 = 0xa00;
852
853 /* This dump the current register page */
854 len += snprintf(page + len, count - len,
855 "\n####################page %x##################\n ", (page0>>8));
856 for(n=0;n<=max;)
857 {
858 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
859 for(i=0;i<4 && n<=max;n+=4,i++)
860 len += snprintf(page + len, count - len,
861 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
862 }
863 len += snprintf(page + len, count - len,"\n");
864 *eof = 1;
865 return len;
866}
867static int proc_get_registers_b(char *page, char **start,
868 off_t offset, int count,
869 int *eof, void *data)
870{
871 struct net_device *dev = data;
872// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
873
874 int len = 0;
875 int i,n,page0;
876
877 int max=0xff;
878 page0 = 0xb00;
879
880 /* This dump the current register page */
881 len += snprintf(page + len, count - len,
882 "\n####################page %x##################\n ", (page0>>8));
883 for(n=0;n<=max;)
884 {
885 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
886 for(i=0;i<4 && n<=max;n+=4,i++)
887 len += snprintf(page + len, count - len,
888 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
889 }
890 len += snprintf(page + len, count - len,"\n");
891 *eof = 1;
892 return len;
893 }
894static int proc_get_registers_c(char *page, char **start,
895 off_t offset, int count,
896 int *eof, void *data)
897{
898 struct net_device *dev = data;
899// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
900
901 int len = 0;
902 int i,n,page0;
903
904 int max=0xff;
905 page0 = 0xc00;
906
907 /* This dump the current register page */
908 len += snprintf(page + len, count - len,
909 "\n####################page %x##################\n ", (page0>>8));
910 for(n=0;n<=max;)
911 {
912 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
913 for(i=0;i<4 && n<=max;n+=4,i++)
914 len += snprintf(page + len, count - len,
915 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
916 }
917 len += snprintf(page + len, count - len,"\n");
918 *eof = 1;
919 return len;
920}
921static int proc_get_registers_d(char *page, char **start,
922 off_t offset, int count,
923 int *eof, void *data)
924{
925 struct net_device *dev = data;
926// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
927
928 int len = 0;
929 int i,n,page0;
930
931 int max=0xff;
932 page0 = 0xd00;
933
934 /* This dump the current register page */
935 len += snprintf(page + len, count - len,
936 "\n####################page %x##################\n ", (page0>>8));
937 for(n=0;n<=max;)
938 {
939 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
940 for(i=0;i<4 && n<=max;n+=4,i++)
941 len += snprintf(page + len, count - len,
942 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
943 }
944 len += snprintf(page + len, count - len,"\n");
945 *eof = 1;
946 return len;
947}
948static int proc_get_registers_e(char *page, char **start,
949 off_t offset, int count,
950 int *eof, void *data)
951{
952 struct net_device *dev = data;
953// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
954
955 int len = 0;
956 int i,n,page0;
957
958 int max=0xff;
959 page0 = 0xe00;
960
961 /* This dump the current register page */
962 len += snprintf(page + len, count - len,
963 "\n####################page %x##################\n ", (page0>>8));
964 for(n=0;n<=max;)
965 {
966 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
967 for(i=0;i<4 && n<=max;n+=4,i++)
968 len += snprintf(page + len, count - len,
969 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
970 }
971 len += snprintf(page + len, count - len,"\n");
972 *eof = 1;
973 return len;
974}
975#else
976static int proc_get_registers(char *page, char **start,
977 off_t offset, int count,
978 int *eof, void *data)
979{
980 struct net_device *dev = data;
981// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
982
983 int len = 0;
984 int i,n;
985
986 int max=0xff;
987
988 /* This dump the current register page */
989len += snprintf(page + len, count - len,
990 "\n####################page 0##################\n ");
991
992 for(n=0;n<=max;)
993 {
994 //printk( "\nD: %2x> ", n);
995 len += snprintf(page + len, count - len,
996 "\nD: %2x > ",n);
997
998 for(i=0;i<16 && n<=max;i++,n++)
999 len += snprintf(page + len, count - len,
1000 "%2x ",read_nic_byte(dev,0x000|n));
1001
1002 // printk("%2x ",read_nic_byte(dev,n));
1003 }
1004#if 1
1005len += snprintf(page + len, count - len,
1006 "\n####################page 1##################\n ");
1007 for(n=0;n<=max;)
1008 {
1009 //printk( "\nD: %2x> ", n);
1010 len += snprintf(page + len, count - len,
1011 "\nD: %2x > ",n);
1012
1013 for(i=0;i<16 && n<=max;i++,n++)
1014 len += snprintf(page + len, count - len,
1015 "%2x ",read_nic_byte(dev,0x100|n));
1016
1017 // printk("%2x ",read_nic_byte(dev,n));
1018 }
1019len += snprintf(page + len, count - len,
1020 "\n####################page 3##################\n ");
1021 for(n=0;n<=max;)
1022 {
1023 //printk( "\nD: %2x> ", n);
1024 len += snprintf(page + len, count - len,
1025 "\nD: %2x > ",n);
1026
1027 for(i=0;i<16 && n<=max;i++,n++)
1028 len += snprintf(page + len, count - len,
1029 "%2x ",read_nic_byte(dev,0x300|n));
1030
1031 // printk("%2x ",read_nic_byte(dev,n));
1032 }
1033
1034#endif
1035
1036 len += snprintf(page + len, count - len,"\n");
1037 *eof = 1;
1038 return len;
1039
1040}
1041#endif
1042
1043#if 0
1044static int proc_get_cck_reg(char *page, char **start,
1045 off_t offset, int count,
1046 int *eof, void *data)
1047{
1048 struct net_device *dev = data;
1049// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1050
1051 int len = 0;
1052 int i,n;
1053
1054 int max = 0x5F;
1055
1056 /* This dump the current register page */
1057 for(n=0;n<=max;)
1058 {
1059 //printk( "\nD: %2x> ", n);
1060 len += snprintf(page + len, count - len,
1061 "\nD: %2x > ",n);
1062
1063 for(i=0;i<16 && n<=max;i++,n++)
1064 len += snprintf(page + len, count - len,
1065 "%2x ",read_phy_cck(dev,n));
1066
1067 // printk("%2x ",read_nic_byte(dev,n));
1068 }
1069 len += snprintf(page + len, count - len,"\n");
1070
1071
1072 *eof = 1;
1073 return len;
1074}
1075
1076#endif
1077
1078#if 0
1079static int proc_get_ofdm_reg(char *page, char **start,
1080 off_t offset, int count,
1081 int *eof, void *data)
1082{
1083 struct net_device *dev = data;
1084// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1085
1086 int len = 0;
1087 int i,n;
1088
1089 //int max=0xff;
1090 int max = 0x40;
1091
1092 /* This dump the current register page */
1093 for(n=0;n<=max;)
1094 {
1095 //printk( "\nD: %2x> ", n);
1096 len += snprintf(page + len, count - len,
1097 "\nD: %2x > ",n);
1098
1099 for(i=0;i<16 && n<=max;i++,n++)
1100 len += snprintf(page + len, count - len,
1101 "%2x ",read_phy_ofdm(dev,n));
1102
1103 // printk("%2x ",read_nic_byte(dev,n));
1104 }
1105 len += snprintf(page + len, count - len,"\n");
1106
1107
1108
1109 *eof = 1;
1110 return len;
1111}
1112
1113#endif
1114
1115#if 0
1116static int proc_get_stats_hw(char *page, char **start,
1117 off_t offset, int count,
1118 int *eof, void *data)
1119{
1120 struct net_device *dev = data;
1121 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1122
1123 int len = 0;
1124
1125 len += snprintf(page + len, count - len,
1126 "NIC int: %lu\n"
1127 "Total int: %lu\n",
1128 priv->stats.ints,
1129 priv->stats.shints);
1130
1131 *eof = 1;
1132 return len;
1133}
1134#endif
1135
1136static int proc_get_stats_tx(char *page, char **start,
1137 off_t offset, int count,
1138 int *eof, void *data)
1139{
1140 struct net_device *dev = data;
1141 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1142
1143 int len = 0;
1144
1145 len += snprintf(page + len, count - len,
1146 "TX VI priority ok int: %lu\n"
1147 "TX VI priority error int: %lu\n"
1148 "TX VO priority ok int: %lu\n"
1149 "TX VO priority error int: %lu\n"
1150 "TX BE priority ok int: %lu\n"
1151 "TX BE priority error int: %lu\n"
1152 "TX BK priority ok int: %lu\n"
1153 "TX BK priority error int: %lu\n"
1154 "TX MANAGE priority ok int: %lu\n"
1155 "TX MANAGE priority error int: %lu\n"
1156 "TX BEACON priority ok int: %lu\n"
1157 "TX BEACON priority error int: %lu\n"
1158// "TX high priority ok int: %lu\n"
1159// "TX high priority failed error int: %lu\n"
1160 "TX queue resume: %lu\n"
1161 "TX queue stopped?: %d\n"
1162 "TX fifo overflow: %lu\n"
1163// "TX beacon: %lu\n"
1164 "TX VI queue: %d\n"
1165 "TX VO queue: %d\n"
1166 "TX BE queue: %d\n"
1167 "TX BK queue: %d\n"
1168// "TX HW queue: %d\n"
1169 "TX VI dropped: %lu\n"
1170 "TX VO dropped: %lu\n"
1171 "TX BE dropped: %lu\n"
1172 "TX BK dropped: %lu\n"
1173 "TX total data packets %lu\n",
1174// "TX beacon aborted: %lu\n",
1175 priv->stats.txviokint,
1176 priv->stats.txvierr,
1177 priv->stats.txvookint,
1178 priv->stats.txvoerr,
1179 priv->stats.txbeokint,
1180 priv->stats.txbeerr,
1181 priv->stats.txbkokint,
1182 priv->stats.txbkerr,
1183 priv->stats.txmanageokint,
1184 priv->stats.txmanageerr,
1185 priv->stats.txbeaconokint,
1186 priv->stats.txbeaconerr,
1187// priv->stats.txhpokint,
1188// priv->stats.txhperr,
1189 priv->stats.txresumed,
1190 netif_queue_stopped(dev),
1191 priv->stats.txoverflow,
1192// priv->stats.txbeacon,
1193 atomic_read(&(priv->tx_pending[VI_PRIORITY])),
1194 atomic_read(&(priv->tx_pending[VO_PRIORITY])),
1195 atomic_read(&(priv->tx_pending[BE_PRIORITY])),
1196 atomic_read(&(priv->tx_pending[BK_PRIORITY])),
1197// read_nic_byte(dev, TXFIFOCOUNT),
1198 priv->stats.txvidrop,
1199 priv->stats.txvodrop,
1200 priv->stats.txbedrop,
1201 priv->stats.txbkdrop,
1202 priv->stats.txdatapkt
1203// priv->stats.txbeaconerr
1204 );
1205
1206 *eof = 1;
1207 return len;
1208}
1209
1210
1211
1212static int proc_get_stats_rx(char *page, char **start,
1213 off_t offset, int count,
1214 int *eof, void *data)
1215{
1216 struct net_device *dev = data;
1217 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1218
1219 int len = 0;
1220
1221 len += snprintf(page + len, count - len,
1222 "RX packets: %lu\n"
1223 "RX urb status error: %lu\n"
1224 "RX invalid urb error: %lu\n",
1225 priv->stats.rxoktotal,
1226 priv->stats.rxstaterr,
1227 priv->stats.rxurberr);
1228
1229 *eof = 1;
1230 return len;
1231}
5f53d8ca 1232
5f53d8ca
JC		 1233void rtl8192_proc_module_init(void)
1234{
1235 RT_TRACE(COMP_INIT, "Initializing proc filesystem");
5f53d8ca 1236 rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, init_net.proc_net);
5f53d8ca
JC		 1237}
1238
1239
1240void rtl8192_proc_module_remove(void)
1241{
5f53d8ca 1242 remove_proc_entry(RTL819xU_MODULE_NAME, init_net.proc_net);
5f53d8ca
JC		 1243}
1244
1245
1246void rtl8192_proc_remove_one(struct net_device *dev)
1247{
1248 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1249
1250
1251 if (priv->dir_dev) {
1252 // remove_proc_entry("stats-hw", priv->dir_dev);
1253 remove_proc_entry("stats-tx", priv->dir_dev);
1254 remove_proc_entry("stats-rx", priv->dir_dev);
1255 // remove_proc_entry("stats-ieee", priv->dir_dev);
1256 remove_proc_entry("stats-ap", priv->dir_dev);
1257 remove_proc_entry("registers", priv->dir_dev);
1258 remove_proc_entry("registers-1", priv->dir_dev);
1259 remove_proc_entry("registers-2", priv->dir_dev);
1260 remove_proc_entry("registers-8", priv->dir_dev);
1261 remove_proc_entry("registers-9", priv->dir_dev);
1262 remove_proc_entry("registers-a", priv->dir_dev);
1263 remove_proc_entry("registers-b", priv->dir_dev);
1264 remove_proc_entry("registers-c", priv->dir_dev);
1265 remove_proc_entry("registers-d", priv->dir_dev);
1266 remove_proc_entry("registers-e", priv->dir_dev);
1267 // remove_proc_entry("cck-registers",priv->dir_dev);
1268 // remove_proc_entry("ofdm-registers",priv->dir_dev);
1269 //remove_proc_entry(dev->name, rtl8192_proc);
1270 remove_proc_entry("wlan0", rtl8192_proc);
1271 priv->dir_dev = NULL;
1272 }
1273}
1274
1275
1276void rtl8192_proc_init_one(struct net_device *dev)
1277{
1278 struct proc_dir_entry *e;
1279 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1280 priv->dir_dev = create_proc_entry(dev->name,
1281 S_IFDIR | S_IRUGO | S_IXUGO,
1282 rtl8192_proc);
1283 if (!priv->dir_dev) {
1284 RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n",
1285 dev->name);
1286 return;
1287 }
1288 #if 0
1289 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
1290 priv->dir_dev, proc_get_stats_hw, dev);
1291
1292 if (!e) {
1293 DMESGE("Unable to initialize "
1294 "/proc/net/rtl8192/%s/stats-hw\n",
1295 dev->name);
1296 }
1297 #endif
1298 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
1299 priv->dir_dev, proc_get_stats_rx, dev);
1300
1301 if (!e) {
1302 RT_TRACE(COMP_ERR,"Unable to initialize "
1303 "/proc/net/rtl8192/%s/stats-rx\n",
1304 dev->name);
1305 }
1306
1307
1308 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
1309 priv->dir_dev, proc_get_stats_tx, dev);
1310
1311 if (!e) {
1312 RT_TRACE(COMP_ERR, "Unable to initialize "
1313 "/proc/net/rtl8192/%s/stats-tx\n",
1314 dev->name);
1315 }
1316 #if 0
1317 e = create_proc_read_entry("stats-ieee", S_IFREG | S_IRUGO,
1318 priv->dir_dev, proc_get_stats_ieee, dev);
1319
1320 if (!e) {
1321 DMESGE("Unable to initialize "
1322 "/proc/net/rtl8192/%s/stats-ieee\n",
1323 dev->name);
1324 }
1325
1326 #endif
1327
1328 e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO,
1329 priv->dir_dev, proc_get_stats_ap, dev);
1330
1331 if (!e) {
1332 RT_TRACE(COMP_ERR, "Unable to initialize "
1333 "/proc/net/rtl8192/%s/stats-ap\n",
1334 dev->name);
1335 }
1336
1337 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
1338 priv->dir_dev, proc_get_registers, dev);
1339 if (!e) {
1340 RT_TRACE(COMP_ERR, "Unable to initialize "
1341 "/proc/net/rtl8192/%s/registers\n",
1342 dev->name);
1343 }
1344#ifdef RTL8192SU
1345 e = create_proc_read_entry("registers-1", S_IFREG | S_IRUGO,
1346 priv->dir_dev, proc_get_registers_1, dev);
1347 if (!e) {
1348 RT_TRACE(COMP_ERR, "Unable to initialize "
1349 "/proc/net/rtl8192/%s/registers-1\n",
1350 dev->name);
1351 }
1352 e = create_proc_read_entry("registers-2", S_IFREG | S_IRUGO,
1353 priv->dir_dev, proc_get_registers_2, dev);
1354 if (!e) {
1355 RT_TRACE(COMP_ERR, "Unable to initialize "
1356 "/proc/net/rtl8192/%s/registers-2\n",
1357 dev->name);
1358 }
1359 e = create_proc_read_entry("registers-8", S_IFREG | S_IRUGO,
1360 priv->dir_dev, proc_get_registers_8, dev);
1361 if (!e) {
1362 RT_TRACE(COMP_ERR, "Unable to initialize "
1363 "/proc/net/rtl8192/%s/registers-8\n",
1364 dev->name);
1365 }
1366 e = create_proc_read_entry("registers-9", S_IFREG | S_IRUGO,
1367 priv->dir_dev, proc_get_registers_9, dev);
1368 if (!e) {
1369 RT_TRACE(COMP_ERR, "Unable to initialize "
1370 "/proc/net/rtl8192/%s/registers-9\n",
1371 dev->name);
1372 }
1373 e = create_proc_read_entry("registers-a", S_IFREG | S_IRUGO,
1374 priv->dir_dev, proc_get_registers_a, dev);
1375 if (!e) {
1376 RT_TRACE(COMP_ERR, "Unable to initialize "
1377 "/proc/net/rtl8192/%s/registers-a\n",
1378 dev->name);
1379 }
1380 e = create_proc_read_entry("registers-b", S_IFREG | S_IRUGO,
1381 priv->dir_dev, proc_get_registers_b, dev);
1382 if (!e) {
1383 RT_TRACE(COMP_ERR, "Unable to initialize "
1384 "/proc/net/rtl8192/%s/registers-b\n",
1385 dev->name);
1386 }
1387 e = create_proc_read_entry("registers-c", S_IFREG | S_IRUGO,
1388 priv->dir_dev, proc_get_registers_c, dev);
1389 if (!e) {
1390 RT_TRACE(COMP_ERR, "Unable to initialize "
1391 "/proc/net/rtl8192/%s/registers-c\n",
1392 dev->name);
1393 }
1394 e = create_proc_read_entry("registers-d", S_IFREG | S_IRUGO,
1395 priv->dir_dev, proc_get_registers_d, dev);
1396 if (!e) {
1397 RT_TRACE(COMP_ERR, "Unable to initialize "
1398 "/proc/net/rtl8192/%s/registers-d\n",
1399 dev->name);
1400 }
1401 e = create_proc_read_entry("registers-e", S_IFREG | S_IRUGO,
1402 priv->dir_dev, proc_get_registers_e, dev);
1403 if (!e) {
1404 RT_TRACE(COMP_ERR, "Unable to initialize "
1405 "/proc/net/rtl8192/%s/registers-e\n",
1406 dev->name);
1407 }
1408#endif
1409#if 0
1410 e = create_proc_read_entry("cck-registers", S_IFREG | S_IRUGO,
1411 priv->dir_dev, proc_get_cck_reg, dev);
1412 if (!e) {
1413 RT_TRACE(COMP_ERR, "Unable to initialize "
1414 "/proc/net/rtl8192/%s/cck-registers\n",
1415 dev->name);
1416 }
1417
1418 e = create_proc_read_entry("ofdm-registers", S_IFREG | S_IRUGO,
1419 priv->dir_dev, proc_get_ofdm_reg, dev);
1420 if (!e) {
1421 RT_TRACE(COMP_ERR, "Unable to initialize "
1422 "/proc/net/rtl8192/%s/ofdm-registers\n",
1423 dev->name);
1424 }
1425#endif
1426}
1427/****************************************************************************
1428 -----------------------------MISC STUFF-------------------------
1429*****************************************************************************/
1430
1431/* this is only for debugging */
1432void print_buffer(u32 *buffer, int len)
1433{
1434 int i;
1435 u8 *buf =(u8*)buffer;
1436
1437 printk("ASCII BUFFER DUMP (len: %x):\n",len);
1438
1439 for(i=0;i<len;i++)
1440 printk("%c",buf[i]);
1441
1442 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
1443
1444 for(i=0;i<len;i++)
1445 printk("%x",buf[i]);
1446
1447 printk("\n");
1448}
1449
1450//short check_nic_enough_desc(struct net_device *dev, priority_t priority)
1451short check_nic_enough_desc(struct net_device *dev,int queue_index)
1452{
1453 struct r8192_priv *priv = ieee80211_priv(dev);
1454 int used = atomic_read(&priv->tx_pending[queue_index]);
1455
1456 return (used < MAX_TX_URB);
1457}
1458
1459void tx_timeout(struct net_device *dev)
1460{
1461 struct r8192_priv *priv = ieee80211_priv(dev);
1462 //rtl8192_commit(dev);
1463
5f53d8ca 1464 schedule_work(&priv->reset_wq);
5f53d8ca
JC		 1465 //DMESG("TXTIMEOUT");
1466}
1467
1468
1469/* this is only for debug */
1470void dump_eprom(struct net_device *dev)
1471{
1472 int i;
1473 for(i=0; i<63; i++)
1474 RT_TRACE(COMP_EPROM, "EEPROM addr %x : %x", i, eprom_read(dev,i));
1475}
1476
1477/* this is only for debug */
1478void rtl8192_dump_reg(struct net_device *dev)
1479{
1480 int i;
1481 int n;
1482 int max=0x1ff;
1483
1484 RT_TRACE(COMP_PHY, "Dumping NIC register map");
1485
1486 for(n=0;n<=max;)
1487 {
1488 printk( "\nD: %2x> ", n);
1489 for(i=0;i<16 && n<=max;i++,n++)
1490 printk("%2x ",read_nic_byte(dev,n));
1491 }
1492 printk("\n");
1493}
1494
1495/****************************************************************************
1496 ------------------------------HW STUFF---------------------------
1497*****************************************************************************/
1498
1499#if 0
1500void rtl8192_irq_enable(struct net_device *dev)
1501{
1502 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1503 //priv->irq_enabled = 1;
1504/*
1505 write_nic_word(dev,INTA_MASK,INTA_RXOK | INTA_RXDESCERR | INTA_RXOVERFLOW |\
1506 INTA_TXOVERFLOW | INTA_HIPRIORITYDESCERR | INTA_HIPRIORITYDESCOK |\
1507 INTA_NORMPRIORITYDESCERR | INTA_NORMPRIORITYDESCOK |\
1508 INTA_LOWPRIORITYDESCERR | INTA_LOWPRIORITYDESCOK | INTA_TIMEOUT);
1509*/
1510 write_nic_word(dev,INTA_MASK, priv->irq_mask);
1511}
1512
1513
1514void rtl8192_irq_disable(struct net_device *dev)
1515{
1516// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1517
1518 write_nic_word(dev,INTA_MASK,0);
1519 force_pci_posting(dev);
1520// priv->irq_enabled = 0;
1521}
1522#endif
1523
1524void rtl8192_set_mode(struct net_device *dev,int mode)
1525{
1526 u8 ecmd;
1527 ecmd=read_nic_byte(dev, EPROM_CMD);
1528 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
1529 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
1530 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
1531 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
1532 write_nic_byte(dev, EPROM_CMD, ecmd);
1533}
1534
1535
1536void rtl8192_update_msr(struct net_device *dev)
1537{
1538 struct r8192_priv *priv = ieee80211_priv(dev);
1539 u8 msr;
1540
1541 msr = read_nic_byte(dev, MSR);
1542 msr &= ~ MSR_LINK_MASK;
1543
1544 /* do not change in link_state != WLAN_LINK_ASSOCIATED.
1545 * msr must be updated if the state is ASSOCIATING.
1546 * this is intentional and make sense for ad-hoc and
1547 * master (see the create BSS/IBSS func)
1548 */
1549 if (priv->ieee80211->state == IEEE80211_LINKED){
1550
1551 if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
1552 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
1553 else if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1554 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
1555 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
1556 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
1557
1558 }else
1559 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
1560
1561 write_nic_byte(dev, MSR, msr);
1562}
1563
1564void rtl8192_set_chan(struct net_device *dev,short ch)
1565{
1566 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1567// u32 tx;
1568 RT_TRACE(COMP_CH, "=====>%s()====ch:%d\n", __FUNCTION__, ch);
1569 //printk("=====>%s()====ch:%d\n", __FUNCTION__, ch);
1570 priv->chan=ch;
1571 #if 0
1572 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC ||
1573 priv->ieee80211->iw_mode == IW_MODE_MASTER){
1574
1575 priv->ieee80211->link_state = WLAN_LINK_ASSOCIATED;
1576 priv->ieee80211->master_chan = ch;
1577 rtl8192_update_beacon_ch(dev);
1578 }
1579 #endif
1580
1581 /* this hack should avoid frame TX during channel setting*/
1582
1583
1584// tx = read_nic_dword(dev,TX_CONF);
1585// tx &= ~TX_LOOPBACK_MASK;
1586
1587#ifndef LOOP_TEST
1588// write_nic_dword(dev,TX_CONF, tx |( TX_LOOPBACK_MAC<<TX_LOOPBACK_SHIFT));
1589
1590 //need to implement rf set channel here WB
1591
1592 if (priv->rf_set_chan)
1593 priv->rf_set_chan(dev,priv->chan);
1594 mdelay(10);
1595// write_nic_dword(dev,TX_CONF,tx | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT));
1596#endif
1597}
1598
5f53d8ca 1599static void rtl8192_rx_isr(struct urb *urb);
5f53d8ca
JC		 1600
1601u32 get_rxpacket_shiftbytes_819xusb(struct ieee80211_rx_stats *pstats)
1602{
1603
5f53d8ca
JC		 1604 return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize
1605 + pstats->RxBufShift);
1606
1607}
1608static int rtl8192_rx_initiate(struct net_device*dev)
1609{
1610 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1611 struct urb *entry;
1612 struct sk_buff *skb;
1613 struct rtl8192_rx_info *info;
1614
1615 /* nomal packet rx procedure */
1616 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB) {
1617 skb = __dev_alloc_skb(RX_URB_SIZE, GFP_KERNEL);
1618 if (!skb)
1619 break;
5f53d8ca 1620 entry = usb_alloc_urb(0, GFP_KERNEL);
5f53d8ca
JC		 1621 if (!entry) {
1622 kfree_skb(skb);
1623 break;
1624 }
1625// printk("nomal packet IN request!\n");
1626 usb_fill_bulk_urb(entry, priv->udev,
1627 usb_rcvbulkpipe(priv->udev, 3), skb->tail,
1628 RX_URB_SIZE, rtl8192_rx_isr, skb);
1629 info = (struct rtl8192_rx_info *) skb->cb;
1630 info->urb = entry;
1631 info->dev = dev;
1632 info->out_pipe = 3; //denote rx normal packet queue
1633 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1634 usb_submit_urb(entry, GFP_KERNEL);
5f53d8ca
JC		 1635 }
1636
1637 /* command packet rx procedure */
1638 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB + 3) {
1639// printk("command packet IN request!\n");
1640 skb = __dev_alloc_skb(RX_URB_SIZE ,GFP_KERNEL);
1641 if (!skb)
1642 break;
5f53d8ca 1643 entry = usb_alloc_urb(0, GFP_KERNEL);
5f53d8ca
JC		 1644 if (!entry) {
1645 kfree_skb(skb);
1646 break;
1647 }
1648 usb_fill_bulk_urb(entry, priv->udev,
1649 usb_rcvbulkpipe(priv->udev, 9), skb->tail,
1650 RX_URB_SIZE, rtl8192_rx_isr, skb);
1651 info = (struct rtl8192_rx_info *) skb->cb;
1652 info->urb = entry;
1653 info->dev = dev;
1654 info->out_pipe = 9; //denote rx cmd packet queue
1655 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1656 usb_submit_urb(entry, GFP_KERNEL);
5f53d8ca
JC		 1657 }
1658
1659 return 0;
1660}
1661
1662void rtl8192_set_rxconf(struct net_device *dev)
1663{
1664 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1665 u32 rxconf;
1666
1667 rxconf=read_nic_dword(dev,RCR);
1668 rxconf = rxconf &~ MAC_FILTER_MASK;
1669 rxconf = rxconf | RCR_AMF;
1670 rxconf = rxconf | RCR_ADF;
1671 rxconf = rxconf | RCR_AB;
1672 rxconf = rxconf | RCR_AM;
1673 //rxconf = rxconf | RCR_ACF;
1674
1675 if (dev->flags & IFF_PROMISC) {DMESG ("NIC in promisc mode");}
1676
1677 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1678 dev->flags & IFF_PROMISC){
1679 rxconf = rxconf | RCR_AAP;
1680 } /*else if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
1681 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
1682 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
1683 }*/else{
1684 rxconf = rxconf | RCR_APM;
1685 rxconf = rxconf | RCR_CBSSID;
1686 }
1687
1688
1689 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1690 rxconf = rxconf | RCR_AICV;
1691 rxconf = rxconf | RCR_APWRMGT;
1692 }
1693
1694 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1695 rxconf = rxconf | RCR_ACRC32;
1696
1697
1698 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
1699 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
1700 rxconf = rxconf &~ MAX_RX_DMA_MASK;
1701 rxconf = rxconf | ((u32)7<<RCR_MXDMA_OFFSET);
1702
1703// rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
1704 rxconf = rxconf | RCR_ONLYERLPKT;
1705
1706// rxconf = rxconf &~ RCR_CS_MASK;
1707// rxconf = rxconf | (1<<RCR_CS_SHIFT);
1708
1709 write_nic_dword(dev, RCR, rxconf);
1710
1711 #ifdef DEBUG_RX
1712 DMESG("rxconf: %x %x",rxconf ,read_nic_dword(dev,RCR));
1713 #endif
1714}
1715//wait to be removed
1716void rtl8192_rx_enable(struct net_device *dev)
1717{
1718 //u8 cmd;
1719
1720 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1721
1722 rtl8192_rx_initiate(dev);
1723
1724// rtl8192_set_rxconf(dev);
1725#if 0
1726 if(NIC_8187 == priv->card_8187) {
1727 cmd=read_nic_byte(dev,CMD);
1728 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
1729 }
1730 else {
1731 //write_nic_dword(dev, RX_CONF, priv->ReceiveConfig);
1732 }
1733#endif
1734}
1735
1736
1737void rtl8192_tx_enable(struct net_device *dev)
1738{
1739#if 0
1740 u8 cmd;
1741 u8 byte;
1742 u32 txconf;
1743 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1744 //test loopback
1745 // priv->TransmitConfig |= (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1746 if(NIC_8187B == priv->card_8187){
1747 write_nic_dword(dev, TX_CONF, priv->TransmitConfig);
1748 byte = read_nic_byte(dev, MSR);
1749 byte |= MSR_LINK_ENEDCA;
1750 write_nic_byte(dev, MSR, byte);
1751 } else {
1752 byte = read_nic_byte(dev,CW_CONF);
1753 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
1754 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
1755 write_nic_byte(dev, CW_CONF, byte);
1756
1757 byte = read_nic_byte(dev, TX_AGC_CTL);
1758 byte &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
1759 byte &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
1760 byte &= ~(1<<TX_AGC_CTL_FEEDBACK_ANT);
1761 write_nic_byte(dev, TX_AGC_CTL, byte);
1762
1763 txconf= read_nic_dword(dev,TX_CONF);
1764
1765
1766 txconf = txconf &~ TX_LOOPBACK_MASK;
1767
1768#ifndef LOOP_TEST
1769 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT);
1770#else
1771 txconf = txconf | (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1772#endif
1773 txconf = txconf &~ TCR_SRL_MASK;
1774 txconf = txconf &~ TCR_LRL_MASK;
1775
1776 txconf = txconf | (priv->retry_data<<TX_LRLRETRY_SHIFT); // long
1777 txconf = txconf | (priv->retry_rts<<TX_SRLRETRY_SHIFT); // short
1778
1779 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
1780
1781 txconf = txconf &~ TCR_MXDMA_MASK;
1782 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
1783
1784 txconf = txconf | TCR_DISReqQsize;
1785 txconf = txconf | TCR_DISCW;
1786 txconf = txconf &~ TCR_SWPLCPLEN;
1787
1788 txconf=txconf | (1<<TX_NOICV_SHIFT);
1789
1790 write_nic_dword(dev,TX_CONF,txconf);
1791
1792#ifdef DEBUG_TX
1793 DMESG("txconf: %x %x",txconf,read_nic_dword(dev,TX_CONF));
1794#endif
1795
1796 cmd=read_nic_byte(dev,CMD);
1797 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1798 }
1799#endif
1800}
1801
1802#if 0
1803void rtl8192_beacon_tx_enable(struct net_device *dev)
1804{
1805 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1806 priv->dma_poll_mask &=~(1<<TX_DMA_STOP_BEACON_SHIFT);
1807 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1808 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1809 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1810}
1811
1812
1813void rtl8192_
1814_disable(struct net_device *dev)
1815{
1816 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1817 priv->dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
1818 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1819 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1820 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1821}
1822
1823#endif
1824
1825
1826void rtl8192_rtx_disable(struct net_device *dev)
1827{
1828 u8 cmd;
1829 struct r8192_priv *priv = ieee80211_priv(dev);
1830 struct sk_buff *skb;
1831 struct rtl8192_rx_info *info;
1832
1833 cmd=read_nic_byte(dev,CMDR);
1834 write_nic_byte(dev, CMDR, cmd &~ \
1835 (CR_TE|CR_RE));
1836 force_pci_posting(dev);
1837 mdelay(10);
1838
1839 while ((skb = __skb_dequeue(&priv->rx_queue))) {
1840 info = (struct rtl8192_rx_info *) skb->cb;
1841 if (!info->urb)
1842 continue;
1843
1844 usb_kill_urb(info->urb);
1845 kfree_skb(skb);
1846 }
1847
1848 if (skb_queue_len(&priv->skb_queue)) {
1849 printk(KERN_WARNING "skb_queue not empty\n");
1850 }
1851
1852 skb_queue_purge(&priv->skb_queue);
1853 return;
1854}
1855
1856
1857int alloc_tx_beacon_desc_ring(struct net_device *dev, int count)
1858{
1859 #if 0
1860 int i;
1861 u32 *tmp;
1862 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1863
1864 priv->txbeaconring = (u32*)pci_alloc_consistent(priv->pdev,
1865 sizeof(u32)*8*count,
1866 &priv->txbeaconringdma);
1867 if (!priv->txbeaconring) return -1;
1868 for (tmp=priv->txbeaconring,i=0;i<count;i++){
1869 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1870 /*
1871 *(tmp+2) = (u32)dma_tmp;
1872 *(tmp+3) = bufsize;
1873 */
1874 if(i+1<count)
1875 *(tmp+4) = (u32)priv->txbeaconringdma+((i+1)*8*4);
1876 else
1877 *(tmp+4) = (u32)priv->txbeaconringdma;
1878
1879 tmp=tmp+8;
1880 }
1881 #endif
1882 return 0;
1883}
1884
1885#if 0
1886void rtl8192_reset(struct net_device *dev)
1887{
1888
1889 //struct r8192_priv *priv = ieee80211_priv(dev);
1890 //u8 cr;
1891
1892
1893 /* make sure the analog power is on before
1894 * reset, otherwise reset may fail
1895 */
1896#if 0
1897 if(NIC_8187 == priv->card_8187) {
1898 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1899 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1900 rtl8192_irq_disable(dev);
1901 mdelay(200);
1902 write_nic_byte_E(dev,0x18,0x10);
1903 write_nic_byte_E(dev,0x18,0x11);
1904 write_nic_byte_E(dev,0x18,0x00);
1905 mdelay(200);
1906 }
1907#endif
1908 printk("=====>reset?\n");
1909#if 0
1910 cr=read_nic_byte(dev,CMD);
1911 cr = cr & 2;
1912 cr = cr | (1<<CMD_RST_SHIFT);
1913 write_nic_byte(dev,CMD,cr);
1914
1915 force_pci_posting(dev);
1916
1917 mdelay(200);
1918
1919 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1920 RT_TRACE(COMP_ERR, "Card reset timeout!\n");
1921 else
1922 RT_TRACE(COMP_DOWN, "Card successfully reset\n");
1923#endif
1924#if 0
1925 if(NIC_8187 == priv->card_8187) {
1926
1927 printk("This is RTL8187 Reset procedure\n");
1928 rtl8192_set_mode(dev,EPROM_CMD_LOAD);
1929 force_pci_posting(dev);
1930 mdelay(200);
1931
1932 /* after the eeprom load cycle, make sure we have
1933 * correct anaparams
1934 */
1935 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1936 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1937 }
1938 else
1939#endif
1940 printk("This is RTL8187B Reset procedure\n");
1941
1942}
1943#endif
1944inline u16 ieeerate2rtlrate(int rate)
1945{
1946 switch(rate){
1947 case 10:
1948 return 0;
1949 case 20:
1950 return 1;
1951 case 55:
1952 return 2;
1953 case 110:
1954 return 3;
1955 case 60:
1956 return 4;
1957 case 90:
1958 return 5;
1959 case 120:
1960 return 6;
1961 case 180:
1962 return 7;
1963 case 240:
1964 return 8;
1965 case 360:
1966 return 9;
1967 case 480:
1968 return 10;
1969 case 540:
1970 return 11;
1971 default:
1972 return 3;
1973
1974 }
1975}
1976static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540};
1977inline u16 rtl8192_rate2rate(short rate)
1978{
1979 if (rate >11) return 0;
1980 return rtl_rate[rate];
1981}
1982
5f53d8ca 1983static void rtl8192_rx_isr(struct urb *urb)
5f53d8ca
JC		 1984{
1985 struct sk_buff *skb = (struct sk_buff *) urb->context;
1986 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
1987 struct net_device *dev = info->dev;
1988 struct r8192_priv *priv = ieee80211_priv(dev);
1989 int out_pipe = info->out_pipe;
1990 int err;
1991 if(!priv->up)
1992 return;
1993 if (unlikely(urb->status)) {
1994 info->urb = NULL;
1995 priv->stats.rxstaterr++;
1996 priv->ieee80211->stats.rx_errors++;
1997 usb_free_urb(urb);
1998 // printk("%s():rx status err\n",__FUNCTION__);
1999 return;
2000 }
1ec9e48d 2001
5f53d8ca 2002 skb_unlink(skb, &priv->rx_queue);
5f53d8ca
JC		 2003 skb_put(skb, urb->actual_length);
2004
2005 skb_queue_tail(&priv->skb_queue, skb);
2006 tasklet_schedule(&priv->irq_rx_tasklet);
2007
2008 skb = dev_alloc_skb(RX_URB_SIZE);
2009 if (unlikely(!skb)) {
2010 usb_free_urb(urb);
2011 printk("%s():can,t alloc skb\n",__FUNCTION__);
2012 /* TODO check rx queue length and refill *somewhere* */
2013 return;
2014 }
2015
2016 usb_fill_bulk_urb(urb, priv->udev,
2017 usb_rcvbulkpipe(priv->udev, out_pipe), skb->tail,
2018 RX_URB_SIZE, rtl8192_rx_isr, skb);
2019
2020 info = (struct rtl8192_rx_info *) skb->cb;
2021 info->urb = urb;
2022 info->dev = dev;
2023 info->out_pipe = out_pipe;
2024
2025 urb->transfer_buffer = skb->tail;
2026 urb->context = skb;
2027 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 2028 err = usb_submit_urb(urb, GFP_ATOMIC);
5f53d8ca
JC		 2029 if(err && err != EPERM)
2030 printk("can not submit rxurb, err is %x,URB status is %x\n",err,urb->status);
2031}
2032
2033u32
2034rtl819xusb_rx_command_packet(
2035 struct net_device *dev,
2036 struct ieee80211_rx_stats *pstats
2037 )
2038{
2039 u32 status;
2040
2041 //RT_TRACE(COMP_RECV, DBG_TRACE, ("---> RxCommandPacketHandle819xUsb()\n"));
2042
2043 status = cmpk_message_handle_rx(dev, pstats);
2044 if (status)
2045 {
2046 DMESG("rxcommandpackethandle819xusb: It is a command packet\n");
2047 }
2048 else
2049 {
2050 //RT_TRACE(COMP_RECV, DBG_TRACE, ("RxCommandPacketHandle819xUsb: It is not a command packet\n"));
2051 }
2052
2053 //RT_TRACE(COMP_RECV, DBG_TRACE, ("<--- RxCommandPacketHandle819xUsb()\n"));
2054 return status;
2055}
2056
2057#if 0
2058void rtl8192_tx_queues_stop(struct net_device *dev)
2059{
2060 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2061 u8 dma_poll_mask = (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2062 dma_poll_mask |= (1<<TX_DMA_STOP_HIPRIORITY_SHIFT);
2063 dma_poll_mask |= (1<<TX_DMA_STOP_NORMPRIORITY_SHIFT);
2064 dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
2065
2066 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2067 write_nic_byte(dev,TX_DMA_POLLING,dma_poll_mask);
2068 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2069}
2070#endif
2071
2072void rtl8192_data_hard_stop(struct net_device *dev)
2073{
2074 //FIXME !!
2075 #if 0
2076 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2077 priv->dma_poll_mask |= (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2078 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2079 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
2080 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2081 #endif
2082}
2083
2084
2085void rtl8192_data_hard_resume(struct net_device *dev)
2086{
2087 // FIXME !!
2088 #if 0
2089 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2090 priv->dma_poll_mask &= ~(1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2091 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2092 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
2093 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2094 #endif
2095}
2096
2097/* this function TX data frames when the ieee80211 stack requires this.
2098 * It checks also if we need to stop the ieee tx queue, eventually do it
2099 */
2100void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate)
2101{
2102 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2103 int ret;
2104 unsigned long flags;
2105 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2106 u8 queue_index = tcb_desc->queue_index;
2107
2108 /* shall not be referred by command packet */
2109 assert(queue_index != TXCMD_QUEUE);
2110
2111 spin_lock_irqsave(&priv->tx_lock,flags);
2112
2113 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
2114// tcb_desc->RATRIndex = 7;
2115// tcb_desc->bTxDisableRateFallBack = 1;
2116// tcb_desc->bTxUseDriverAssingedRate = 1;
2117 tcb_desc->bTxEnableFwCalcDur = 1;
2118 skb_push(skb, priv->ieee80211->tx_headroom);
2119 ret = priv->ops->rtl819x_tx(dev, skb);
2120
2121 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2122 //priv->ieee80211->stats.tx_packets++;
2123
2124 spin_unlock_irqrestore(&priv->tx_lock,flags);
2125
2126// return ret;
2127 return;
2128}
2129
2130/* This is a rough attempt to TX a frame
2131 * This is called by the ieee 80211 stack to TX management frames.
2132 * If the ring is full packet are dropped (for data frame the queue
2133 * is stopped before this can happen).
2134 */
2135int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
2136{
2137 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2138 int ret;
2139 unsigned long flags;
2140 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2141 u8 queue_index = tcb_desc->queue_index;
2142
2143
2144 spin_lock_irqsave(&priv->tx_lock,flags);
2145
2146 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
2147 if(queue_index == TXCMD_QUEUE) {
2148 skb_push(skb, USB_HWDESC_HEADER_LEN);
2149 priv->ops->rtl819x_tx_cmd(dev, skb);
2150 ret = 1;
2151 spin_unlock_irqrestore(&priv->tx_lock,flags);
2152 return ret;
2153 } else {
2154 skb_push(skb, priv->ieee80211->tx_headroom);
2155 ret = priv->ops->rtl819x_tx(dev, skb);
2156 }
2157
2158 spin_unlock_irqrestore(&priv->tx_lock,flags);
2159
2160 return ret;
2161}
2162
2163
2164void rtl8192_try_wake_queue(struct net_device *dev, int pri);
2165
5f53d8ca 2166
5f53d8ca 2167static void rtl8192_tx_isr(struct urb *tx_urb)
5f53d8ca
JC		 2168{
2169 struct sk_buff *skb = (struct sk_buff*)tx_urb->context;
2170 struct net_device *dev = NULL;
2171 struct r8192_priv *priv = NULL;
2172 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2173 u8 queue_index = tcb_desc->queue_index;
2174// bool bToSend0Byte;
2175// u16 BufLen = skb->len;
2176
2177 memcpy(&dev,(struct net_device*)(skb->cb),sizeof(struct net_device*));
2178 priv = ieee80211_priv(dev);
2179
2180 if(tcb_desc->queue_index != TXCMD_QUEUE) {
2181 if(tx_urb->status == 0) {
2182 // dev->trans_start = jiffies;
2183 // As act as station mode, destion shall be unicast address.
2184 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2185 //priv->ieee80211->stats.tx_packets++;
2186 priv->stats.txoktotal++;
2187 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
2188 priv->stats.txbytesunicast += (skb->len - priv->ieee80211->tx_headroom);
2189 } else {
2190 priv->ieee80211->stats.tx_errors++;
2191 //priv->stats.txmanageerr++;
2192 /* TODO */
2193 }
2194 }
2195
2196 /* free skb and tx_urb */
2197 if(skb != NULL) {
2198 dev_kfree_skb_any(skb);
2199 usb_free_urb(tx_urb);
2200 atomic_dec(&priv->tx_pending[queue_index]);
2201 }
2202
2203#if 0 //we need to send zero byte packet just after 512 byte(64 byte)packet is transmitted, or we will halt. It will greatly reduced available page in FW, and ruin our throughput. WB 2008.08.27
2204 if(BufLen > 0 && ((BufLen % 512 == 0)||(BufLen % 64 == 0))) {
2205 bToSend0Byte = true;
2206 }
2207
2208 bToSend0Byte = false;
2209 //
2210 // Note that, we at most handle 1 MPDU to send here, either
2211 // fragment or MPDU in wait queue.
2212 //
2213 if(!bToSend0Byte)
2214#endif
2215 {
2216 //
2217 // Handle HW Beacon:
2218 // We had transfer our beacon frame to host controler at this moment.
2219 //
2220#if 0
2221 if(tcb_desc->tx_queue == BEACON_QUEUE)
2222 {
2223 priv->bSendingBeacon = FALSE;
2224 }
2225#endif
2226 //
2227 // Caution:
2228 // Handling the wait queue of command packets.
2229 // For Tx command packets, we must not do TCB fragment because it is not handled right now.
2230 // We must cut the packets to match the size of TX_CMD_PKT before we send it.
2231 //
2232 if (queue_index == MGNT_QUEUE){
2233 if (priv->ieee80211->ack_tx_to_ieee){
2234 if (rtl8192_is_tx_queue_empty(dev)){
2235 priv->ieee80211->ack_tx_to_ieee = 0;
2236 ieee80211_ps_tx_ack(priv->ieee80211, 1);
2237 }
2238 }
2239 }
2240 /* Handle MPDU in wait queue. */
2241 if(queue_index != BEACON_QUEUE) {
2242 /* Don't send data frame during scanning.*/
2243 if((skb_queue_len(&priv->ieee80211->skb_waitQ[queue_index]) != 0)&&\
2244 (!(priv->ieee80211->queue_stop))) {
2245 if(NULL != (skb = skb_dequeue(&(priv->ieee80211->skb_waitQ[queue_index]))))
2246 priv->ieee80211->softmac_hard_start_xmit(skb, dev);
2247
2248 return; //modified by david to avoid further processing AMSDU
2249 }
5f53d8ca
JC		 2250 }
2251 }
2252
2253#if 0
2254 else
2255 {
2256 RT_TRACE( COMP_SEND,"HalUsbOutComplete(%d): bToSend0Byte.\n", PipeIndex);
2257
2258 //
2259 // In this case, we don't return skb now.
2260 // It will be returned when the 0-byte request completed.
2261 //
2262
2263 //
2264 // Bulk out an 0-byte padding transfer.
2265 //
2266 HalUsbOut0Byte(pAdapter, PipeIndex, skb);
2267 }
2268
2269#endif
2270}
2271
2272void rtl8192_beacon_stop(struct net_device *dev)
2273{
2274 u8 msr, msrm, msr2;
2275 struct r8192_priv *priv = ieee80211_priv(dev);
2276
2277 msr = read_nic_byte(dev, MSR);
2278 msrm = msr & MSR_LINK_MASK;
2279 msr2 = msr & ~MSR_LINK_MASK;
2280
2281 if(NIC_8192U == priv->card_8192) {
2282 usb_kill_urb(priv->rx_urb[MAX_RX_URB]);
2283 }
2284 if ((msrm == (MSR_LINK_ADHOC<<MSR_LINK_SHIFT) ||
2285 (msrm == (MSR_LINK_MASTER<<MSR_LINK_SHIFT)))){
2286 write_nic_byte(dev, MSR, msr2 | MSR_LINK_NONE);
2287 write_nic_byte(dev, MSR, msr);
2288 }
2289}
2290
2291void rtl8192_config_rate(struct net_device* dev, u16* rate_config)
2292{
2293 struct r8192_priv *priv = ieee80211_priv(dev);
2294 struct ieee80211_network *net;
2295 u8 i=0, basic_rate = 0;
2296 net = & priv->ieee80211->current_network;
2297
2298 for (i=0; i<net->rates_len; i++)
2299 {
2300 basic_rate = net->rates[i]&0x7f;
2301 switch(basic_rate)
2302 {
2303 case MGN_1M: *rate_config |= RRSR_1M; break;
2304 case MGN_2M: *rate_config |= RRSR_2M; break;
2305 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2306 case MGN_11M: *rate_config |= RRSR_11M; break;
2307 case MGN_6M: *rate_config |= RRSR_6M; break;
2308 case MGN_9M: *rate_config |= RRSR_9M; break;
2309 case MGN_12M: *rate_config |= RRSR_12M; break;
2310 case MGN_18M: *rate_config |= RRSR_18M; break;
2311 case MGN_24M: *rate_config |= RRSR_24M; break;
2312 case MGN_36M: *rate_config |= RRSR_36M; break;
2313 case MGN_48M: *rate_config |= RRSR_48M; break;
2314 case MGN_54M: *rate_config |= RRSR_54M; break;
2315 }
2316 }
2317 for (i=0; i<net->rates_ex_len; i++)
2318 {
2319 basic_rate = net->rates_ex[i]&0x7f;
2320 switch(basic_rate)
2321 {
2322 case MGN_1M: *rate_config |= RRSR_1M; break;
2323 case MGN_2M: *rate_config |= RRSR_2M; break;
2324 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2325 case MGN_11M: *rate_config |= RRSR_11M; break;
2326 case MGN_6M: *rate_config |= RRSR_6M; break;
2327 case MGN_9M: *rate_config |= RRSR_9M; break;
2328 case MGN_12M: *rate_config |= RRSR_12M; break;
2329 case MGN_18M: *rate_config |= RRSR_18M; break;
2330 case MGN_24M: *rate_config |= RRSR_24M; break;
2331 case MGN_36M: *rate_config |= RRSR_36M; break;
2332 case MGN_48M: *rate_config |= RRSR_48M; break;
2333 case MGN_54M: *rate_config |= RRSR_54M; break;
2334 }
2335 }
2336}
2337
2338
2339#define SHORT_SLOT_TIME 9
2340#define NON_SHORT_SLOT_TIME 20
2341
2342void rtl8192_update_cap(struct net_device* dev, u16 cap)
2343{
2344 //u32 tmp = 0;
2345 struct r8192_priv *priv = ieee80211_priv(dev);
2346 struct ieee80211_network *net = &priv->ieee80211->current_network;
2347 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
2348
2349 //LZM MOD 090303 HW_VAR_ACK_PREAMBLE
2350#ifdef RTL8192SU
2351 if(0)
2352 {
2353 u8 tmp = 0;
2354 tmp = ((priv->nCur40MhzPrimeSC) << 5);
2355 if (priv->short_preamble)
2356 tmp |= 0x80;
2357 write_nic_byte(dev, RRSR+2, tmp);
2358 }
2359#else
2360 {
2361 u32 tmp = 0;
2362 tmp = priv->basic_rate;
2363 if (priv->short_preamble)
2364 tmp |= BRSR_AckShortPmb;
2365 write_nic_dword(dev, RRSR, tmp);
2366 }
2367#endif
2368
2369 if (net->mode & (IEEE_G|IEEE_N_24G))
2370 {
2371 u8 slot_time = 0;
2372 if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime))
2373 {//short slot time
2374 slot_time = SHORT_SLOT_TIME;
2375 }
2376 else //long slot time
2377 slot_time = NON_SHORT_SLOT_TIME;
2378 priv->slot_time = slot_time;
2379 write_nic_byte(dev, SLOT_TIME, slot_time);
2380 }
2381
2382}
2383void rtl8192_net_update(struct net_device *dev)
2384{
2385
2386 struct r8192_priv *priv = ieee80211_priv(dev);
2387 struct ieee80211_network *net;
2388 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
2389 u16 rate_config = 0;
2390 net = & priv->ieee80211->current_network;
2391
2392 rtl8192_config_rate(dev, &rate_config);
2393 priv->basic_rate = rate_config &= 0x15f;
2394
2395 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
2396 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
2397 //for(i=0;i<ETH_ALEN;i++)
2398 // write_nic_byte(dev,BSSID+i,net->bssid[i]);
2399
2400 rtl8192_update_msr(dev);
2401// rtl8192_update_cap(dev, net->capability);
2402 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
2403 {
2404 write_nic_word(dev, ATIMWND, 2);
2405 write_nic_word(dev, BCN_DMATIME, 1023);
2406 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
2407// write_nic_word(dev, BcnIntTime, 100);
2408 write_nic_word(dev, BCN_DRV_EARLY_INT, 1);
2409 write_nic_byte(dev, BCN_ERR_THRESH, 100);
2410 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
2411 // TODO: BcnIFS may required to be changed on ASIC
2412 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
2413
2414 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
2415 }
2416
2417
2418
2419}
2420
2421//temporary hw beacon is not used any more.
2422//open it when necessary
2423#if 1
2424void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate)
2425{
2426
2427#if 0
2428 struct r8192_priv *priv = ieee80211_priv(dev);
2429 struct sk_buff *skb;
2430 int i = 0;
2431 //u8 cr;
2432
2433 rtl8192_net_update(dev);
2434
2435 skb = ieee80211_get_beacon(priv->ieee80211);
2436 if(!skb){
2437 DMESG("not enought memory for allocating beacon");
2438 return;
2439 }
2440
2441
2442 write_nic_byte(dev, BQREQ, read_nic_byte(dev, BQREQ) | (1<<7));
2443
2444 i=0;
2445 //while(!read_nic_byte(dev,BQREQ & (1<<7)))
2446 while( (read_nic_byte(dev, BQREQ) & (1<<7)) == 0 )
2447 {
2448 msleep_interruptible_rtl(HZ/2);
2449 if(i++ > 10){
2450 DMESGW("get stuck to wait HW beacon to be ready");
2451 return ;
2452 }
2453 }
2454 skb->cb[0] = NORM_PRIORITY;
2455 skb->cb[1] = 0; //morefragment = 0
2456 skb->cb[2] = ieeerate2rtlrate(tx_rate);
2457
2458 rtl8192_tx(dev,skb);
2459
2460#endif
2461}
2462#endif
2463inline u8 rtl8192_IsWirelessBMode(u16 rate)
2464{
2465 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
2466 return 1;
2467 else return 0;
2468}
2469
2470u16 N_DBPSOfRate(u16 DataRate);
2471
2472u16 ComputeTxTime(
2473 u16 FrameLength,
2474 u16 DataRate,
2475 u8 bManagementFrame,
2476 u8 bShortPreamble
2477)
2478{
2479 u16 FrameTime;
2480 u16 N_DBPS;
2481 u16 Ceiling;
2482
2483 if( rtl8192_IsWirelessBMode(DataRate) )
2484 {
2485 if( bManagementFrame || !bShortPreamble || DataRate == 10 )
2486 { // long preamble
2487 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
2488 }
2489 else
2490 { // Short preamble
2491 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
2492 }
2493 if( ( FrameLength*8 % (DataRate/10) ) != 0 ) //Get the Ceilling
2494 FrameTime ++;
2495 } else { //802.11g DSSS-OFDM PLCP length field calculation.
2496 N_DBPS = N_DBPSOfRate(DataRate);
2497 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
2498 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
2499 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
2500 }
2501 return FrameTime;
2502}
2503
2504u16 N_DBPSOfRate(u16 DataRate)
2505{
2506 u16 N_DBPS = 24;
2507
2508 switch(DataRate)
2509 {
2510 case 60:
2511 N_DBPS = 24;
2512 break;
2513
2514 case 90:
2515 N_DBPS = 36;
2516 break;
2517
2518 case 120:
2519 N_DBPS = 48;
2520 break;
2521
2522 case 180:
2523 N_DBPS = 72;
2524 break;
2525
2526 case 240:
2527 N_DBPS = 96;
2528 break;
2529
2530 case 360:
2531 N_DBPS = 144;
2532 break;
2533
2534 case 480:
2535 N_DBPS = 192;
2536 break;
2537
2538 case 540:
2539 N_DBPS = 216;
2540 break;
2541
2542 default:
2543 break;
2544 }
2545
2546 return N_DBPS;
2547}
2548
2549void rtl819xU_cmd_isr(struct urb *tx_cmd_urb, struct pt_regs *regs)
2550{
2551#if 0
2552 struct net_device *dev = (struct net_device*)tx_cmd_urb->context;
2553 struct r8192_priv *priv = ieee80211_priv(dev);
2554 int last_init_packet = 0;
2555 u8 *ptr_cmd_buf;
2556 u16 cmd_buf_len;
2557
2558 if(tx_cmd_urb->status != 0) {
2559 priv->pFirmware.firmware_seg_index = 0; //only begin transter, should it can be set to 1
2560 }
2561
2562 /* Free the urb and the corresponding buf for common Tx cmd packet, or
2563 * last segment of each firmware img.
2564 */
2565 if((priv->pFirmware.firmware_seg_index == 0) ||(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum)) {
2566 priv->pFirmware.firmware_seg_index = 0;//only begin transter, should it can be set to 1
2567 } else {
2568 /* prepare for last transfer */
2569 /* update some infomation for */
2570 /* last segment of the firmware img need indicate to device */
2571 priv->pFirmware.firmware_seg_index++;
2572 if(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum) {
2573 last_init_packet = 1;
2574 }
2575
2576 cmd_buf_len = priv->pFirmware.firmware_seg_container[priv->pFirmware.firmware_seg_index-1].seg_size;
2577 ptr_cmd_buf = priv->pFfirmware.firmware_seg_container[priv->pFfirmware.firmware_seg_index-1].seg_ptr;
2578 rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT);
2579 }
2580
2581 kfree(tx_cmd_urb->transfer_buffer);
2582#endif
2583 usb_free_urb(tx_cmd_urb);
2584}
2585
2586unsigned int txqueue2outpipe(struct r8192_priv* priv,unsigned int tx_queue) {
2587
2588 if(tx_queue >= 9)
2589 {
2590 RT_TRACE(COMP_ERR,"%s():Unknown queue ID!!!\n",__FUNCTION__);
2591 return 0x04;
2592 }
2593 return priv->txqueue_to_outpipemap[tx_queue];
2594}
2595
2596#ifdef RTL8192SU
2597short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
2598{
2599 struct r8192_priv *priv = ieee80211_priv(dev);
2600 int status;
2601 struct urb *tx_urb;
2602 unsigned int idx_pipe;
2603 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
2604 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2605 u8 queue_index = tcb_desc->queue_index;
2606 u32 PktSize = 0;
2607
2608 //printk("\n %s::::::::::::::::::::::queue_index = %d\n",__FUNCTION__, queue_index);
2609 atomic_inc(&priv->tx_pending[queue_index]);
2610
5f53d8ca 2611 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2612 if(!tx_urb){
2613 dev_kfree_skb(skb);
2614 return -ENOMEM;
2615 }
2616
2617 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
2618
2619 /* Tx descriptor ought to be set according to the skb->cb */
2620 pdesc->LINIP = tcb_desc->bLastIniPkt;
2621 PktSize = (u16)(skb->len - USB_HWDESC_HEADER_LEN);
2622 pdesc->PktSize = PktSize;
2623 //printk("PKTSize = %d %x\n",pdesc->PktSize,pdesc->PktSize);
2624 //----------------------------------------------------------------------------
2625 // Fill up USB_OUT_CONTEXT.
2626 //----------------------------------------------------------------------------
2627 // Get index to out pipe from specified QueueID.
2628 idx_pipe = txqueue2outpipe(priv,queue_index);
2629 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,queue_index,priv->RtOutPipes[idx_pipe]);
2630
2631#ifdef JOHN_DUMP_TXDESC
2632 int i;
2633 printk("Len = %d\n", skb->len);
2634 for (i = 0; i < 8; i++)
2635 printk("%2.2x ", *((u8*)skb->data+i));
2636 printk("\n");
2637#endif
2638
2639 usb_fill_bulk_urb(tx_urb,
2640 priv->udev,
2641 usb_sndbulkpipe(priv->udev,priv->RtOutPipes[idx_pipe]),
2642 skb->data,
2643 skb->len,
2644 rtl8192_tx_isr,
2645 skb);
2646
5f53d8ca 2647 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 2648 if (!status){
2649 return 0;
2650 }else{
2651 printk("Error TX CMD URB, error %d",
2652 status);
2653 return -1;
2654 }
2655}
2656#else
2657short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
2658{
2659 struct r8192_priv *priv = ieee80211_priv(dev);
2660 //u8 *tx;
2661 int status;
2662 struct urb *tx_urb;
2663 //int urb_buf_len;
2664 unsigned int idx_pipe;
2665 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
2666 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2667 u8 queue_index = tcb_desc->queue_index;
2668
2669 //printk("\n %s::queue_index = %d\n",__FUNCTION__, queue_index);
2670 atomic_inc(&priv->tx_pending[queue_index]);
1ec9e48d 2671
5f53d8ca 2672 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2673 if(!tx_urb){
2674 dev_kfree_skb(skb);
2675 return -ENOMEM;
2676 }
2677
2678 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
2679 /* Tx descriptor ought to be set according to the skb->cb */
2680 pdesc->FirstSeg = 1;//bFirstSeg;
2681 pdesc->LastSeg = 1;//bLastSeg;
2682 pdesc->CmdInit = tcb_desc->bCmdOrInit;
2683 pdesc->TxBufferSize = tcb_desc->txbuf_size;
2684 pdesc->OWN = 1;
2685 pdesc->LINIP = tcb_desc->bLastIniPkt;
2686
2687 //----------------------------------------------------------------------------
2688 // Fill up USB_OUT_CONTEXT.
2689 //----------------------------------------------------------------------------
2690 // Get index to out pipe from specified QueueID.
5f53d8ca 2691 idx_pipe = txqueue2outpipe(priv,queue_index);
5f53d8ca
JC		 2692#ifdef JOHN_DUMP_TXDESC
2693 int i;
2694 printk("<Tx descriptor>--rate %x---",rate);
2695 for (i = 0; i < 8; i++)
2696 printk("%8x ", tx[i]);
2697 printk("\n");
2698#endif
2699 usb_fill_bulk_urb(tx_urb,priv->udev, usb_sndbulkpipe(priv->udev,idx_pipe), \
2700 skb->data, skb->len, rtl8192_tx_isr, skb);
2701
5f53d8ca 2702 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 2703 if (!status){
2704 return 0;
2705 }else{
2706 DMESGE("Error TX CMD URB, error %d",
2707 status);
2708 return -1;
2709 }
2710}
2711#endif
2712
2713/*
2714 * Mapping Software/Hardware descriptor queue id to "Queue Select Field"
2715 * in TxFwInfo data structure
2716 * 2006.10.30 by Emily
2717 *
2718 * \param QUEUEID Software Queue
2719*/
2720u8 MapHwQueueToFirmwareQueue(u8 QueueID)
2721{
2722 u8 QueueSelect = 0x0; //defualt set to
2723
2724 switch(QueueID) {
2725 case BE_QUEUE:
2726 QueueSelect = QSLT_BE; //or QSelect = pTcb->priority;
2727 break;
2728
2729 case BK_QUEUE:
2730 QueueSelect = QSLT_BK; //or QSelect = pTcb->priority;
2731 break;
2732
2733 case VO_QUEUE:
2734 QueueSelect = QSLT_VO; //or QSelect = pTcb->priority;
2735 break;
2736
2737 case VI_QUEUE:
2738 QueueSelect = QSLT_VI; //or QSelect = pTcb->priority;
2739 break;
2740 case MGNT_QUEUE:
2741 QueueSelect = QSLT_MGNT;
2742 break;
2743
2744 case BEACON_QUEUE:
2745 QueueSelect = QSLT_BEACON;
2746 break;
2747
2748 // TODO: 2006.10.30 mark other queue selection until we verify it is OK
2749 // TODO: Remove Assertions
2750//#if (RTL819X_FPGA_VER & RTL819X_FPGA_GUANGAN_070502)
2751 case TXCMD_QUEUE:
2752 QueueSelect = QSLT_CMD;
2753 break;
2754//#endif
2755 case HIGH_QUEUE:
2756 QueueSelect = QSLT_HIGH;
2757 break;
2758
2759 default:
2760 RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID);
2761 break;
2762 }
2763 return QueueSelect;
2764}
2765
2766#ifdef RTL8192SU
2767u8 MRateToHwRate8190Pci(u8 rate)
2768{
2769 u8 ret = DESC92S_RATE1M;
2770
2771 switch(rate)
2772 {
2773 // CCK and OFDM non-HT rates
2774 case MGN_1M: ret = DESC92S_RATE1M; break;
2775 case MGN_2M: ret = DESC92S_RATE2M; break;
2776 case MGN_5_5M: ret = DESC92S_RATE5_5M; break;
2777 case MGN_11M: ret = DESC92S_RATE11M; break;
2778 case MGN_6M: ret = DESC92S_RATE6M; break;
2779 case MGN_9M: ret = DESC92S_RATE9M; break;
2780 case MGN_12M: ret = DESC92S_RATE12M; break;
2781 case MGN_18M: ret = DESC92S_RATE18M; break;
2782 case MGN_24M: ret = DESC92S_RATE24M; break;
2783 case MGN_36M: ret = DESC92S_RATE36M; break;
2784 case MGN_48M: ret = DESC92S_RATE48M; break;
2785 case MGN_54M: ret = DESC92S_RATE54M; break;
2786
2787 // HT rates since here
2788 case MGN_MCS0: ret = DESC92S_RATEMCS0; break;
2789 case MGN_MCS1: ret = DESC92S_RATEMCS1; break;
2790 case MGN_MCS2: ret = DESC92S_RATEMCS2; break;
2791 case MGN_MCS3: ret = DESC92S_RATEMCS3; break;
2792 case MGN_MCS4: ret = DESC92S_RATEMCS4; break;
2793 case MGN_MCS5: ret = DESC92S_RATEMCS5; break;
2794 case MGN_MCS6: ret = DESC92S_RATEMCS6; break;
2795 case MGN_MCS7: ret = DESC92S_RATEMCS7; break;
2796 case MGN_MCS8: ret = DESC92S_RATEMCS8; break;
2797 case MGN_MCS9: ret = DESC92S_RATEMCS9; break;
2798 case MGN_MCS10: ret = DESC92S_RATEMCS10; break;
2799 case MGN_MCS11: ret = DESC92S_RATEMCS11; break;
2800 case MGN_MCS12: ret = DESC92S_RATEMCS12; break;
2801 case MGN_MCS13: ret = DESC92S_RATEMCS13; break;
2802 case MGN_MCS14: ret = DESC92S_RATEMCS14; break;
2803 case MGN_MCS15: ret = DESC92S_RATEMCS15; break;
2804
2805 // Set the highest SG rate
2806 case MGN_MCS0_SG:
2807 case MGN_MCS1_SG:
2808 case MGN_MCS2_SG:
2809 case MGN_MCS3_SG:
2810 case MGN_MCS4_SG:
2811 case MGN_MCS5_SG:
2812 case MGN_MCS6_SG:
2813 case MGN_MCS7_SG:
2814 case MGN_MCS8_SG:
2815 case MGN_MCS9_SG:
2816 case MGN_MCS10_SG:
2817 case MGN_MCS11_SG:
2818 case MGN_MCS12_SG:
2819 case MGN_MCS13_SG:
2820 case MGN_MCS14_SG:
2821 case MGN_MCS15_SG:
2822 {
2823 ret = DESC92S_RATEMCS15_SG;
2824 break;
2825 }
2826
2827 default: break;
2828 }
2829 return ret;
2830}
2831#else
2832u8 MRateToHwRate8190Pci(u8 rate)
2833{
2834 u8 ret = DESC90_RATE1M;
2835
2836 switch(rate) {
2837 case MGN_1M: ret = DESC90_RATE1M; break;
2838 case MGN_2M: ret = DESC90_RATE2M; break;
2839 case MGN_5_5M: ret = DESC90_RATE5_5M; break;
2840 case MGN_11M: ret = DESC90_RATE11M; break;
2841 case MGN_6M: ret = DESC90_RATE6M; break;
2842 case MGN_9M: ret = DESC90_RATE9M; break;
2843 case MGN_12M: ret = DESC90_RATE12M; break;
2844 case MGN_18M: ret = DESC90_RATE18M; break;
2845 case MGN_24M: ret = DESC90_RATE24M; break;
2846 case MGN_36M: ret = DESC90_RATE36M; break;
2847 case MGN_48M: ret = DESC90_RATE48M; break;
2848 case MGN_54M: ret = DESC90_RATE54M; break;
2849
2850 // HT rate since here
2851 case MGN_MCS0: ret = DESC90_RATEMCS0; break;
2852 case MGN_MCS1: ret = DESC90_RATEMCS1; break;
2853 case MGN_MCS2: ret = DESC90_RATEMCS2; break;
2854 case MGN_MCS3: ret = DESC90_RATEMCS3; break;
2855 case MGN_MCS4: ret = DESC90_RATEMCS4; break;
2856 case MGN_MCS5: ret = DESC90_RATEMCS5; break;
2857 case MGN_MCS6: ret = DESC90_RATEMCS6; break;
2858 case MGN_MCS7: ret = DESC90_RATEMCS7; break;
2859 case MGN_MCS8: ret = DESC90_RATEMCS8; break;
2860 case MGN_MCS9: ret = DESC90_RATEMCS9; break;
2861 case MGN_MCS10: ret = DESC90_RATEMCS10; break;
2862 case MGN_MCS11: ret = DESC90_RATEMCS11; break;
2863 case MGN_MCS12: ret = DESC90_RATEMCS12; break;
2864 case MGN_MCS13: ret = DESC90_RATEMCS13; break;
2865 case MGN_MCS14: ret = DESC90_RATEMCS14; break;
2866 case MGN_MCS15: ret = DESC90_RATEMCS15; break;
2867 case (0x80|0x20): ret = DESC90_RATEMCS32; break;
2868
2869 default: break;
2870 }
2871 return ret;
2872}
2873#endif
2874
2875u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc)
2876{
2877 u8 tmp_Short;
2878
2879 tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0);
2880
2881 if(TxHT==1 && TxRate != DESC90_RATEMCS15)
2882 tmp_Short = 0;
2883
2884 return tmp_Short;
2885}
2886
5f53d8ca 2887static void tx_zero_isr(struct urb *tx_urb)
5f53d8ca
JC		 2888{
2889 return;
2890}
2891
2892
2893#ifdef RTL8192SU
2894/*
2895 * The tx procedure is just as following, skb->cb will contain all the following
2896 *information: * priority, morefrag, rate, &dev.
2897 * */
2898 // <Note> Buffer format for 8192S Usb bulk out:
2899//
2900// --------------------------------------------------
2901// | 8192S Usb Tx Desc | 802_11_MAC_header | data |
2902// --------------------------------------------------
2903// | 32 bytes | 24 bytes |0-2318 bytes|
2904// --------------------------------------------------
2905// |<------------ BufferLen ------------------------->|
2906
2907short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb)
2908{
2909 struct r8192_priv *priv = ieee80211_priv(dev);
2910 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2911 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
2912 //tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);//92su del
2913 struct usb_device *udev = priv->udev;
2914 int pend;
2915 int status;
2916 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
2917 //int urb_len;
2918 unsigned int idx_pipe;
2919 u16 MPDUOverhead = 0;
2920 //RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
2921
2922#if 0
2923 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
2924 RT_ENC_ALG EncAlg = NO_Encryption;
2925#endif
2926
2927
2928 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
2929 /* we are locked here so the two atomic_read and inc are executed
2930 * without interleaves * !!! For debug purpose */
2931 if( pend > MAX_TX_URB){
2932 switch (tcb_desc->queue_index) {
2933 case VO_PRIORITY:
2934 priv->stats.txvodrop++;
2935 break;
2936 case VI_PRIORITY:
2937 priv->stats.txvidrop++;
2938 break;
2939 case BE_PRIORITY:
2940 priv->stats.txbedrop++;
2941 break;
2942 default://BK_PRIORITY
2943 priv->stats.txbkdrop++;
2944 break;
2945 }
2946 printk("To discard skb packet!\n");
2947 dev_kfree_skb_any(skb);
2948 return -1;
2949 }
2950
5f53d8ca 2951 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2952 if(!tx_urb){
2953 dev_kfree_skb_any(skb);
2954 return -ENOMEM;
2955 }
2956
2957 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
2958
2959
5f53d8ca 2960 tx_desc->NonQos = (IsQoSDataFrame(skb->data)==TRUE)? 0:1;
5f53d8ca
JC		 2961
2962 /* Fill Tx descriptor */
2963 //memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
2964
2965 // This part can just fill to the first descriptor of the frame.
2966 /* DWORD 0 */
2967 tx_desc->TxHT = (tcb_desc->data_rate&0x80)?1:0;
2968
5f53d8ca
JC		 2969
2970 tx_desc->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
2971 //tx_desc->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
2972 tx_desc->TxShort = QueryIsShort(tx_desc->TxHT, tx_desc->TxRate, tcb_desc);
2973
2974
2975 // Aggregation related
2976 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
2977 tx_desc->AllowAggregation = 1;
2978 /* DWORD 1 */
2979 //tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
2980 //tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
2981 } else {
2982 tx_desc->AllowAggregation = 0;
2983 /* DWORD 1 */
2984 //tx_fwinfo->RxMF = 0;
2985 //tx_fwinfo->RxAMD = 0;
2986 }
2987
2988 //
2989 // <Roger_Notes> For AMPDU case, we must insert SSN into TX_DESC,
2990 // FW according as this SSN to do necessary packet retry.
2991 // 2008.06.06.
2992 //
2993 {
2994 u8 *pSeq;
2995 u16 Temp;
2996 //pSeq = (u8 *)(VirtualAddress+USB_HWDESC_HEADER_LEN + FRAME_OFFSET_SEQUENCE);
2997 pSeq = (u8 *)(skb->data+USB_HWDESC_HEADER_LEN + 22);
2998 Temp = pSeq[0];
2999 Temp <<= 12;
3000 Temp |= (*(u16 *)pSeq)>>4;
3001 tx_desc->Seq = Temp;
3002 }
3003
3004 /* Protection mode related */
3005 tx_desc->RTSEn = (tcb_desc->bRTSEnable)?1:0;
3006 tx_desc->CTS2Self = (tcb_desc->bCTSEnable)?1:0;
3007 tx_desc->RTSSTBC = (tcb_desc->bRTSSTBC)?1:0;
3008 tx_desc->RTSHT = (tcb_desc->rts_rate&0x80)?1:0;
3009 tx_desc->RTSRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
3010 tx_desc->RTSSubcarrier = (tx_desc->RTSHT==0)?(tcb_desc->RTSSC):0;
3011 tx_desc->RTSBW = (tx_desc->RTSHT==1)?((tcb_desc->bRTSBW)?1:0):0;
3012 tx_desc->RTSShort = (tx_desc->RTSHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
3013 (tcb_desc->bRTSUseShortGI?1:0);
3014 //LZM 090219
3015 tx_desc->DisRTSFB = 0;
3016 tx_desc->RTSRateFBLmt = 0xf;
3017
3018 // <Roger_EXP> 2008.09.22. We disable RTS rate fallback temporarily.
3019 //tx_desc->DisRTSFB = 0x01;
3020
3021 /* Set Bandwidth and sub-channel settings. */
3022 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
3023 {
3024 if(tcb_desc->bPacketBW) {
3025 tx_desc->TxBandwidth = 1;
3026 tx_desc->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
3027 } else {
3028 tx_desc->TxBandwidth = 0;
3029 tx_desc->TxSubCarrier = priv->nCur40MhzPrimeSC;
3030 }
3031 } else {
3032 tx_desc->TxBandwidth = 0;
3033 tx_desc->TxSubCarrier = 0;
3034 }
3035
5f53d8ca
JC		 3036
3037 //memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3038 /* DWORD 0 */
3039 tx_desc->LINIP = 0;
3040 //tx_desc->CmdInit = 1; //92su del
3041 tx_desc->Offset = USB_HWDESC_HEADER_LEN;
3042
5f53d8ca
JC		 3043 {
3044 tx_desc->PktSize = (skb->len - USB_HWDESC_HEADER_LEN) & 0xffff;
3045 }
3046
3047 /*DWORD 1*/
3048 //tx_desc->SecCAMID= 0;//92su del
3049 tx_desc->RaBRSRID= tcb_desc->RATRIndex;
3050//#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE
3051#if 0//LZM 090219
3052 tx_desc->RaBRSRID= 1;
3053#endif
3054
3055#if 0
3056 /* Fill security related */
3057 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
3058 {
3059 EncAlg = SecGetEncryptionOverhead(
3060 Adapter,
3061 &EncryptionMPDUHeadOverhead,
3062 &EncryptionMPDUTailOverhead,
3063 NULL,
3064 NULL,
3065 FALSE,
3066 FALSE);
3067 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
3068 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
3069 MPDUOverhead = EncryptionMPDUTailOverhead;
3070 tx_desc->NoEnc = 0;
3071 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
3072 //CamDumpAll(Adapter);
3073 }
3074 else
3075#endif
3076 {
3077 MPDUOverhead = 0;
3078 //tx_desc->NoEnc = 1;//92su del
3079 }
3080#if 0
3081 switch(EncAlg){
3082 case NO_Encryption:
3083 tx_desc->SecType = 0x0;
3084 break;
3085 case WEP40_Encryption:
3086 case WEP104_Encryption:
3087 tx_desc->SecType = 0x1;
3088 break;
3089 case TKIP_Encryption:
3090 tx_desc->SecType = 0x2;
3091 break;
3092 case AESCCMP_Encryption:
3093 tx_desc->SecType = 0x3;
3094 break;
3095 default:
3096 tx_desc->SecType = 0x0;
3097 break;
3098 }
3099#else
3100 tx_desc->SecType = 0x0;
3101#endif
3102 if (tcb_desc->bHwSec)
3103 {
3104 switch (priv->ieee80211->pairwise_key_type)
3105 {
3106 case KEY_TYPE_WEP40:
3107 case KEY_TYPE_WEP104:
3108 tx_desc->SecType = 0x1;
3109 //tx_desc->NoEnc = 0;//92su del
3110 break;
3111 case KEY_TYPE_TKIP:
3112 tx_desc->SecType = 0x2;
3113 //tx_desc->NoEnc = 0;//92su del
3114 break;
3115 case KEY_TYPE_CCMP:
3116 tx_desc->SecType = 0x3;
3117 //tx_desc->NoEnc = 0;//92su del
3118 break;
3119 case KEY_TYPE_NA:
3120 tx_desc->SecType = 0x0;
3121 //tx_desc->NoEnc = 1;//92su del
3122 break;
3123 default:
3124 tx_desc->SecType = 0x0;
3125 //tx_desc->NoEnc = 1;//92su del
3126 break;
3127 }
3128 }
3129
3130 //tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);//92su del
3131
3132
3133 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
3134 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
3135 tx_desc->DataRateFBLmt = 0x1F;// Alwasy enable all rate fallback range
3136
3137 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
3138
3139
3140 /* Fill fields that are required to be initialized in all of the descriptors */
3141 //DWORD 0
3142#if 0
3143 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
3144 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
3145#else
3146 tx_desc->FirstSeg = 1;
3147 tx_desc->LastSeg = 1;
3148#endif
3149 tx_desc->OWN = 1;
3150
5f53d8ca
JC		 3151 {
3152 //DWORD 2
3153 //tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
3154 tx_desc->TxBufferSize = (u32)(skb->len);//92su mod FIXLZM
3155 }
3156
3157#if 0
3158 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(1)TxFillDescriptor8192SUsb(): DataRate(%#x)\n", pTcb->DataRate));
3159 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(2)TxFillDescriptor8192SUsb(): bTxUseDriverAssingedRate(%#x)\n", pTcb->bTxUseDriverAssingedRate));
3160 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(3)TxFillDescriptor8192SUsb(): bAMPDUEnable(%d)\n", pTcb->bAMPDUEnable));
3161 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(4)TxFillDescriptor8192SUsb(): bRTSEnable(%d)\n", pTcb->bRTSEnable));
3162 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(5)TxFillDescriptor8192SUsb(): RTSRate(%#x)\n", pTcb->RTSRate));
3163 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(6)TxFillDescriptor8192SUsb(): bCTSEnable(%d)\n", pTcb->bCTSEnable));
3164 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(7)TxFillDescriptor8192SUsb(): bUseShortGI(%d)\n", pTcb->bUseShortGI));
3165 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(8)TxFillDescriptor8192SUsb(): bPacketBW(%d)\n", pTcb->bPacketBW));
3166 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(9)TxFillDescriptor8192SUsb(): CurrentChannelBW(%d)\n", pHalData->CurrentChannelBW));
3167 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(10)TxFillDescriptor8192SUsb(): bTxDisableRateFallBack(%d)\n", pTcb->bTxDisableRateFallBack));
3168 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(11)TxFillDescriptor8192SUsb(): RATRIndex(%d)\n", pTcb->RATRIndex));
3169#endif
3170
3171 /* Get index to out pipe from specified QueueID */
3172 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
3173 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,tcb_desc->queue_index,priv->RtOutPipes[idx_pipe]);
3174
3175 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
3176 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
3177
3178 /* To submit bulk urb */
3179 usb_fill_bulk_urb(tx_urb,
3180 udev,
3181 usb_sndbulkpipe(udev,priv->RtOutPipes[idx_pipe]),
3182 skb->data,
3183 skb->len, rtl8192_tx_isr, skb);
3184
5f53d8ca 3185 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 3186 if (!status){
3187//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
3188 bool bSend0Byte = false;
3189 u8 zero = 0;
3190 if(udev->speed == USB_SPEED_HIGH)
3191 {
3192 if (skb->len > 0 && skb->len % 512 == 0)
3193 bSend0Byte = true;
3194 }
3195 else
3196 {
3197 if (skb->len > 0 && skb->len % 64 == 0)
3198 bSend0Byte = true;
3199 }
3200 if (bSend0Byte)
3201 {
3202#if 1
5f53d8ca 3203 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3204 if(!tx_urb_zero){
3205 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
3206 return -ENOMEM;
3207 }
3208 usb_fill_bulk_urb(tx_urb_zero,udev,
3209 usb_sndbulkpipe(udev,idx_pipe), &zero,
3210 0, tx_zero_isr, dev);
5f53d8ca 3211 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
5f53d8ca
JC		 3212 if (status){
3213 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
3214 return -1;
3215 }
3216#endif
3217 }
3218 dev->trans_start = jiffies;
3219 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
3220 return 0;
3221 }else{
3222 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
3223 status);
3224 return -1;
3225 }
3226}
3227#else
3228
3229/*
3230 * The tx procedure is just as following,
3231 * skb->cb will contain all the following information,
3232 * priority, morefrag, rate, &dev.
3233 * */
3234short rtl8192_tx(struct net_device *dev, struct sk_buff* skb)
3235{
3236 struct r8192_priv *priv = ieee80211_priv(dev);
3237 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3238 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
3239 tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);
3240 struct usb_device *udev = priv->udev;
3241 int pend;
3242 int status;
3243 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
3244 //int urb_len;
3245 unsigned int idx_pipe;
3246// RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
3247#if 0
3248 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
3249 RT_ENC_ALG EncAlg = NO_Encryption;
3250#endif
3251// printk("=============> %s\n", __FUNCTION__);
3252 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
3253 /* we are locked here so the two atomic_read and inc are executed
3254 * without interleaves
3255 * !!! For debug purpose
3256 */
3257 if( pend > MAX_TX_URB){
3258#if 0
3259 switch (tcb_desc->queue_index) {
3260 case VO_PRIORITY:
3261 priv->stats.txvodrop++;
3262 break;
3263 case VI_PRIORITY:
3264 priv->stats.txvidrop++;
3265 break;
3266 case BE_PRIORITY:
3267 priv->stats.txbedrop++;
3268 break;
3269 default://BK_PRIORITY
3270 priv->stats.txbkdrop++;
3271 break;
3272 }
3273#endif
3274 printk("To discard skb packet!\n");
3275 dev_kfree_skb_any(skb);
3276 return -1;
3277 }
3278
5f53d8ca 3279 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3280 if(!tx_urb){
3281 dev_kfree_skb_any(skb);
3282 return -ENOMEM;
3283 }
3284
3285 /* Fill Tx firmware info */
3286 memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
3287 /* DWORD 0 */
3288 tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0;
3289 tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
3290 tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
3291 tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc);
3292 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
3293 tx_fwinfo->AllowAggregation = 1;
3294 /* DWORD 1 */
3295 tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
3296 tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
3297 } else {
3298 tx_fwinfo->AllowAggregation = 0;
3299 /* DWORD 1 */
3300 tx_fwinfo->RxMF = 0;
3301 tx_fwinfo->RxAMD = 0;
3302 }
3303
3304 /* Protection mode related */
3305 tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0;
3306 tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0;
3307 tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0;
3308 tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0;
3309 tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
3310 tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0;
3311 tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0;
3312 tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
3313 (tcb_desc->bRTSUseShortGI?1:0);
3314
3315 /* Set Bandwidth and sub-channel settings. */
3316 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
3317 {
3318 if(tcb_desc->bPacketBW) {
3319 tx_fwinfo->TxBandwidth = 1;
3320 tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
3321 } else {
3322 tx_fwinfo->TxBandwidth = 0;
3323 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
3324 }
3325 } else {
3326 tx_fwinfo->TxBandwidth = 0;
3327 tx_fwinfo->TxSubCarrier = 0;
3328 }
3329
5f53d8ca
JC		 3330 /* Fill Tx descriptor */
3331 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3332 /* DWORD 0 */
3333 tx_desc->LINIP = 0;
3334 tx_desc->CmdInit = 1;
3335 tx_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8;
3336
5f53d8ca
JC		 3337 {
3338 tx_desc->PktSize = (skb->len - TX_PACKET_SHIFT_BYTES) & 0xffff;
3339 }
3340
3341 /*DWORD 1*/
3342 tx_desc->SecCAMID= 0;
3343 tx_desc->RATid = tcb_desc->RATRIndex;
3344#if 0
3345 /* Fill security related */
3346 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
3347 {
3348 EncAlg = SecGetEncryptionOverhead(
3349 Adapter,
3350 &EncryptionMPDUHeadOverhead,
3351 &EncryptionMPDUTailOverhead,
3352 NULL,
3353 NULL,
3354 FALSE,
3355 FALSE);
3356 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
3357 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
3358 MPDUOverhead = EncryptionMPDUTailOverhead;
3359 tx_desc->NoEnc = 0;
3360 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
3361 //CamDumpAll(Adapter);
3362 }
3363 else
3364#endif
3365 {
3366 //MPDUOverhead = 0;
3367 tx_desc->NoEnc = 1;
3368 }
3369#if 0
3370 switch(EncAlg){
3371 case NO_Encryption:
3372 tx_desc->SecType = 0x0;
3373 break;
3374 case WEP40_Encryption:
3375 case WEP104_Encryption:
3376 tx_desc->SecType = 0x1;
3377 break;
3378 case TKIP_Encryption:
3379 tx_desc->SecType = 0x2;
3380 break;
3381 case AESCCMP_Encryption:
3382 tx_desc->SecType = 0x3;
3383 break;
3384 default:
3385 tx_desc->SecType = 0x0;
3386 break;
3387 }
3388#else
3389 tx_desc->SecType = 0x0;
3390#endif
3391 if (tcb_desc->bHwSec)
3392 {
3393 switch (priv->ieee80211->pairwise_key_type)
3394 {
3395 case KEY_TYPE_WEP40:
3396 case KEY_TYPE_WEP104:
3397 tx_desc->SecType = 0x1;
3398 tx_desc->NoEnc = 0;
3399 break;
3400 case KEY_TYPE_TKIP:
3401 tx_desc->SecType = 0x2;
3402 tx_desc->NoEnc = 0;
3403 break;
3404 case KEY_TYPE_CCMP:
3405 tx_desc->SecType = 0x3;
3406 tx_desc->NoEnc = 0;
3407 break;
3408 case KEY_TYPE_NA:
3409 tx_desc->SecType = 0x0;
3410 tx_desc->NoEnc = 1;
3411 break;
3412 }
3413 }
3414
3415 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
3416 tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);
3417
3418 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
3419 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
3420
3421 /* Fill fields that are required to be initialized in all of the descriptors */
3422 //DWORD 0
3423#if 0
3424 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
3425 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
3426#else
3427 tx_desc->FirstSeg = 1;
3428 tx_desc->LastSeg = 1;
3429#endif
3430 tx_desc->OWN = 1;
3431
5f53d8ca
JC		 3432 {
3433 //DWORD 2
3434 tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
3435 }
3436 /* Get index to out pipe from specified QueueID */
5f53d8ca 3437 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
5f53d8ca
JC		 3438
3439 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
3440 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
3441
3442 /* To submit bulk urb */
3443 usb_fill_bulk_urb(tx_urb,udev,
3444 usb_sndbulkpipe(udev,idx_pipe), skb->data,
3445 skb->len, rtl8192_tx_isr, skb);
3446
5f53d8ca 3447 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 3448 if (!status){
3449//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
3450 bool bSend0Byte = false;
3451 u8 zero = 0;
3452 if(udev->speed == USB_SPEED_HIGH)
3453 {
3454 if (skb->len > 0 && skb->len % 512 == 0)
3455 bSend0Byte = true;
3456 }
3457 else
3458 {
3459 if (skb->len > 0 && skb->len % 64 == 0)
3460 bSend0Byte = true;
3461 }
3462 if (bSend0Byte)
3463 {
3464#if 1
5f53d8ca 3465 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3466 if(!tx_urb_zero){
3467 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
3468 return -ENOMEM;
3469 }
3470 usb_fill_bulk_urb(tx_urb_zero,udev,
3471 usb_sndbulkpipe(udev,idx_pipe), &zero,
3472 0, tx_zero_isr, dev);
5f53d8ca 3473 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
5f53d8ca
JC		 3474 if (status){
3475 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
3476 return -1;
3477 }
3478#endif
3479 }
3480 dev->trans_start = jiffies;
3481 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
3482 return 0;
3483 }else{
3484 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
3485 status);
3486 return -1;
3487 }
3488}
3489#endif
3490
3491#if 0
3492void rtl8192_set_rate(struct net_device *dev)
3493{
3494 int i;
3495 u16 word;
3496 int basic_rate,min_rr_rate,max_rr_rate;
3497
3498// struct r8192_priv *priv = ieee80211_priv(dev);
3499
3500 //if (ieee80211_is_54g(priv->ieee80211->current_network) &&
3501// priv->ieee80211->state == IEEE80211_LINKED){
3502 basic_rate = ieeerate2rtlrate(240);
3503 min_rr_rate = ieeerate2rtlrate(60);
3504 max_rr_rate = ieeerate2rtlrate(240);
3505
3506//
3507// }else{
3508// basic_rate = ieeerate2rtlrate(20);
3509// min_rr_rate = ieeerate2rtlrate(10);
3510// max_rr_rate = ieeerate2rtlrate(110);
3511// }
3512
3513 write_nic_byte(dev, RESP_RATE,
3514 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3515
3516 //word = read_nic_word(dev, BRSR);
3517 word = read_nic_word(dev, BRSR_8187);
3518 word &= ~BRSR_MBR_8185;
3519
3520
3521 for(i=0;i<=basic_rate;i++)
3522 word |= (1<<i);
3523
3524 //write_nic_word(dev, BRSR, word);
3525 write_nic_word(dev, BRSR_8187, word);
3526 //DMESG("RR:%x BRSR: %x", read_nic_byte(dev,RESP_RATE), read_nic_word(dev,BRSR));
3527}
3528#endif
3529
3530
3531#ifdef RTL8192SU
3532void rtl8192SU_net_update(struct net_device *dev)
3533{
3534
3535 struct r8192_priv *priv = ieee80211_priv(dev);
3536 struct ieee80211_device* ieee = priv->ieee80211;
3537 struct ieee80211_network *net = &priv->ieee80211->current_network;
3538 //u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
3539 u16 rate_config = 0;
3540 u32 regTmp = 0;
3541 u8 rateIndex = 0;
3542 u8 retrylimit = 0x30;
3543 u16 cap = net->capability;
3544
3545 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
3546
3547//HW_VAR_BASIC_RATE
3548 //update Basic rate: RR, BRSR
3549 rtl8192_config_rate(dev, &rate_config); //HalSetBrateCfg
3550
5f53d8ca 3551 priv->basic_rate = rate_config = rate_config & 0x15f;
5f53d8ca
JC		 3552
3553 // Set RRSR rate table.
3554 write_nic_byte(dev, RRSR, rate_config&0xff);
3555 write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff);
3556
3557 // Set RTS initial rate
3558 while(rate_config > 0x1)
3559 {
3560 rate_config = (rate_config>> 1);
3561 rateIndex++;
3562 }
3563 write_nic_byte(dev, INIRTSMCS_SEL, rateIndex);
3564//HW_VAR_BASIC_RATE
3565
3566 //set ack preample
3567 regTmp = (priv->nCur40MhzPrimeSC) << 5;
3568 if (priv->short_preamble)
3569 regTmp |= 0x80;
3570 write_nic_byte(dev, RRSR+2, regTmp);
3571
3572 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
3573 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
3574
3575 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
3576 //2008.10.24 added by tynli for beacon changed.
3577 PHY_SetBeaconHwReg( dev, net->beacon_interval);
3578
3579 rtl8192_update_cap(dev, cap);
3580
3581 if (ieee->iw_mode == IW_MODE_ADHOC){
3582 retrylimit = 7;
3583 //we should enable ibss interrupt here, but disable it temporarily
3584 if (0){
3585 priv->irq_mask |= (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3586 //rtl8192_irq_disable(dev);
3587 //rtl8192_irq_enable(dev);
3588 }
3589 }
3590 else{
3591 if (0){
3592 priv->irq_mask &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3593 //rtl8192_irq_disable(dev);
3594 //rtl8192_irq_enable(dev);
3595 }
3596 }
3597
3598 priv->ShortRetryLimit = priv->LongRetryLimit = retrylimit;
3599
3600 write_nic_word(dev, RETRY_LIMIT,
3601 retrylimit << RETRY_LIMIT_SHORT_SHIFT | \
3602 retrylimit << RETRY_LIMIT_LONG_SHIFT);
3603}
3604
3605void rtl8192SU_update_ratr_table(struct net_device* dev)
3606{
3607 struct r8192_priv* priv = ieee80211_priv(dev);
3608 struct ieee80211_device* ieee = priv->ieee80211;
3609 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
3610 //struct ieee80211_network *net = &ieee->current_network;
3611 u32 ratr_value = 0;
3612
3613 u8 rate_index = 0;
3614 int WirelessMode = ieee->mode;
3615 u8 MimoPs = ieee->pHTInfo->PeerMimoPs;
3616
3617 u8 bNMode = 0;
3618
3619 rtl8192_config_rate(dev, (u16*)(&ratr_value));
3620 ratr_value |= (*(u16*)(pMcsRate)) << 12;
3621
3622 //switch (ieee->mode)
3623 switch (WirelessMode)
3624 {
3625 case IEEE_A:
3626 ratr_value &= 0x00000FF0;
3627 break;
3628 case IEEE_B:
3629 ratr_value &= 0x0000000D;
3630 break;
3631 case IEEE_G:
3632 ratr_value &= 0x00000FF5;
3633 break;
3634 case IEEE_N_24G:
3635 case IEEE_N_5G:
3636 {
3637 bNMode = 1;
3638
3639 if (MimoPs == 0) //MIMO_PS_STATIC
3640 {
3641 ratr_value &= 0x0007F005;
3642 }
3643 else
3644 { // MCS rate only => for 11N mode.
3645 u32 ratr_mask;
3646
3647 // 1T2R or 1T1R, Spatial Stream 2 should be disabled
3648 if ( priv->rf_type == RF_1T2R ||
3649 priv->rf_type == RF_1T1R ||
3650 (ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_2SS) )
3651 ratr_mask = 0x000ff005;
3652 else
3653 ratr_mask = 0x0f0ff005;
3654
3655 if((ieee->pHTInfo->bCurTxBW40MHz) &&
3656 !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ))
3657 ratr_mask |= 0x00000010; // Set 6MBps
3658
3659 // Select rates for rate adaptive mechanism.
3660 ratr_value &= ratr_mask;
3661 }
3662 }
3663 break;
3664 default:
3665 if(0)
3666 {
3667 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
3668 {
3669 ratr_value &= 0x000ff0f5;
3670 }
3671 else
3672 {
3673 ratr_value &= 0x0f0ff0f5;
3674 }
3675 }
3676 //printk("====>%s(), mode is not correct:%x\n", __FUNCTION__, ieee->mode);
3677 break;
3678 }
3679
5f53d8ca 3680 ratr_value &= 0x0FFFFFFF;
5f53d8ca
JC		 3681
3682 // Get MAX MCS available.
3683 if ( (bNMode && ((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0)) &&
3684 ((ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI40MHz) ||
3685 (!ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI20MHz)))
3686 {
3687 u8 shortGI_rate = 0;
3688 u32 tmp_ratr_value = 0;
3689 ratr_value |= 0x10000000;//???
3690 tmp_ratr_value = (ratr_value>>12);
3691 for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--)
3692 {
3693 if((1<<shortGI_rate) & tmp_ratr_value)
3694 break;
3695 }
3696 shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate);
3697 write_nic_byte(dev, SG_RATE, shortGI_rate);
3698 //printk("==>SG_RATE:%x\n", read_nic_byte(dev, SG_RATE));
3699 }
3700 write_nic_dword(dev, ARFR0+rate_index*4, ratr_value);
3701 printk("=============>ARFR0+rate_index*4:%#x\n", ratr_value);
3702
3703 //2 UFWP
3704 if (ratr_value & 0xfffff000){
3705 //printk("===>set to N mode\n");
3706 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_N);
3707 }
3708 else {
3709 //printk("===>set to B/G mode\n");
3710 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_BG);
3711 }
3712}
3713
3714void rtl8192SU_link_change(struct net_device *dev)
3715{
3716 struct r8192_priv *priv = ieee80211_priv(dev);
3717 struct ieee80211_device* ieee = priv->ieee80211;
3718 //unsigned long flags;
3719 u32 reg = 0;
3720
3721 printk("=====>%s 1\n", __func__);
3722 reg = read_nic_dword(dev, RCR);
3723
3724 if (ieee->state == IEEE80211_LINKED)
3725 {
3726
3727 rtl8192SU_net_update(dev);
3728 rtl8192SU_update_ratr_table(dev);
3729 ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE);
3730 priv->ReceiveConfig = reg |= RCR_CBSSID;
3731
3732 }else{
3733 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
3734
3735 }
3736
3737 write_nic_dword(dev, RCR, reg);
3738 rtl8192_update_msr(dev);
3739
3740 printk("<=====%s 2\n", __func__);
3741}
3742#else
3743extern void rtl8192_update_ratr_table(struct net_device* dev);
3744void rtl8192_link_change(struct net_device *dev)
3745{
3746// int i;
3747
3748 struct r8192_priv *priv = ieee80211_priv(dev);
3749 struct ieee80211_device* ieee = priv->ieee80211;
3750 //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval);
3751 if (ieee->state == IEEE80211_LINKED)
3752 {
3753 rtl8192_net_update(dev);
3754 rtl8192_update_ratr_table(dev);
3755#if 1
3756 //add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08
3757 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
3758 EnableHWSecurityConfig8192(dev);
3759#endif
3760 }
3761 /*update timing params*/
3762// RT_TRACE(COMP_CH, "========>%s(), chan:%d\n", __FUNCTION__, priv->chan);
3763// rtl8192_set_chan(dev, priv->chan);
3764 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
3765 {
3766 u32 reg = 0;
3767 reg = read_nic_dword(dev, RCR);
3768 if (priv->ieee80211->state == IEEE80211_LINKED)
3769 priv->ReceiveConfig = reg |= RCR_CBSSID;
3770 else
3771 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
3772 write_nic_dword(dev, RCR, reg);
3773 }
3774
3775// rtl8192_set_rxconf(dev);
3776}
3777#endif
3778
3779static struct ieee80211_qos_parameters def_qos_parameters = {
3780 {3,3,3,3},/* cw_min */
3781 {7,7,7,7},/* cw_max */
3782 {2,2,2,2},/* aifs */
3783 {0,0,0,0},/* flags */
3784 {0,0,0,0} /* tx_op_limit */
3785};
3786
3787
5f53d8ca
JC		 3788void rtl8192_update_beacon(struct work_struct * work)
3789{
3790 struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work);
3791 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 3792 struct ieee80211_device* ieee = priv->ieee80211;
3793 struct ieee80211_network* net = &ieee->current_network;
3794
3795 if (ieee->pHTInfo->bCurrentHTSupport)
3796 HTUpdateSelfAndPeerSetting(ieee, net);
3797 ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime;
3798 // Joseph test for turbo mode with AP
3799 ieee->pHTInfo->RT2RT_HT_Mode = net->bssht.RT2RT_HT_Mode;
3800 rtl8192_update_cap(dev, net->capability);
3801}
3802/*
3803* background support to run QoS activate functionality
3804*/
3805int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO};
1ec9e48d 3806
5f53d8ca
JC		 3807void rtl8192_qos_activate(struct work_struct * work)
3808{
3809 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
3810 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 3811 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
3812 u8 mode = priv->ieee80211->current_network.mode;
3813 //u32 size = sizeof(struct ieee80211_qos_parameters);
3814 u8 u1bAIFS;
3815 u32 u4bAcParam;
3816 int i;
3817
3818 if (priv == NULL)
3819 return;
3820
5f53d8ca 3821 mutex_lock(&priv->mutex);
1ec9e48d 3822
5f53d8ca
JC		 3823 if(priv->ieee80211->state != IEEE80211_LINKED)
3824 goto success;
3825 RT_TRACE(COMP_QOS,"qos active process with associate response received\n");
3826 /* It better set slot time at first */
3827 /* For we just support b/g mode at present, let the slot time at 9/20 selection */
3828 /* update the ac parameter to related registers */
3829 for(i = 0; i < QOS_QUEUE_NUM; i++) {
3830 //Mode G/A: slotTimeTimer = 9; Mode B: 20
3831 u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
3832 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
3833 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
3834 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
3835 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
3836
3837 write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
3838 //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4322);
3839 }
3840
3841success:
5f53d8ca 3842 mutex_unlock(&priv->mutex);
5f53d8ca
JC		 3843}
3844
3845static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv,
3846 int active_network,
3847 struct ieee80211_network *network)
3848{
3849 int ret = 0;
3850 u32 size = sizeof(struct ieee80211_qos_parameters);
3851
3852 if(priv->ieee80211->state !=IEEE80211_LINKED)
3853 return ret;
3854
3855 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
3856 return ret;
3857
3858 if (network->flags & NETWORK_HAS_QOS_MASK) {
3859 if (active_network &&
3860 (network->flags & NETWORK_HAS_QOS_PARAMETERS))
3861 network->qos_data.active = network->qos_data.supported;
3862
3863 if ((network->qos_data.active == 1) && (active_network == 1) &&
3864 (network->flags & NETWORK_HAS_QOS_PARAMETERS) &&
3865 (network->qos_data.old_param_count !=
3866 network->qos_data.param_count)) {
3867 network->qos_data.old_param_count =
3868 network->qos_data.param_count;
5f53d8ca 3869 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 3870 RT_TRACE (COMP_QOS, "QoS parameters change call "
3871 "qos_activate\n");
3872 }
3873 } else {
3874 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
3875 &def_qos_parameters, size);
3876
3877 if ((network->qos_data.active == 1) && (active_network == 1)) {
5f53d8ca 3878 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 3879 RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate \n");
3880 }
3881 network->qos_data.active = 0;
3882 network->qos_data.supported = 0;
3883 }
3884
3885 return 0;
3886}
3887
3888/* handle manage frame frame beacon and probe response */
3889static int rtl8192_handle_beacon(struct net_device * dev,
3890 struct ieee80211_beacon * beacon,
3891 struct ieee80211_network * network)
3892{
3893 struct r8192_priv *priv = ieee80211_priv(dev);
3894
3895 rtl8192_qos_handle_probe_response(priv,1,network);
5f53d8ca 3896 queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0);
5f53d8ca 3897
5f53d8ca
JC		 3898 return 0;
3899
3900}
3901
3902/*
3903* handling the beaconing responses. if we get different QoS setting
3904* off the network from the associated setting, adjust the QoS
3905* setting
3906*/
3907static int rtl8192_qos_association_resp(struct r8192_priv *priv,
3908 struct ieee80211_network *network)
3909{
3910 int ret = 0;
3911 unsigned long flags;
3912 u32 size = sizeof(struct ieee80211_qos_parameters);
3913 int set_qos_param = 0;
3914
3915 if ((priv == NULL) || (network == NULL))
3916 return ret;
3917
3918 if(priv->ieee80211->state !=IEEE80211_LINKED)
3919 return ret;
3920
3921 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
3922 return ret;
3923
3924 spin_lock_irqsave(&priv->ieee80211->lock, flags);
3925 if(network->flags & NETWORK_HAS_QOS_PARAMETERS) {
3926 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
3927 &network->qos_data.parameters,\
3928 sizeof(struct ieee80211_qos_parameters));
3929 priv->ieee80211->current_network.qos_data.active = 1;
3930#if 0
3931 if((priv->ieee80211->current_network.qos_data.param_count != \
3932 network->qos_data.param_count))
3933#endif
3934 {
3935 set_qos_param = 1;
3936 /* update qos parameter for current network */
3937 priv->ieee80211->current_network.qos_data.old_param_count = \
3938 priv->ieee80211->current_network.qos_data.param_count;
3939 priv->ieee80211->current_network.qos_data.param_count = \
3940 network->qos_data.param_count;
3941 }
3942 } else {
3943 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
3944 &def_qos_parameters, size);
3945 priv->ieee80211->current_network.qos_data.active = 0;
3946 priv->ieee80211->current_network.qos_data.supported = 0;
3947 set_qos_param = 1;
3948 }
3949
3950 spin_unlock_irqrestore(&priv->ieee80211->lock, flags);
3951
3952 RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n",__FUNCTION__,network->flags ,priv->ieee80211->current_network.qos_data.active);
3953 if (set_qos_param == 1)
5f53d8ca 3954 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 3955
3956 return ret;
3957}
3958
3959
3960static int rtl8192_handle_assoc_response(struct net_device *dev,
3961 struct ieee80211_assoc_response_frame *resp,
3962 struct ieee80211_network *network)
3963{
3964 struct r8192_priv *priv = ieee80211_priv(dev);
3965 rtl8192_qos_association_resp(priv, network);
3966 return 0;
3967}
3968
3969
3970void rtl8192_update_ratr_table(struct net_device* dev)
3971 // POCTET_STRING posLegacyRate,
3972 // u8* pMcsRate)
3973 // PRT_WLAN_STA pEntry)
3974{
3975 struct r8192_priv* priv = ieee80211_priv(dev);
3976 struct ieee80211_device* ieee = priv->ieee80211;
3977 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
3978 //struct ieee80211_network *net = &ieee->current_network;
3979 u32 ratr_value = 0;
3980 u8 rate_index = 0;
3981 rtl8192_config_rate(dev, (u16*)(&ratr_value));
3982 ratr_value |= (*(u16*)(pMcsRate)) << 12;
3983// switch (net->mode)
3984 switch (ieee->mode)
3985 {
3986 case IEEE_A:
3987 ratr_value &= 0x00000FF0;
3988 break;
3989 case IEEE_B:
3990 ratr_value &= 0x0000000F;
3991 break;
3992 case IEEE_G:
3993 ratr_value &= 0x00000FF7;
3994 break;
3995 case IEEE_N_24G:
3996 case IEEE_N_5G:
3997 if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC
3998 ratr_value &= 0x0007F007;
3999 else{
4000 if (priv->rf_type == RF_1T2R)
4001 ratr_value &= 0x000FF007;
4002 else
4003 ratr_value &= 0x0F81F007;
4004 }
4005 break;
4006 default:
4007 break;
4008 }
4009 ratr_value &= 0x0FFFFFFF;
4010 if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){
4011 ratr_value |= 0x80000000;
4012 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
4013 ratr_value |= 0x80000000;
4014 }
4015 write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
4016 write_nic_byte(dev, UFWP, 1);
4017}
4018
4019static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04};
4020static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04};
4021bool GetNmodeSupportBySecCfg8192(struct net_device*dev)
4022{
4023#if 1
4024 struct r8192_priv* priv = ieee80211_priv(dev);
4025 struct ieee80211_device* ieee = priv->ieee80211;
4026 struct ieee80211_network * network = &ieee->current_network;
4027 int wpa_ie_len= ieee->wpa_ie_len;
4028 struct ieee80211_crypt_data* crypt;
4029 int encrypt;
5f53d8ca 4030 return TRUE;
5f53d8ca
JC		 4031
4032 crypt = ieee->crypt[ieee->tx_keyidx];
4033 //we use connecting AP's capability instead of only security config on our driver to distinguish whether it should use N mode or G mode
4034 encrypt = (network->capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && (0 == strcmp(crypt->ops->name,"WEP")));
4035
4036 /* simply judge */
4037 if(encrypt && (wpa_ie_len == 0)) {
4038 /* wep encryption, no N mode setting */
4039 return false;
4040// } else if((wpa_ie_len != 0)&&(memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) {
4041 } else if((wpa_ie_len != 0)) {
4042 /* parse pairwise key type */
4043 //if((pairwisekey = WEP40)||(pairwisekey = WEP104)||(pairwisekey = TKIP))
4044 if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4))))
4045 return true;
4046 else
4047 return false;
4048 } else {
4049 return true;
4050 }
4051
4052#if 0
4053 //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate.
4054 //We can't force in G mode if Pairwie key is AES and group key is TKIP
4055 if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) ||
4056 (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) ||
4057 (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption))
4058 {
4059 return false;
4060 }
4061 else
4062 return true;
4063#endif
4064 return true;
4065#endif
4066}
4067
4068bool GetHalfNmodeSupportByAPs819xUsb(struct net_device* dev)
4069{
4070 bool Reval;
4071 struct r8192_priv* priv = ieee80211_priv(dev);
4072 struct ieee80211_device* ieee = priv->ieee80211;
4073
4074// Added by Roger, 2008.08.29.
4075#ifdef RTL8192SU
4076 return false;
4077#endif
4078
4079 if(ieee->bHalfWirelessN24GMode == true)
4080 Reval = true;
4081 else
4082 Reval = false;
4083
4084 return Reval;
4085}
4086
4087void rtl8192_refresh_supportrate(struct r8192_priv* priv)
4088{
4089 struct ieee80211_device* ieee = priv->ieee80211;
4090 //we donot consider set support rate for ABG mode, only HT MCS rate is set here.
4091 if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G)
4092 {
4093 memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
4094 //RT_DEBUG_DATA(COMP_INIT, ieee->RegHTSuppRateSet, 16);
4095 //RT_DEBUG_DATA(COMP_INIT, ieee->Regdot11HTOperationalRateSet, 16);
4096 }
4097 else
4098 memset(ieee->Regdot11HTOperationalRateSet, 0, 16);
4099 return;
4100}
4101
4102u8 rtl8192_getSupportedWireleeMode(struct net_device*dev)
4103{
4104 struct r8192_priv *priv = ieee80211_priv(dev);
4105 u8 ret = 0;
4106 switch(priv->rf_chip)
4107 {
4108 case RF_8225:
4109 case RF_8256:
4110 case RF_PSEUDO_11N:
4111 case RF_6052:
4112 ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B);
4113 break;
4114 case RF_8258:
4115 ret = (WIRELESS_MODE_A|WIRELESS_MODE_N_5G);
4116 break;
4117 default:
4118 ret = WIRELESS_MODE_B;
4119 break;
4120 }
4121 return ret;
4122}
4123void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode)
4124{
4125 struct r8192_priv *priv = ieee80211_priv(dev);
4126 u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev);
4127
4128#if 1
4129 if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0))
4130 {
4131 if(bSupportMode & WIRELESS_MODE_N_24G)
4132 {
4133 wireless_mode = WIRELESS_MODE_N_24G;
4134 }
4135 else if(bSupportMode & WIRELESS_MODE_N_5G)
4136 {
4137 wireless_mode = WIRELESS_MODE_N_5G;
4138 }
4139 else if((bSupportMode & WIRELESS_MODE_A))
4140 {
4141 wireless_mode = WIRELESS_MODE_A;
4142 }
4143 else if((bSupportMode & WIRELESS_MODE_G))
4144 {
4145 wireless_mode = WIRELESS_MODE_G;
4146 }
4147 else if((bSupportMode & WIRELESS_MODE_B))
4148 {
4149 wireless_mode = WIRELESS_MODE_B;
4150 }
4151 else{
4152 RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode);
4153 wireless_mode = WIRELESS_MODE_B;
4154 }
4155 }
4156#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA
4157 ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting );
4158#endif
4159#ifdef RTL8192SU
4160 //LZM 090306 usb crash here, mark it temp
4161 //write_nic_word(dev, SIFS_OFDM, 0x0e0e);
4162#endif
4163 priv->ieee80211->mode = wireless_mode;
4164
4165 if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G))
4166 priv->ieee80211->pHTInfo->bEnableHT = 1;
4167 else
4168 priv->ieee80211->pHTInfo->bEnableHT = 0;
4169 RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode);
4170 rtl8192_refresh_supportrate(priv);
4171#endif
4172
4173}
4174
4175
4176short rtl8192_is_tx_queue_empty(struct net_device *dev)
4177{
4178 int i=0;
4179 struct r8192_priv *priv = ieee80211_priv(dev);
4180 //struct ieee80211_device* ieee = priv->ieee80211;
4181 for (i=0; i<=MGNT_QUEUE; i++)
4182 {
4183 if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) )
4184 continue;
4185 if (atomic_read(&priv->tx_pending[i]))
4186 {
4187 printk("===>tx queue is not empty:%d, %d\n", i, atomic_read(&priv->tx_pending[i]));
4188 return 0;
4189 }
4190 }
4191 return 1;
4192}
4193#if 0
4194void rtl8192_rq_tx_ack(struct net_device *dev)
4195{
4196 struct r8192_priv *priv = ieee80211_priv(dev);
4197 priv->ieee80211->ack_tx_to_ieee = 1;
4198}
4199#endif
4200void rtl8192_hw_sleep_down(struct net_device *dev)
4201{
4202 RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__);
4203#ifdef TODO
4204// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
4205#endif
4206}
1ec9e48d 4207
5f53d8ca
JC		 4208void rtl8192_hw_sleep_wq (struct work_struct *work)
4209{
4210// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4211// struct ieee80211_device * ieee = (struct ieee80211_device*)
4212// container_of(work, struct ieee80211_device, watch_dog_wq);
4213 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4214 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
4215 struct net_device *dev = ieee->dev;
1ec9e48d 4216
5f53d8ca
JC		 4217 //printk("=========>%s()\n", __FUNCTION__);
4218 rtl8192_hw_sleep_down(dev);
4219}
4220// printk("dev is %d\n",dev);
4221// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__);
4222void rtl8192_hw_wakeup(struct net_device* dev)
4223{
4224// u32 flags = 0;
4225
4226// spin_lock_irqsave(&priv->ps_lock,flags);
4227 RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__);
4228#ifdef TODO
4229// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
4230#endif
4231 //FIXME: will we send package stored while nic is sleep?
4232// spin_unlock_irqrestore(&priv->ps_lock,flags);
4233}
1ec9e48d 4234
5f53d8ca
JC		 4235void rtl8192_hw_wakeup_wq (struct work_struct *work)
4236{
4237// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4238// struct ieee80211_device * ieee = (struct ieee80211_device*)
4239// container_of(work, struct ieee80211_device, watch_dog_wq);
4240 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4241 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
4242 struct net_device *dev = ieee->dev;
5f53d8ca 4243
1ec9e48d 4244 rtl8192_hw_wakeup(dev);
5f53d8ca
JC		 4245}
4246
4247#define MIN_SLEEP_TIME 50
4248#define MAX_SLEEP_TIME 10000
4249void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl)
4250{
4251
4252 struct r8192_priv *priv = ieee80211_priv(dev);
4253
4254 u32 rb = jiffies;
4255 unsigned long flags;
4256
4257 spin_lock_irqsave(&priv->ps_lock,flags);
4258
4259 /* Writing HW register with 0 equals to disable
4260 * the timer, that is not really what we want
4261 */
4262 tl -= MSECS(4+16+7);
4263
4264 //if(tl == 0) tl = 1;
4265
4266 /* FIXME HACK FIXME HACK */
4267// force_pci_posting(dev);
4268 //mdelay(1);
4269
4270// rb = read_nic_dword(dev, TSFTR);
4271
4272 /* If the interval in witch we are requested to sleep is too
4273 * short then give up and remain awake
4274 */
4275 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
4276 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
4277 spin_unlock_irqrestore(&priv->ps_lock,flags);
4278 printk("too short to sleep\n");
4279 return;
4280 }
4281
4282// write_nic_dword(dev, TimerInt, tl);
4283// rb = read_nic_dword(dev, TSFTR);
4284 {
4285 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
4286 // if (tl<rb)
4287
5f53d8ca 4288 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
5f53d8ca
JC		 4289 }
4290 /* if we suspect the TimerInt is gone beyond tl
4291 * while setting it, then give up
4292 */
4293#if 1
4294 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
4295 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
4296 printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME));
4297 spin_unlock_irqrestore(&priv->ps_lock,flags);
4298 return;
4299 }
4300#endif
4301// if(priv->rf_sleep)
4302// priv->rf_sleep(dev);
4303
4304 //printk("<=========%s()\n", __FUNCTION__);
5f53d8ca 4305 queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0);
1ec9e48d 4306
5f53d8ca
JC		 4307 spin_unlock_irqrestore(&priv->ps_lock,flags);
4308}
4309//init priv variables here. only non_zero value should be initialized here.
4310static void rtl8192_init_priv_variable(struct net_device* dev)
4311{
4312 struct r8192_priv *priv = ieee80211_priv(dev);
4313 u8 i;
4314 priv->card_8192 = NIC_8192U;
4315 priv->chan = 1; //set to channel 1
4316 priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO
4317 priv->ieee80211->iw_mode = IW_MODE_INFRA;
4318 priv->ieee80211->ieee_up=0;
4319 priv->retry_rts = DEFAULT_RETRY_RTS;
4320 priv->retry_data = DEFAULT_RETRY_DATA;
4321 priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD;
4322 priv->ieee80211->rate = 110; //11 mbps
4323 priv->ieee80211->short_slot = 1;
4324 priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
4325 priv->CckPwEnl = 6;
4326 //for silent reset
4327 priv->IrpPendingCount = 1;
4328 priv->ResetProgress = RESET_TYPE_NORESET;
4329 priv->bForcedSilentReset = 0;
4330 priv->bDisableNormalResetCheck = false;
4331 priv->force_reset = false;
4332
4333 priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available.
4334 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
4335 priv->ieee80211->iw_mode = IW_MODE_INFRA;
4336 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
4337 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
4338 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE |
4339 IEEE_SOFTMAC_BEACONS;//added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE;
4340
4341 priv->ieee80211->active_scan = 1;
4342 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION;
4343 priv->ieee80211->host_encrypt = 1;
4344 priv->ieee80211->host_decrypt = 1;
4345 priv->ieee80211->start_send_beacons = NULL;//rtl819xusb_beacon_tx;//-by amy 080604
4346 priv->ieee80211->stop_send_beacons = NULL;//rtl8192_beacon_stop;//-by amy 080604
4347 priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit;
4348 priv->ieee80211->set_chan = rtl8192_set_chan;
4349 priv->ieee80211->link_change = priv->ops->rtl819x_link_change;
4350 priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit;
4351 priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop;
4352 priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume;
4353 priv->ieee80211->init_wmmparam_flag = 0;
4354 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
4355 priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc;
4356 priv->ieee80211->tx_headroom = TX_PACKET_SHIFT_BYTES;
4357 priv->ieee80211->qos_support = 1;
4358
4359 //added by WB
4360// priv->ieee80211->SwChnlByTimerHandler = rtl8192_phy_SwChnl;
4361 priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode;
4362 priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response;
4363 priv->ieee80211->handle_beacon = rtl8192_handle_beacon;
4364 //for LPS
4365 priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup;
4366// priv->ieee80211->ps_request_tx_ack = rtl8192_rq_tx_ack;
4367 priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep;
4368 priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty;
4369 //added by david
4370 priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8192;
4371 priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xUsb;
4372 priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode;
4373 //added by amy
4374 priv->ieee80211->InitialGainHandler = priv->ops->rtl819x_initial_gain;
4375 priv->card_type = USB;
4376
4377#ifdef RTL8192SU
4378//1 RTL8192SU/
4379 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
4380 priv->ieee80211->SetFwCmdHandler = HalSetFwCmd8192S;
4381 priv->bRFSiOrPi = 0;//o=si,1=pi;
4382 //lzm add
4383 priv->bInHctTest = false;
4384
4385 priv->MidHighPwrTHR_L1 = 0x3B;
4386 priv->MidHighPwrTHR_L2 = 0x40;
4387
4388 if(priv->bInHctTest)
4389 {
4390 priv->ShortRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
4391 priv->LongRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
4392 }
4393 else
4394 {
4395 priv->ShortRetryLimit = HAL_RETRY_LIMIT_INFRA;
4396 priv->LongRetryLimit = HAL_RETRY_LIMIT_INFRA;
4397 }
4398
4399 priv->SetFwCmdInProgress = false; //is set FW CMD in Progress? 92S only
4400 priv->CurrentFwCmdIO = 0;
4401
4402 priv->MinSpaceCfg = 0;
4403
4404 priv->EarlyRxThreshold = 7;
4405 priv->enable_gpio0 = 0;
4406 priv->TransmitConfig =
4407 ((u32)TCR_MXDMA_2048<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
4408 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit
4409 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
4410 (false ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
4411 if(priv->bInHctTest)
4412 priv->ReceiveConfig = //priv->CSMethod |
4413 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
4414 RCR_ACF |RCR_APPFCS| //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
4415 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
4416 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
4417 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
4418 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
4419 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
4420 (priv->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
4421 else
4422 priv->ReceiveConfig = //priv->CSMethod |
4423 RCR_AMF | RCR_ADF | RCR_AB |
4424 RCR_AM | RCR_APM |RCR_AAP |RCR_ADD3|RCR_APP_ICV|
4425 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
4426 RCR_APP_MIC | RCR_APPFCS;
4427
4428 // <Roger_EXP> 2008.06.16.
4429 priv->IntrMask = (u16)(IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \
4430 IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \
4431 IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW | \
4432 IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
4433
4434//1 End
4435
4436#else
4437
4438#ifdef TO_DO_LIST
4439 if(Adapter->bInHctTest)
4440 {
4441 pHalData->ShortRetryLimit = 7;
4442 pHalData->LongRetryLimit = 7;
4443 }
4444#endif
4445 {
4446 priv->ShortRetryLimit = 0x30;
4447 priv->LongRetryLimit = 0x30;
4448 }
4449 priv->EarlyRxThreshold = 7;
4450 priv->enable_gpio0 = 0;
4451 priv->TransmitConfig =
4452 // TCR_DurProcMode | //for RTL8185B, duration setting by HW
4453 //? TCR_DISReqQsize |
4454 (TCR_MXDMA_2048<<TCR_MXDMA_OFFSET)| // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
4455 (priv->ShortRetryLimit<<TCR_SRL_OFFSET)| // Short retry limit
4456 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
4457 (false ? TCR_SAT: 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
4458#ifdef TO_DO_LIST
4459 if(Adapter->bInHctTest)
4460 pHalData->ReceiveConfig = pHalData->CSMethod |
4461 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
4462 //guangan200710
4463 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
4464 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
4465 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
4466 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
4467 (pHalData->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
4468 (pHalData->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
4469 else
4470
4471#endif
4472 priv->ReceiveConfig =
4473 RCR_AMF | RCR_ADF | //accept management/data
4474 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
4475 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
4476 //RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
4477 ((u32)7<<RCR_MXDMA_OFFSET)| // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
4478 (priv->EarlyRxThreshold<<RX_FIFO_THRESHOLD_SHIFT) | // Rx FIFO Threshold, 7: No Rx threshold.
4479 (priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0);
4480#endif
4481
4482 priv->AcmControl = 0;
4483 priv->pFirmware = (rt_firmware*)vmalloc(sizeof(rt_firmware));
4484 if (priv->pFirmware)
4485 memset(priv->pFirmware, 0, sizeof(rt_firmware));
4486
4487 /* rx related queue */
4488 skb_queue_head_init(&priv->rx_queue);
4489 skb_queue_head_init(&priv->skb_queue);
4490
4491 /* Tx related queue */
4492 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
4493 skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]);
4494 }
4495 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
4496 skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]);
4497 }
4498 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
4499 skb_queue_head_init(&priv->ieee80211->skb_drv_aggQ [i]);
4500 }
4501 priv->rf_set_chan = rtl8192_phy_SwChnl;
4502}
4503
4504//init lock here
4505static void rtl8192_init_priv_lock(struct r8192_priv* priv)
4506{
4507 spin_lock_init(&priv->tx_lock);
4508 spin_lock_init(&priv->irq_lock);//added by thomas
4509 //spin_lock_init(&priv->rf_lock);//use rf_sem, or will crash in some OS.
4510 sema_init(&priv->wx_sem,1);
4511 sema_init(&priv->rf_sem,1);
4512 spin_lock_init(&priv->ps_lock);
5f53d8ca 4513 mutex_init(&priv->mutex);
5f53d8ca
JC		 4514}
4515
5f53d8ca 4516extern void rtl819x_watchdog_wqcallback(struct work_struct *work);
5f53d8ca
JC		 4517
4518void rtl8192_irq_rx_tasklet(struct r8192_priv *priv);
4519//init tasklet and wait_queue here. only 2.6 above kernel is considered
4520#define DRV_NAME "wlan0"
4521static void rtl8192_init_priv_task(struct net_device* dev)
4522{
4523 struct r8192_priv *priv = ieee80211_priv(dev);
4524
5f53d8ca
JC		 4525#ifdef PF_SYNCTHREAD
4526 priv->priv_wq = create_workqueue(DRV_NAME,0);
4527#else
4528 priv->priv_wq = create_workqueue(DRV_NAME);
4529#endif
5f53d8ca 4530
5f53d8ca
JC		 4531 INIT_WORK(&priv->reset_wq, rtl8192_restart);
4532
4533 //INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog);
4534 INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback);
4535 INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback);
4536// INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
4537 INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback);
4538 INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon);
4539 INIT_DELAYED_WORK(&priv->initialgain_operate_wq, InitialGainOperateWorkItemCallBack);
4540 //INIT_WORK(&priv->SwChnlWorkItem, rtl8192_SwChnl_WorkItem);
4541 //INIT_WORK(&priv->SetBWModeWorkItem, rtl8192_SetBWModeWorkItem);
4542 INIT_WORK(&priv->qos_activate, rtl8192_qos_activate);
4543 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq);
4544 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq);
4545
5f53d8ca
JC		 4546 tasklet_init(&priv->irq_rx_tasklet,
4547 (void(*)(unsigned long))rtl8192_irq_rx_tasklet,
4548 (unsigned long)priv);
4549}
4550
4551static void rtl8192_get_eeprom_size(struct net_device* dev)
4552{
4553 u16 curCR = 0;
4554 struct r8192_priv *priv = ieee80211_priv(dev);
4555 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
4556 curCR = read_nic_word_E(dev,EPROM_CMD);
4557 RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR);
4558 //whether need I consider BIT5?
4559 priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46;
4560 RT_TRACE(COMP_EPROM, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype);
4561}
4562
4563//used to swap endian. as ntohl & htonl are not neccessary to swap endian, so use this instead.
4564static inline u16 endian_swap(u16* data)
4565{
4566 u16 tmp = *data;
4567 *data = (tmp >> 8) | (tmp << 8);
4568 return *data;
4569}
4570
4571#ifdef RTL8192SU
4572u8 rtl8192SU_UsbOptionToEndPointNumber(u8 UsbOption)
4573{
4574 u8 nEndPoint = 0;
4575 switch(UsbOption)
4576 {
4577 case 0:
4578 nEndPoint = 6;
4579 break;
4580 case 1:
4581 nEndPoint = 11;
4582 break;
4583 case 2:
4584 nEndPoint = 4;
4585 break;
4586 default:
4587 RT_TRACE(COMP_INIT, "UsbOptionToEndPointNumber(): Invalid UsbOption(%#x)\n", UsbOption);
4588 break;
4589 }
4590 return nEndPoint;
4591}
4592
4593u8 rtl8192SU_BoardTypeToRFtype(struct net_device* dev, u8 Boardtype)
4594{
4595 u8 RFtype = RF_1T2R;
4596
4597 switch(Boardtype)
4598 {
4599 case 0:
4600 RFtype = RF_1T1R;
4601 break;
4602 case 1:
4603 RFtype = RF_1T2R;
4604 break;
4605 case 2:
4606 RFtype = RF_2T2R;
4607 break;
4608 case 3:
4609 RFtype = RF_2T2R_GREEN;
4610 break;
4611 default:
4612 break;
4613 }
4614
4615 return RFtype;
4616}
4617
4618//
4619// Description:
4620// Config HW adapter information into initial value.
4621//
4622// Assumption:
4623// 1. After Auto load fail(i.e, check CR9346 fail)
4624//
4625// Created by Roger, 2008.10.21.
4626//
4627void
4628rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
4629{
4630 struct r8192_priv *priv = ieee80211_priv(dev);
4631 //u16 i,usValue;
4632 //u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
4633 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
4634 int i;
4635
4636 RT_TRACE(COMP_INIT, "====> ConfigAdapterInfo8192SForAutoLoadFail\n");
4637
4638 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4639 //PlatformStallExecution(10000);
4640 mdelay(10);
4641 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
4642
4643 //RT_ASSERT(priv->AutoloadFailFlag==TRUE, ("ReadAdapterInfo8192SEEPROM(): AutoloadFailFlag !=TRUE\n"));
4644
4645 // Initialize IC Version && Channel Plan
4646 priv->eeprom_vid = 0;
4647 priv->eeprom_pid = 0;
4648 priv->card_8192_version = 0;
4649 priv->eeprom_ChannelPlan = 0;
4650 priv->eeprom_CustomerID = 0;
4651 priv->eeprom_SubCustomerID = 0;
4652 priv->bIgnoreDiffRateTxPowerOffset = false;
4653
4654 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
4655 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
4656 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
4657 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
4658 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
4659 RT_TRACE(COMP_INIT, "IgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
4660
4661
4662
4663 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
4664 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
4665
4666 for(i=0; i<5; i++)
4667 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
4668
4669 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("EFUSE USB PHY Param: \n"), priv->EEPROMUsbPhyParam, 5);
4670
4671 {
4672 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
4673 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
4674 u8 i;
4675
4676 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
4677
4678 for(i = 0; i < 6; i++)
4679 dev->dev_addr[i] = sMacAddr[i];
4680 }
4681 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
4682 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
4683 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
4684
4685 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
4686 dev->dev_addr[0], dev->dev_addr[1],
4687 dev->dev_addr[2], dev->dev_addr[3],
4688 dev->dev_addr[4], dev->dev_addr[5]);
4689
4690 priv->EEPROMBoardType = EEPROM_Default_BoardType;
4691 priv->rf_type = RF_1T2R; //RF_2T2R
4692 priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
4693 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
4694 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
4695 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
4696 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
4697 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
4698 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
4699
4700
5f53d8ca
JC		 4701
4702 for (rf_path = 0; rf_path < 2; rf_path++)
4703 {
4704 for (i = 0; i < 3; i++)
4705 {
4706 // Read CCK RF A & B Tx power
4707 priv->RfCckChnlAreaTxPwr[rf_path][i] =
4708 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
4709 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
4710 (u8)(EEPROM_Default_TxPower & 0xff);
4711 }
4712 }
4713
4714 for (i = 0; i < 3; i++)
4715 {
4716 //RT_TRACE((COMP_EFUSE), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
4717 //priv->RfCckChnlAreaTxPwr[rf_path][i]);
4718 //RT_TRACE((COMP_EFUSE), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
4719 //priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
4720 //RT_TRACE((COMP_EFUSE), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
4721 //priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
4722 }
4723
4724 // Assign dedicated channel tx power
4725 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
4726 {
4727 if (i < 3) // Cjanel 1-3
4728 index = 0;
4729 else if (i < 9) // Channel 4-9
4730 index = 1;
4731 else // Channel 10-14
4732 index = 2;
4733
4734 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
4735 priv->RfTxPwrLevelCck[rf_path][i] =
4736 priv->RfCckChnlAreaTxPwr[rf_path][index];
4737 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
4738 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
4739 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
4740 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
4741 }
4742
4743 for(i=0; i<14; i++)
4744 {
4745 //RT_TRACE((COMP_EFUSE), "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
4746 //rf_path, i, priv->RfTxPwrLevelCck[0][i],
4747 //priv->RfTxPwrLevelOfdm1T[0][i] ,
4748 //priv->RfTxPwrLevelOfdm2T[0][i] );
4749 }
5f53d8ca
JC		 4750
4751 //
4752 // Update remained HAL variables.
4753 //
4754 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
4755 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;//new
4756 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
4757 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit0~3
4758 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit4~7
4759 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit12~15
4760 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
4761 priv->LedStrategy = SW_LED_MODE0;
4762
4763 init_rate_adaptive(dev);
4764
4765 RT_TRACE(COMP_INIT, "<==== ConfigAdapterInfo8192SForAutoLoadFail\n");
4766
4767}
4768
4769#if 0
4770static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
4771{
4772 u16 EEPROMId = 0;
4773 u8 bLoad_From_EEPOM = false;
4774 struct r8192_priv *priv = ieee80211_priv(dev);
4775 u16 tmpValue = 0;
4776 u8 tmpBuffer[30];
4777 int i;
4778
4779 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
4780
4781
4782 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4783 udelay(10000);
4784 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
4785
4786
4787 EEPROMId = eprom_read(dev, 0); //first read EEPROM ID out;
4788 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", EEPROMId);
4789
4790 if (EEPROMId != RTL8190_EEPROM_ID)
4791 {
4792 priv->AutoloadFailFlag = true;
4793 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", EEPROMId, RTL8190_EEPROM_ID);
4794 }
4795 else
4796 {
4797 priv->AutoloadFailFlag = false;
4798 bLoad_From_EEPOM = true;
4799 }
4800
4801 if (bLoad_From_EEPOM)
4802 {
4803 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
4804 priv->eeprom_vid = endian_swap(&tmpValue);
4805 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
4806
4807 // Version ID, Channel plan
4808 tmpValue = eprom_read(dev, (EEPROM_Version>>1));
4809 //pHalData->card_8192_version = (VERSION_8192S)((usValue&0x00ff));
4810 priv->eeprom_ChannelPlan =(tmpValue&0xff00)>>8;
4811 priv->bTXPowerDataReadFromEEPORM = true;
4812
4813 // Customer ID, 0x00 and 0xff are reserved for Realtek.
4814 tmpValue = eprom_read(dev, (u16)(EEPROM_CustomID>>1)) ;
4815 priv->eeprom_CustomerID = (u8)( tmpValue & 0xff);
4816 priv->eeprom_SubCustomerID = (u8)((tmpValue & 0xff00)>>8);
4817 }
4818 else
4819 {
4820 priv->eeprom_vid = 0;
4821 priv->eeprom_pid = 0;
4822 //priv->card_8192_version = VERSION_8192SU_A;
4823 priv->eeprom_ChannelPlan = 0;
4824 priv->eeprom_CustomerID = 0;
4825 priv->eeprom_SubCustomerID = 0;
4826 }
4827 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
4828 //set channelplan from eeprom
4829 priv->ChannelPlan = priv->eeprom_ChannelPlan;// FIXLZM
4830
4831 RT_TRACE(COMP_INIT, "EEPROMId = 0x%4x\n", EEPROMId);
4832 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
4833 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
4834 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
4835 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
4836 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
4837 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
4838
4839 // Read USB optional function.
4840 if(bLoad_From_EEPOM)
4841 {
4842 tmpValue = eprom_read(dev, (EEPROM_USB_OPTIONAL>>1));
4843 priv->EEPROMUsbOption = (u8)(tmpValue&0xff);
4844 }
4845 else
4846 {
4847 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
4848 }
4849
4850 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
4851
4852
4853 if (bLoad_From_EEPOM)
4854 {
4855 int i;
4856 for (i=0; i<6; i+=2)
4857 {
4858 u16 tmp = 0;
4859 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
4860 *(u16*)(&dev->dev_addr[i]) = tmp;
4861 }
4862 }
4863 else
4864 {
4865 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
4866 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
4867 u8 i;
4868
4869 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
4870
4871 for(i = 0; i < 6; i++)
4872 dev->dev_addr[i] = sMacAddr[i];
4873
4874 //memcpy(dev->dev_addr, sMacAddr, 6);
4875 //should I set IDR0 here?
4876 }
4877 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
4878 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
4879 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
4880
4881 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
5f53d8ca
JC		 4882 priv->rf_chip = RF_6052;
4883 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
4884 //priv->card_8192_version = VERSION_8192SU_A; //Over write for temporally experiment. 2008.10.16. By Roger.
5f53d8ca
JC		 4885
4886 {
4887#if 0
4888 if(bLoad_From_EEPOM)
4889 {
4890 tempval = (ReadEEprom(Adapter, (EEPROM_RFInd_PowerDiff>>1))) & 0xff;
4891 if (tempval&0x80) //RF-indication, bit[7]
4892 pHalData->RF_Type = RF_1T2R;
4893 else
4894 pHalData->RF_Type = RF_2T4R;
4895 }
4896#endif
4897
4898 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
4899 RT_TRACE(COMP_INIT, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff);
4900
4901
4902 //
4903 // Read antenna tx power offset of B/C/D to A from EEPROM
4904 // and read ThermalMeter from EEPROM
4905 //
4906 if(bLoad_From_EEPOM)
4907 {
4908 tmpValue = eprom_read(dev, (EEPROM_PwDiff>>1));
4909 priv->EEPROMPwDiff = tmpValue&0x00ff;
4910 priv->EEPROMThermalMeter = (tmpValue&0xff00)>>8;
4911 }
4912 else
4913 {
4914 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
4915 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
4916 }
4917 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
4918 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
4919
4920 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
4921
4922
4923 // Read CrystalCap from EEPROM
4924 if(bLoad_From_EEPOM)
4925 {
4926 priv->EEPROMCrystalCap =(u8) (((eprom_read(dev, (EEPROM_CrystalCap>>1)))&0xf000)>>12);
4927 }
4928 else
4929 {
4930 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
4931 }
4932 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
4933
4934
4935 //if(pHalData->EEPROM_Def_Ver == 0) // old eeprom definition
4936 {
4937
4938 //
4939 // Get Tx Power Base.//===>
4940 //
4941 if(bLoad_From_EEPOM)
4942 {
4943 priv->EEPROMTxPwrBase =(u8) ((eprom_read(dev, (EEPROM_TxPowerBase>>1)))&0xff);
4944 }
4945 else
4946 {
4947 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
4948 }
4949
4950 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
4951
4952 //
4953 // Get CustomerID(Boad Type)
4954 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
4955 // Others: Reserved. Default is 0x2: RTL8192SU.
4956 //
4957 if(bLoad_From_EEPOM)
4958 {
4959 tmpValue = eprom_read(dev, (u16) (EEPROM_BoardType>>1));
4960 priv->EEPROMBoardType = (u8)(tmpValue&0xff);
4961 }
4962 else
4963 {
4964 priv->EEPROMBoardType = EEPROM_Default_BoardType;
4965 }
4966
4967 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
4968
5f53d8ca
JC		 4969 // Please add code in the section!!!!
4970 // And merge tx power difference section.
5f53d8ca
JC		 4971
4972 //
4973 // Get TSSI value for each path.
4974 //
4975 if(bLoad_From_EEPOM)
4976 {
4977 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_A)>>1));
4978 priv->EEPROMTSSI_A = (u8)((tmpValue&0xff00)>>8);
4979 }
4980 else
4981 { // Default setting for Empty EEPROM
4982 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
4983 }
4984
4985 if(bLoad_From_EEPOM)
4986 {
4987 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_B)>>1));
4988 priv->EEPROMTSSI_B = (u8)(tmpValue&0xff);
4989 priv->EEPROMTxPwrTkMode = (u8)((tmpValue&0xff00)>>8);
4990 }
4991 else
4992 { // Default setting for Empty EEPROM
4993 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
4994 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
4995 }
4996
4997 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
4998 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
4999
5f53d8ca 5000
5f53d8ca
JC		 5001 }
5002
5f53d8ca 5003
5f53d8ca
JC		 5004 priv->TxPowerDiff = priv->EEPROMPwDiff;
5005 // Antenna B gain offset to antenna A, bit0~3
5006 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
5007 // Antenna C gain offset to antenna A, bit4~7
5008 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
5009 // CrystalCap, bit12~15
5010 priv->CrystalCap = priv->EEPROMCrystalCap;
5011 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5012 // 92U does not enable TX power tracking.
5013 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
5014 }
5015
5016 priv->LedStrategy = SW_LED_MODE0;
5017
5018 if(priv->rf_type == RF_1T2R)
5019 {
5020 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
5021 }
5022 else
5023 {
5024 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
5025 }
5026
5027 // 2008/01/16 MH We can only know RF type in the function. So we have to init
5028 // DIG RATR table again.
5029 init_rate_adaptive(dev);
5030 //we need init DIG RATR table here again.
5031
5032 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
5033 return;
5034}
5035
5036//
5037// Description:
5038// 1. Read HW adapter information by E-Fuse.
5039// 2. Refered from SD1 Richard.
5040//
5041// Assumption:
5042// 1. Boot from E-Fuse and CR9346 regiser has verified.
5043// 2. PASSIVE_LEVEL (USB interface)
5044//
5045// Created by Roger, 2008.10.21.
5046//
5047void
5048rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
5049{
5050 struct r8192_priv *priv = ieee80211_priv(dev);
5051 u16 i,usValue;
5052 u16 EEPROMId;
5053 u8 readbyte;
5054 u8 OFDMTxPwr[14];
5055 u8 CCKTxPwr[14];
5056 u8 HT2T_TxPwr[6];
5057 u8 UsbPhyParam[5];
5058 u8 hwinfo[HWSET_MAX_SIZE_92S];
5059
5060
5061 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SEFuse\n");
5062
5063 //
5064 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
5065 // from suspend mode.
5066 // 2008.10.21.
5067 //
5068 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5069 //PlatformStallExecution(10000);
5070 mdelay(10);
5071 write_nic_byte(dev, SYS_FUNC_EN+1, 0x40);
5072 write_nic_byte(dev, SYS_FUNC_EN+1, 0x50);
5073
5074 readbyte = read_nic_byte(dev, EFUSE_TEST+3);
5075 write_nic_byte(dev, EFUSE_TEST+3, (readbyte | 0x80));
5076 write_nic_byte(dev, EFUSE_TEST+3, 0x72);
5077 write_nic_byte(dev, EFUSE_CLK, 0x03);
5078
5079 //
5080 // Dump EFUSe at init time for later use
5081 //
5082 // Read EFUSE real map to shadow!!
5083 EFUSE_ShadowMapUpdate(dev);
5084
5085 memcpy(hwinfo, (void*)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
5086 //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("MAP \n"), hwinfo, HWSET_MAX_SIZE_92S);
5087
5088 //
5089 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
5090 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
5091 // 2008.10.21.
5092 //
5093 ReadEFuse(dev, 0, 2, (unsigned char*) &EEPROMId);
5094
5095 if( EEPROMId != RTL8190_EEPROM_ID )
5096 {
5097 RT_TRACE(COMP_INIT, "EEPROM ID(%#x) is invalid!!\n", EEPROMId);
5098 priv->AutoloadFailFlag=true;
5099 }
5100 else
5101 {
5102 priv->AutoloadFailFlag=false;
5103 }
5104
5105 // Read IC Version && Channel Plan
5106 if(!priv->AutoloadFailFlag)
5107 {
5108
5109 // VID, PID
5110 ReadEFuse(dev, EEPROM_VID, 2, (unsigned char*) &priv->eeprom_vid);
5111 ReadEFuse(dev, EEPROM_PID, 2, (unsigned char*) &priv->eeprom_pid);
5112
5113 // Version ID, Channel plan
5114 ReadEFuse(dev, EEPROM_Version, 2, (unsigned char*) &usValue);
5115 //pHalData->VersionID = (VERSION_8192S)(usValue&0x00ff);
5116 priv->eeprom_ChannelPlan = (usValue&0xff00>>8);
5117 priv->bTXPowerDataReadFromEEPORM = true;
5118
5119 // Customer ID, 0x00 and 0xff are reserved for Realtek.
5120 ReadEFuse(dev, EEPROM_CustomID, 2, (unsigned char*) &usValue);
5121 priv->eeprom_CustomerID = (u8)( usValue & 0xff);
5122 priv->eeprom_SubCustomerID = (u8)((usValue & 0xff00)>>8);
5123 }
5124 else
5125 {
5126 priv->eeprom_vid = 0;
5127 priv->eeprom_pid = 0;
5128 priv->eeprom_ChannelPlan = 0;
5129 priv->eeprom_CustomerID = 0;
5130 priv->eeprom_SubCustomerID = 0;
5131 }
5132
5133 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
5134 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5135 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5136 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
5137 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5138 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5139 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5140
5141
5142 // Read USB optional function.
5143 if(!priv->AutoloadFailFlag)
5144 {
5145 ReadEFuse(dev, EEPROM_USB_OPTIONAL, 1, (unsigned char*) &priv->EEPROMUsbOption);
5146 }
5147 else
5148 {
5149 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5150 }
5151
5152 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5153
5154
5155 // Read USB PHY parameters.
5156 if(!priv->AutoloadFailFlag)
5157 {
5158 ReadEFuse(dev, EEPROM_USB_PHY_PARA1, 5, (unsigned char*)UsbPhyParam);
5159 for(i=0; i<5; i++)
5160 {
5161 priv->EEPROMUsbPhyParam[i] = UsbPhyParam[i];
5162 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
5163 }
5164 }
5165 else
5166 {
5167 for(i=0; i<5; i++)
5168 {
5169 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
5170 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
5171 }
5172 }
5173
5174
5175 //Read Permanent MAC address
5176 if(!priv->AutoloadFailFlag)
5177 {
5178 u8 macaddr[6] = {0x00, 0xe1, 0x86, 0x4c, 0x92, 0x00};
5179
5180 ReadEFuse(dev, EEPROM_NODE_ADDRESS_BYTE_0, 6, (unsigned char*)macaddr);
5181 for(i=0; i<6; i++)
5182 dev->dev_addr[i] = macaddr[i];
5183 }
5184 else
5185 {//Auto load fail
5186
5187 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5188 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5189 u8 i;
5190
5191 //if(!Adapter->bInHctTest)
5192 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5193
5194 for(i = 0; i < 6; i++)
5195 dev->dev_addr[i] = sMacAddr[i];
5196 }
5197
5198 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
5199 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5200 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5201
5202 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
5203 dev->dev_addr[0], dev->dev_addr[1],
5204 dev->dev_addr[2], dev->dev_addr[3],
5205 dev->dev_addr[4], dev->dev_addr[5]);
5206
5207 // 2007/11/15 MH For RTL8192USB we assign as 1T2R now.
5208 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; // default : 1T2R
5209
5f53d8ca
JC		 5210 priv->rf_chip = RF_6052;
5211 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
5f53d8ca
JC		 5212
5213 {
5214 //
5215 // Read antenna tx power offset of B/C/D to A from EEPROM
5216 // and read ThermalMeter from EEPROM
5217 //
5218 if(!priv->AutoloadFailFlag)
5219 {
5220 ReadEFuse(dev, EEPROM_PwDiff, 2, (unsigned char*) &usValue);
5221 priv->EEPROMPwDiff = usValue&0x00ff;
5222 priv->EEPROMThermalMeter = (usValue&0xff00)>>8;
5223 }
5224 else
5225 {
5226 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
5227 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5228 }
5229
5230 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
5231 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5232
5233 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5234
5235 //
5236 // Read Tx Power gain offset of legacy OFDM to HT rate.
5237 // Read CrystalCap from EEPROM
5238 //
5239 if(!priv->AutoloadFailFlag)
5240 {
5241 ReadEFuse(dev, EEPROM_CrystalCap, 1, (unsigned char*) &usValue);
5242 priv->EEPROMCrystalCap = (u8)((usValue&0xf0)>>4);
5243 }
5244 else
5245 {
5246 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5247 }
5248
5249 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
5250
5251 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
5252 RT_TRACE(COMP_INIT, "TxPowerDiff = %d\n", priv->EEPROMTxPowerDiff);
5253
5254
5255 //
5256 // Get Tx Power Base.
5257 //
5258 if(!priv->AutoloadFailFlag)
5259 {
5260 ReadEFuse(dev, EEPROM_TxPowerBase, 1, (unsigned char*) &priv->EEPROMTxPwrBase );
5261 }
5262 else
5263 {
5264 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5265 }
5266
5267 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
5268
5269 //
5270 // Get CustomerID(Boad Type)
5271 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
5272 // Others: Reserved. Default is 0x2: RTL8192SU.
5273 //
5274 if(!priv->AutoloadFailFlag)
5275 {
5276 ReadEFuse(dev, EEPROM_BoardType, 1, (unsigned char*) &priv->EEPROMBoardType );
5277 }
5278 else
5279 {
5280 priv->EEPROMBoardType = EEPROM_Default_BoardType;
5281 }
5282
5283 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
5284
5285 //if(pHalData->EEPROM_Def_Ver == 0)
5286 {
5f53d8ca
JC		 5287 // Please add code in the section!!!!
5288 // And merge tx power difference section.
5f53d8ca
JC		 5289
5290 //
5291 // Get TSSI value for each path.
5292 //
5293 if(!priv->AutoloadFailFlag)
5294 {
5295 ReadEFuse(dev, EEPROM_TSSI_A, 2, (unsigned char*)&usValue);
5296 priv->EEPROMTSSI_A = (u8)(usValue&0xff);
5297 priv->EEPROMTSSI_B = (u8)((usValue&0xff00)>>8);
5298 }
5299 else
5300 { // Default setting for Empty EEPROM
5301 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5302 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5303 }
5304
5305 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n",
5306 priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5307
5308 //
5309 // Get Tx Power tracking mode.
5310 //
5311 if(!priv->AutoloadFailFlag)
5312 {
5313 ReadEFuse(dev, EEPROM_TxPwTkMode, 1, (unsigned char*)&priv->EEPROMTxPwrTkMode);
5314 }
5315 else
5316 { // Default setting for Empty EEPROM
5317 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5318 }
5319
5320 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5321
5322
5323 // TODO: The following HT 2T Path A and B Power Index should be updated.!! Added by Roger, 2008.20.23.
5324
5325 //
5326 // Get HT 2T Path A and B Power Index.
5327 //
5328 if(!priv->AutoloadFailFlag)
5329 {
5330 ReadEFuse(dev, EEPROM_HT2T_CH1_A, 6, (unsigned char*)HT2T_TxPwr);
5331 for(i=0; i<6; i++)
5332 {
5333 priv->EEPROMHT2T_TxPwr[i] = HT2T_TxPwr[i];
5334 }
5335 }
5336 else
5337 { // Default setting for Empty EEPROM
5338 for(i=0; i<6; i++)
5339 {
5340 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5341 }
5342 }
5343
5344 for(i=0; i<6; i++)
5345 {
5346 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n",
5347 i, priv->EEPROMHT2T_TxPwr[i]);
5348 }
5349 }
5350
5f53d8ca 5351
5f53d8ca
JC		 5352 priv->TxPowerDiff = priv->EEPROMPwDiff;
5353 // Antenna B gain offset to antenna A, bit0~3
5354 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
5355 // Antenna C gain offset to antenna A, bit4~7
5356 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
5357 // CrystalCap, bit12~15
5358 priv->CrystalCap = priv->EEPROMCrystalCap;
5359 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5360 // 92U does not enable TX power tracking.
5361 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
5362 }
5363
5364 priv->LedStrategy = SW_LED_MODE0;
5365
5366 init_rate_adaptive(dev);
5367
5368 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SEFuse\n");
5369
5370}
5371#endif
5372
5373//
5374// Description:
5375// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
5376//
5377// Assumption:
5378// 1. CR9346 regiser has verified.
5379// 2. PASSIVE_LEVEL (USB interface)
5380//
5381// Created by Roger, 2008.10.21.
5382//
5383void
5384rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
5385{
5386 struct r8192_priv *priv = ieee80211_priv(dev);
5387 u16 i,usValue;
5388 u8 tmpU1b, tempval;
5389 u16 EEPROMId;
5390 u8 hwinfo[HWSET_MAX_SIZE_92S];
5391 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
5392
5393
5394 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
5395
5396 //
5397 // <Roger_Note> The following operation are prevent Efuse leakage by turn on 2.5V.
5398 // 2008.11.25.
5399 //
5400 tmpU1b = read_nic_byte(dev, EFUSE_TEST+3);
5401 write_nic_byte(dev, EFUSE_TEST+3, tmpU1b|0x80);
5402 //PlatformStallExecution(1000);
5403 mdelay(10);
5404 write_nic_byte(dev, EFUSE_TEST+3, (tmpU1b&(~BIT7)));
5405
5406 // Retrieve Chip version.
5407 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
5408 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
5409
5410 switch(priv->card_8192_version)
5411 {
5412 case 0:
5413 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_ACUT.\n");
5414 break;
5415 case 1:
5416 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_BCUT.\n");
5417 break;
5418 case 2:
5419 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_CCUT.\n");
5420 break;
5421 default:
5422 RT_TRACE(COMP_INIT, "Unknown Chip Version!!\n");
5423 priv->card_8192_version = VERSION_8192S_BCUT;
5424 break;
5425 }
5426
5427 //if (IS_BOOT_FROM_EEPROM(Adapter))
5428 if(priv->EepromOrEfuse)
5429 { // Read frin EEPROM
5430 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5431 //PlatformStallExecution(10000);
5432 mdelay(10);
5433 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
5434 // Read all Content from EEPROM or EFUSE.
5435 for(i = 0; i < HWSET_MAX_SIZE_92S; i += 2)
5436 {
5437 usValue = eprom_read(dev, (u16) (i>>1));
5438 *((u16*)(&hwinfo[i])) = usValue;
5439 }
5440 }
5441 else if (!(priv->EepromOrEfuse))
5442 { // Read from EFUSE
5443
5444 //
5445 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
5446 // from suspend mode.
5447 // 2008.10.21.
5448 //
5449 //PlatformEFIOWrite1Byte(Adapter, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5450 //PlatformStallExecution(10000);
5451 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x40);
5452 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x50);
5453
5454 //tmpU1b = PlatformEFIORead1Byte(Adapter, EFUSE_TEST+3);
5455 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, (tmpU1b | 0x80));
5456 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, 0x72);
5457 //PlatformEFIOWrite1Byte(Adapter, EFUSE_CLK, 0x03);
5458
5459 // Read EFUSE real map to shadow.
5460 EFUSE_ShadowMapUpdate(dev);
5461 memcpy(hwinfo, &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
5462 }
5463 else
5464 {
5465 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SUsb(): Invalid boot type!!\n");
5466 }
5467
5468 //YJ,test,090106
5469 //dump_buf(hwinfo,HWSET_MAX_SIZE_92S);
5470 //
5471 // <Roger_Notes> The following are EFUSE/EEPROM independent operations!!
5472 //
5473 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("MAP: \n"), hwinfo, HWSET_MAX_SIZE_92S);
5474
5475 //
5476 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
5477 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
5478 // 2008.10.21.
5479 //
5480 EEPROMId = *((u16 *)&hwinfo[0]);
5481
5482 if( EEPROMId != RTL8190_EEPROM_ID )
5483 {
5484 RT_TRACE(COMP_INIT, "ID(%#x) is invalid!!\n", EEPROMId);
5485 priv->bTXPowerDataReadFromEEPORM = FALSE;
5486 priv->AutoloadFailFlag=TRUE;
5487 }
5488 else
5489 {
5490 priv->AutoloadFailFlag=FALSE;
5f53d8ca 5491 priv->bTXPowerDataReadFromEEPORM = TRUE;
5f53d8ca
JC		 5492 }
5493 // Read IC Version && Channel Plan
5494 if(!priv->AutoloadFailFlag)
5495 {
5496 // VID, PID
5497 priv->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
5498 priv->eeprom_pid = *(u16 *)&hwinfo[EEPROM_PID];
5499 priv->bIgnoreDiffRateTxPowerOffset = false; //cosa for test
5500
5501
5502 // EEPROM Version ID, Channel plan
5503 priv->EEPROMVersion = *(u8 *)&hwinfo[EEPROM_Version];
5504 priv->eeprom_ChannelPlan = *(u8 *)&hwinfo[EEPROM_ChannelPlan];
5505
5506 // Customer ID, 0x00 and 0xff are reserved for Realtek.
5507 priv->eeprom_CustomerID = *(u8 *)&hwinfo[EEPROM_CustomID];
5508 priv->eeprom_SubCustomerID = *(u8 *)&hwinfo[EEPROM_SubCustomID];
5509 }
5510 else
5511 {
5512 //priv->eeprom_vid = 0;
5513 //priv->eeprom_pid = 0;
5514 //priv->EEPROMVersion = 0;
5515 //priv->eeprom_ChannelPlan = 0;
5516 //priv->eeprom_CustomerID = 0;
5517 //priv->eeprom_SubCustomerID = 0;
5518
5519 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
5520 return;
5521 }
5522
5523
5524 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
5525 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5526 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5527 RT_TRACE(COMP_INIT, "EEPROM Version ID: 0x%2x\n", priv->EEPROMVersion);
5528 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5529 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5530 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5531 RT_TRACE(COMP_INIT, "bIgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
5532
5533
5534 // Read USB optional function.
5535 if(!priv->AutoloadFailFlag)
5536 {
5537 priv->EEPROMUsbOption = *(u8 *)&hwinfo[EEPROM_USB_OPTIONAL];
5538 }
5539 else
5540 {
5541 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5542 }
5543
5544
5545 priv->EEPROMUsbEndPointNumber = rtl8192SU_UsbOptionToEndPointNumber((priv->EEPROMUsbOption&EEPROM_EP_NUMBER)>>3);
5546
5547 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5548 RT_TRACE(COMP_INIT, "EndPoint Number = %#x\n", priv->EEPROMUsbEndPointNumber);
5549
5550#ifdef TO_DO_LIST
5551 //
5552 // Decide CustomerID according to VID/DID or EEPROM
5553 //
5554 switch(pHalData->EEPROMCustomerID)
5555 {
5556 case EEPROM_CID_ALPHA:
5557 pMgntInfo->CustomerID = RT_CID_819x_ALPHA;
5558 break;
5559
5560 case EEPROM_CID_CAMEO:
5561 pMgntInfo->CustomerID = RT_CID_819x_CAMEO;
5562 break;
5563
5564 case EEPROM_CID_SITECOM:
5565 pMgntInfo->CustomerID = RT_CID_819x_Sitecom;
5566 RT_TRACE(COMP_INIT, DBG_LOUD, ("CustomerID = 0x%4x\n", pMgntInfo->CustomerID));
5567
5568 break;
5569
5570 case EEPROM_CID_WHQL:
5571 Adapter->bInHctTest = TRUE;
5572
5573 pMgntInfo->bSupportTurboMode = FALSE;
5574 pMgntInfo->bAutoTurboBy8186 = FALSE;
5575
5576 pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
5577 pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
5578 pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
5579 pMgntInfo->keepAliveLevel = 0;
5580 break;
5581
5582 default:
5583 pMgntInfo->CustomerID = RT_CID_DEFAULT;
5584 break;
5585
5586 }
5587
5588 //
5589 // Led mode
5590 //
5591 switch(pMgntInfo->CustomerID)
5592 {
5593 case RT_CID_DEFAULT:
5594 case RT_CID_819x_ALPHA:
5595 pHalData->LedStrategy = SW_LED_MODE1;
5596 pHalData->bRegUseLed = TRUE;
5597 pHalData->SwLed1.bLedOn = TRUE;
5598 break;
5599 case RT_CID_819x_CAMEO:
5600 pHalData->LedStrategy = SW_LED_MODE1;
5601 pHalData->bRegUseLed = TRUE;
5602 break;
5603
5604 case RT_CID_819x_Sitecom:
5605 pHalData->LedStrategy = SW_LED_MODE2;
5606 pHalData->bRegUseLed = TRUE;
5607 break;
5608
5609 default:
5610 pHalData->LedStrategy = SW_LED_MODE0;
5611 break;
5612 }
5613#endif
5614
5615 // Read USB PHY parameters.
5616 for(i=0; i<5; i++)
5617 priv->EEPROMUsbPhyParam[i] = *(u8 *)&hwinfo[EEPROM_USB_PHY_PARA1+i];
5618
5619 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("USB PHY Param: \n"), pHalData->EEPROMUsbPhyParam, 5);
5620
5621
5622 //Read Permanent MAC address
5623 for(i=0; i<6; i++)
5624 dev->dev_addr[i] = *(u8 *)&hwinfo[EEPROM_NODE_ADDRESS_BYTE_0+i];
5625
5626 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
5627 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5628 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5629
5630 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
5631 dev->dev_addr[0], dev->dev_addr[1],
5632 dev->dev_addr[2], dev->dev_addr[3],
5633 dev->dev_addr[4], dev->dev_addr[5]);
5634
5635 //
5636 // Get CustomerID(Boad Type)
5637 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
5638 // Others: Reserved. Default is 0x2: RTL8192SU.
5639 //
5640 //if(!priv->AutoloadFailFlag)
5641 //{
5642 priv->EEPROMBoardType = *(u8 *)&hwinfo[EEPROM_BoardType];
5643 priv->rf_type = rtl8192SU_BoardTypeToRFtype(dev, priv->EEPROMBoardType);
5644 //}
5645 //else
5646 //{
5647 // priv->EEPROMBoardType = EEPROM_Default_BoardType;
5648 // priv->rf_type = RF_1T2R;
5649 //}
5650
5f53d8ca 5651 priv->rf_chip = RF_6052;
5f53d8ca
JC		 5652
5653 priv->rf_chip = RF_6052;//lzm test
5654 RT_TRACE(COMP_INIT, "BoardType = 0x%2x\n", priv->EEPROMBoardType);
5655 RT_TRACE(COMP_INIT, "RF_Type = 0x%2x\n", priv->rf_type);
5656
5657 //
5658 // Read antenna tx power offset of B/C/D to A from EEPROM
5659 // and read ThermalMeter from EEPROM
5660 //
5661 //if(!priv->AutoloadFailFlag)
5662 {
5663 priv->EEPROMTxPowerDiff = *(u8 *)&hwinfo[EEPROM_PwDiff];
5664 priv->EEPROMThermalMeter = *(u8 *)&hwinfo[EEPROM_ThermalMeter];
5665 }
5666 //else
5667 //{
5668 // priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
5669 // priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5670 //}
5671
5672 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMTxPowerDiff);
5673 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5674
5675 //
5676 // Read Tx Power gain offset of legacy OFDM to HT rate.
5677 // Read CrystalCap from EEPROM
5678 //
5679 //if(!priv->AutoloadFailFlag)
5680 {
5681 priv->EEPROMCrystalCap = *(u8 *)&hwinfo[EEPROM_CrystalCap];
5682 }
5683 //else
5684 //{
5685 // priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5686 //}
5687
5688 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
5689
5690 //
5691 // Get Tx Power Base.
5692 //
5693 //if(!priv->AutoloadFailFlag)
5694 {
5695 priv->EEPROMTxPwrBase = *(u8 *)&hwinfo[EEPROM_TxPowerBase];
5696 }
5697 //else
5698 //{
5699 // priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5700 //}
5701
5702 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
5703
5704
5705 //
5706 // Get TSSI value for each path.
5707 //
5708 //if(!priv->AutoloadFailFlag)
5709 {
5710 priv->EEPROMTSSI_A = *(u8 *)&hwinfo[EEPROM_TSSI_A];
5711 priv->EEPROMTSSI_B = *(u8 *)&hwinfo[EEPROM_TSSI_B];
5712 }
5713 //else
5714 //{ // Default setting for Empty EEPROM
5715 // priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5716 // priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5717 //}
5718
5719 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5720
5721 //
5722 // Get Tx Power tracking mode.
5723 //
5724 //if(!priv->AutoloadFailFlag)
5725 {
5726 priv->EEPROMTxPwrTkMode = *(u8 *)&hwinfo[EEPROM_TxPwTkMode];
5727 }
5728
5729 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5730
5731
5f53d8ca
JC		 5732 {
5733 //
5734 // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes)
5735 // Update CCK, OFDM (1T/2T)Tx Power Index from above buffer.
5736 //
5737
5738 //
5739 // Get Tx Power Level by Channel
5740 //
5741 //if(!priv->AutoloadFailFlag)
5742 {
5743 // Read Tx power of Channel 1 ~ 14 from EFUSE.
5744 // 92S suupport RF A & B
5745 for (rf_path = 0; rf_path < 2; rf_path++)
5746 {
5747 for (i = 0; i < 3; i++)
5748 {
5749 // Read CCK RF A & B Tx power
5750 priv->RfCckChnlAreaTxPwr[rf_path][i] =
5751 hwinfo[EEPROM_TxPwIndex+rf_path*3+i];
5752
5753 // Read OFDM RF A & B Tx power for 1T
5754 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
5755 hwinfo[EEPROM_TxPwIndex+6+rf_path*3+i];
5756
5757 // Read OFDM RF A & B Tx power for 2T
5758 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
5759 hwinfo[EEPROM_TxPwIndex+12+rf_path*3+i];
5760 }
5761 }
5762
5763 }
5764//
5765 // Update Tx Power HAL variables.
5766//
5767 for (rf_path = 0; rf_path < 2; rf_path++)
5768 {
5769 for (i = 0; i < 3; i++)
5770 {
5771 RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5772 priv->RfCckChnlAreaTxPwr[rf_path][i]);
5773 RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5774 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
5775 RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
5776 }
5777
5778 // Assign dedicated channel tx power
5779 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
5780 {
5781 if (i < 3) // Cjanel 1-3
5782 index = 0;
5783 else if (i < 9) // Channel 4-9
5784 index = 1;
5785 else // Channel 10-14
5786 index = 2;
5787
5788 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
5789 priv->RfTxPwrLevelCck[rf_path][i] =
5790 priv->RfCckChnlAreaTxPwr[rf_path][index];
5791 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
5792 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
5793 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
5794 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
5795 if (rf_path == 0)
5796 {
5797 priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ;
5798 priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i];
5799 }
5800 }
5801
5802 for(i=0; i<14; i++)
5803 {
5804 RT_TRACE((COMP_INIT),
5805 "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
5806 rf_path, i, priv->RfTxPwrLevelCck[rf_path][i],
5807 priv->RfTxPwrLevelOfdm1T[rf_path][i] ,
5808 priv->RfTxPwrLevelOfdm2T[rf_path][i] );
5809 }
5810 }
5811 }
5812
5813 //
5814 // 2009/02/09 Cosa add for new EEPROM format
5815 //
5816 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
5817 {
5818 // Read tx power difference between HT OFDM 20/40 MHZ
5819 if (i < 3) // Cjanel 1-3
5820 index = 0;
5821 else if (i < 9) // Channel 4-9
5822 index = 1;
5823 else // Channel 10-14
5824 index = 2;
5825
5826 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF+index])&0xff;
5827 priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF);
5828 priv->TxPwrHt20Diff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
5829
5830 // Read OFDM<->HT tx power diff
5831 if (i < 3) // Cjanel 1-3
5832 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF])&0xff;
5833 else if (i < 9) // Channel 4-9
5834 tempval = (*(u8 *)&hwinfo[EEPROM_PwDiff])&0xff;
5835 else // Channel 10-14
5836 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+1])&0xff;
5837
5838 //cosa tempval = (*(u1Byte *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+index])&0xff;
5839 priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF);
5840 priv->TxPwrLegacyHtDiff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
5841
5842 //
5843 // Read Band Edge tx power offset and check if user enable the ability
5844 //
5845 // HT 40 band edge channel
5846 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE])&0xff;
5847 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
5848 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
5849 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+1])&0xff;
5850 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
5851 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
5852 // HT 20 band edge channel
5853 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+2])&0xff;
5854 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
5855 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
5856 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+3])&0xff;
5857 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
5858 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
5859 // OFDM band edge channel
5860 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+4])&0xff;
5861 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
5862 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
5863 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+5])&0xff;
5864 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
5865 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
5866
5867 priv->TxPwrbandEdgeFlag = (*(u8 *)&hwinfo[TX_PWR_BAND_EDGE_CHK]);
5868 }
5869
5870 for(i=0; i<14; i++)
5871 RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]);
5872 for(i=0; i<14; i++)
5873 RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][i]);
5874 for(i=0; i<14; i++)
5875 RT_TRACE(COMP_INIT, "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_B][i]);
5876 for(i=0; i<14; i++)
5877 RT_TRACE(COMP_INIT, "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_B][i]);
5878 RT_TRACE(COMP_INIT, "RF-A HT40 band-edge low/high power diff = 0x%x/0x%x\n",
5879 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0],
5880 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]);
5881 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT40 band-edge low/high power diff = 0x%x/0x%x\n",
5882 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0],
5883 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1]);
5884
5885 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A HT20 band-edge low/high power diff = 0x%x/0x%x\n",
5886 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0],
5887 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]);
5888 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT20 band-edge low/high power diff = 0x%x/0x%x\n",
5889 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0],
5890 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1]);
5891
5892 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A OFDM band-edge low/high power diff = 0x%x/0x%x\n",
5893 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0],
5894 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]);
5895 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B OFDM band-edge low/high power diff = 0x%x/0x%x\n",
5896 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0],
5897 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]);
5898 RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag);
5f53d8ca
JC		 5899
5900 //
5901 // Update remained HAL variables.
5902 //
5903 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5904 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;
5905 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
5906 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit[3:0]
5907 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit[7:4]
5908 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit[15:12]
5909 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter&0x1f);// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5910 priv->LedStrategy = SW_LED_MODE0;
5911
5912 init_rate_adaptive(dev);
5913
5914 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
5915
5916 //return RT_STATUS_SUCCESS;
5917}
5918
5919
5920//
5921// Description:
5922// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
5923//
5924// Assumption:
5925// 1. CR9346 regiser has verified.
5926// 2. PASSIVE_LEVEL (USB interface)
5927//
5928// Created by Roger, 2008.10.21.
5929//
5930static void rtl8192SU_read_eeprom_info(struct net_device *dev)
5931{
5932 struct r8192_priv *priv = ieee80211_priv(dev);
5933 u8 tmpU1b;
5934
5935 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
5936
5937 // Retrieve Chip version.
5938 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
5939 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
5940
5941 tmpU1b = read_nic_byte(dev, EPROM_CMD);//CR9346
5942
5943 // To check system boot selection.
5944 if (tmpU1b & CmdEERPOMSEL)
5945 {
5946 RT_TRACE(COMP_INIT, "Boot from EEPROM\n");
5947 priv->EepromOrEfuse = TRUE;
5948 }
5949 else
5950 {
5951 RT_TRACE(COMP_INIT, "Boot from EFUSE\n");
5952 priv->EepromOrEfuse = FALSE;
5953 }
5954
5955 // To check autoload success or not.
5956 if (tmpU1b & CmdEEPROM_En)
5957 {
5958 RT_TRACE(COMP_INIT, "Autoload OK!!\n");
5959 priv->AutoloadFailFlag=FALSE;
5960 rtl8192SU_ReadAdapterInfo8192SUsb(dev);//eeprom or e-fuse
5961 }
5962 else
5963 { // Auto load fail.
5964 RT_TRACE(COMP_INIT, "AutoLoad Fail reported from CR9346!!\n");
5965 priv->AutoloadFailFlag=TRUE;
5966 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
5967
5968 //if (IS_BOOT_FROM_EFUSE(Adapter))
5969 if(!priv->EepromOrEfuse)
5970 {
5971 RT_TRACE(COMP_INIT, "Update shadow map for EFuse future use!!\n");
5972 EFUSE_ShadowMapUpdate(dev);
5973 }
5974 }
5975#ifdef TO_DO_LIST
5976 if((priv->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
5977 {
5978 pMgntInfo->ChannelPlan = HalMapChannelPlan8192S(Adapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
5979 pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
5980 }
5981 else
5982 {
5983 pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
5984 }
5985
5986 switch(pMgntInfo->ChannelPlan)
5987 {
5988 case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
5989 {
5990 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
5991
5992 pDot11dInfo->bEnabled = TRUE;
5993 }
5994 RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
5995 break;
5996 }
5997
5998 RT_TRACE(COMP_INIT, DBG_LOUD, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
5999 RT_TRACE(COMP_INIT, DBG_LOUD, ("ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
6000
6001 RT_TRACE(COMP_INIT, DBG_LOUD, ("<==== ReadAdapterInfo8192S\n"));
6002#endif
6003
6004 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
6005
6006 //return RT_STATUS_SUCCESS;
6007}
6008#else
6009static void rtl8192_read_eeprom_info(struct net_device* dev)
6010{
6011 u16 wEPROM_ID = 0;
6012 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x02};
6013 u8 bLoad_From_EEPOM = false;
6014 struct r8192_priv *priv = ieee80211_priv(dev);
6015 u16 tmpValue = 0;
6016 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
6017 wEPROM_ID = eprom_read(dev, 0); //first read EEPROM ID out;
6018 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", wEPROM_ID);
6019
6020 if (wEPROM_ID != RTL8190_EEPROM_ID)
6021 {
6022 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", wEPROM_ID, RTL8190_EEPROM_ID);
6023 }
6024 else
6025 bLoad_From_EEPOM = true;
6026
6027 if (bLoad_From_EEPOM)
6028 {
6029 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
6030 priv->eeprom_vid = endian_swap(&tmpValue);
6031 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
6032 tmpValue = eprom_read(dev, (EEPROM_ChannelPlan>>1));
6033 priv->eeprom_ChannelPlan =((tmpValue&0xff00)>>8);
6034 priv->btxpowerdata_readfromEEPORM = true;
6035 priv->eeprom_CustomerID = eprom_read(dev, (EEPROM_Customer_ID>>1)) >>8;
6036 }
6037 else
6038 {
6039 priv->eeprom_vid = 0;
6040 priv->eeprom_pid = 0;
6041 priv->card_8192_version = VERSION_819xU_B;
6042 priv->eeprom_ChannelPlan = 0;
6043 priv->eeprom_CustomerID = 0;
6044 }
6045 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
6046 //set channelplan from eeprom
6047 priv->ChannelPlan = priv->eeprom_ChannelPlan;
6048 if (bLoad_From_EEPOM)
6049 {
6050 int i;
6051 for (i=0; i<6; i+=2)
6052 {
6053 u16 tmp = 0;
6054 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
6055 *(u16*)(&dev->dev_addr[i]) = tmp;
6056 }
6057 }
6058 else
6059 {
6060 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
6061 //should I set IDR0 here?
6062 }
6063 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
6064 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
6065 priv->rf_chip = RF_8256;
6066
6067 if (priv->card_8192_version == (u8)VERSION_819xU_A)
6068 {
6069 //read Tx power gain offset of legacy OFDM to HT rate
6070 if (bLoad_From_EEPOM)
6071 priv->EEPROMTxPowerDiff = (eprom_read(dev, (EEPROM_TxPowerDiff>>1))&0xff00) >> 8;
6072 else
6073 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPower;
6074 RT_TRACE(COMP_EPROM, "TxPowerDiff:%d\n", priv->EEPROMTxPowerDiff);
6075 //read ThermalMeter from EEPROM
6076 if (bLoad_From_EEPOM)
6077 priv->EEPROMThermalMeter = (u8)(eprom_read(dev, (EEPROM_ThermalMeter>>1))&0x00ff);
6078 else
6079 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
6080 RT_TRACE(COMP_EPROM, "ThermalMeter:%d\n", priv->EEPROMThermalMeter);
6081 //vivi, for tx power track
6082 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
6083 //read antenna tx power offset of B/C/D to A from EEPROM
6084 if (bLoad_From_EEPOM)
6085 priv->EEPROMPwDiff = (eprom_read(dev, (EEPROM_PwDiff>>1))&0x0f00)>>8;
6086 else
6087 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
6088 RT_TRACE(COMP_EPROM, "TxPwDiff:%d\n", priv->EEPROMPwDiff);
6089 // Read CrystalCap from EEPROM
6090 if (bLoad_From_EEPOM)
6091 priv->EEPROMCrystalCap = (eprom_read(dev, (EEPROM_CrystalCap>>1))&0x0f);
6092 else
6093 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
6094 RT_TRACE(COMP_EPROM, "CrystalCap = %d\n", priv->EEPROMCrystalCap);
6095 //get per-channel Tx power level
6096 if (bLoad_From_EEPOM)
6097 priv->EEPROM_Def_Ver = (eprom_read(dev, (EEPROM_TxPwIndex_Ver>>1))&0xff00)>>8;
6098 else
6099 priv->EEPROM_Def_Ver = 1;
6100 RT_TRACE(COMP_EPROM, "EEPROM_DEF_VER:%d\n", priv->EEPROM_Def_Ver);
6101 if (priv->EEPROM_Def_Ver == 0) //old eeprom definition
6102 {
6103 int i;
6104 if (bLoad_From_EEPOM)
6105 priv->EEPROMTxPowerLevelCCK = (eprom_read(dev, (EEPROM_TxPwIndex_CCK>>1))&0xff) >> 8;
6106 else
6107 priv->EEPROMTxPowerLevelCCK = 0x10;
6108 RT_TRACE(COMP_EPROM, "CCK Tx Power Levl: 0x%02x\n", priv->EEPROMTxPowerLevelCCK);
6109 for (i=0; i<3; i++)
6110 {
6111 if (bLoad_From_EEPOM)
6112 {
6113 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G+i)>>1);
6114 if (((EEPROM_TxPwIndex_OFDM_24G+i) % 2) == 0)
6115 tmpValue = tmpValue & 0x00ff;
6116 else
6117 tmpValue = (tmpValue & 0xff00) >> 8;
6118 }
6119 else
6120 tmpValue = 0x10;
6121 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8) tmpValue;
6122 RT_TRACE(COMP_EPROM, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK);
6123 }
6124 }//end if EEPROM_DEF_VER == 0
6125 else if (priv->EEPROM_Def_Ver == 1)
6126 {
6127 if (bLoad_From_EEPOM)
6128 {
6129 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1>>1));
6130 tmpValue = (tmpValue & 0xff00) >> 8;
6131 }
6132 else
6133 tmpValue = 0x10;
6134 priv->EEPROMTxPowerLevelCCK_V1[0] = (u8)tmpValue;
6135
6136 if (bLoad_From_EEPOM)
6137 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1 + 2)>>1);
6138 else
6139 tmpValue = 0x1010;
6140 *((u16*)(&priv->EEPROMTxPowerLevelCCK_V1[1])) = tmpValue;
6141 if (bLoad_From_EEPOM)
6142 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1>>1));
6143 else
6144 tmpValue = 0x1010;
6145 *((u16*)(&priv->EEPROMTxPowerLevelOFDM24G[0])) = tmpValue;
6146 if (bLoad_From_EEPOM)
6147 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1+2)>>1);
6148 else
6149 tmpValue = 0x10;
6150 priv->EEPROMTxPowerLevelOFDM24G[2] = (u8)tmpValue;
6151 }//endif EEPROM_Def_Ver == 1
6152
6153 //update HAL variables
6154 //
6155 {
6156 int i;
6157 for (i=0; i<14; i++)
6158 {
6159 if (i<=3)
6160 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[0];
6161 else if (i>=4 && i<=9)
6162 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[1];
6163 else
6164 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[2];
6165 }
6166
6167 for (i=0; i<14; i++)
6168 {
6169 if (priv->EEPROM_Def_Ver == 0)
6170 {
6171 if (i<=3)
6172 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[0] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]);
6173 else if (i>=4 && i<=9)
6174 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK;
6175 else
6176 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[2] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]);
6177 }
6178 else if (priv->EEPROM_Def_Ver == 1)
6179 {
6180 if (i<=3)
6181 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[0];
6182 else if (i>=4 && i<=9)
6183 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[1];
6184 else
6185 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[2];
6186 }
6187 }
6188 }//end update HAL variables
6189 priv->TxPowerDiff = priv->EEPROMPwDiff;
6190// Antenna B gain offset to antenna A, bit0~3
6191 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
6192 // Antenna C gain offset to antenna A, bit4~7
6193 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
6194 // CrystalCap, bit12~15
6195 priv->CrystalCap = priv->EEPROMCrystalCap;
6196 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
6197 // 92U does not enable TX power tracking.
6198 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
6199 }//end if VersionID == VERSION_819xU_A
6200
6201//added by vivi, for dlink led, 20080416
6202 switch(priv->eeprom_CustomerID)
6203 {
6204 case EEPROM_CID_RUNTOP:
6205 priv->CustomerID = RT_CID_819x_RUNTOP;
6206 break;
6207
6208 case EEPROM_CID_DLINK:
6209 priv->CustomerID = RT_CID_DLINK;
6210 break;
6211
6212 default:
6213 priv->CustomerID = RT_CID_DEFAULT;
6214 break;
6215
6216 }
6217
6218 switch(priv->CustomerID)
6219 {
6220 case RT_CID_819x_RUNTOP:
6221 priv->LedStrategy = SW_LED_MODE2;
6222 break;
6223
6224 case RT_CID_DLINK:
6225 priv->LedStrategy = SW_LED_MODE4;
6226 break;
6227
6228 default:
6229 priv->LedStrategy = SW_LED_MODE0;
6230 break;
6231
6232 }
6233
6234
6235 if(priv->rf_type == RF_1T2R)
6236 {
6237 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
6238 }
6239 else
6240 {
6241 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
6242 }
6243
6244 // 2008/01/16 MH We can only know RF type in the function. So we have to init
6245 // DIG RATR table again.
6246 init_rate_adaptive(dev);
6247 //we need init DIG RATR table here again.
6248
6249 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
6250 return;
6251}
6252#endif
6253
6254short rtl8192_get_channel_map(struct net_device * dev)
6255{
6256 struct r8192_priv *priv = ieee80211_priv(dev);
5f53d8ca
JC		 6257 if(priv->ChannelPlan > COUNTRY_CODE_GLOBAL_DOMAIN){
6258 printk("rtl8180_init:Error channel plan! Set to default.\n");
6259 priv->ChannelPlan= 0;
6260 }
6261 RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan);
6262
6263 rtl819x_set_channel_map(priv->ChannelPlan, priv);
5f53d8ca
JC		 6264 return 0;
6265}
6266
6267short rtl8192_init(struct net_device *dev)
6268{
6269
6270 struct r8192_priv *priv = ieee80211_priv(dev);
6271
6272#ifndef RTL8192SU
6273 memset(&(priv->stats),0,sizeof(struct Stats));
6274 memset(priv->txqueue_to_outpipemap,0,9);
6275#ifdef PIPE12
6276 {
6277 int i=0;
6278 u8 queuetopipe[]={3,2,1,0,4,8,7,6,5};
6279 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
6280/* for(i=0;i<9;i++)
6281 printk("%d ",priv->txqueue_to_outpipemap[i]);
6282 printk("\n");*/
6283 }
6284#else
6285 {
6286 u8 queuetopipe[]={3,2,1,0,4,4,0,4,4};
6287 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
6288/* for(i=0;i<9;i++)
6289 printk("%d ",priv->txqueue_to_outpipemap[i]);
6290 printk("\n");*/
6291 }
6292#endif
6293#endif
6294 rtl8192_init_priv_variable(dev);
6295 rtl8192_init_priv_lock(priv);
6296 rtl8192_init_priv_task(dev);
6297 rtl8192_get_eeprom_size(dev);
6298 priv->ops->rtl819x_read_eeprom_info(dev);
6299 rtl8192_get_channel_map(dev);
6300 init_hal_dm(dev);
6301 init_timer(&priv->watch_dog_timer);
6302 priv->watch_dog_timer.data = (unsigned long)dev;
6303 priv->watch_dog_timer.function = watch_dog_timer_callback;
6304
6305 //rtl8192_adapter_start(dev);
6306#ifdef DEBUG_EPROM
6307 dump_eprom(dev);
6308#endif
6309 return 0;
6310}
6311
6312/******************************************************************************
6313 *function: This function actually only set RRSR, RATR and BW_OPMODE registers
6314 * not to do all the hw config as its name says
6315 * input: net_device dev
6316 * output: none
6317 * return: none
6318 * notice: This part need to modified according to the rate set we filtered
6319 * ****************************************************************************/
6320void rtl8192_hwconfig(struct net_device* dev)
6321{
6322 u32 regRATR = 0, regRRSR = 0;
6323 u8 regBwOpMode = 0, regTmp = 0;
6324 struct r8192_priv *priv = ieee80211_priv(dev);
6325
6326// Set RRSR, RATR, and BW_OPMODE registers
6327 //
6328 switch(priv->ieee80211->mode)
6329 {
6330 case WIRELESS_MODE_B:
6331 regBwOpMode = BW_OPMODE_20MHZ;
6332 regRATR = RATE_ALL_CCK;
6333 regRRSR = RATE_ALL_CCK;
6334 break;
6335 case WIRELESS_MODE_A:
6336 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
6337 regRATR = RATE_ALL_OFDM_AG;
6338 regRRSR = RATE_ALL_OFDM_AG;
6339 break;
6340 case WIRELESS_MODE_G:
6341 regBwOpMode = BW_OPMODE_20MHZ;
6342 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6343 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6344 break;
6345 case WIRELESS_MODE_AUTO:
6346#ifdef TO_DO_LIST
6347 if (Adapter->bInHctTest)
6348 {
6349 regBwOpMode = BW_OPMODE_20MHZ;
6350 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6351 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6352 }
6353 else
6354#endif
6355 {
6356 regBwOpMode = BW_OPMODE_20MHZ;
6357 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6358 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6359 }
6360 break;
6361 case WIRELESS_MODE_N_24G:
6362 // It support CCK rate by default.
6363 // CCK rate will be filtered out only when associated AP does not support it.
6364 regBwOpMode = BW_OPMODE_20MHZ;
6365 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6366 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6367 break;
6368 case WIRELESS_MODE_N_5G:
6369 regBwOpMode = BW_OPMODE_5G;
6370 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6371 regRRSR = RATE_ALL_OFDM_AG;
6372 break;
6373 }
6374
6375 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
6376 {
6377 u32 ratr_value = 0;
6378 ratr_value = regRATR;
6379 if (priv->rf_type == RF_1T2R)
6380 {
6381 ratr_value &= ~(RATE_ALL_OFDM_2SS);
6382 }
6383 write_nic_dword(dev, RATR0, ratr_value);
6384 write_nic_byte(dev, UFWP, 1);
6385 }
6386 regTmp = read_nic_byte(dev, 0x313);
6387 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
6388 write_nic_dword(dev, RRSR, regRRSR);
6389
6390 //
6391 // Set Retry Limit here
6392 //
6393 write_nic_word(dev, RETRY_LIMIT,
6394 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | \
6395 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
6396 // Set Contention Window here
6397
6398 // Set Tx AGC
6399
6400 // Set Tx Antenna including Feedback control
6401
6402 // Set Auto Rate fallback control
6403
6404
6405}
6406
6407#ifdef RTL8192SU
5f53d8ca
JC		 6408
6409//
6410// Description:
6411// Initial HW relted registers.
6412//
6413// Assumption:
6414// Config RTL8192S USB MAC, we should config MAC before download FW.
6415//
6416// 2008.09.03, Added by Roger.
6417//
6418static void rtl8192SU_MacConfigBeforeFwDownloadASIC(struct net_device *dev)
6419{
6420 u8 tmpU1b;// i;
6421// u16 tmpU2b;
6422// u32 tmpU4b;
6423 u8 PollingCnt = 20;
6424
6425 RT_TRACE(COMP_INIT, "--->MacConfigBeforeFwDownloadASIC()\n");
6426
6427 //2MAC Initialization for power on sequence, Revised by Roger. 2008.09.03.
6428
6429 //
6430 //<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and
6431 // MAC I/O to solve FW download fail when system from resume sate.
6432 // 2008.11.04.
6433 //
6434 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
6435 if(tmpU1b & 0x80)
6436 {
6437 tmpU1b &= 0x3f;
6438 write_nic_byte(dev, SYS_CLKR+1, tmpU1b);
6439 }
6440 // Clear FW RPWM for FW control LPS. by tynli. 2009.02.23
6441 write_nic_byte(dev, RPWM, 0x0);
6442
6443 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
6444 tmpU1b &= 0x73;
6445 write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b);
6446 udelay(1000);
6447
6448 //Revised POS, suggested by SD1 Alex, 2008.09.27.
6449 write_nic_byte(dev, SPS0_CTRL+1, 0x53);
6450 write_nic_byte(dev, SPS0_CTRL, 0x57);
6451
6452 //Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
6453 tmpU1b = read_nic_byte(dev, AFE_MISC);
6454 write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_BGEN|AFE_MBEN));
6455
6456 //Enable PLL Power (LDOA15V)
6457 tmpU1b = read_nic_byte(dev, LDOA15_CTRL);
6458 write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|LDA15_EN));
6459
6460 //Enable LDOV12D block
6461 tmpU1b = read_nic_byte(dev, LDOV12D_CTRL);
6462 write_nic_byte(dev, LDOV12D_CTRL, (tmpU1b|LDV12_EN));
6463
6464 //mpU1b = read_nic_byte(Adapter, SPS1_CTRL);
6465 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_LDEN));
6466
6467 //PlatformSleepUs(2000);
6468
6469 //Enable Switch Regulator Block
6470 //tmpU1b = read_nic_byte(Adapter, SPS1_CTRL);
6471 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_SWEN));
6472
6473 //write_nic_dword(Adapter, SPS1_CTRL, 0x00a7b267);
6474
6475 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
6476 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b|0x08));
6477
6478 //Engineer Packet CP test Enable
6479 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
6480 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x20));
6481
6482 //Support 64k IMEM, suggested by SD1 Alex.
6483 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
6484 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b& 0x68));
6485
6486 //Enable AFE clock
6487 tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL+1);
6488 write_nic_byte(dev, AFE_XTAL_CTRL+1, (tmpU1b& 0xfb));
6489
6490 //Enable AFE PLL Macro Block
6491 tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL);
6492 write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|0x11));
6493
6494 //Attatch AFE PLL to MACTOP/BB/PCIe Digital
6495 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL);
6496 write_nic_byte(dev, SYS_ISO_CTRL, (tmpU1b&0xEE));
6497
6498 // Switch to 40M clock
6499 write_nic_byte(dev, SYS_CLKR, 0x00);
6500
6501 //SSC Disable
6502 tmpU1b = read_nic_byte(dev, SYS_CLKR);
6503 //write_nic_byte(dev, SYS_CLKR, (tmpU1b&0x5f));
6504 write_nic_byte(dev, SYS_CLKR, (tmpU1b|0xa0));
6505
6506 //Enable MAC clock
6507 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
6508 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x18));
6509
6510 //Revised POS, suggested by SD1 Alex, 2008.09.27.
6511 write_nic_byte(dev, PMC_FSM, 0x02);
6512
6513 //Enable Core digital and enable IOREG R/W
6514 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
6515 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x08));
6516
6517 //Enable REG_EN
6518 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
6519 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x80));
6520
6521 //Switch the control path to FW
6522 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
6523 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x80)& 0xBF);
6524
6525 write_nic_byte(dev, CMDR, 0xFC);
6526 write_nic_byte(dev, CMDR+1, 0x37);
6527
6528 //Fix the RX FIFO issue(usb error), 970410
6529 tmpU1b = read_nic_byte_E(dev, 0x5c);
6530 write_nic_byte_E(dev, 0x5c, (tmpU1b|BIT7));
6531
6532 //For power save, used this in the bit file after 970621
6533 tmpU1b = read_nic_byte(dev, SYS_CLKR);
6534 write_nic_byte(dev, SYS_CLKR, tmpU1b&(~SYS_CPU_CLKSEL));
6535
6536 // Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16.
6537 write_nic_byte_E(dev, 0x1c, 0x80);
6538
6539 //
6540 // <Roger_EXP> To make sure that TxDMA can ready to download FW.
6541 // We should reset TxDMA if IMEM RPT was not ready.
6542 // Suggested by SD1 Alex. 2008.10.23.
6543 //
6544 do
6545 {
6546 tmpU1b = read_nic_byte(dev, TCR);
6547 if((tmpU1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
6548 break;
6549 //PlatformStallExecution(5);
6550 udelay(5);
6551 }while(PollingCnt--); // Delay 1ms
6552
6553 if(PollingCnt <= 0 )
6554 {
6555 RT_TRACE(COMP_INIT, "MacConfigBeforeFwDownloadASIC(): Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpU1b);
6556 tmpU1b = read_nic_byte(dev, CMDR);
6557 write_nic_byte(dev, CMDR, tmpU1b&(~TXDMA_EN));
6558 udelay(2);
6559 write_nic_byte(dev, CMDR, tmpU1b|TXDMA_EN);// Reset TxDMA
6560 }
6561
6562
6563 RT_TRACE(COMP_INIT, "<---MacConfigBeforeFwDownloadASIC()\n");
6564}
5f53d8ca
JC		 6565
6566
5f53d8ca
JC		 6567#if 0
6568static void rtl8192SU_SetHwRegAmpduMinSpace(struct net_device *dev, u8 MinSpaceCfg)
6569{
6570 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
6571 struct ieee80211_device* ieee = priv->ieee80211;
6572 u8 MinSpacingToSet;
6573 u8 SecMinSpace;
6574
5f53d8ca
JC		 6575 MinSpacingToSet = MinSpaceCfg;
6576 if(MinSpacingToSet <= 7)
6577 {
6578 switch(ieee->pairwise_key_type)
6579 {
6580 case KEY_TYPE_NA: SecMinSpace = 0; break;
6581 case KEY_TYPE_CCMP:
6582 case KEY_TYPE_WEP40:
6583 case KEY_TYPE_WEP104:
6584 case KEY_TYPE_TKIP: SecMinSpace = 6; break;
6585 default: SecMinSpace = 7; break;
6586 }
6587
6588 if(MinSpacingToSet < SecMinSpace)
6589 MinSpacingToSet = SecMinSpace;
6590 priv->MinSpaceCfg = ((priv->MinSpaceCfg&0xf8) |MinSpacingToSet);
6591 RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg);
6592 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
6593 }
6594
5f53d8ca
JC		 6595}
6596#endif
6597
6598//
6599// Description:
6600// Initial HW relted registers.
6601//
6602// Assumption:
6603// 1. This function is only invoked at driver intialization once.
6604// 2. PASSIVE LEVEL.
6605//
6606// 2008.06.10, Added by Roger.
6607//
6608static void rtl8192SU_MacConfigAfterFwDownload(struct net_device *dev)
6609{
6610 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
6611 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
6612 //u8 tmpU1b, RxPageCfg, i;
6613 u16 tmpU2b;
6614 u8 tmpU1b;//, i;
6615
6616
6617 RT_TRACE(COMP_INIT, "--->MacConfigAfterFwDownload()\n");
6618
6619 // Enable Tx/Rx
6620 tmpU2b = (BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN|
6621 FW2HW_EN|RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN); //3
6622 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_COMMAND, &tmpU1b );
6623 write_nic_word(dev, CMDR, tmpU2b); //LZM REGISTER COM 090305
6624
6625 // Loopback mode or not
6626 priv->LoopbackMode = RTL8192SU_NO_LOOPBACK; // Set no loopback as default.
6627 if(priv->LoopbackMode == RTL8192SU_NO_LOOPBACK)
6628 tmpU1b = LBK_NORMAL;
6629 else if (priv->LoopbackMode == RTL8192SU_MAC_LOOPBACK )
6630 tmpU1b = LBK_MAC_DLB;
6631 else
6632 RT_TRACE(COMP_INIT, "Serious error: wrong loopback mode setting\n");
6633
6634 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_LBK_MODE, &tmpU1b);
6635 write_nic_byte(dev, LBKMD_SEL, tmpU1b);
6636
6637 // Set RCR
6638 write_nic_dword(dev, RCR, priv->ReceiveConfig);
6639 RT_TRACE(COMP_INIT, "MacConfigAfterFwDownload(): Current RCR settings(%#x)\n", priv->ReceiveConfig);
6640
6641
6642 // Set RQPN
6643 //
6644 // <Roger_Notes> 2008.08.18.
6645 // 6 endpoints:
6646 // (1) Page number on CMDQ is 0x03.
6647 // (2) Page number on BCNQ, HQ and MGTQ is 0.
6648 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
6649 // (4) Page number on PUBQ is 0xdd
6650 //
6651 // 11 endpoints:
6652 // (1) Page number on CMDQ is 0x00.
6653 // (2) Page number on BCNQ is 0x02, HQ and MGTQ are 0x03.
6654 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
6655 // (4) Page number on PUBQ is 0xd8
6656 //
6657 //write_nic_dword(Adapter, 0xa0, 0x07070707); //BKQ, BEQ, VIQ and VOQ
6658 //write_nic_byte(dev, 0xa4, 0x00); // HCCAQ
6659#if 0 //LZM 090219
6660#ifdef USE_SIX_USB_ENDPOINT
6661 //write_nic_dword(Adapter, 0xa5, 0x00000003); //CMDQ, MGTQ, HQ and BCNQ
6662 //write_nic_byte(dev, 0xa9, 0xdd); // PUBQ
6663 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
6664 write_nic_byte(dev, 0xab, tmpU1b|BIT7|BIT6);// reduce to 6 endpoints.
6665#else
6666 write_nic_dword(dev, 0xa5, 0x02030300); //CMDQ, MGTQ, HQ and BCNQ
6667 write_nic_byte(dev, 0xa9, 0xd8); // PUBQ
6668 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
6669 write_nic_byte(dev, 0xab, (tmpU1b&(~BIT6))|BIT7); // Disable reduced endpoint.
6670#endif
6671#endif
6672
5f53d8ca
JC		 6673
6674 // Fix the RX FIFO issue(USB error), Rivesed by Roger, 2008-06-14
6675 tmpU1b = read_nic_byte_E(dev, 0x5C);
6676 write_nic_byte_E(dev, 0x5C, tmpU1b|BIT7);
6677
5f53d8ca
JC		 6678#if 0 //LZM 090219
6679 //
6680 // Suggested by SD1 Alex, 2008-06-14.
6681 //
6682 write_nic_byte(dev, TXOP_STALL_CTRL, 0x80);//NAV
6683
6684
6685 //
6686 // Set Data Auto Rate Fallback Retry Count register.
6687 //
6688 write_nic_dword(dev, DARFRC, 0x04010000);
6689 write_nic_dword(dev, DARFRC+4, 0x09070605);
6690 write_nic_dword(dev, RARFRC, 0x04010000);
6691 write_nic_dword(dev, RARFRC+4, 0x09070605);
6692
6693 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
6694 for (i = 0; i < 8; i++)
5f53d8ca 6695 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
5f53d8ca
JC		 6696
6697 //
6698 // Set driver info, we only accept PHY status now.
6699 //
6700 //write_nic_byte(dev, RXDRVINFO_SZ, 4);
6701
6702 //
6703 // Aggregation length limit. Revised by Roger. 2008.09.22.
6704 //
6705 write_nic_dword(dev, AGGLEN_LMT_L, 0x66666666); // Long GI
6706 write_nic_byte(dev, AGGLEN_LMT_H, 0x06); // Set AMPDU length to 12Kbytes for ShortGI case.
6707
6708 //
6709 // For Min Spacing configuration.
6710 //
6711 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AMPDU_MIN_SPACE, (u8*)(&Adapter->MgntInfo.MinSpaceCfg));
6712 rtl8192SU_SetHwRegAmpduMinSpace(dev,priv->MinSpaceCfg);
6713#endif
6714
6715 // For EFUSE init configuration.
6716 //if (IS_BOOT_FROM_EFUSE(Adapter)) // We may R/W EFUSE in EFUSE mode
6717 if (priv->bBootFromEfuse)
6718 {
6719 u8 tempval;
6720
6721 tempval = read_nic_byte(dev, SYS_ISO_CTRL+1);
6722 tempval &= 0xFE;
6723 write_nic_byte(dev, SYS_ISO_CTRL+1, tempval);
6724
6725 // Enable LDO 2.5V for write action
6726 //tempval = read_nic_byte(Adapter, EFUSE_TEST+3);
6727 //write_nic_byte(Adapter, EFUSE_TEST+3, (tempval | 0x80));
6728
6729 // Change Efuse Clock for write action
6730 //write_nic_byte(Adapter, EFUSE_CLK, 0x03);
6731
6732 // Change Program timing
6733 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);
6734 //printk("!!!!!!!!!!!!!!!!!!!!!%s: write 0x33 with 0x72\n",__FUNCTION__);
6735 RT_TRACE(COMP_INIT, "EFUSE CONFIG OK\n");
6736 }
6737
6738
6739 RT_TRACE(COMP_INIT, "<---MacConfigAfterFwDownload()\n");
6740}
6741
6742void rtl8192SU_HwConfigureRTL8192SUsb(struct net_device *dev)
6743{
6744
6745 struct r8192_priv *priv = ieee80211_priv(dev);
6746 u8 regBwOpMode = 0;
6747 u32 regRATR = 0, regRRSR = 0;
6748 u8 regTmp = 0;
6749 u32 i = 0;
6750
6751 //1 This part need to modified according to the rate set we filtered!!
6752 //
6753 // Set RRSR, RATR, and BW_OPMODE registers
6754 //
6755 switch(priv->ieee80211->mode)
6756 {
6757 case WIRELESS_MODE_B:
6758 regBwOpMode = BW_OPMODE_20MHZ;
6759 regRATR = RATE_ALL_CCK;
6760 regRRSR = RATE_ALL_CCK;
6761 break;
6762 case WIRELESS_MODE_A:
6763 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
6764 regRATR = RATE_ALL_OFDM_AG;
6765 regRRSR = RATE_ALL_OFDM_AG;
6766 break;
6767 case WIRELESS_MODE_G:
6768 regBwOpMode = BW_OPMODE_20MHZ;
6769 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6770 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6771 break;
6772 case WIRELESS_MODE_AUTO:
6773 if (priv->bInHctTest)
6774 {
6775 regBwOpMode = BW_OPMODE_20MHZ;
6776 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6777 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6778 }
6779 else
6780 {
6781 regBwOpMode = BW_OPMODE_20MHZ;
6782 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6783 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6784 }
6785 break;
6786 case WIRELESS_MODE_N_24G:
6787 // It support CCK rate by default.
6788 // CCK rate will be filtered out only when associated AP does not support it.
6789 regBwOpMode = BW_OPMODE_20MHZ;
6790 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6791 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6792 break;
6793 case WIRELESS_MODE_N_5G:
6794 regBwOpMode = BW_OPMODE_5G;
6795 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6796 regRRSR = RATE_ALL_OFDM_AG;
6797 break;
6798 }
6799
6800 //
6801 // <Roger_Notes> We disable CCK response rate until FIB CCK rate IC's back.
6802 // 2008.09.23.
6803 //
6804 regTmp = read_nic_byte(dev, INIRTSMCS_SEL);
5f53d8ca 6805 regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp;
5f53d8ca
JC		 6806
6807 //
6808 // Update SIFS timing.
6809 //
6810 //priv->SifsTime = 0x0e0e0a0a;
6811 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SIFS, (pu1Byte)&pHalData->SifsTime);
6812 { u8 val[4] = {0x0e, 0x0e, 0x0a, 0x0a};
6813 // SIFS for CCK Data ACK
6814 write_nic_byte(dev, SIFS_CCK, val[0]);
6815 // SIFS for CCK consecutive tx like CTS data!
6816 write_nic_byte(dev, SIFS_CCK+1, val[1]);
6817
6818 // SIFS for OFDM Data ACK
6819 write_nic_byte(dev, SIFS_OFDM, val[2]);
6820 // SIFS for OFDM consecutive tx like CTS data!
6821 write_nic_byte(dev, SIFS_OFDM+1, val[3]);
6822 }
6823
6824 write_nic_dword(dev, INIRTSMCS_SEL, regRRSR);
6825 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
6826
6827 //
6828 // Suggested by SD1 Alex, 2008-06-14.
6829 //
6830 //PlatformEFIOWrite1Byte(Adapter, TXOP_STALL_CTRL, 0x80);//NAV to protect all TXOP.
6831
6832 //
6833 // Set Data Auto Rate Fallback Retry Count register.
6834 //
6835 write_nic_dword(dev, DARFRC, 0x02010000);
6836 write_nic_dword(dev, DARFRC+4, 0x06050403);
6837 write_nic_dword(dev, RARFRC, 0x02010000);
6838 write_nic_dword(dev, RARFRC+4, 0x06050403);
6839
6840 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
6841 for (i = 0; i < 8; i++)
5f53d8ca 6842 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
5f53d8ca
JC		 6843
6844 //
6845 // Aggregation length limit. Revised by Roger. 2008.09.22.
6846 //
6847 write_nic_byte(dev, AGGLEN_LMT_H, 0x0f); // Set AMPDU length to 12Kbytes for ShortGI case.
6848 write_nic_dword(dev, AGGLEN_LMT_L, 0xddd77442); // Long GI
6849 write_nic_dword(dev, AGGLEN_LMT_L+4, 0xfffdd772);
6850
6851 // Set NAV protection length
6852 write_nic_word(dev, NAV_PROT_LEN, 0x0080);
6853
6854 // Set TXOP stall control for several queue/HI/BCN/MGT/
6855 write_nic_byte(dev, TXOP_STALL_CTRL, 0x00); // NAV Protect next packet.
6856
6857 // Set MSDU lifetime.
6858 write_nic_byte(dev, MLT, 0x8f);
6859
6860 // Set CCK/OFDM SIFS
6861 write_nic_word(dev, SIFS_CCK, 0x0a0a); // CCK SIFS shall always be 10us.
6862 write_nic_word(dev, SIFS_OFDM, 0x0e0e);
6863
6864 write_nic_byte(dev, ACK_TIMEOUT, 0x40);
6865
6866 // CF-END Threshold
6867 write_nic_byte(dev, CFEND_TH, 0xFF);
6868
6869 //
6870 // For Min Spacing configuration.
6871 //
6872 switch(priv->rf_type)
6873 {
6874 case RF_1T2R:
6875 case RF_1T1R:
6876 RT_TRACE(COMP_INIT, "Initializeadapter: RF_Type%s\n", (priv->rf_type==RF_1T1R? "(1T1R)":"(1T2R)"));
6877 priv->MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
6878 break;
6879 case RF_2T2R:
6880 case RF_2T2R_GREEN:
6881 RT_TRACE(COMP_INIT, "Initializeadapter:RF_Type(2T2R)\n");
6882 priv->MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
6883 break;
6884 }
6885 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
6886
6887 //LZM 090219
6888 //
6889 // For Min Spacing configuration.
6890 //
6891 //priv->MinSpaceCfg = 0x00;
6892 //rtl8192SU_SetHwRegAmpduMinSpace(dev, priv->MinSpaceCfg);
6893}
6894
6895#endif
6896
6897#ifdef RTL8192SU
6898// Description: Initial HW relted registers.
6899//
6900// Assumption: This function is only invoked at driver intialization once.
6901//
6902// 2008.06.10, Added by Roger.
6903bool rtl8192SU_adapter_start(struct net_device *dev)
6904{
6905 struct r8192_priv *priv = ieee80211_priv(dev);
6906 //u32 dwRegRead = 0;
6907 //bool init_status = true;
6908 //u32 ulRegRead;
6909 bool rtStatus = true;
6910 //u8 PipeIndex;
6911 //u8 eRFPath, tmpU1b;
6912 u8 fw_download_times = 1;
6913
6914
6915 RT_TRACE(COMP_INIT, "--->InitializeAdapter8192SUsb()\n");
6916
6917 //pHalData->bGPIOChangeRF = FALSE;
6918
6919
6920 //
6921 // <Roger_Notes> 2008.06.15.
6922 //
6923 // Initialization Steps on RTL8192SU:
6924 // a. MAC initialization prior to sending down firmware code.
6925 // b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
6926 // c. MAC configuration after firmware has been download successfully.
6927 // d. Initialize BB related configurations.
6928 // e. Initialize RF related configurations.
6929 // f. Start to BulkIn transfer.
6930 //
6931
6932 //
6933 //a. MAC initialization prior to send down firmware code.
6934 //
6935start:
6936 rtl8192SU_MacConfigBeforeFwDownloadASIC(dev);
6937
6938 //
6939 //b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
6940 //
6941 rtStatus = FirmwareDownload92S(dev);
6942 if(rtStatus != true)
6943 {
6944 if(fw_download_times == 1){
6945 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed once, Download again!!\n");
6946 fw_download_times = fw_download_times + 1;
6947 goto start;
6948 }else{
6949 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed twice, end!!\n");
6950 goto end;
6951 }
6952 }
6953 //
6954 //c. MAC configuration after firmware has been download successfully.
6955 //
6956 rtl8192SU_MacConfigAfterFwDownload(dev);
6957
5f53d8ca
JC		 6958 //priv->bLbusEnable = TRUE;
6959 //if(priv->RegRfOff == TRUE)
6960 // priv->eRFPowerState = eRfOff;
6961
6962 // Save target channel
6963 // <Roger_Notes> Current Channel will be updated again later.
6964 //priv->CurrentChannel = Channel;
6965 rtStatus = PHY_MACConfig8192S(dev);//===>ok
6966 if(rtStatus != true)
6967 {
6968 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure MAC!!\n");
6969 goto end;
6970 }
6971 if (1){
6972 int i;
6973 for (i=0; i<4; i++)
6974 write_nic_dword(dev,WDCAPARA_ADD[i], 0x5e4322);
6975 write_nic_byte(dev,AcmHwCtrl, 0x01);
6976 }
6977
6978
6979 //
6980 //d. Initialize BB related configurations.
6981 //
6982
6983 rtStatus = PHY_BBConfig8192S(dev);//===>ok
6984 if(rtStatus != true)
6985 {
6986 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure BB!!\n");
6987 goto end;
6988 }
6989
6990 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);//===>ok
6991
6992 //
6993 // e. Initialize RF related configurations.
6994 //
6995 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
6996 priv->Rf_Mode = RF_OP_By_SW_3wire;
6997
6998 // For RF test only from Scott's suggestion
6999 //write_nic_byte(dev, 0x27, 0xDB);
7000 //write_nic_byte(dev, 0x1B, 0x07);
7001
7002
7003 write_nic_byte(dev, AFE_XTAL_CTRL+1, 0xDB);
7004
7005 // <Roger_Notes> The following IOs are configured for each RF modules.
7006 // Enable RF module and reset RF and SDM module. 2008.11.17.
7007 if(priv->card_8192_version == VERSION_8192S_ACUT)
7008 write_nic_byte(dev, SPS1_CTRL+3, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB)); // Fix A-Cut bug.
7009 else
7010 write_nic_byte(dev, RF_CTRL, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB));
7011
7012 rtStatus = PHY_RFConfig8192S(dev);//===>ok
7013 if(rtStatus != true)
7014 {
7015 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure RF!!\n");
7016 goto end;
7017 }
7018
7019
7020 // Set CCK and OFDM Block "ON"
7021 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
7022 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
7023
7024 //
7025 // Turn off Radio B while RF type is 1T1R by SD3 Wilsion's request.
7026 // Revised by Roger, 2008.12.18.
7027 //
7028 if(priv->rf_type == RF_1T1R)
7029 {
7030 // This is needed for PHY_REG after 20081219
7031 rtl8192_setBBreg(dev, rFPGA0_RFMOD, 0xff000000, 0x03);
7032 // This is needed for PHY_REG before 20081219
7033 //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x11);
7034 }
7035
5f53d8ca
JC		 7036
7037 //LZM 090219
7038 // Set CCK and OFDM Block "ON"
7039 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
7040 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
7041
7042
7043 //3//Get hardware version, do it in read eeprom?
7044 //GetHardwareVersion819xUsb(Adapter);
7045
7046 //3//
7047 //3 //Set Hardware
7048 //3//
7049 rtl8192SU_HwConfigureRTL8192SUsb(dev);//==>ok
7050
7051 //
7052 // <Roger_Notes> We set MAC address here if autoload was failed before,
7053 // otherwise IDR0 will NOT contain any value.
7054 //
7055 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
7056 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
7057 if(!priv->bInHctTest)
7058 {
7059 if(priv->ResetProgress == RESET_TYPE_NORESET)
7060 {
7061 //RT_TRACE(COMP_MLME, DBG_LOUD, ("Initializeadapter8192SUsb():RegWirelessMode(%#x) \n", Adapter->RegWirelessMode));
7062 //Adapter->HalFunc.SetWirelessModeHandler(Adapter, Adapter->RegWirelessMode);
7063 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);//===>ok
7064 }
7065 }
7066 else
7067 {
7068 priv->ieee80211->mode = WIRELESS_MODE_G;
7069 rtl8192_SetWirelessMode(dev, WIRELESS_MODE_G);
7070 }
7071
7072 //Security related.
7073 //-----------------------------------------------------------------------------
7074 // Set up security related. 070106, by rcnjko:
7075 // 1. Clear all H/W keys.
7076 // 2. Enable H/W encryption/decryption.
7077 //-----------------------------------------------------------------------------
7078 //CamResetAllEntry(Adapter);
7079 //Adapter->HalFunc.EnableHWSecCfgHandler(Adapter);
7080
7081 //SecClearAllKeys(Adapter);
7082 CamResetAllEntry(dev);
7083 //SecInit(Adapter);
7084 {
7085 u8 SECR_value = 0x0;
7086 SECR_value |= SCR_TxEncEnable;
7087 SECR_value |= SCR_RxDecEnable;
7088 SECR_value |= SCR_NoSKMC;
7089 write_nic_byte(dev, SECR, SECR_value);
7090 }
7091
7092#if 0
7093
7094 if(pHalData->VersionID == VERSION_8192SU_A)
7095 {
7096 // cosa add for tx power level initialization.
7097 GetTxPowerOriginalOffset(Adapter);
7098 SetTxPowerLevel819xUsb(Adapter, Channel);
7099 }
7100#endif
7101
7102
7103#ifdef TO_DO_LIST
7104
7105 //PHY_UpdateInitialGain(dev);
7106
7107 if(priv->RegRfOff == true)
7108 { // User disable RF via registry.
7109 u8 eRFPath = 0;
7110
7111 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RegRfOff ----------\n");
7112 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW);
7113 // Those action will be discard in MgntActSet_RF_State because off the same state
7114 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
7115 rtl8192_setBBreg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
7116 }
7117 else if(priv->RfOffReason > RF_CHANGE_BY_PS)
7118 { // H/W or S/W RF OFF before sleep.
7119 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RfOffReason(%d) ----------\n", priv->RfOffReason);
7120 MgntActSet_RF_State(dev, eRfOff, priv->RfOffReason);
7121 }
7122 else
7123 {
7124 priv->eRFPowerState = eRfOn;
7125 priv->RfOffReason = 0;
7126 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): RF is on ----------\n");
7127 }
7128
7129#endif
7130
7131
7132//
7133// f. Start to BulkIn transfer.
7134//
7135#ifdef TO_DO_LIST
7136
7137#ifndef UNDER_VISTA
7138 {
7139 u8 i;
7140 PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
7141
7142 for(PipeIndex=0; PipeIndex < MAX_RX_QUEUE; PipeIndex++)
7143 {
7144 if (PipeIndex == 0)
7145 {
7146 for(i=0; i<32; i++)
7147 HalUsbInMpdu(Adapter, PipeIndex);
7148 }
7149 else
7150 {
7151 //HalUsbInMpdu(Adapter, PipeIndex);
7152 //HalUsbInMpdu(Adapter, PipeIndex);
7153 //HalUsbInMpdu(Adapter, PipeIndex);
7154 }
7155 }
7156 PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
7157 }
7158#else
7159 // Joseph add to 819X code base for Vista USB platform.
7160 // This part may need to be add to Hal819xU code base. too.
7161 PlatformUsbEnableInPipes(Adapter);
7162#endif
7163
7164 RT_TRACE(COMP_INIT, "HighestOperaRate = %x\n", Adapter->MgntInfo.HighestOperaRate);
7165
7166 PlatformStartWorkItem( &(pHalData->RtUsbCheckForHangWorkItem) );
7167
7168 //
7169 // <Roger_EXP> The following configurations are for ASIC verification temporally.
7170 // 2008.07.10.
7171 //
7172
7173#endif
7174
7175 //
7176 // Read EEPROM TX power index and PHY_REG_PG.txt to capture correct
7177 // TX power index for different rate set.
7178 //
7179 //if(priv->card_8192_version >= VERSION_8192S_ACUT)
7180 {
7181 // Get original hw reg values
7182 PHY_GetHWRegOriginalValue(dev);
7183
7184 // Write correct tx power index//FIXLZM
7185 PHY_SetTxPowerLevel8192S(dev, priv->chan);
7186 }
7187
7188 {
7189 u8 tmpU1b = 0;
7190 // EEPROM R/W workaround
7191 tmpU1b = read_nic_byte(dev, MAC_PINMUX_CFG);
7192 write_nic_byte(dev, MAC_PINMUX_CFG, tmpU1b&(~GPIOMUX_EN));
7193 }
7194
7195//
7196//<Roger_Notes> 2008.08.19.
7197// We return status here for temporal FPGA verification, 2008.08.19.
7198
7199#ifdef RTL8192SU_FW_IQK
7200 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
7201 ChkFwCmdIoDone(dev);
7202#endif
7203
7204 //
7205 // <Roger_Notes> We enable high power mechanism after NIC initialized.
7206 // 2008.11.27.
7207 //
7208 write_nic_dword(dev, WFM5, FW_RA_RESET);
7209 ChkFwCmdIoDone(dev);
7210 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
7211 ChkFwCmdIoDone(dev);
7212 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
7213 ChkFwCmdIoDone(dev);
7214 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
7215
7216// <Roger_Notes> We return status here for temporal FPGA verification. 2008.05.12.
7217//
5f53d8ca
JC		 7218
7219// The following IO was for FPGA verification purpose. Added by Roger, 2008.09.11.
7220#if 0
7221 // 2008/08/19 MH From SD1 Jong, we must write some register for true PHY/MAC FPGA.
7222 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x30);
7223 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x30);
7224
7225 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
7226
7227 //write_nic_dword(Adapter, RCR, 0x817FF02F);
7228
7229 write_nic_dword(Adapter, rTxAGC_Mcs15_Mcs12, 0x06060606);
7230#endif
7231end:
7232return rtStatus;
7233}
7234
7235#else
7236
7237//InitializeAdapter and PhyCfg
7238bool rtl8192_adapter_start(struct net_device *dev)
7239{
7240 struct r8192_priv *priv = ieee80211_priv(dev);
7241 u32 dwRegRead = 0;
7242 bool init_status = true;
7243 RT_TRACE(COMP_INIT, "====>%s()\n", __FUNCTION__);
7244 priv->Rf_Mode = RF_OP_By_SW_3wire;
7245 //for ASIC power on sequence
7246 write_nic_byte_E(dev, 0x5f, 0x80);
7247 mdelay(50);
7248 write_nic_byte_E(dev, 0x5f, 0xf0);
7249 write_nic_byte_E(dev, 0x5d, 0x00);
7250 write_nic_byte_E(dev, 0x5e, 0x80);
7251 write_nic_byte(dev, 0x17, 0x37);
7252 mdelay(10);
7253//#ifdef TO_DO_LIST
7254 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
7255 //config CPUReset Register
7256 //Firmware Reset or not?
7257 dwRegRead = read_nic_dword(dev, CPU_GEN);
7258 if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
7259 dwRegRead |= CPU_GEN_SYSTEM_RESET; //do nothing here?
7260 else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
7261 dwRegRead |= CPU_GEN_FIRMWARE_RESET;
7262 else
7263 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
7264
7265 write_nic_dword(dev, CPU_GEN, dwRegRead);
7266 //mdelay(30);
7267 //config BB.
7268 rtl8192_BBConfig(dev);
7269
7270#if 1
7271 //Loopback mode or not
7272 priv->LoopbackMode = RTL819xU_NO_LOOPBACK;
7273// priv->LoopbackMode = RTL819xU_MAC_LOOPBACK;
7274
7275 dwRegRead = read_nic_dword(dev, CPU_GEN);
7276 if (priv->LoopbackMode == RTL819xU_NO_LOOPBACK)
7277 dwRegRead = ((dwRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
7278 else if (priv->LoopbackMode == RTL819xU_MAC_LOOPBACK)
7279 dwRegRead |= CPU_CCK_LOOPBACK;
7280 else
7281 RT_TRACE(COMP_ERR, "Serious error in %s(): wrong loopback mode setting(%d)\n", __FUNCTION__, priv->LoopbackMode);
7282
7283 write_nic_dword(dev, CPU_GEN, dwRegRead);
7284
7285 //after reset cpu, we need wait for a seconds to write in register.
7286 udelay(500);
7287
7288 //xiong add for new bitfile:usb suspend reset pin set to 1. //do we need?
7289 write_nic_byte_E(dev, 0x5f, (read_nic_byte_E(dev, 0x5f)|0x20));
7290
7291 //Set Hardware
7292 rtl8192_hwconfig(dev);
7293
7294 //turn on Tx/Rx
7295 write_nic_byte(dev, CMDR, CR_RE|CR_TE);
7296
7297 //set IDR0 here
7298 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
7299 write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
7300
7301 //set RCR
7302 write_nic_dword(dev, RCR, priv->ReceiveConfig);
7303
7304 //Initialize Number of Reserved Pages in Firmware Queue
7305 write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |\
7306 NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT | \
7307 NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT | \
7308 NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
7309 write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT |\
7310 NUM_OF_PAGE_IN_FW_QUEUE_CMD << RSVD_FW_QUEUE_PAGE_CMD_SHIFT);
7311 write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW| \
7312 NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT
7313// | NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT
7314 );
7315 write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
7316
7317 //Set AckTimeout
7318 // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
7319 write_nic_byte(dev, ACK_TIMEOUT, 0x30);
7320
7321// RT_TRACE(COMP_INIT, "%s():priv->ResetProgress is %d\n", __FUNCTION__,priv->ResetProgress);
7322 if(priv->ResetProgress == RESET_TYPE_NORESET)
7323 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);
7324 if(priv->ResetProgress == RESET_TYPE_NORESET){
7325 CamResetAllEntry(dev);
7326 {
7327 u8 SECR_value = 0x0;
7328 SECR_value |= SCR_TxEncEnable;
7329 SECR_value |= SCR_RxDecEnable;
7330 SECR_value |= SCR_NoSKMC;
7331 write_nic_byte(dev, SECR, SECR_value);
7332 }
7333 }
7334
7335 //Beacon related
7336 write_nic_word(dev, ATIMWND, 2);
7337 write_nic_word(dev, BCN_INTERVAL, 100);
7338
7339 {
7340#define DEFAULT_EDCA 0x005e4332
7341 int i;
7342 for (i=0; i<QOS_QUEUE_NUM; i++)
7343 write_nic_dword(dev, WDCAPARA_ADD[i], DEFAULT_EDCA);
7344 }
5f53d8ca
JC		 7345
7346 rtl8192_phy_configmac(dev);
7347
7348 if (priv->card_8192_version == (u8) VERSION_819xU_A)
7349 {
7350 rtl8192_phy_getTxPower(dev);
7351 rtl8192_phy_setTxPower(dev, priv->chan);
7352 }
7353
7354
7355 priv->usb_error = false;
7356 //Firmware download
7357 init_status = init_firmware(dev);
7358 if(!init_status)
7359 {
7360 RT_TRACE(COMP_ERR,"ERR!!! %s(): Firmware download is failed\n", __FUNCTION__);
7361 return init_status;
7362 }
7363 RT_TRACE(COMP_INIT, "%s():after firmware download\n", __FUNCTION__);
7364 //
7365#ifdef TO_DO_LIST
7366if(Adapter->ResetProgress == RESET_TYPE_NORESET)
7367 {
7368 if(pMgntInfo->RegRfOff == TRUE)
7369 { // User disable RF via registry.
7370 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RegRfOff ----------\n"));
7371 MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
7372 // Those action will be discard in MgntActSet_RF_State because off the same state
7373 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
7374 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
7375 }
7376 else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS)
7377 { // H/W or S/W RF OFF before sleep.
7378 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RfOffReason(%d) ----------\n", pMgntInfo->RfOffReason));
7379 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
7380 }
7381 else
7382 {
7383 pHalData->eRFPowerState = eRfOn;
7384 pMgntInfo->RfOffReason = 0;
7385 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): RF is on ----------\n"));
7386 }
7387 }
7388 else
7389 {
7390 if(pHalData->eRFPowerState == eRfOff)
7391 {
7392 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
7393 // Those action will be discard in MgntActSet_RF_State because off the same state
7394 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
7395 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
7396 }
7397 }
7398#endif
7399 //config RF.
7400 if(priv->ResetProgress == RESET_TYPE_NORESET){
7401 rtl8192_phy_RFConfig(dev);
7402 RT_TRACE(COMP_INIT, "%s():after phy RF config\n", __FUNCTION__);
7403 }
7404
7405
7406 if(priv->ieee80211->FwRWRF)
7407 // We can force firmware to do RF-R/W
7408 priv->Rf_Mode = RF_OP_By_FW;
7409 else
7410 priv->Rf_Mode = RF_OP_By_SW_3wire;
7411
7412
7413 rtl8192_phy_updateInitGain(dev);
7414 /*--set CCK and OFDM Block "ON"--*/
7415 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
7416 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
7417
7418 if(priv->ResetProgress == RESET_TYPE_NORESET)
7419 {
7420 //if D or C cut
7421 u8 tmpvalue = read_nic_byte(dev, 0x301);
7422 if(tmpvalue ==0x03)
7423 {
7424 priv->bDcut = TRUE;
7425 RT_TRACE(COMP_POWER_TRACKING, "D-cut\n");
7426 }
7427 else
7428 {
7429 priv->bDcut = FALSE;
7430 RT_TRACE(COMP_POWER_TRACKING, "C-cut\n");
7431 }
7432 dm_initialize_txpower_tracking(dev);
7433
7434 if(priv->bDcut == TRUE)
7435 {
7436 u32 i, TempCCk;
7437 u32 tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);
7438 // u32 tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);
7439 for(i = 0; i<TxBBGainTableLength; i++)
7440 {
7441 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
7442 {
7443 priv->rfa_txpowertrackingindex= (u8)i;
7444 priv->rfa_txpowertrackingindex_real= (u8)i;
7445 priv->rfa_txpowertracking_default= priv->rfa_txpowertrackingindex;
7446 break;
7447 }
7448 }
7449
7450 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
7451
7452 for(i=0 ; i<CCKTxBBGainTableLength ; i++)
7453 {
7454
7455 if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
7456 {
7457 priv->cck_present_attentuation_20Mdefault=(u8) i;
7458 break;
7459 }
7460 }
7461 priv->cck_present_attentuation_40Mdefault= 0;
7462 priv->cck_present_attentuation_difference= 0;
7463 priv->cck_present_attentuation = priv->cck_present_attentuation_20Mdefault;
7464
7465 // pMgntInfo->bTXPowerTracking = FALSE;//TEMPLY DISABLE
7466 }
7467 }
7468 write_nic_byte(dev, 0x87, 0x0);
7469
7470
7471#endif
7472 return init_status;
7473}
7474
7475#endif
7476/* this configures registers for beacon tx and enables it via
7477 * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might
7478 * be used to stop beacon transmission
7479 */
7480#if 0
7481void rtl8192_start_tx_beacon(struct net_device *dev)
7482{
7483 int i;
7484 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
7485 u16 word;
7486 DMESG("Enabling beacon TX");
7487 //write_nic_byte(dev, TX_CONF,0xe6);// TX_CONF
7488 //rtl8192_init_beacon(dev);
7489 //set_nic_txring(dev);
7490// rtl8192_prepare_beacon(dev);
7491 rtl8192_irq_disable(dev);
7492// rtl8192_beacon_tx_enable(dev);
7493 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
7494 //write_nic_byte(dev,0x9d,0x20); //DMA Poll
7495 //write_nic_word(dev,0x7a,0);
7496 //write_nic_word(dev,0x7a,0x8000);
7497
7498
7499 word = read_nic_word(dev, BcnItv);
7500 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
7501 write_nic_word(dev, BcnItv, word);
7502
7503 write_nic_word(dev, AtimWnd,
7504 read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd);
7505
7506 word = read_nic_word(dev, BCN_INTR_ITV);
7507 word &= ~BCN_INTR_ITV_MASK;
7508
7509 //word |= priv->ieee80211->beacon_interval *
7510 // ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
7511 // FIXME:FIXME check if correct ^^ worked with 0x3e8;
7512
7513 write_nic_word(dev, BCN_INTR_ITV, word);
7514
7515 //write_nic_word(dev,0x2e,0xe002);
7516 //write_nic_dword(dev,0x30,0xb8c7832e);
7517 for(i=0; i<ETH_ALEN; i++)
7518 write_nic_byte(dev, BSSID+i, priv->ieee80211->beacon_cell_ssid[i]);
7519
7520// rtl8192_update_msr(dev);
7521
7522
7523 //write_nic_byte(dev,CONFIG4,3); /* !!!!!!!!!! */
7524
7525 rtl8192_set_mode(dev, EPROM_CMD_NORMAL);
7526
7527 rtl8192_irq_enable(dev);
7528
7529 /* VV !!!!!!!!!! VV*/
7530 /*
7531 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
7532 write_nic_byte(dev,0x9d,0x00);
7533 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
7534*/
7535}
7536#endif
7537/***************************************************************************
7538 -------------------------------NET STUFF---------------------------
7539***************************************************************************/
7540
7541static struct net_device_stats *rtl8192_stats(struct net_device *dev)
7542{
7543 struct r8192_priv *priv = ieee80211_priv(dev);
7544
7545 return &priv->ieee80211->stats;
7546}
7547
7548bool
7549HalTxCheckStuck819xUsb(
7550 struct net_device *dev
7551 )
7552{
7553 struct r8192_priv *priv = ieee80211_priv(dev);
7554 u16 RegTxCounter = read_nic_word(dev, 0x128);
7555 bool bStuck = FALSE;
7556 RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
7557 if(priv->TxCounter==RegTxCounter)
7558 bStuck = TRUE;
7559
7560 priv->TxCounter = RegTxCounter;
7561
7562 return bStuck;
7563}
7564
7565/*
7566* <Assumption: RT_TX_SPINLOCK is acquired.>
7567* First added: 2006.11.19 by emily
7568*/
7569RESET_TYPE
7570TxCheckStuck(struct net_device *dev)
7571{
7572 struct r8192_priv *priv = ieee80211_priv(dev);
7573 u8 QueueID;
7574// PRT_TCB pTcb;
7575// u8 ResetThreshold;
7576 bool bCheckFwTxCnt = false;
7577 //unsigned long flags;
7578
7579 //
7580 // Decide Stuch threshold according to current power save mode
7581 //
7582
7583// RT_TRACE(COMP_RESET, " ==> TxCheckStuck()\n");
7584// PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
7585// spin_lock_irqsave(&priv->ieee80211->lock,flags);
7586 for (QueueID = 0; QueueID<=BEACON_QUEUE;QueueID ++)
7587 {
7588 if(QueueID == TXCMD_QUEUE)
7589 continue;
7590#if 1
5f53d8ca 7591 if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0))
5f53d8ca
JC		 7592 continue;
7593#endif
7594
7595 bCheckFwTxCnt = true;
7596 }
7597// PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
7598// spin_unlock_irqrestore(&priv->ieee80211->lock,flags);
7599// RT_TRACE(COMP_RESET,"bCheckFwTxCnt is %d\n",bCheckFwTxCnt);
7600#if 1
7601 if(bCheckFwTxCnt)
7602 {
7603 if(HalTxCheckStuck819xUsb(dev))
7604 {
7605 RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no Tx condition! \n");
7606 return RESET_TYPE_SILENT;
7607 }
7608 }
7609#endif
7610 return RESET_TYPE_NORESET;
7611}
7612
7613bool
7614HalRxCheckStuck819xUsb(struct net_device *dev)
7615{
7616 u16 RegRxCounter = read_nic_word(dev, 0x130);
7617 struct r8192_priv *priv = ieee80211_priv(dev);
7618 bool bStuck = FALSE;
7619//#ifdef RTL8192SU
7620
7621//#else
7622 static u8 rx_chk_cnt = 0;
7623 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
7624 // If rssi is small, we should check rx for long time because of bad rx.
7625 // or maybe it will continuous silent reset every 2 seconds.
7626 rx_chk_cnt++;
7627 if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5))
7628 {
7629 rx_chk_cnt = 0; //high rssi, check rx stuck right now.
7630 }
7631 else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) &&
7632 ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) ||
7633 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) )
7634 {
7635 if(rx_chk_cnt < 2)
7636 {
7637 return bStuck;
7638 }
7639 else
7640 {
7641 rx_chk_cnt = 0;
7642 }
7643 }
7644 else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) ||
7645 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) &&
7646 priv->undecorated_smoothed_pwdb >= VeryLowRSSI)
7647 {
7648 if(rx_chk_cnt < 4)
7649 {
7650 //DbgPrint("RSSI < %d && RSSI >= %d, no check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
7651 return bStuck;
7652 }
7653 else
7654 {
7655 rx_chk_cnt = 0;
7656 //DbgPrint("RSSI < %d && RSSI >= %d, check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
7657 }
7658 }
7659 else
7660 {
7661 if(rx_chk_cnt < 8)
7662 {
7663 //DbgPrint("RSSI <= %d, no check this time \n", VeryLowRSSI);
7664 return bStuck;
7665 }
7666 else
7667 {
7668 rx_chk_cnt = 0;
7669 //DbgPrint("RSSI <= %d, check this time \n", VeryLowRSSI);
7670 }
7671 }
7672//#endif
7673
7674 if(priv->RxCounter==RegRxCounter)
7675 bStuck = TRUE;
7676
7677 priv->RxCounter = RegRxCounter;
7678
7679 return bStuck;
7680}
7681
7682RESET_TYPE
7683RxCheckStuck(struct net_device *dev)
7684{
7685 struct r8192_priv *priv = ieee80211_priv(dev);
7686 //int i;
7687 bool bRxCheck = FALSE;
7688
7689// RT_TRACE(COMP_RESET," ==> RxCheckStuck()\n");
7690 //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
7691
7692 if(priv->IrpPendingCount > 1)
7693 bRxCheck = TRUE;
7694 //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
7695
7696// RT_TRACE(COMP_RESET,"bRxCheck is %d \n",bRxCheck);
7697 if(bRxCheck)
7698 {
7699 if(HalRxCheckStuck819xUsb(dev))
7700 {
7701 RT_TRACE(COMP_RESET, "RxStuck Condition\n");
7702 return RESET_TYPE_SILENT;
7703 }
7704 }
7705 return RESET_TYPE_NORESET;
7706}
7707
7708
7709/**
7710* This function is called by Checkforhang to check whether we should ask OS to reset driver
7711*
7712* \param pAdapter The adapter context for this miniport
7713*
7714* Note:NIC with USB interface sholud not call this function because we cannot scan descriptor
7715* to judge whether there is tx stuck.
7716* Note: This function may be required to be rewrite for Vista OS.
7717* <<<Assumption: Tx spinlock has been acquired >>>
7718*
7719* 8185 and 8185b does not implement this function. This is added by Emily at 2006.11.24
7720*/
7721RESET_TYPE
7722rtl819x_ifcheck_resetornot(struct net_device *dev)
7723{
7724 struct r8192_priv *priv = ieee80211_priv(dev);
7725 RESET_TYPE TxResetType = RESET_TYPE_NORESET;
7726 RESET_TYPE RxResetType = RESET_TYPE_NORESET;
7727 RT_RF_POWER_STATE rfState;
7728
5f53d8ca 7729 return RESET_TYPE_NORESET;
5f53d8ca
JC		 7730
7731 rfState = priv->ieee80211->eRFPowerState;
7732
7733 TxResetType = TxCheckStuck(dev);
7734#if 1
7735 if( rfState != eRfOff ||
7736 /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/
7737 (priv->ieee80211->iw_mode != IW_MODE_ADHOC))
7738 {
7739 // If driver is in the status of firmware download failure , driver skips RF initialization and RF is
7740 // in turned off state. Driver should check whether Rx stuck and do silent reset. And
7741 // if driver is in firmware download failure status, driver should initialize RF in the following
7742 // silent reset procedure Emily, 2008.01.21
7743
7744 // Driver should not check RX stuck in IBSS mode because it is required to
7745 // set Check BSSID in order to send beacon, however, if check BSSID is
7746 // set, STA cannot hear any packet a all. Emily, 2008.04.12
7747 RxResetType = RxCheckStuck(dev);
7748 }
7749#endif
7750 if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL)
7751 return RESET_TYPE_NORMAL;
7752 else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT){
7753 RT_TRACE(COMP_RESET,"%s():silent reset\n",__FUNCTION__);
7754 return RESET_TYPE_SILENT;
7755 }
7756 else
7757 return RESET_TYPE_NORESET;
7758
7759}
7760
7761void rtl8192_cancel_deferred_work(struct r8192_priv* priv);
7762int _rtl8192_up(struct net_device *dev);
7763int rtl8192_close(struct net_device *dev);
7764
7765
7766
7767void
7768CamRestoreAllEntry( struct net_device *dev)
7769{
7770 u8 EntryId = 0;
7771 struct r8192_priv *priv = ieee80211_priv(dev);
7772 u8* MacAddr = priv->ieee80211->current_network.bssid;
7773
7774 static u8 CAM_CONST_ADDR[4][6] = {
7775 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
7776 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
7777 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
7778 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}};
7779 static u8 CAM_CONST_BROAD[] =
7780 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
7781
7782 RT_TRACE(COMP_SEC, "CamRestoreAllEntry: \n");
7783
7784
7785 if ((priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP40)||
7786 (priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP104))
7787 {
7788
7789 for(EntryId=0; EntryId<4; EntryId++)
7790 {
7791 {
7792 MacAddr = CAM_CONST_ADDR[EntryId];
7793 setKey(dev,
7794 EntryId ,
7795 EntryId,
7796 priv->ieee80211->pairwise_key_type,
7797 MacAddr,
7798 0,
7799 NULL);
7800 }
7801 }
7802
7803 }
7804 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_TKIP)
7805 {
7806
7807 {
7808 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
7809 setKey(dev,
7810 4,
7811 0,
7812 priv->ieee80211->pairwise_key_type,
7813 (u8*)dev->dev_addr,
7814 0,
7815 NULL);
7816 else
7817 setKey(dev,
7818 4,
7819 0,
7820 priv->ieee80211->pairwise_key_type,
7821 MacAddr,
7822 0,
7823 NULL);
7824 }
7825 }
7826 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP)
7827 {
7828
7829 {
7830 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
7831 setKey(dev,
7832 4,
7833 0,
7834 priv->ieee80211->pairwise_key_type,
7835 (u8*)dev->dev_addr,
7836 0,
7837 NULL);
7838 else
7839 setKey(dev,
7840 4,
7841 0,
7842 priv->ieee80211->pairwise_key_type,
7843 MacAddr,
7844 0,
7845 NULL);
7846 }
7847 }
7848
7849
7850
7851 if(priv->ieee80211->group_key_type == KEY_TYPE_TKIP)
7852 {
7853 MacAddr = CAM_CONST_BROAD;
7854 for(EntryId=1 ; EntryId<4 ; EntryId++)
7855 {
7856 {
7857 setKey(dev,
7858 EntryId,
7859 EntryId,
7860 priv->ieee80211->group_key_type,
7861 MacAddr,
7862 0,
7863 NULL);
7864 }
7865 }
7866 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
7867 setKey(dev,
7868 0,
7869 0,
7870 priv->ieee80211->group_key_type,
7871 CAM_CONST_ADDR[0],
7872 0,
7873 NULL);
7874 }
7875 else if(priv->ieee80211->group_key_type == KEY_TYPE_CCMP)
7876 {
7877 MacAddr = CAM_CONST_BROAD;
7878 for(EntryId=1; EntryId<4 ; EntryId++)
7879 {
7880 {
7881 setKey(dev,
7882 EntryId ,
7883 EntryId,
7884 priv->ieee80211->group_key_type,
7885 MacAddr,
7886 0,
7887 NULL);
7888 }
7889 }
7890
7891 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
7892 setKey(dev,
7893 0 ,
7894 0,
7895 priv->ieee80211->group_key_type,
7896 CAM_CONST_ADDR[0],
7897 0,
7898 NULL);
7899 }
7900}
7901//////////////////////////////////////////////////////////////
7902// This function is used to fix Tx/Rx stop bug temporarily.
7903// This function will do "system reset" to NIC when Tx or Rx is stuck.
7904// The method checking Tx/Rx stuck of this function is supported by FW,
7905// which reports Tx and Rx counter to register 0x128 and 0x130.
7906//////////////////////////////////////////////////////////////
7907void
7908rtl819x_ifsilentreset(struct net_device *dev)
7909{
7910 //OCTET_STRING asocpdu;
7911 struct r8192_priv *priv = ieee80211_priv(dev);
7912 u8 reset_times = 0;
7913 int reset_status = 0;
7914 struct ieee80211_device *ieee = priv->ieee80211;
7915
7916
7917 // 2007.07.20. If we need to check CCK stop, please uncomment this line.
7918 //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter);
7919
7920 if(priv->ResetProgress==RESET_TYPE_NORESET)
7921 {
7922RESET_START:
7923
7924 RT_TRACE(COMP_RESET,"=========>Reset progress!! \n");
7925
7926 // Set the variable for reset.
7927 priv->ResetProgress = RESET_TYPE_SILENT;
7928// rtl8192_close(dev);
7929#if 1
7930 down(&priv->wx_sem);
7931 if(priv->up == 0)
7932 {
7933 RT_TRACE(COMP_ERR,"%s():the driver is not up! return\n",__FUNCTION__);
7934 up(&priv->wx_sem);
7935 return ;
7936 }
7937 priv->up = 0;
7938 RT_TRACE(COMP_RESET,"%s():======>start to down the driver\n",__FUNCTION__);
7939// if(!netif_queue_stopped(dev))
7940// netif_stop_queue(dev);
7941
7942 rtl8192_rtx_disable(dev);
7943 rtl8192_cancel_deferred_work(priv);
7944 deinit_hal_dm(dev);
7945 del_timer_sync(&priv->watch_dog_timer);
7946
7947 ieee->sync_scan_hurryup = 1;
7948 if(ieee->state == IEEE80211_LINKED)
7949 {
7950 down(&ieee->wx_sem);
7951 printk("ieee->state is IEEE80211_LINKED\n");
7952 ieee80211_stop_send_beacons(priv->ieee80211);
7953 del_timer_sync(&ieee->associate_timer);
5f53d8ca 7954 cancel_delayed_work(&ieee->associate_retry_wq);
5f53d8ca
JC		 7955 ieee80211_stop_scan(ieee);
7956 netif_carrier_off(dev);
7957 up(&ieee->wx_sem);
7958 }
7959 else{
7960 printk("ieee->state is NOT LINKED\n");
7961 ieee80211_softmac_stop_protocol(priv->ieee80211); }
7962 up(&priv->wx_sem);
7963 RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__);
7964 //rtl8192_irq_disable(dev);
7965 RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__);
7966 reset_status = _rtl8192_up(dev);
7967
7968 RT_TRACE(COMP_RESET,"%s():<===========up process is finished\n",__FUNCTION__);
7969 if(reset_status == -EAGAIN)
7970 {
7971 if(reset_times < 3)
7972 {
7973 reset_times++;
7974 goto RESET_START;
7975 }
7976 else
7977 {
7978 RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n", __FUNCTION__);
7979 }
7980 }
7981#endif
7982 ieee->is_silent_reset = 1;
7983#if 1
7984 EnableHWSecurityConfig8192(dev);
7985#if 1
7986 if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA)
7987 {
7988 ieee->set_chan(ieee->dev, ieee->current_network.channel);
7989
7990#if 1
5f53d8ca 7991 queue_work(ieee->wq, &ieee->associate_complete_wq);
5f53d8ca
JC		 7992#endif
7993
7994 }
7995 else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC)
7996 {
7997 ieee->set_chan(ieee->dev, ieee->current_network.channel);
7998 ieee->link_change(ieee->dev);
7999
8000 // notify_wx_assoc_event(ieee);
8001
8002 ieee80211_start_send_beacons(ieee);
8003
8004 if (ieee->data_hard_resume)
8005 ieee->data_hard_resume(ieee->dev);
8006 netif_carrier_on(ieee->dev);
8007 }
8008#endif
8009
8010 CamRestoreAllEntry(dev);
8011
8012 priv->ResetProgress = RESET_TYPE_NORESET;
8013 priv->reset_count++;
8014
8015 priv->bForcedSilentReset =false;
8016 priv->bResetInProgress = false;
8017
8018 // For test --> force write UFWP.
8019 write_nic_byte(dev, UFWP, 1);
8020 RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
8021#endif
8022 }
8023}
8024
8025void CAM_read_entry(
8026 struct net_device *dev,
8027 u32 iIndex
8028)
8029{
8030 u32 target_command=0;
8031 u32 target_content=0;
8032 u8 entry_i=0;
8033 u32 ulStatus;
8034 s32 i=100;
8035// printk("=======>start read CAM\n");
8036 for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
8037 {
8038 // polling bit, and No Write enable, and address
8039 target_command= entry_i+CAM_CONTENT_COUNT*iIndex;
8040 target_command= target_command | BIT31;
8041
8042 //Check polling bit is clear
8043// mdelay(1);
8044#if 1
8045 while((i--)>=0)
8046 {
8047 ulStatus = read_nic_dword(dev, RWCAM);
8048 if(ulStatus & BIT31){
8049 continue;
8050 }
8051 else{
8052 break;
8053 }
8054 }
8055#endif
8056 write_nic_dword(dev, RWCAM, target_command);
8057 RT_TRACE(COMP_SEC,"CAM_read_entry(): WRITE A0: %x \n",target_command);
8058 // printk("CAM_read_entry(): WRITE A0: %lx \n",target_command);
8059 target_content = read_nic_dword(dev, RCAMO);
8060 RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n",target_content);
8061 // printk("CAM_read_entry(): WRITE A8: %lx \n",target_content);
8062 }
8063 printk("\n");
8064}
8065
8066void rtl819x_update_rxcounts(
8067 struct r8192_priv *priv,
8068 u32* TotalRxBcnNum,
8069 u32* TotalRxDataNum
8070)
8071{
8072 u16 SlotIndex;
8073 u8 i;
8074
8075 *TotalRxBcnNum = 0;
8076 *TotalRxDataNum = 0;
8077
8078 SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum);
8079 priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod;
8080 priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod;
8081 for( i=0; i<priv->ieee80211->LinkDetectInfo.SlotNum; i++ ){
8082 *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i];
8083 *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i];
8084 }
8085}
8086
5f53d8ca
JC		 8087extern void rtl819x_watchdog_wqcallback(struct work_struct *work)
8088{
8089 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
8090 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq);
8091 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 8092 struct ieee80211_device* ieee = priv->ieee80211;
8093 RESET_TYPE ResetType = RESET_TYPE_NORESET;
8094 static u8 check_reset_cnt=0;
8095 bool bBusyTraffic = false;
8096
8097 if(!priv->up)
8098 return;
8099 hal_dm_watchdog(dev);
8100
8101 {//to get busy traffic condition
8102 if(ieee->state == IEEE80211_LINKED)
8103 {
8104 //windows mod 666 to 100.
8105 //if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 ||
8106 // ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) {
8107 if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 ||
8108 ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) {
8109 bBusyTraffic = true;
8110 }
8111 ieee->LinkDetectInfo.NumRxOkInPeriod = 0;
8112 ieee->LinkDetectInfo.NumTxOkInPeriod = 0;
8113 ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
8114 }
8115 }
8116 //added by amy for AP roaming
8117 {
8118 if(priv->ieee80211->state == IEEE80211_LINKED && priv->ieee80211->iw_mode == IW_MODE_INFRA)
8119 {
8120 u32 TotalRxBcnNum = 0;
8121 u32 TotalRxDataNum = 0;
8122
8123 rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum);
8124 if((TotalRxBcnNum+TotalRxDataNum) == 0)
8125 {
8126 #ifdef TODO
8127 if(rfState == eRfOff)
8128 RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__);
8129 #endif
8130 printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__);
8131 // Dot11d_Reset(dev);
8132 priv->ieee80211->state = IEEE80211_ASSOCIATING;
8133 notify_wx_assoc_event(priv->ieee80211);
8134 RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid);
8135 ieee->is_roaming = true;
8136 priv->ieee80211->link_change(dev);
5f53d8ca 8137 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
5f53d8ca
JC		 8138 }
8139 }
8140 priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod=0;
8141 priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod=0;
8142 }
8143// CAM_read_entry(dev,4);
8144 //check if reset the driver
8145 if(check_reset_cnt++ >= 3 && !ieee->is_roaming)
8146 {
8147 ResetType = rtl819x_ifcheck_resetornot(dev);
8148 check_reset_cnt = 3;
8149 //DbgPrint("Start to check silent reset\n");
8150 }
8151 // RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
8152#if 1
8153 if( (priv->force_reset) || (priv->ResetProgress==RESET_TYPE_NORESET &&
8154 (priv->bForcedSilentReset ||
8155 (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT)))) // This is control by OID set in Pomelo
8156 {
8157 RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
8158 rtl819x_ifsilentreset(dev);
8159 }
8160#endif
8161 priv->force_reset = false;
8162 priv->bForcedSilentReset = false;
8163 priv->bResetInProgress = false;
8164 RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n");
8165
8166}
8167
8168void watch_dog_timer_callback(unsigned long data)
8169{
8170 struct r8192_priv *priv = ieee80211_priv((struct net_device *) data);
8171 //printk("===============>watch_dog timer\n");
5f53d8ca 8172 queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq, 0);
5f53d8ca
JC		 8173 mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME));
8174#if 0
8175 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
8176 add_timer(&priv->watch_dog_timer);
8177#endif
8178}
8179int _rtl8192_up(struct net_device *dev)
8180{
8181 struct r8192_priv *priv = ieee80211_priv(dev);
8182 //int i;
8183 int init_status = 0;
8184 priv->up=1;
8185 priv->ieee80211->ieee_up=1;
8186 RT_TRACE(COMP_INIT, "Bringing up iface");
8187 init_status = priv->ops->rtl819x_adapter_start(dev);
8188 if(!init_status)
8189 {
8190 RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n", __FUNCTION__);
8191 priv->up=priv->ieee80211->ieee_up = 0;
8192 return -EAGAIN;
8193 }
8194 RT_TRACE(COMP_INIT, "start adapter finished\n");
8195 rtl8192_rx_enable(dev);
8196// rtl8192_tx_enable(dev);
8197 if(priv->ieee80211->state != IEEE80211_LINKED)
8198 ieee80211_softmac_start_protocol(priv->ieee80211);
8199 ieee80211_reset_queue(priv->ieee80211);
8200 watch_dog_timer_callback((unsigned long) dev);
8201 if(!netif_queue_stopped(dev))
8202 netif_start_queue(dev);
8203 else
8204 netif_wake_queue(dev);
8205
8206 /*
8207 * Make sure that drop_unencrypted is initialized as "0"
8208 * No packets will be sent in non-security mode if we had set drop_unencrypted.
8209 * ex, After kill wpa_supplicant process, make the driver up again.
8210 * drop_unencrypted remains as "1", which is set by wpa_supplicant. 2008/12/04.john
8211 */
8212 priv->ieee80211->drop_unencrypted = 0;
8213
8214 return 0;
8215}
8216
8217
8218int rtl8192_open(struct net_device *dev)
8219{
8220 struct r8192_priv *priv = ieee80211_priv(dev);
8221 int ret;
8222 down(&priv->wx_sem);
8223 ret = rtl8192_up(dev);
8224 up(&priv->wx_sem);
8225 return ret;
8226
8227}
8228
8229
8230int rtl8192_up(struct net_device *dev)
8231{
8232 struct r8192_priv *priv = ieee80211_priv(dev);
8233
8234 if (priv->up == 1) return -1;
8235
8236 return _rtl8192_up(dev);
8237}
8238
8239
8240int rtl8192_close(struct net_device *dev)
8241{
8242 struct r8192_priv *priv = ieee80211_priv(dev);
8243 int ret;
8244
8245 down(&priv->wx_sem);
8246
8247 ret = rtl8192_down(dev);
8248
8249 up(&priv->wx_sem);
8250
8251 return ret;
8252
8253}
8254
8255int rtl8192_down(struct net_device *dev)
8256{
8257 struct r8192_priv *priv = ieee80211_priv(dev);
8258 int i;
8259
8260 if (priv->up == 0) return -1;
8261
8262 priv->up=0;
8263 priv->ieee80211->ieee_up = 0;
8264 RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__);
8265/* FIXME */
8266 if (!netif_queue_stopped(dev))
8267 netif_stop_queue(dev);
8268
8269 rtl8192_rtx_disable(dev);
8270 //rtl8192_irq_disable(dev);
8271
8272 /* Tx related queue release */
8273 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
8274 skb_queue_purge(&priv->ieee80211->skb_waitQ [i]);
8275 }
8276 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
8277 skb_queue_purge(&priv->ieee80211->skb_aggQ [i]);
8278 }
8279
8280 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
8281 skb_queue_purge(&priv->ieee80211->skb_drv_aggQ [i]);
8282 }
8283
8284 //as cancel_delayed_work will del work->timer, so if work is not definedas struct delayed_work, it will corrupt
8285// flush_scheduled_work();
8286 rtl8192_cancel_deferred_work(priv);
8287 deinit_hal_dm(dev);
8288 del_timer_sync(&priv->watch_dog_timer);
8289
8290
8291 ieee80211_softmac_stop_protocol(priv->ieee80211);
8292 memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list));
8293 RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__);
8294
8295 return 0;
8296}
8297
8298
8299void rtl8192_commit(struct net_device *dev)
8300{
8301 struct r8192_priv *priv = ieee80211_priv(dev);
8302 int reset_status = 0;
8303 //u8 reset_times = 0;
8304 if (priv->up == 0) return ;
8305 priv->up = 0;
8306
8307 rtl8192_cancel_deferred_work(priv);
8308 del_timer_sync(&priv->watch_dog_timer);
8309 //cancel_delayed_work(&priv->SwChnlWorkItem);
8310
8311 ieee80211_softmac_stop_protocol(priv->ieee80211);
8312
8313 //rtl8192_irq_disable(dev);
8314 rtl8192_rtx_disable(dev);
8315 reset_status = _rtl8192_up(dev);
8316
8317}
8318
8319/*
8320void rtl8192_restart(struct net_device *dev)
8321{
8322 struct r8192_priv *priv = ieee80211_priv(dev);
8323*/
5f53d8ca
JC		 8324void rtl8192_restart(struct work_struct *work)
8325{
8326 struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq);
8327 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 8328
8329 down(&priv->wx_sem);
8330
8331 rtl8192_commit(dev);
8332
8333 up(&priv->wx_sem);
8334}
8335
8336static void r8192_set_multicast(struct net_device *dev)
8337{
8338 struct r8192_priv *priv = ieee80211_priv(dev);
8339 short promisc;
8340
8341 //down(&priv->wx_sem);
8342
8343 /* FIXME FIXME */
8344
8345 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
8346
8347 if (promisc != priv->promisc)
8348 // rtl8192_commit(dev);
8349
8350 priv->promisc = promisc;
8351
8352 //schedule_work(&priv->reset_wq);
8353 //up(&priv->wx_sem);
8354}
8355
8356
8357int r8192_set_mac_adr(struct net_device *dev, void *mac)
8358{
8359 struct r8192_priv *priv = ieee80211_priv(dev);
8360 struct sockaddr *addr = mac;
8361
8362 down(&priv->wx_sem);
8363
8364 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
8365
5f53d8ca 8366 schedule_work(&priv->reset_wq);
1ec9e48d 8367
5f53d8ca
JC		 8368 up(&priv->wx_sem);
8369
8370 return 0;
8371}
8372
8373/* based on ipw2200 driver */
8374int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
8375{
8376 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8377 struct iwreq *wrq = (struct iwreq *)rq;
8378 int ret=-1;
8379 struct ieee80211_device *ieee = priv->ieee80211;
8380 u32 key[4];
8381 u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
8382 u8 zero_addr[6] = {0};
8383 struct iw_point *p = &wrq->u.data;
8384 struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer;
8385
8386 down(&priv->wx_sem);
8387
8388
8389 if (p->length < sizeof(struct ieee_param) || !p->pointer){
8390 ret = -EINVAL;
8391 goto out;
8392 }
8393
8394 ipw = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL);
8395 if (ipw == NULL){
8396 ret = -ENOMEM;
8397 goto out;
8398 }
8399 if (copy_from_user(ipw, p->pointer, p->length)) {
8400 kfree(ipw);
8401 ret = -EFAULT;
8402 goto out;
8403 }
8404
8405 switch (cmd) {
8406 case RTL_IOCTL_WPA_SUPPLICANT:
8407 //parse here for HW security
8408 if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION)
8409 {
8410 if (ipw->u.crypt.set_tx)
8411 {
8412 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
8413 ieee->pairwise_key_type = KEY_TYPE_CCMP;
8414 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
8415 ieee->pairwise_key_type = KEY_TYPE_TKIP;
8416 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
8417 {
8418 if (ipw->u.crypt.key_len == 13)
8419 ieee->pairwise_key_type = KEY_TYPE_WEP104;
8420 else if (ipw->u.crypt.key_len == 5)
8421 ieee->pairwise_key_type = KEY_TYPE_WEP40;
8422 }
8423 else
8424 ieee->pairwise_key_type = KEY_TYPE_NA;
8425
8426 if (ieee->pairwise_key_type)
8427 {
8428 // FIXME:these two lines below just to fix ipw interface bug, that is, it will never set mode down to driver. So treat it as ADHOC mode, if no association procedure. WB. 2009.02.04
8429 if (memcmp(ieee->ap_mac_addr, zero_addr, 6) == 0)
8430 ieee->iw_mode = IW_MODE_ADHOC;
8431 memcpy((u8*)key, ipw->u.crypt.key, 16);
8432 EnableHWSecurityConfig8192(dev);
8433 //we fill both index entry and 4th entry for pairwise key as in IPW interface, adhoc will only get here, so we need index entry for its default key serching!
8434 //added by WB.
8435 setKey(dev, 4, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
8436 if (ieee->iw_mode == IW_MODE_ADHOC)
8437 setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
8438 }
8439 }
8440 else //if (ipw->u.crypt.idx) //group key use idx > 0
8441 {
8442 memcpy((u8*)key, ipw->u.crypt.key, 16);
8443 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
8444 ieee->group_key_type= KEY_TYPE_CCMP;
8445 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
8446 ieee->group_key_type = KEY_TYPE_TKIP;
8447 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
8448 {
8449 if (ipw->u.crypt.key_len == 13)
8450 ieee->group_key_type = KEY_TYPE_WEP104;
8451 else if (ipw->u.crypt.key_len == 5)
8452 ieee->group_key_type = KEY_TYPE_WEP40;
8453 }
8454 else
8455 ieee->group_key_type = KEY_TYPE_NA;
8456
8457 if (ieee->group_key_type)
8458 {
8459 setKey( dev,
8460 ipw->u.crypt.idx,
8461 ipw->u.crypt.idx, //KeyIndex
8462 ieee->group_key_type, //KeyType
8463 broadcast_addr, //MacAddr
8464 0, //DefaultKey
8465 key); //KeyContent
8466 }
8467 }
8468 }
8469#ifdef JOHN_HWSEC_DEBUG
8470 //john's test 0711
8471 printk("@@ wrq->u pointer = ");
8472 for(i=0;i<wrq->u.data.length;i++){
8473 if(i%10==0) printk("\n");
8474 printk( "%8x|", ((u32*)wrq->u.data.pointer)[i] );
8475 }
8476 printk("\n");
8477#endif /*JOHN_HWSEC_DEBUG*/
8478 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
8479 break;
8480
8481 default:
8482 ret = -EOPNOTSUPP;
8483 break;
8484 }
8485 kfree(ipw);
8486 ipw = NULL;
8487out:
8488 up(&priv->wx_sem);
8489 return ret;
8490}
8491
8492#ifdef RTL8192SU
8493u8 rtl8192SU_HwRateToMRate(bool bIsHT, u8 rate,bool bFirstAMPDU)
8494{
8495
8496 u8 ret_rate = 0x02;
8497
8498 if( bFirstAMPDU )
8499 {
8500 if(!bIsHT)
8501 {
8502 switch(rate)
8503 {
8504
8505 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
8506 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
8507 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
8508 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
8509 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
8510 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
8511 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
8512 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
8513 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
8514 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
8515 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
8516 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
8517
8518 default:
8519 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
8520 break;
8521 }
8522 }
8523 else
8524 {
8525 switch(rate)
8526 {
8527
8528 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
8529 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
8530 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
8531 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
8532 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
8533 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
8534 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
8535 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
8536 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
8537 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
8538 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
8539 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
8540 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
8541 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
8542 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
8543 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
8544 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
8545
8546 default:
8547 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
8548 break;
8549 }
8550
8551 }
8552 }
8553 else
8554 {
8555 switch(rate)
8556 {
8557
8558 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
8559 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
8560 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
8561 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
8562 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
8563 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
8564 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
8565 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
8566 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
8567 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
8568 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
8569 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
8570 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
8571 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
8572 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
8573 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
8574 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
8575 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
8576 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
8577 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
8578 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
8579 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
8580 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
8581 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
8582 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
8583 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
8584 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
8585 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
8586 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
8587
8588 default:
8589 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
8590 break;
8591 }
8592 }
8593 return ret_rate;
8594}
8595#endif
8596
8597u8 HwRateToMRate90(bool bIsHT, u8 rate)
8598{
8599 u8 ret_rate = 0xff;
8600
8601 if(!bIsHT) {
8602 switch(rate) {
8603 case DESC90_RATE1M: ret_rate = MGN_1M; break;
8604 case DESC90_RATE2M: ret_rate = MGN_2M; break;
8605 case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break;
8606 case DESC90_RATE11M: ret_rate = MGN_11M; break;
8607 case DESC90_RATE6M: ret_rate = MGN_6M; break;
8608 case DESC90_RATE9M: ret_rate = MGN_9M; break;
8609 case DESC90_RATE12M: ret_rate = MGN_12M; break;
8610 case DESC90_RATE18M: ret_rate = MGN_18M; break;
8611 case DESC90_RATE24M: ret_rate = MGN_24M; break;
8612 case DESC90_RATE36M: ret_rate = MGN_36M; break;
8613 case DESC90_RATE48M: ret_rate = MGN_48M; break;
8614 case DESC90_RATE54M: ret_rate = MGN_54M; break;
8615
8616 default:
8617 ret_rate = 0xff;
8618 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
8619 break;
8620 }
8621
8622 } else {
8623 switch(rate) {
8624 case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break;
8625 case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break;
8626 case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break;
8627 case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break;
8628 case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break;
8629 case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break;
8630 case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break;
8631 case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break;
8632 case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break;
8633 case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break;
8634 case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break;
8635 case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break;
8636 case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break;
8637 case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break;
8638 case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break;
8639 case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break;
8640 case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break;
8641
8642 default:
8643 ret_rate = 0xff;
8644 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT);
8645 break;
8646 }
8647 }
8648
8649 return ret_rate;
8650}
8651
8652/**
8653 * Function: UpdateRxPktTimeStamp
8654 * Overview: Recored down the TSF time stamp when receiving a packet
8655 *
8656 * Input:
8657 * PADAPTER Adapter
8658 * PRT_RFD pRfd,
8659 *
8660 * Output:
8661 * PRT_RFD pRfd
8662 * (pRfd->Status.TimeStampHigh is updated)
8663 * (pRfd->Status.TimeStampLow is updated)
8664 * Return:
8665 * None
8666 */
8667void UpdateRxPktTimeStamp8190 (struct net_device *dev, struct ieee80211_rx_stats *stats)
8668{
8669 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8670
8671 if(stats->bIsAMPDU && !stats->bFirstMPDU) {
8672 stats->mac_time[0] = priv->LastRxDescTSFLow;
8673 stats->mac_time[1] = priv->LastRxDescTSFHigh;
8674 } else {
8675 priv->LastRxDescTSFLow = stats->mac_time[0];
8676 priv->LastRxDescTSFHigh = stats->mac_time[1];
8677 }
8678}
8679
8680//by amy 080606
8681
8682long rtl819x_translate_todbm(u8 signal_strength_index )// 0-100 index.
8683{
8684 long signal_power; // in dBm.
8685
8686 // Translate to dBm (x=0.5y-95).
8687 signal_power = (long)((signal_strength_index + 1) >> 1);
8688 signal_power -= 95;
8689
8690 return signal_power;
8691}
8692
8693
8694/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
8695 be a local static. Otherwise, it may increase when we return from S3/S4. The
8696 value will be kept in memory or disk. We must delcare the value in adapter
8697 and it will be reinitialized when return from S3/S4. */
8698void rtl8192_process_phyinfo(struct r8192_priv * priv,u8* buffer, struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats)
8699{
8700 bool bcheck = false;
8701 u8 rfpath;
8702 u32 nspatial_stream, tmp_val;
8703 //u8 i;
8704 static u32 slide_rssi_index=0, slide_rssi_statistics=0;
8705 static u32 slide_evm_index=0, slide_evm_statistics=0;
8706 static u32 last_rssi=0, last_evm=0;
8707
8708 static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0;
8709 static u32 last_beacon_adc_pwdb=0;
8710
8711 struct ieee80211_hdr_3addr *hdr;
8712 u16 sc ;
8713 unsigned int frag,seq;
8714 hdr = (struct ieee80211_hdr_3addr *)buffer;
8715 sc = le16_to_cpu(hdr->seq_ctl);
8716 frag = WLAN_GET_SEQ_FRAG(sc);
8717 seq = WLAN_GET_SEQ_SEQ(sc);
8718 //cosa add 04292008 to record the sequence number
8719 pcurrent_stats->Seq_Num = seq;
8720 //
8721 // Check whether we should take the previous packet into accounting
8722 //
8723 if(!pprevious_stats->bIsAMPDU)
8724 {
8725 // if previous packet is not aggregated packet
8726 bcheck = true;
8727 }else
8728 {
8729 #if 0
8730 // if previous packet is aggregated packet, and current packet
8731 // (1) is not AMPDU
8732 // (2) is the first packet of one AMPDU
8733 // that means the previous packet is the last one aggregated packet
8734 if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU)
8735 bcheck = true;
8736 #endif
8737 }
8738
8739
8740 if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX)
8741 {
8742 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
8743 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
8744 priv->stats.slide_rssi_total -= last_rssi;
8745 }
8746 priv->stats.slide_rssi_total += pprevious_stats->SignalStrength;
8747
8748 priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength;
8749 if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
8750 slide_rssi_index = 0;
8751
8752 // <1> Showed on UI for user, in dbm
8753 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
8754 priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val);
8755 pcurrent_stats->rssi = priv->stats.signal_strength;
8756 //
8757 // If the previous packet does not match the criteria, neglect it
8758 //
8759 if(!pprevious_stats->bPacketMatchBSSID)
8760 {
8761 if(!pprevious_stats->bToSelfBA)
8762 return;
8763 }
8764
8765 if(!bcheck)
8766 return;
8767
8768
8769 //rtl8190_process_cck_rxpathsel(priv,pprevious_stats);//only rtl8190 supported
8770
8771 //
8772 // Check RSSI
8773 //
8774 priv->stats.num_process_phyinfo++;
8775
8776 /* record the general signal strength to the sliding window. */
8777
8778
8779 // <2> Showed on UI for engineering
8780 // hardware does not provide rssi information for each rf path in CCK
8781 if(!pprevious_stats->bIsCCK && (pprevious_stats->bPacketToSelf || pprevious_stats->bToSelfBA))
8782 {
8783 for (rfpath = RF90_PATH_A; rfpath < priv->NumTotalRFPath; rfpath++)
8784 {
8785 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath))
8786 continue;
8787
8788 //Fixed by Jacken 2008-03-20
8789 if(priv->stats.rx_rssi_percentage[rfpath] == 0)
8790 {
8791 priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath];
8792 //DbgPrint("MIMO RSSI initialize \n");
8793 }
8794 if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath])
8795 {
8796 priv->stats.rx_rssi_percentage[rfpath] =
8797 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
8798 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
8799 priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1;
8800 }
8801 else
8802 {
8803 priv->stats.rx_rssi_percentage[rfpath] =
8804 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
8805 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
8806 }
8807 RT_TRACE(COMP_DBG,"priv->stats.rx_rssi_percentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] );
8808 }
8809 }
8810
8811
8812 //
8813 // Check PWDB.
8814 //
8815 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
8816 pprevious_stats->bIsCCK? "CCK": "OFDM",
8817 pprevious_stats->RxPWDBAll);
8818
8819 if(pprevious_stats->bPacketBeacon)
8820 {
8821/* record the beacon pwdb to the sliding window. */
8822 if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX)
8823 {
8824 slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX;
8825 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index];
8826 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
8827 //DbgPrint("slide_beacon_adc_pwdb_index = %d, last_beacon_adc_pwdb = %d, Adapter->RxStats.Slide_Beacon_Total = %d\n",
8828 // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total);
8829 }
8830 priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll;
8831 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll;
8832 //DbgPrint("slide_beacon_adc_pwdb_index = %d, pPreviousRfd->Status.RxPWDBAll = %d\n", slide_beacon_adc_pwdb_index, pPreviousRfd->Status.RxPWDBAll);
8833 slide_beacon_adc_pwdb_index++;
8834 if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
8835 slide_beacon_adc_pwdb_index = 0;
8836 pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics;
8837 if(pprevious_stats->RxPWDBAll >= 3)
8838 pprevious_stats->RxPWDBAll -= 3;
8839 }
8840
8841 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
8842 pprevious_stats->bIsCCK? "CCK": "OFDM",
8843 pprevious_stats->RxPWDBAll);
8844
8845
8846 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
8847 {
8848 if(priv->undecorated_smoothed_pwdb < 0) // initialize
8849 {
8850 priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll;
8851 //DbgPrint("First pwdb initialize \n");
8852 }
8853#if 1
8854 if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb)
8855 {
8856 priv->undecorated_smoothed_pwdb =
8857 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
8858 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
8859 priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1;
8860 }
8861 else
8862 {
8863 priv->undecorated_smoothed_pwdb =
8864 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
8865 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
8866 }
8867#else
8868 //Fixed by Jacken 2008-03-20
8869 if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB)
8870 {
8871 pHalData->UndecoratedSmoothedPWDB =
8872 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
8873 pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1;
8874 }
8875 else
8876 {
8877 pHalData->UndecoratedSmoothedPWDB =
8878 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
8879 }
8880#endif
8881
8882 }
8883
8884 //
8885 // Check EVM
8886 //
8887 /* record the general EVM to the sliding window. */
8888 if(pprevious_stats->SignalQuality == 0)
8889 {
8890 }
8891 else
8892 {
8893 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){
8894 if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){
8895 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
8896 last_evm = priv->stats.slide_evm[slide_evm_index];
8897 priv->stats.slide_evm_total -= last_evm;
8898 }
8899
8900 priv->stats.slide_evm_total += pprevious_stats->SignalQuality;
8901
8902 priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality;
8903 if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
8904 slide_evm_index = 0;
8905
8906 // <1> Showed on UI for user, in percentage.
8907 tmp_val = priv->stats.slide_evm_total/slide_evm_statistics;
8908 priv->stats.signal_quality = tmp_val;
8909 //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality.
8910 priv->stats.last_signal_strength_inpercent = tmp_val;
8911 }
8912
8913 // <2> Showed on UI for engineering
8914 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
8915 {
8916 for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream
8917 {
8918 if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1)
8919 {
8920 if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize
8921 {
8922 priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream];
8923 }
8924 priv->stats.rx_evm_percentage[nspatial_stream] =
8925 ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) +
8926 (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor);
8927 }
8928 }
8929 }
8930 }
8931
8932
8933}
8934
8935/*-----------------------------------------------------------------------------
8936 * Function: rtl819x_query_rxpwrpercentage()
8937 *
8938 * Overview:
8939 *
8940 * Input: char antpower
8941 *
8942 * Output: NONE
8943 *
8944 * Return: 0-100 percentage
8945 *
8946 * Revised History:
8947 * When Who Remark
8948 * 05/26/2008 amy Create Version 0 porting from windows code.
8949 *
8950 *---------------------------------------------------------------------------*/
8951static u8 rtl819x_query_rxpwrpercentage(
8952 char antpower
8953 )
8954{
8955 if ((antpower <= -100) || (antpower >= 20))
8956 {
8957 return 0;
8958 }
8959 else if (antpower >= 0)
8960 {
8961 return 100;
8962 }
8963 else
8964 {
8965 return (100+antpower);
8966 }
8967
8968} /* QueryRxPwrPercentage */
8969
8970static u8
8971rtl819x_evm_dbtopercentage(
8972 char value
8973 )
8974{
8975 char ret_val;
8976
8977 ret_val = value;
8978
8979 if(ret_val >= 0)
8980 ret_val = 0;
8981 if(ret_val <= -33)
8982 ret_val = -33;
8983 ret_val = 0 - ret_val;
8984 ret_val*=3;
8985 if(ret_val == 99)
8986 ret_val = 100;
8987 return(ret_val);
8988}
8989//
8990// Description:
8991// We want good-looking for signal strength/quality
8992// 2007/7/19 01:09, by cosa.
8993//
8994long
8995rtl819x_signal_scale_mapping(
8996 long currsig
8997 )
8998{
8999 long retsig;
9000
9001 // Step 1. Scale mapping.
9002 if(currsig >= 61 && currsig <= 100)
9003 {
9004 retsig = 90 + ((currsig - 60) / 4);
9005 }
9006 else if(currsig >= 41 && currsig <= 60)
9007 {
9008 retsig = 78 + ((currsig - 40) / 2);
9009 }
9010 else if(currsig >= 31 && currsig <= 40)
9011 {
9012 retsig = 66 + (currsig - 30);
9013 }
9014 else if(currsig >= 21 && currsig <= 30)
9015 {
9016 retsig = 54 + (currsig - 20);
9017 }
9018 else if(currsig >= 5 && currsig <= 20)
9019 {
9020 retsig = 42 + (((currsig - 5) * 2) / 3);
9021 }
9022 else if(currsig == 4)
9023 {
9024 retsig = 36;
9025 }
9026 else if(currsig == 3)
9027 {
9028 retsig = 27;
9029 }
9030 else if(currsig == 2)
9031 {
9032 retsig = 18;
9033 }
9034 else if(currsig == 1)
9035 {
9036 retsig = 9;
9037 }
9038 else
9039 {
9040 retsig = currsig;
9041 }
9042
9043 return retsig;
9044}
9045
9046#ifdef RTL8192SU
9047/*-----------------------------------------------------------------------------
9048 * Function: QueryRxPhyStatus8192S()
9049 *
9050 * Overview:
9051 *
9052 * Input: NONE
9053 *
9054 * Output: NONE
9055 *
9056 * Return: NONE
9057 *
9058 * Revised History:
9059 * When Who Remark
9060 * 06/01/2007 MHC Create Version 0.
9061 * 06/05/2007 MHC Accordign to HW's new data sheet, we add CCK and OFDM
9062 * descriptor definition.
9063 * 07/04/2007 MHC According to Jerry and Bryant's document. We read
9064 * ir_isolation and ext_lna for RF's init value and use
9065 * to compensate RSSI after receiving packets.
9066 * 09/10/2008 MHC Modify name and PHY status field for 92SE.
9067 * 09/19/2008 MHC Add CCK/OFDM SS/SQ for 92S series.
9068 *
9069 *---------------------------------------------------------------------------*/
9070static void rtl8192SU_query_rxphystatus(
9071 struct r8192_priv * priv,
9072 struct ieee80211_rx_stats * pstats,
9073 rx_desc_819x_usb *pDesc,
9074 rx_drvinfo_819x_usb * pdrvinfo,
9075 struct ieee80211_rx_stats * precord_stats,
9076 bool bpacket_match_bssid,
9077 bool bpacket_toself,
9078 bool bPacketBeacon,
9079 bool bToSelfBA
9080 )
9081{
9082 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
9083 //PHY_STS_CCK_8192S_T *pCck_buf;
9084 phy_sts_cck_819xusb_t * pcck_buf;
9085 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
9086 //u8 *prxpkt;
9087 //u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
9088 u8 i, max_spatial_stream, rxsc_sgien_exflg;
9089 char rx_pwr[4], rx_pwr_all=0;
9090 //long rx_avg_pwr = 0;
9091 //char rx_snrX, rx_evmX;
9092 u8 evm, pwdb_all;
9093 u32 RSSI, total_rssi=0;//, total_evm=0;
9094// long signal_strength_index = 0;
9095 u8 is_cck_rate=0;
9096 u8 rf_rx_num = 0;
9097
9098
9099
9100 priv->stats.numqry_phystatus++;
9101
9102 is_cck_rate = rx_hal_is_cck_rate(pDesc);
9103
9104 // Record it for next packet processing
9105 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
9106 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
9107 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
9108 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
9109 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
9110 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
9111
9112#ifndef RTL8192SU
9113 phy_sts_ofdm_819xusb_t* pofdm_buf = NULL;
9114 prxpkt = (u8*)pdrvinfo;
9115
9116 /* Move pointer to the 16th bytes. Phy status start address. */
9117 prxpkt += sizeof(rx_drvinfo_819x_usb);
9118
9119 /* Initial the cck and ofdm buffer pointer */
9120 pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt;
9121 pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt;
9122#endif
9123
9124 pstats->RxMIMOSignalQuality[0] = -1;
9125 pstats->RxMIMOSignalQuality[1] = -1;
9126 precord_stats->RxMIMOSignalQuality[0] = -1;
9127 precord_stats->RxMIMOSignalQuality[1] = -1;
9128
9129 if(is_cck_rate)
9130 {
9131 u8 report;//, tmp_pwdb;
9132 //char cck_adc_pwdb[4];
9133
9134 // CCK Driver info Structure is not the same as OFDM packet.
9135 pcck_buf = (phy_sts_cck_819xusb_t *)pdrvinfo;
9136
9137 //
9138 // (1)Hardware does not provide RSSI for CCK
9139 //
9140
9141 //
9142 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
9143 //
9144
9145 priv->stats.numqry_phystatusCCK++;
9146
9147 if(!priv->bCckHighPower)
9148 {
9149 report = pcck_buf->cck_agc_rpt & 0xc0;
9150 report = report>>6;
9151 switch(report)
9152 {
9153 //Fixed by Jacken from Bryant 2008-03-20
9154 //Original value is -38 , -26 , -14 , -2
9155 //Fixed value is -35 , -23 , -11 , 6
9156 case 0x3:
9157 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
9158 break;
9159 case 0x2:
9160 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
9161 break;
9162 case 0x1:
9163 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
9164 break;
9165 case 0x0:
9166 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);//6->8
9167 break;
9168 }
9169 }
9170 else
9171 {
9172 report = pdrvinfo->cfosho[0] & 0x60;
9173 report = report>>5;
9174 switch(report)
9175 {
9176 case 0x3:
9177 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
9178 break;
9179 case 0x2:
9180 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
9181 break;
9182 case 0x1:
9183 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
9184 break;
9185 case 0x0:
9186 rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;//6->-8
9187 break;
9188 }
9189 }
9190
9191 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);//check it
9192 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
9193 //pstats->RecvSignalPower = pwdb_all;
9194 pstats->RecvSignalPower = rx_pwr_all;
9195
9196 //
9197 // (3) Get Signal Quality (EVM)
9198 //
9199 //if(bpacket_match_bssid)
9200 {
9201 u8 sq;
9202
9203 if(pstats->RxPWDBAll > 40)
9204 {
9205 sq = 100;
9206 }else
9207 {
9208 sq = pcck_buf->sq_rpt;
9209
9210 if(pcck_buf->sq_rpt > 64)
9211 sq = 0;
9212 else if (pcck_buf->sq_rpt < 20)
9213 sq = 100;
9214 else
9215 sq = ((64-sq) * 100) / 44;
9216 }
9217 pstats->SignalQuality = precord_stats->SignalQuality = sq;
9218 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
9219 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
9220 }
9221 }
9222 else
9223 {
9224 priv->stats.numqry_phystatusHT++;
9225
9226 // 2008/09/19 MH For 92S debug, RX RF path always enable!!
9227 priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = TRUE;
9228
9229 //
9230 // (1)Get RSSI for HT rate
9231 //
9232 //for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
9233 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
9234 {
9235 // 2008/01/30 MH we will judge RF RX path now.
9236 if (priv->brfpath_rxenable[i])
9237 rf_rx_num++;
9238 //else
9239 // continue;
9240
9241 //if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
9242 // continue;
9243
9244 //Fixed by Jacken from Bryant 2008-03-20
9245 //Original value is 106
9246 //rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
9247 rx_pwr[i] = ((pdrvinfo->gain_trsw[i]&0x3F)*2) - 110;
9248
9249 /* Translate DBM to percentage. */
9250 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); //check ok
9251 total_rssi += RSSI;
9252 RT_TRACE(COMP_RF, "RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI);
9253
9254 //Get Rx snr value in DB
9255 //tmp_rxsnr = pofdm_buf->rxsnr_X[i];
9256 //rx_snrX = (char)(tmp_rxsnr);
9257 //rx_snrX /= 2;
9258 //priv->stats.rxSNRdB[i] = (long)rx_snrX;
9259 priv->stats.rxSNRdB[i] = (long)(pdrvinfo->rxsnr[i]/2);
9260
9261 /* Translate DBM to percentage. */
9262 //RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
9263 //total_rssi += RSSI;
9264
9265 /* Record Signal Strength for next packet */
9266 //if(bpacket_match_bssid)
9267 {
9268 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
9269 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
9270 }
9271 }
9272
9273
9274 //
9275 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
9276 //
9277 //Fixed by Jacken from Bryant 2008-03-20
9278 //Original value is 106
9279 //rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
9280 rx_pwr_all = (((pdrvinfo->pwdb_all ) >> 1 )& 0x7f) -106;
9281 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
9282
9283 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
9284 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
9285 pstats->RecvSignalPower = rx_pwr_all;
9286
9287 //
9288 // (3)EVM of HT rate
9289 //
9290 //if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
9291 // pdrvinfo->RxRate<=DESC90_RATEMCS15)
9292 if(pDesc->RxHT && pDesc->RxMCS>=DESC92S_RATEMCS8 &&
9293 pDesc->RxMCS<=DESC92S_RATEMCS15)
9294 max_spatial_stream = 2; //both spatial stream make sense
9295 else
9296 max_spatial_stream = 1; //only spatial stream 1 makes sense
9297
9298 for(i=0; i<max_spatial_stream; i++)
9299 {
9300 //tmp_rxevm = pofdm_buf->rxevm_X[i];
9301 //rx_evmX = (char)(tmp_rxevm);
9302
9303 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
9304 // fill most significant bit to "zero" when doing shifting operation which may change a negative
9305 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
9306 //rx_evmX /= 2; //dbm
9307
9308 //evm = rtl819x_evm_dbtopercentage(rx_evmX);
9309 evm = rtl819x_evm_dbtopercentage( (pdrvinfo->rxevm[i] /*/ 2*/)); //dbm
9310 RT_TRACE(COMP_RF, "RXRATE=%x RXEVM=%x EVM=%s%d\n", pDesc->RxMCS, pdrvinfo->rxevm[i], "%", evm);
9311#if 0
9312 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100//=====>from here
9313#endif
9314
9315 //if(bpacket_match_bssid)
9316 {
9317 if(i==0) // Fill value in RFD, Get the first spatial stream only
9318 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
9319 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
9320 }
9321 }
9322
9323
9324 /* record rx statistics for debug */
9325 //rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
9326 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
9327 //if(pdrvinfo->BW) //40M channel
9328 if(pDesc->BW) //40M channel
9329 priv->stats.received_bwtype[1+pdrvinfo->rxsc]++;
9330 else //20M channel
9331 priv->stats.received_bwtype[0]++;
9332 }
9333
9334 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
9335 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
9336 if(is_cck_rate)
9337 {
9338 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;//check ok
9339
9340 }
9341 else
9342 {
9343 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
9344 // We can judge RX path number now.
9345 if (rf_rx_num != 0)
9346 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
9347 }
9348}/* QueryRxPhyStatus8192S */
9349#else
9350static void rtl8192_query_rxphystatus(
9351 struct r8192_priv * priv,
9352 struct ieee80211_rx_stats * pstats,
9353 rx_drvinfo_819x_usb * pdrvinfo,
9354 struct ieee80211_rx_stats * precord_stats,
9355 bool bpacket_match_bssid,
9356 bool bpacket_toself,
9357 bool bPacketBeacon,
9358 bool bToSelfBA
9359 )
9360{
9361 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
9362 phy_sts_ofdm_819xusb_t* pofdm_buf;
9363 phy_sts_cck_819xusb_t * pcck_buf;
9364 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
9365 u8 *prxpkt;
9366 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
9367 char rx_pwr[4], rx_pwr_all=0;
9368 //long rx_avg_pwr = 0;
9369 char rx_snrX, rx_evmX;
9370 u8 evm, pwdb_all;
9371 u32 RSSI, total_rssi=0;//, total_evm=0;
9372// long signal_strength_index = 0;
9373 u8 is_cck_rate=0;
9374 u8 rf_rx_num = 0;
9375
9376
9377 priv->stats.numqry_phystatus++;
9378
9379 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
9380
9381 // Record it for next packet processing
9382 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
9383 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
9384 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
9385 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
9386 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
9387 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
9388
9389 prxpkt = (u8*)pdrvinfo;
9390
9391 /* Move pointer to the 16th bytes. Phy status start address. */
9392 prxpkt += sizeof(rx_drvinfo_819x_usb);
9393
9394 /* Initial the cck and ofdm buffer pointer */
9395 pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt;
9396 pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt;
9397
9398 pstats->RxMIMOSignalQuality[0] = -1;
9399 pstats->RxMIMOSignalQuality[1] = -1;
9400 precord_stats->RxMIMOSignalQuality[0] = -1;
9401 precord_stats->RxMIMOSignalQuality[1] = -1;
9402
9403 if(is_cck_rate)
9404 {
9405 //
9406 // (1)Hardware does not provide RSSI for CCK
9407 //
9408
9409 //
9410 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
9411 //
9412 u8 report;//, cck_agc_rpt;
9413
9414 priv->stats.numqry_phystatusCCK++;
9415
9416 if(!priv->bCckHighPower)
9417 {
9418 report = pcck_buf->cck_agc_rpt & 0xc0;
9419 report = report>>6;
9420 switch(report)
9421 {
9422 //Fixed by Jacken from Bryant 2008-03-20
9423 //Original value is -38 , -26 , -14 , -2
9424 //Fixed value is -35 , -23 , -11 , 6
9425 case 0x3:
9426 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
9427 break;
9428 case 0x2:
9429 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
9430 break;
9431 case 0x1:
9432 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
9433 break;
9434 case 0x0:
9435 rx_pwr_all = 6 - (pcck_buf->cck_agc_rpt & 0x3e);
9436 break;
9437 }
9438 }
9439 else
9440 {
9441 report = pcck_buf->cck_agc_rpt & 0x60;
9442 report = report>>5;
9443 switch(report)
9444 {
9445 case 0x3:
9446 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
9447 break;
9448 case 0x2:
9449 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
9450 break;
9451 case 0x1:
9452 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
9453 break;
9454 case 0x0:
9455 rx_pwr_all = 6 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
9456 break;
9457 }
9458 }
9459
9460 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
9461 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
9462 pstats->RecvSignalPower = pwdb_all;
9463
9464 //
9465 // (3) Get Signal Quality (EVM)
9466 //
9467 //if(bpacket_match_bssid)
9468 {
9469 u8 sq;
9470
9471 if(pstats->RxPWDBAll > 40)
9472 {
9473 sq = 100;
9474 }else
9475 {
9476 sq = pcck_buf->sq_rpt;
9477
9478 if(pcck_buf->sq_rpt > 64)
9479 sq = 0;
9480 else if (pcck_buf->sq_rpt < 20)
9481 sq = 100;
9482 else
9483 sq = ((64-sq) * 100) / 44;
9484 }
9485 pstats->SignalQuality = precord_stats->SignalQuality = sq;
9486 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
9487 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
9488 }
9489 }
9490 else
9491 {
9492 priv->stats.numqry_phystatusHT++;
9493 //
9494 // (1)Get RSSI for HT rate
9495 //
9496 for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
9497 {
9498 // 2008/01/30 MH we will judge RF RX path now.
9499 if (priv->brfpath_rxenable[i])
9500 rf_rx_num++;
9501 else
9502 continue;
9503
9504 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
9505 continue;
9506
9507 //Fixed by Jacken from Bryant 2008-03-20
9508 //Original value is 106
9509 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
9510
9511 //Get Rx snr value in DB
9512 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
9513 rx_snrX = (char)(tmp_rxsnr);
9514 //rx_snrX >>= 1;;
9515 rx_snrX /= 2;
9516 priv->stats.rxSNRdB[i] = (long)rx_snrX;
9517
9518 /* Translate DBM to percentage. */
9519 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
9520 total_rssi += RSSI;
9521
9522 /* Record Signal Strength for next packet */
9523 //if(bpacket_match_bssid)
9524 {
9525 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
9526 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
9527 }
9528 }
9529
9530
9531 //
9532 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
9533 //
9534 //Fixed by Jacken from Bryant 2008-03-20
9535 //Original value is 106
9536 rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
9537 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
9538
9539 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
9540 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
9541
9542 //
9543 // (3)EVM of HT rate
9544 //
9545 if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
9546 pdrvinfo->RxRate<=DESC90_RATEMCS15)
9547 max_spatial_stream = 2; //both spatial stream make sense
9548 else
9549 max_spatial_stream = 1; //only spatial stream 1 makes sense
9550
9551 for(i=0; i<max_spatial_stream; i++)
9552 {
9553 tmp_rxevm = pofdm_buf->rxevm_X[i];
9554 rx_evmX = (char)(tmp_rxevm);
9555
9556 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
9557 // fill most significant bit to "zero" when doing shifting operation which may change a negative
9558 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
9559 rx_evmX /= 2; //dbm
9560
9561 evm = rtl819x_evm_dbtopercentage(rx_evmX);
9562#if 0
9563 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100
9564#endif
9565 //if(bpacket_match_bssid)
9566 {
9567 if(i==0) // Fill value in RFD, Get the first spatial stream only
9568 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
9569 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
9570 }
9571 }
9572
9573
9574 /* record rx statistics for debug */
9575 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
9576 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
9577 if(pdrvinfo->BW) //40M channel
9578 priv->stats.received_bwtype[1+prxsc->rxsc]++;
9579 else //20M channel
9580 priv->stats.received_bwtype[0]++;
9581 }
9582
9583 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
9584 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
9585 if(is_cck_rate)
9586 {
9587 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;
9588
9589 }
9590 else
9591 {
9592 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
9593 // We can judge RX path number now.
9594 if (rf_rx_num != 0)
9595 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
9596 }
9597} /* QueryRxPhyStatus8190Pci */
9598#endif
9599
9600void
9601rtl8192_record_rxdesc_forlateruse(
9602 struct ieee80211_rx_stats * psrc_stats,
9603 struct ieee80211_rx_stats * ptarget_stats
9604)
9605{
9606 ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU;
9607 ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU;
9608 ptarget_stats->Seq_Num = psrc_stats->Seq_Num;
9609}
9610
9611#ifdef RTL8192SU
9612static void rtl8192SU_query_rxphystatus(
9613 struct r8192_priv * priv,
9614 struct ieee80211_rx_stats * pstats,
9615 rx_desc_819x_usb *pDesc,
9616 rx_drvinfo_819x_usb * pdrvinfo,
9617 struct ieee80211_rx_stats * precord_stats,
9618 bool bpacket_match_bssid,
9619 bool bpacket_toself,
9620 bool bPacketBeacon,
9621 bool bToSelfBA
9622 );
9623void rtl8192SU_TranslateRxSignalStuff(struct sk_buff *skb,
9624 struct ieee80211_rx_stats * pstats,
9625 rx_desc_819x_usb *pDesc,
9626 rx_drvinfo_819x_usb *pdrvinfo)
9627{
9628 // TODO: We must only check packet for current MAC address. Not finish
9629 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
9630 struct net_device *dev=info->dev;
9631 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9632 bool bpacket_match_bssid, bpacket_toself;
9633 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
9634 static struct ieee80211_rx_stats previous_stats;
9635 struct ieee80211_hdr_3addr *hdr;//by amy
9636 u16 fc,type;
9637
9638 // Get Signal Quality for only RX data queue (but not command queue)
9639
9640 u8* tmp_buf;
9641 //u16 tmp_buf_len = 0;
9642 u8 *praddr;
9643
9644 /* Get MAC frame start address. */
9645 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
9646
9647 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
9648 fc = le16_to_cpu(hdr->frame_ctl);
9649 type = WLAN_FC_GET_TYPE(fc);
9650 praddr = hdr->addr1;
9651
9652 /* Check if the received packet is acceptabe. */
9653 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
9654 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
9655 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
9656 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
9657
9658#if 1//cosa
9659 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
9660 {
9661 bPacketBeacon = true;
9662 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
9663 }
9664 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
9665 {
9666 if((eqMacAddr(praddr,dev->dev_addr)))
9667 bToSelfBA = true;
9668 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
9669 }
9670
9671#endif
9672
9673
9674 if(bpacket_match_bssid)
9675 {
9676 priv->stats.numpacket_matchbssid++;
9677 }
9678 if(bpacket_toself){
9679 priv->stats.numpacket_toself++;
9680 }
9681 //
9682 // Process PHY information for previous packet (RSSI/PWDB/EVM)
9683 //
9684 // Because phy information is contained in the last packet of AMPDU only, so driver
9685 // should process phy information of previous packet
9686 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
9687 rtl8192SU_query_rxphystatus(priv, pstats, pDesc, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
9688 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
9689
9690}
9691#else
9692void TranslateRxSignalStuff819xUsb(struct sk_buff *skb,
9693 struct ieee80211_rx_stats * pstats,
9694 rx_drvinfo_819x_usb *pdrvinfo)
9695{
9696 // TODO: We must only check packet for current MAC address. Not finish
9697 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
9698 struct net_device *dev=info->dev;
9699 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9700 bool bpacket_match_bssid, bpacket_toself;
9701 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
9702 static struct ieee80211_rx_stats previous_stats;
9703 struct ieee80211_hdr_3addr *hdr;//by amy
9704 u16 fc,type;
9705
9706 // Get Signal Quality for only RX data queue (but not command queue)
9707
9708 u8* tmp_buf;
9709 //u16 tmp_buf_len = 0;
9710 u8 *praddr;
9711
9712 /* Get MAC frame start address. */
9713 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
9714
9715 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
9716 fc = le16_to_cpu(hdr->frame_ctl);
9717 type = WLAN_FC_GET_TYPE(fc);
9718 praddr = hdr->addr1;
9719
9720 /* Check if the received packet is acceptabe. */
9721 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
9722 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
9723 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
9724 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
9725
9726#if 1//cosa
9727 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
9728 {
9729 bPacketBeacon = true;
9730 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
9731 }
9732 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
9733 {
9734 if((eqMacAddr(praddr,dev->dev_addr)))
9735 bToSelfBA = true;
9736 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
9737 }
9738
9739#endif
9740
9741
9742 if(bpacket_match_bssid)
9743 {
9744 priv->stats.numpacket_matchbssid++;
9745 }
9746 if(bpacket_toself){
9747 priv->stats.numpacket_toself++;
9748 }
9749 //
9750 // Process PHY information for previous packet (RSSI/PWDB/EVM)
9751 //
9752 // Because phy information is contained in the last packet of AMPDU only, so driver
9753 // should process phy information of previous packet
9754 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
9755 rtl8192_query_rxphystatus(priv, pstats, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
9756 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
9757
9758}
9759#endif
9760
9761/**
9762* Function: UpdateReceivedRateHistogramStatistics
9763* Overview: Recored down the received data rate
9764*
9765* Input:
9766* struct net_device *dev
9767* struct ieee80211_rx_stats *stats
9768*
9769* Output:
9770*
9771* (priv->stats.ReceivedRateHistogram[] is updated)
9772* Return:
9773* None
9774*/
9775void
9776UpdateReceivedRateHistogramStatistics8190(
9777 struct net_device *dev,
9778 struct ieee80211_rx_stats *stats
9779 )
9780{
9781 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9782 u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV
9783 u32 rateIndex;
9784 u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI
9785
9786
9787 if(stats->bCRC)
9788 rcvType = 2;
9789 else if(stats->bICV)
9790 rcvType = 3;
9791
9792 if(stats->bShortPreamble)
9793 preamble_guardinterval = 1;// short
9794 else
9795 preamble_guardinterval = 0;// long
9796
9797 switch(stats->rate)
9798 {
9799 //
9800 // CCK rate
9801 //
9802 case MGN_1M: rateIndex = 0; break;
9803 case MGN_2M: rateIndex = 1; break;
9804 case MGN_5_5M: rateIndex = 2; break;
9805 case MGN_11M: rateIndex = 3; break;
9806 //
9807 // Legacy OFDM rate
9808 //
9809 case MGN_6M: rateIndex = 4; break;
9810 case MGN_9M: rateIndex = 5; break;
9811 case MGN_12M: rateIndex = 6; break;
9812 case MGN_18M: rateIndex = 7; break;
9813 case MGN_24M: rateIndex = 8; break;
9814 case MGN_36M: rateIndex = 9; break;
9815 case MGN_48M: rateIndex = 10; break;
9816 case MGN_54M: rateIndex = 11; break;
9817 //
9818 // 11n High throughput rate
9819 //
9820 case MGN_MCS0: rateIndex = 12; break;
9821 case MGN_MCS1: rateIndex = 13; break;
9822 case MGN_MCS2: rateIndex = 14; break;
9823 case MGN_MCS3: rateIndex = 15; break;
9824 case MGN_MCS4: rateIndex = 16; break;
9825 case MGN_MCS5: rateIndex = 17; break;
9826 case MGN_MCS6: rateIndex = 18; break;
9827 case MGN_MCS7: rateIndex = 19; break;
9828 case MGN_MCS8: rateIndex = 20; break;
9829 case MGN_MCS9: rateIndex = 21; break;
9830 case MGN_MCS10: rateIndex = 22; break;
9831 case MGN_MCS11: rateIndex = 23; break;
9832 case MGN_MCS12: rateIndex = 24; break;
9833 case MGN_MCS13: rateIndex = 25; break;
9834 case MGN_MCS14: rateIndex = 26; break;
9835 case MGN_MCS15: rateIndex = 27; break;
9836 default: rateIndex = 28; break;
9837 }
9838 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
9839 priv->stats.received_rate_histogram[0][rateIndex]++; //total
9840 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
9841}
9842
9843#ifdef RTL8192SU
9844void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
9845{
9846 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
9847 struct net_device *dev=info->dev;
9848 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9849 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
9850 rx_drvinfo_819x_usb *driver_info = NULL;
9851
9852 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
9853 //PHAL_DATA_8192SUSB pHalData = GET_HAL_DATA(Adapter);
9854 //pu1Byte pDesc = (pu1Byte)pDescIn;
9855 //PRX_DRIVER_INFO_8192S pDrvInfo;
9856
5f53d8ca
JC		 9857 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
9858
9859 if(0)
9860 {
9861 int m = 0;
9862 printk("========================");
9863 for(m=0; m<skb->len; m++){
9864 if((m%32) == 0)
9865 printk("\n");
9866 printk("%2x ",((u8*)skb->data)[m]);
9867 }
9868 printk("\n========================\n");
9869
9870 }
9871
9872
9873 //
9874 //Get Rx Descriptor Raw Information
9875 //
9876 stats->Length = desc->Length ;
9877 stats->RxDrvInfoSize = desc->RxDrvInfoSize*RX_DRV_INFO_SIZE_UNIT;
9878 stats->RxBufShift = (desc->Shift)&0x03;
9879 stats->bICV = desc->ICV;
9880 stats->bCRC = desc->CRC32;
9881 stats->bHwError = stats->bCRC|stats->bICV;
9882 stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet
9883 stats->bIsAMPDU = (desc->AMSDU==1);
9884 stats->bFirstMPDU = (desc->PAGGR==1) && (desc->FAGGR==1);
9885 stats->bShortPreamble = desc->SPLCP;
9886 stats->RxIs40MHzPacket = (desc->BW==1);
9887 stats->TimeStampLow = desc->TSFL;
9888
9889 if((desc->FAGGR==1) || (desc->PAGGR==1))
9890 {// Rx A-MPDU
9891 RT_TRACE(COMP_RXDESC, "FirstAGGR = %d, PartAggr = %d\n", desc->FAGGR, desc->PAGGR);
9892 }
9893//YJ,test,090310
9894if(stats->bHwError)
9895{
9896 if(stats->bICV)
9897 printk("%s: Receive ICV error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
9898 if(stats->bCRC)
9899 printk("%s: Receive CRC error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
9900}
9901
9902 if(IS_UNDER_11N_AES_MODE(priv->ieee80211))
9903 {
9904 // Always received ICV error packets in AES mode.
9905 // This fixed HW later MIC write bug.
9906 if(stats->bICV && !stats->bCRC)
9907 {
9908 stats->bICV = FALSE;
9909 stats->bHwError = FALSE;
9910 }
9911 }
9912
9913 // Transform HwRate to MRate
9914 if(!stats->bHwError)
9915 //stats->DataRate = HwRateToMRate(
9916 // (BOOLEAN)GET_RX_DESC_RXHT(pDesc),
9917 // (u1Byte)GET_RX_DESC_RXMCS(pDesc),
9918 // (BOOLEAN)GET_RX_DESC_PAGGR(pDesc));
9919 stats->rate = rtl8192SU_HwRateToMRate(desc->RxHT, desc->RxMCS, desc->PAGGR);
9920 else
9921 stats->rate = MGN_1M;
9922
9923 //
9924 // Collect Rx rate/AMPDU/TSFL
9925 //
9926 //UpdateRxdRateHistogramStatistics8192S(Adapter, pRfd);
9927 //UpdateRxAMPDUHistogramStatistics8192S(Adapter, pRfd);
9928 //UpdateRxPktTimeStamp8192S(Adapter, pRfd);
9929 UpdateReceivedRateHistogramStatistics8190(dev, stats);
9930 //UpdateRxAMPDUHistogramStatistics8192S(dev, stats); //FIXLZM
9931 UpdateRxPktTimeStamp8190(dev, stats);
9932
9933 //
9934 // Get PHY Status and RSVD parts.
9935 // <Roger_Notes> It only appears on last aggregated packet.
9936 //
9937 if (desc->PHYStatus)
9938 {
9939 //driver_info = (rx_drvinfo_819x_usb *)(skb->data + RX_DESC_SIZE + stats->RxBufShift);
9940 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
9941 stats->RxBufShift);
9942 if(0)
9943 {
9944 int m = 0;
9945 printk("========================\n");
9946 printk("RX_DESC_SIZE:%d, RxBufShift:%d, RxDrvInfoSize:%d\n",
9947 RX_DESC_SIZE, stats->RxBufShift, stats->RxDrvInfoSize);
9948 for(m=0; m<32; m++){
9949 printk("%2x ",((u8*)driver_info)[m]);
9950 }
9951 printk("\n========================\n");
9952
9953 }
9954
9955 }
9956
9957 //YJ,add,090107
9958 skb_pull(skb, sizeof(rx_desc_819x_usb));
9959 //YJ,add,090107,end
9960
9961 //
9962 // Get Total offset of MPDU Frame Body
9963 //
9964 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
9965 {
9966 stats->bShift = 1;
9967 //YJ,add,090107
9968 skb_pull(skb, stats->RxBufShift + stats->RxDrvInfoSize);
9969 //YJ,add,090107,end
9970 }
9971
9972 //
9973 // Get PHY Status and RSVD parts.
9974 // <Roger_Notes> It only appears on last aggregated packet.
9975 //
9976 if (desc->PHYStatus)
9977 {
9978 rtl8192SU_TranslateRxSignalStuff(skb, stats, desc, driver_info);
9979 }
9980}
9981#else
9982void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
9983{
9984 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
9985 struct net_device *dev=info->dev;
9986 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9987 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
9988 rx_drvinfo_819x_usb *driver_info = NULL;
9989
9990 //
9991 //Get Rx Descriptor Information
9992 //
5f53d8ca
JC		 9993 {
9994 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
9995
9996 stats->Length = desc->Length;
9997 stats->RxDrvInfoSize = desc->RxDrvInfoSize;
9998 stats->RxBufShift = 0;//desc->Shift&0x03;
9999 stats->bICV = desc->ICV;
10000 stats->bCRC = desc->CRC32;
10001 stats->bHwError = stats->bCRC|stats->bICV;
10002 //RTL8190 set this bit to indicate that Hw does not decrypt packet
10003 stats->Decrypted = !desc->SWDec;
10004 }
10005
10006 if((priv->ieee80211->pHTInfo->bCurrentHTSupport == true) && (priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP))
10007 {
10008 stats->bHwError = false;
10009 }
10010 else
10011 {
10012 stats->bHwError = stats->bCRC|stats->bICV;
10013 }
10014
10015 if(stats->Length < 24 || stats->Length > MAX_8192U_RX_SIZE)
10016 stats->bHwError |= 1;
10017 //
10018 //Get Driver Info
10019 //
10020 // TODO: Need to verify it on FGPA platform
10021 //Driver info are written to the RxBuffer following rx desc
10022 if (stats->RxDrvInfoSize != 0) {
10023 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
10024 stats->RxBufShift);
10025 /* unit: 0.5M */
10026 /* TODO */
10027 if(!stats->bHwError){
10028 u8 ret_rate;
10029 ret_rate = HwRateToMRate90(driver_info->RxHT, driver_info->RxRate);
10030 if(ret_rate == 0xff)
10031 {
10032 // Abnormal Case: Receive CRC OK packet with Rx descriptor indicating non supported rate.
10033 // Special Error Handling here, 2008.05.16, by Emily
10034
10035 stats->bHwError = 1;
10036 stats->rate = MGN_1M; //Set 1M rate by default
10037 }else
10038 {
10039 stats->rate = ret_rate;
10040 }
10041 }
10042 else
10043 stats->rate = 0x02;
10044
10045 stats->bShortPreamble = driver_info->SPLCP;
10046
10047
10048 UpdateReceivedRateHistogramStatistics8190(dev, stats);
10049
10050 stats->bIsAMPDU = (driver_info->PartAggr==1);
10051 stats->bFirstMPDU = (driver_info->PartAggr==1) && (driver_info->FirstAGGR==1);
10052#if 0
10053 // TODO: it is debug only. It should be disabled in released driver. 2007.1.12 by Joseph
10054 UpdateRxAMPDUHistogramStatistics8190(Adapter, pRfd);
10055#endif
10056 stats->TimeStampLow = driver_info->TSFL;
10057 // xiong mask it, 070514
10058 //pRfd->Status.TimeStampHigh = PlatformEFIORead4Byte(Adapter, TSFR+4);
10059 // stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
10060
10061 UpdateRxPktTimeStamp8190(dev, stats);
10062
10063 //
10064 // Rx A-MPDU
10065 //
10066 if(driver_info->FirstAGGR==1 || driver_info->PartAggr == 1)
10067 RT_TRACE(COMP_RXDESC, "driver_info->FirstAGGR = %d, driver_info->PartAggr = %d\n",
10068 driver_info->FirstAGGR, driver_info->PartAggr);
10069
10070 }
10071
10072 skb_pull(skb,sizeof(rx_desc_819x_usb));
10073 //
10074 // Get Total offset of MPDU Frame Body
10075 //
10076 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0) {
10077 stats->bShift = 1;
10078 skb_pull(skb,stats->RxBufShift + stats->RxDrvInfoSize);
10079 }
10080
5f53d8ca
JC		 10081 /* for debug 2008.5.29 */
10082#if 0
10083 {
10084 int i;
10085 printk("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
10086 for(i = 0; i < skb->len; i++) {
10087 if(i % 10 == 0) printk("\n");
10088 printk("%02x ", skb->data[i]);
10089 }
10090 printk("\n<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
10091 }
10092#endif
10093
10094 //added by vivi, for MP, 20080108
10095 stats->RxIs40MHzPacket = driver_info->BW;
10096 if(stats->RxDrvInfoSize != 0)
10097 TranslateRxSignalStuff819xUsb(skb, stats, driver_info);
10098
10099}
10100#endif
10101
10102#ifdef RTL8192SU
10103#if 0
10104/*-----------------------------------------------------------------------------
10105 * Function: UpdateRxAMPDUHistogramStatistics8192S
10106 *
10107 * Overview: Recored down the received A-MPDU aggregation size and pkt number
10108 *
10109 * Input: Adapter
10110 *
10111 * Output: Adapter
10112 * (Adapter->RxStats.RxAMPDUSizeHistogram[] is updated)
10113 * (Adapter->RxStats.RxAMPDUNumHistogram[] is updated)
10114 *
10115 * Return: NONE
10116 *
10117 * Revised History:
10118 * When Who Remark
10119 * 09/18/2008 MHC Create Version 0.
10120 *
10121 *---------------------------------------------------------------------------*/
10122static void
10123UpdateRxAMPDUHistogramStatistics8192S(
10124 struct net_device *dev,
10125 struct ieee80211_rx_stats *stats
10126 )
10127{
10128 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
10129 u8 size_index;
10130 u8 num_index;
10131 u16 update_size = 0;
10132 u8 update_num = 0;
10133
10134 if(stats->bIsAMPDU)
10135 {
10136 if(stats->bFirstMPDU)
10137 {
10138 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
10139 {
10140 update_size = stats->nRxAMPDU_Size;
10141 update_num = stats->nRxAMPDU_AggrNum;
10142 }
10143 stats->nRxAMPDU_Size = stats->Length;
10144 stats->nRxAMPDU_AggrNum = 1;
10145 }
10146 else
10147 {
10148 stats->nRxAMPDU_Size += stats->Length;
10149 stats->nRxAMPDU_AggrNum++;
10150 }
10151 }
10152 else
10153 {
10154 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
10155 {
10156 update_size = stats->nRxAMPDU_Size;
10157 update_num = stats->nRxAMPDU_AggrNum;
10158 }
10159 stats->nRxAMPDU_Size = 0;
10160 stats->nRxAMPDU_AggrNum = 0;
10161 }
10162
10163 if(update_size!=0 && update_num!= 0)
10164 {
10165 if(update_size < 4096)
10166 size_index = 0;
10167 else if(update_size < 8192)
10168 size_index = 1;
10169 else if(update_size < 16384)
10170 size_index = 2;
10171 else if(update_size < 32768)
10172 size_index = 3;
10173 else if(update_size < 65536)
10174 size_index = 4;
10175 else
10176 {
10177 RT_TRACE(COMP_RXDESC,
10178 ("UpdateRxAMPDUHistogramStatistics8192S(): A-MPDU too large\n");
10179 }
10180
10181 Adapter->RxStats.RxAMPDUSizeHistogram[size_index]++;
10182
10183 if(update_num < 5)
10184 num_index = 0;
10185 else if(update_num < 10)
10186 num_index = 1;
10187 else if(update_num < 20)
10188 num_index = 2;
10189 else if(update_num < 40)
10190 num_index = 3;
10191 else
10192 num_index = 4;
10193
10194 Adapter->RxStats.RxAMPDUNumHistogram[num_index]++;
10195 }
10196} // UpdateRxAMPDUHistogramStatistics8192S
10197#endif
10198
10199#endif
10200
10201
10202#ifdef RTL8192SU
10203//
10204// Description:
10205// The strarting address of wireless lan header will shift 1 or 2 or 3 or "more" bytes for the following reason :
10206// (1) QoS control : shift 2 bytes
10207// (2) Mesh Network : shift 1 or 3 bytes
10208// (3) RxDriverInfo occupies the front parts of Rx Packets buffer(shift units is in 8Bytes)
10209//
10210// It is because Lextra CPU used by 8186 or 865x series assert exception if the statrting address
10211// of IP header is not double word alignment.
10212// This features is supported in 818xb and 8190 only, but not 818x.
10213//
10214// parameter: PRT_RFD, Pointer of Reeceive frame descriptor which is initialized according to
10215// Rx Descriptor
10216// return value: unsigned int, number of total shifted bytes
10217//
10218// Notes: 2008/06/28, created by Roger
10219//
10220u32 GetRxPacketShiftBytes8192SU(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
10221{
10222 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
10223
10224 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + Status->RxBufShift);
10225}
10226
10227void rtl8192SU_rx_nomal(struct sk_buff* skb)
10228{
10229 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10230 struct net_device *dev=info->dev;
10231 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10232 struct ieee80211_rx_stats stats = {
10233 .signal = 0,
10234 .noise = -98,
10235 .rate = 0,
10236 // .mac_time = jiffies,
10237 .freq = IEEE80211_24GHZ_BAND,
10238 };
10239 u32 rx_pkt_len = 0;
10240 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
10241 bool unicast_packet = false;
10242
5f53d8ca
JC		 10243 //printk("**********skb->len = %d\n", skb->len);
10244 /* 20 is for ps-poll */
10245 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
10246
10247 /* first packet should not contain Rx aggregation header */
10248 rtl8192SU_query_rxdesc_status(skb, &stats, false);
10249 /* TODO */
10250
10251 /* hardware related info */
5f53d8ca
JC		 10252 priv->stats.rxoktotal++; //YJ,test,090108
10253
10254 /* Process the MPDU recevied */
10255 skb_trim(skb, skb->len - 4/*sCrcLng*/);//FIXLZM
10256
10257 rx_pkt_len = skb->len;
10258 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
10259 unicast_packet = false;
10260 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
10261 //TODO
10262 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
10263 //TODO
10264 }else {
10265 /* unicast packet */
10266 unicast_packet = true;
10267 }
10268
10269 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
10270 dev_kfree_skb_any(skb);
10271 } else {
10272 // priv->stats.rxoktotal++; //YJ,test,090108
10273 if(unicast_packet) {
10274 priv->stats.rxbytesunicast += rx_pkt_len;
10275 }
10276 }
10277
10278 //up is firs pkt, follow is next and next
5f53d8ca
JC		 10279 }
10280 else
10281 {
10282 priv->stats.rxurberr++;
10283 printk("actual_length:%d\n", skb->len);
10284 dev_kfree_skb_any(skb);
10285 }
10286
10287}
10288#else
10289u32 GetRxPacketShiftBytes819xUsb(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
10290{
5f53d8ca
JC		 10291 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize
10292 + Status->RxBufShift);
10293}
10294
10295void rtl8192_rx_nomal(struct sk_buff* skb)
10296{
10297 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10298 struct net_device *dev=info->dev;
10299 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10300 struct ieee80211_rx_stats stats = {
10301 .signal = 0,
10302 .noise = -98,
10303 .rate = 0,
10304 // .mac_time = jiffies,
10305 .freq = IEEE80211_24GHZ_BAND,
10306 };
10307 u32 rx_pkt_len = 0;
10308 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
10309 bool unicast_packet = false;
5f53d8ca
JC		 10310
10311 /* 20 is for ps-poll */
10312 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
5f53d8ca
JC		 10313 /* first packet should not contain Rx aggregation header */
10314 query_rxdesc_status(skb, &stats, false);
10315 /* TODO */
10316 /* hardware related info */
5f53d8ca
JC		 10317 /* Process the MPDU recevied */
10318 skb_trim(skb, skb->len - 4/*sCrcLng*/);
10319
10320 rx_pkt_len = skb->len;
10321 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
10322 unicast_packet = false;
10323 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
10324 //TODO
10325 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
10326 //TODO
10327 }else {
10328 /* unicast packet */
10329 unicast_packet = true;
10330 }
10331
10332 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
10333 dev_kfree_skb_any(skb);
10334 } else {
10335 priv->stats.rxoktotal++;
10336 if(unicast_packet) {
10337 priv->stats.rxbytesunicast += rx_pkt_len;
10338 }
10339 }
5f53d8ca
JC		 10340 } else {
10341 priv->stats.rxurberr++;
10342 printk("actual_length:%d\n", skb->len);
10343 dev_kfree_skb_any(skb);
10344 }
10345
10346}
10347
10348#endif
10349
10350void
10351rtl819xusb_process_received_packet(
10352 struct net_device *dev,
10353 struct ieee80211_rx_stats *pstats
10354 )
10355{
10356// bool bfreerfd=false, bqueued=false;
10357 u8* frame;
10358 u16 frame_len=0;
10359 struct r8192_priv *priv = ieee80211_priv(dev);
10360// u8 index = 0;
10361// u8 TID = 0;
10362 //u16 seqnum = 0;
10363 //PRX_TS_RECORD pts = NULL;
10364
10365 // Get shifted bytes of Starting address of 802.11 header. 2006.09.28, by Emily
10366 //porting by amy 080508
10367 pstats->virtual_address += get_rxpacket_shiftbytes_819xusb(pstats);
10368 frame = pstats->virtual_address;
10369 frame_len = pstats->packetlength;
10370#ifdef TODO // by amy about HCT
10371 if(!Adapter->bInHctTest)
10372 CountRxErrStatistics(Adapter, pRfd);
10373#endif
10374 {
10375 #ifdef ENABLE_PS //by amy for adding ps function in future
10376 RT_RF_POWER_STATE rtState;
10377 // When RF is off, we should not count the packet for hw/sw synchronize
10378 // reason, ie. there may be a duration while sw switch is changed and hw
10379 // switch is being changed. 2006.12.04, by shien chang.
10380 Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (u8* )(&rtState));
10381 if (rtState == eRfOff)
10382 {
10383 return;
10384 }
10385 #endif
10386 priv->stats.rxframgment++;
10387
10388 }
10389#ifdef TODO
10390 RmMonitorSignalStrength(Adapter, pRfd);
10391#endif
10392 /* 2007/01/16 MH Add RX command packet handle here. */
10393 /* 2007/03/01 MH We have to release RFD and return if rx pkt is cmd pkt. */
10394 if (rtl819xusb_rx_command_packet(dev, pstats))
10395 {
10396 return;
10397 }
10398
10399#ifdef SW_CRC_CHECK
10400 SwCrcCheck();
10401#endif
10402
10403
10404}
10405
10406void query_rx_cmdpkt_desc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats)
10407{
10408// rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10409// struct net_device *dev=info->dev;
10410// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10411 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
10412// rx_drvinfo_819x_usb *driver_info;
10413
10414 //
10415 //Get Rx Descriptor Information
10416 //
10417 stats->virtual_address = (u8*)skb->data;
10418 stats->Length = desc->Length;
10419 stats->RxDrvInfoSize = 0;
10420 stats->RxBufShift = 0;
10421 stats->packetlength = stats->Length-scrclng;
10422 stats->fraglength = stats->packetlength;
10423 stats->fragoffset = 0;
10424 stats->ntotalfrag = 1;
10425}
10426
10427#ifdef RTL8192SU
10428void rtl8192SU_rx_cmd(struct sk_buff *skb)
10429{
10430 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10431 struct net_device *dev = info->dev;
10432
10433 /* TODO */
10434 struct ieee80211_rx_stats stats = {
10435 .signal = 0,
10436 .noise = -98,
10437 .rate = 0,
10438 // .mac_time = jiffies,
10439 .freq = IEEE80211_24GHZ_BAND,
10440 };
10441
10442 //
10443 // Check buffer length to determine if this is a valid MPDU.
10444 //
10445 if( (skb->len >= sizeof(rx_desc_819x_usb)) && (skb->len <= RX_URB_SIZE) )//&&
10446 //(pHalData->SwChnlInProgress == FALSE))
10447 {
10448 //
10449 // Collection information in Rx descriptor.
10450 //
10451#if 0
10452 pRxDesc = pContext->Buffer;
10453
10454 pRfd->Buffer.VirtualAddress = pContext->Buffer; // 061109, rcnjko, for multi-platform consideration..
10455
10456 pRtRfdStatus->Length = (u2Byte)GET_RX_DESC_PKT_LEN(pRxDesc);
10457 pRtRfdStatus->RxDrvInfoSize = 0;
10458 pRtRfdStatus->RxBufShift = 0;
10459
10460 pRfd->PacketLength = pRfd->Status.Length - sCrcLng;
10461 pRfd->FragLength = pRfd->PacketLength;
10462 pRfd->FragOffset = 0;
10463 pRfd->nTotalFrag = 1;
10464 pRfd->queue_id = PipeIndex;
10465#endif
10466 query_rx_cmdpkt_desc_status(skb,&stats);
10467 // this is to be done by amy 080508 prfd->queue_id = 1;
10468
10469 //
10470 // Process the MPDU recevied.
10471 //
10472 rtl819xusb_process_received_packet(dev,&stats);
10473
10474 dev_kfree_skb_any(skb);
10475 }
10476 else
10477 {
10478 //RTInsertTailListWithCnt(&pAdapter->RfdIdleQueue, &pRfd->List, &pAdapter->NumIdleRfd);
10479 //RT_ASSERT(pAdapter->NumIdleRfd <= pAdapter->NumRfd, ("HalUsbInCommandComplete8192SUsb(): Adapter->NumIdleRfd(%d)\n", pAdapter->NumIdleRfd));
10480 //RT_TRACE(COMP_RECV, DBG_LOUD, ("HalUsbInCommandComplete8192SUsb(): NOT enough Resources!! BufLenUsed(%d), NumIdleRfd(%d)\n",
10481 //pContext->BufLenUsed, pAdapter->NumIdleRfd));
10482 }
10483
10484 //
10485 // Reuse USB_IN_CONTEXT since we had finished processing the
10486 // buffer in USB_IN_CONTEXT.
10487 //
10488 //HalUsbReturnInContext(pAdapter, pContext);
10489
10490 //
10491 // Issue another bulk IN transfer.
10492 //
10493 //HalUsbInMpdu(pAdapter, PipeIndex);
10494
10495 RT_TRACE(COMP_RECV, "<--- HalUsbInCommandComplete8192SUsb()\n");
10496
10497}
10498#else
10499void rtl8192_rx_cmd(struct sk_buff *skb)
10500{
10501 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10502 struct net_device *dev = info->dev;
10503 //int ret;
10504// struct urb *rx_urb = info->urb;
10505 /* TODO */
10506 struct ieee80211_rx_stats stats = {
10507 .signal = 0,
10508 .noise = -98,
10509 .rate = 0,
10510 // .mac_time = jiffies,
10511 .freq = IEEE80211_24GHZ_BAND,
10512 };
10513
10514 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE))
10515 {
10516
10517 query_rx_cmdpkt_desc_status(skb,&stats);
10518 // this is to be done by amy 080508 prfd->queue_id = 1;
10519
10520
10521 //
10522 // Process the command packet received.
10523 //
10524
10525 rtl819xusb_process_received_packet(dev,&stats);
10526
10527 dev_kfree_skb_any(skb);
10528 }
10529 else
10530 ;
10531
10532
10533#if 0
10534 desc = (u32*)(skb->data);
10535 cmd = (desc[0] >> 30) & 0x03;
10536
10537 if(cmd == 0x00) {//beacon interrupt
10538 //send beacon packet
10539 skb = ieee80211_get_beacon(priv->ieee80211);
10540
10541 if(!skb){
10542 DMESG("not enought memory for allocating beacon");
10543 return;
10544 }
10545 skb->cb[0] = BEACON_PRIORITY;
10546 skb->cb[1] = 0;
10547 skb->cb[2] = ieeerate2rtlrate(priv->ieee80211->basic_rate);
10548 ret = rtl8192_tx(dev, skb);
10549
10550 if( ret != 0 ){
10551 printk(KERN_ALERT "tx beacon packet error : %d !\n", ret);
10552 }
10553 dev_kfree_skb_any(skb);
10554 } else {//0x00
10555 //{ log the device information
10556 // At present, It is not implemented just now.
10557 //}
10558 }
10559#endif
10560}
10561#endif
10562
10563void rtl8192_irq_rx_tasklet(struct r8192_priv *priv)
10564{
10565 struct sk_buff *skb;
10566 struct rtl8192_rx_info *info;
10567
10568 while (NULL != (skb = skb_dequeue(&priv->skb_queue))) {
10569 info = (struct rtl8192_rx_info *)skb->cb;
10570 switch (info->out_pipe) {
10571 /* Nomal packet pipe */
10572 case 3:
10573 //RT_TRACE(COMP_RECV, "normal in-pipe index(%d)\n",info->out_pipe);
10574 priv->IrpPendingCount--;
10575 priv->ops->rtl819x_rx_nomal(skb);
10576 break;
10577
10578 /* Command packet pipe */
10579 case 9:
10580 RT_TRACE(COMP_RECV, "command in-pipe index(%d)\n",\
10581 info->out_pipe);
10582 priv->ops->rtl819x_rx_cmd(skb);
10583 break;
10584
10585 default: /* should never get here! */
10586 RT_TRACE(COMP_ERR, "Unknown in-pipe index(%d)\n",\
10587 info->out_pipe);
10588 dev_kfree_skb(skb);
10589 break;
10590
10591 }
10592 }
10593}
10594
10595
10596
10597/****************************************************************************
10598 ---------------------------- USB_STUFF---------------------------
10599*****************************************************************************/
5f53d8ca
JC		 10600//LZM Merge from windows HalUsbSetQueuePipeMapping8192SUsb 090319
10601static void HalUsbSetQueuePipeMapping8192SUsb(struct usb_interface *intf, struct net_device *dev)
10602{
10603 struct r8192_priv *priv = ieee80211_priv(dev);
10604 struct usb_host_interface *iface_desc;
10605 struct usb_endpoint_descriptor *endpoint;
10606 u8 i = 0;
10607
10608 priv->ep_in_num = 0;
10609 priv->ep_out_num = 0;
10610 memset(priv->RtOutPipes,0,16);
10611 memset(priv->RtInPipes,0,16);
10612
5f53d8ca
JC		 10613 iface_desc = intf->cur_altsetting;
10614 priv->ep_num = iface_desc->desc.bNumEndpoints;
10615
10616 for (i = 0; i < priv->ep_num; ++i) {
10617 endpoint = &iface_desc->endpoint[i].desc;
5f53d8ca
JC		 10618 if (usb_endpoint_is_bulk_in(endpoint)) {
10619 priv->RtInPipes[priv->ep_in_num] = usb_endpoint_num(endpoint);
10620 priv->ep_in_num ++;
10621 //printk("in_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
10622 } else if (usb_endpoint_is_bulk_out(endpoint)) {
10623 priv->RtOutPipes[priv->ep_out_num] = usb_endpoint_num(endpoint);
10624 priv->ep_out_num ++;
10625 //printk("out_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
10626 }
5f53d8ca
JC		 10627 }
10628 {
10629 memset(priv->txqueue_to_outpipemap,0,9);
10630 if (priv->ep_num == 6) {
10631 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
10632 u8 queuetopipe[] = {3, 2, 1, 0, 4, 4, 4, 4, 4};
10633
10634 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
10635 } else if (priv->ep_num == 4) {
10636 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
10637 u8 queuetopipe[] = {1, 1, 0, 0, 2, 2, 2, 2, 2};
10638
10639 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
10640 } else if (priv->ep_num > 9) {
10641 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
10642 u8 queuetopipe[] = {3, 2, 1, 0, 4, 8, 7, 6, 5};
10643
10644 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
10645 } else {//use sigle pipe
10646 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
10647 u8 queuetopipe[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
10648 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
10649 }
10650 }
10651 printk("==>ep_num:%d, in_ep_num:%d, out_ep_num:%d\n", priv->ep_num, priv->ep_in_num, priv->ep_out_num);
10652
10653 printk("==>RtInPipes:");
10654 for(i=0; i < priv->ep_in_num; i++)
10655 printk("%d ", priv->RtInPipes[i]);
10656 printk("\n");
10657
10658 printk("==>RtOutPipes:");
10659 for(i=0; i < priv->ep_out_num; i++)
10660 printk("%d ", priv->RtOutPipes[i]);
10661 printk("\n");
10662
10663 printk("==>txqueue_to_outpipemap for BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON:\n");
10664 for(i=0; i < 9; i++)
10665 printk("%d ", priv->txqueue_to_outpipemap[i]);
10666 printk("\n");
5f53d8ca
JC		 10667
10668 return;
10669}
5f53d8ca 10670
77b92881
BZ		 10671static const struct net_device_ops rtl8192_netdev_ops = {
10672 .ndo_open = rtl8192_open,
10673 .ndo_stop = rtl8192_close,
10674 .ndo_get_stats = rtl8192_stats,
10675 .ndo_tx_timeout = tx_timeout,
10676 .ndo_do_ioctl = rtl8192_ioctl,
10677 .ndo_set_multicast_list = r8192_set_multicast,
10678 .ndo_set_mac_address = r8192_set_mac_adr,
10679 .ndo_validate_addr = eth_validate_addr,
10680 .ndo_change_mtu = eth_change_mtu,
ce9c010c 10681 .ndo_start_xmit = rtl8192_ieee80211_xmit,
77b92881
BZ		 10682};
10683
5f53d8ca
JC		 10684static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
10685 const struct usb_device_id *id)
5f53d8ca
JC		 10686{
10687// unsigned long ioaddr = 0;
10688 struct net_device *dev = NULL;
10689 struct r8192_priv *priv= NULL;
5f53d8ca 10690 struct usb_device *udev = interface_to_usbdev(intf);
1ec9e48d 10691
5f53d8ca
JC		 10692 RT_TRACE(COMP_INIT, "Oops: i'm coming\n");
10693
10694 dev = alloc_ieee80211(sizeof(struct r8192_priv));
10695
5f53d8ca
JC		 10696 usb_set_intfdata(intf, dev);
10697 SET_NETDEV_DEV(dev, &intf->dev);
5f53d8ca 10698 priv = ieee80211_priv(dev);
5f53d8ca 10699 priv->ieee80211 = netdev_priv(dev);
5f53d8ca
JC		 10700 priv->udev=udev;
10701
10702#ifdef RTL8192SU
5f53d8ca 10703 HalUsbSetQueuePipeMapping8192SUsb(intf, dev);
5f53d8ca
JC		 10704#endif
10705
10706#ifdef RTL8192SU
10707 //printk("===============>NIC 8192SU\n");
10708 priv->ops = &rtl8192su_ops;
10709#else
10710 //printk("===============>NIC 8192U\n");
10711 priv->ops = &rtl8192u_ops;
10712#endif
10713
77b92881 10714 dev->netdev_ops = &rtl8192_netdev_ops;
5f53d8ca
JC		 10715
10716 //DMESG("Oops: i'm coming\n");
5f53d8ca 10717 dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def;
3bd709f2 10718
5f53d8ca
JC		 10719 dev->type=ARPHRD_ETHER;
10720
10721 dev->watchdog_timeo = HZ*3; //modified by john, 0805
10722
10723 if (dev_alloc_name(dev, ifname) < 0){
10724 RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n");
10725 ifname = "wlan%d";
10726 dev_alloc_name(dev, ifname);
10727 }
10728
10729 RT_TRACE(COMP_INIT, "Driver probe completed1\n");
10730#if 1
10731 if(rtl8192_init(dev)!=0){
10732 RT_TRACE(COMP_ERR, "Initialization failed");
10733 goto fail;
10734 }
10735#endif
10736 netif_carrier_off(dev);
10737 netif_stop_queue(dev);
10738
10739 register_netdev(dev);
10740 RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name);
10741 rtl8192_proc_init_one(dev);
10742
10743
10744 RT_TRACE(COMP_INIT, "Driver probe completed\n");
5f53d8ca 10745 return 0;
5f53d8ca
JC		 10746fail:
10747 free_ieee80211(dev);
10748
10749 RT_TRACE(COMP_ERR, "wlan driver load failed\n");
5f53d8ca 10750 return -ENODEV;
5f53d8ca
JC		 10751}
10752
10753//detach all the work and timer structure declared or inititialize in r8192U_init function.
10754void rtl8192_cancel_deferred_work(struct r8192_priv* priv)
10755{
5f53d8ca
JC		 10756 cancel_work_sync(&priv->reset_wq);
10757 cancel_work_sync(&priv->qos_activate);
10758 cancel_delayed_work(&priv->watch_dog_wq);
10759 cancel_delayed_work(&priv->update_beacon_wq);
10760 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
10761 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
10762 //cancel_work_sync(&priv->SetBWModeWorkItem);
10763 //cancel_work_sync(&priv->SwChnlWorkItem);
5f53d8ca
JC		 10764}
10765
5f53d8ca 10766static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf)
5f53d8ca 10767{
5f53d8ca 10768 struct net_device *dev = usb_get_intfdata(intf);
5f53d8ca
JC		 10769 struct r8192_priv *priv = ieee80211_priv(dev);
10770 if(dev){
10771
10772 unregister_netdev(dev);
10773
10774 RT_TRACE(COMP_DOWN, "=============>wlan driver to be removed\n");
10775 rtl8192_proc_remove_one(dev);
10776
10777 rtl8192_down(dev);
10778 if (priv->pFirmware)
10779 {
10780 vfree(priv->pFirmware);
10781 priv->pFirmware = NULL;
10782 }
10783 // priv->rf_close(dev);
10784// rtl8192_SetRFPowerState(dev, eRfOff);
5f53d8ca 10785 destroy_workqueue(priv->priv_wq);
5f53d8ca
JC		 10786 //rtl8192_irq_disable(dev);
10787 //rtl8192_reset(dev);
10788 mdelay(10);
10789
10790 }
10791 free_ieee80211(dev);
10792 RT_TRACE(COMP_DOWN, "wlan driver removed\n");
10793}
10794
10795static int __init rtl8192_usb_module_init(void)
10796{
10797 printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n");
10798 printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n");
10799 RT_TRACE(COMP_INIT, "Initializing module");
10800 RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT);
10801 rtl8192_proc_module_init();
10802 return usb_register(&rtl8192_usb_driver);
10803}
10804
10805
10806static void __exit rtl8192_usb_module_exit(void)
10807{
10808 usb_deregister(&rtl8192_usb_driver);
10809
10810 RT_TRACE(COMP_DOWN, "Exiting");
10811 rtl8192_proc_module_remove();
10812}
10813
10814
10815void rtl8192_try_wake_queue(struct net_device *dev, int pri)
10816{
10817 unsigned long flags;
10818 short enough_desc;
10819 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10820
10821 spin_lock_irqsave(&priv->tx_lock,flags);
10822 enough_desc = check_nic_enough_desc(dev,pri);
10823 spin_unlock_irqrestore(&priv->tx_lock,flags);
10824
10825 if(enough_desc)
10826 ieee80211_wake_queue(priv->ieee80211);
10827}
10828
10829#if 0
10830void DisableHWSecurityConfig8192SUsb(struct net_device *dev)
10831{
10832 u8 SECR_value = 0x0;
10833 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
10834}
10835#endif
10836
10837void EnableHWSecurityConfig8192(struct net_device *dev)
10838{
10839 u8 SECR_value = 0x0;
10840 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10841 struct ieee80211_device* ieee = priv->ieee80211;
10842
10843 SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;
10844#if 1
10845 if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2))
10846 {
10847 SECR_value |= SCR_RxUseDK;
10848 SECR_value |= SCR_TxUseDK;
10849 }
10850 else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP)))
10851 {
10852 SECR_value |= SCR_RxUseDK;
10853 SECR_value |= SCR_TxUseDK;
10854 }
10855#endif
10856 //add HWSec active enable here.
10857//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4
10858
10859 ieee->hwsec_active = 1;
10860
10861 if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off
10862 {
10863 ieee->hwsec_active = 0;
10864 SECR_value &= ~SCR_RxDecEnable;
10865 }
10866
10867 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, \
10868 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
10869 {
10870 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
10871 }
10872}
10873
10874
10875void setKey( struct net_device *dev,
10876 u8 EntryNo,
10877 u8 KeyIndex,
10878 u16 KeyType,
10879 u8 *MacAddr,
10880 u8 DefaultKey,
10881 u32 *KeyContent )
10882{
10883 u32 TargetCommand = 0;
10884 u32 TargetContent = 0;
10885 u16 usConfig = 0;
10886 u8 i;
10887 if (EntryNo >= TOTAL_CAM_ENTRY)
10888 RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n");
10889
10890 RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr));
10891
10892 if (DefaultKey)
10893 usConfig |= BIT15 | (KeyType<<2);
10894 else
10895 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
10896// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex;
10897
10898
10899 for(i=0 ; i<CAM_CONTENT_COUNT; i++){
10900 TargetCommand = i+CAM_CONTENT_COUNT*EntryNo;
10901 TargetCommand |= BIT31|BIT16;
10902
10903 if(i==0){//MAC|Config
10904 TargetContent = (u32)(*(MacAddr+0)) << 16|
10905 (u32)(*(MacAddr+1)) << 24|
10906 (u32)usConfig;
10907
10908 write_nic_dword(dev, WCAMI, TargetContent);
10909 write_nic_dword(dev, RWCAM, TargetCommand);
10910 // printk("setkey cam =%8x\n", read_cam(dev, i+6*EntryNo));
10911 }
10912 else if(i==1){//MAC
10913 TargetContent = (u32)(*(MacAddr+2)) |
10914 (u32)(*(MacAddr+3)) << 8|
10915 (u32)(*(MacAddr+4)) << 16|
10916 (u32)(*(MacAddr+5)) << 24;
10917 write_nic_dword(dev, WCAMI, TargetContent);
10918 write_nic_dword(dev, RWCAM, TargetCommand);
10919 }
10920 else {
10921 //Key Material
10922 if(KeyContent !=NULL){
10923 write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) );
10924 write_nic_dword(dev, RWCAM, TargetCommand);
10925 }
10926 }
10927 }
10928
10929}
10930
10931/***************************************************************************
10932 ------------------- module init / exit stubs ----------------
10933****************************************************************************/
10934module_init(rtl8192_usb_module_init);
10935module_exit(rtl8192_usb_module_exit);
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