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Staging: rtl8192su: remove kernel version compatibility wrappers
[net-next-2.6.git] / drivers / staging / rtl8192su / r8192U_core.c
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5f53d8ca
JC		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 * Linux device driver for RTL8192U
4 *
5 * Based on the r8187 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Jerry chuang <wlanfae@realtek.com>
25 */
26
27#ifndef CONFIG_FORCE_HARD_FLOAT
28double __floatsidf (int i) { return i; }
29unsigned int __fixunsdfsi (double d) { return d; }
30double __adddf3(double a, double b) { return a+b; }
31double __addsf3(float a, float b) { return a+b; }
32double __subdf3(double a, double b) { return a-b; }
33double __extendsfdf2(float a) {return a;}
34#endif
35
36#undef LOOP_TEST
37#undef DUMP_RX
38#undef DUMP_TX
39#undef DEBUG_TX_DESC2
40#undef RX_DONT_PASS_UL
41#undef DEBUG_EPROM
42#undef DEBUG_RX_VERBOSE
43#undef DUMMY_RX
44#undef DEBUG_ZERO_RX
45#undef DEBUG_RX_SKB
46#undef DEBUG_TX_FRAG
47#undef DEBUG_RX_FRAG
48#undef DEBUG_TX_FILLDESC
49#undef DEBUG_TX
50#undef DEBUG_IRQ
51#undef DEBUG_RX
52#undef DEBUG_RXALLOC
53#undef DEBUG_REGISTERS
54#undef DEBUG_RING
55#undef DEBUG_IRQ_TASKLET
56#undef DEBUG_TX_ALLOC
57#undef DEBUG_TX_DESC
58
59#define CONFIG_RTL8192_IO_MAP
60
61#ifdef RTL8192SU
62#include <asm/uaccess.h>
63#include "r8192U.h"
64//#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
65#include "r8180_93cx6.h" /* Card EEPROM */
66#include "r8192U_wx.h"
67
68#include "r8192S_rtl8225.h"
69#include "r8192S_hw.h"
70#include "r8192S_phy.h"
71#include "r8192S_phyreg.h"
72#include "r8192S_Efuse.h"
73
74#include "r819xU_cmdpkt.h"
75#include "r8192U_dm.h"
76//#include "r8192xU_phyreg.h"
77#include <linux/usb.h>
5f53d8ca
JC		 78
79#ifdef CONFIG_RTL8192_PM
80#include "r8192U_pm.h"
81#endif
82
83#ifdef ENABLE_DOT11D
2a7d71ad 84#include "ieee80211/dot11d.h"
5f53d8ca
JC		 85#endif
86
87#else
88
89#include <asm/uaccess.h>
90#include "r8192U_hw.h"
91#include "r8192U.h"
92#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
93#include "r8180_93cx6.h" /* Card EEPROM */
94#include "r8192U_wx.h"
95#include "r819xU_phy.h" //added by WB 4.30.2008
96#include "r819xU_phyreg.h"
97#include "r819xU_cmdpkt.h"
98#include "r8192U_dm.h"
99//#include "r8192xU_phyreg.h"
100#include <linux/usb.h>
5f53d8ca
JC		 101
102#ifdef CONFIG_RTL8192_PM
103#include "r8192U_pm.h"
104#endif
105
106#ifdef ENABLE_DOT11D
2a7d71ad 107#include "ieee80211/dot11d.h"
5f53d8ca
JC		 108#endif
109
110#endif
111
112
113#ifdef RTL8192SU
114u32 rt_global_debug_component = \
115// COMP_TRACE |
116// COMP_DBG |
117// COMP_INIT |
118// COMP_RECV |
119// COMP_SEND |
120// COMP_IO |
121 COMP_POWER |
122// COMP_EPROM |
123 COMP_SWBW |
124 COMP_POWER_TRACKING |
125 COMP_TURBO |
126 COMP_QOS |
127// COMP_RATE |
128// COMP_RM |
129 COMP_DIG |
130// COMP_EFUSE |
131// COMP_CH |
132// COMP_TXAGC |
133 COMP_HIPWR |
134// COMP_HALDM |
135 COMP_SEC |
136 COMP_LED |
137// COMP_RF |
138// COMP_RXDESC |
139 COMP_FIRMWARE |
140 COMP_HT |
141 COMP_AMSDU |
142 COMP_SCAN |
143// COMP_CMD |
144 COMP_DOWN |
145 COMP_RESET |
146 COMP_ERR; //always open err flags on
147#else
148//set here to open your trace code. //WB
149u32 rt_global_debug_component = \
150 // COMP_INIT |
151// COMP_DBG |
152 // COMP_EPROM |
153// COMP_PHY |
154 // COMP_RF |
155// COMP_FIRMWARE |
156// COMP_CH |
157 // COMP_POWER_TRACKING |
158// COMP_RATE |
159 // COMP_TXAGC |
160 // COMP_TRACE |
161 COMP_DOWN |
162 // COMP_RECV |
163 // COMP_SWBW |
164 COMP_SEC |
165 // COMP_RESET |
166 // COMP_SEND |
167 // COMP_EVENTS |
168 COMP_ERR ; //always open err flags on
169#endif
170
171#define TOTAL_CAM_ENTRY 32
172#define CAM_CONTENT_COUNT 8
173
174static struct usb_device_id rtl8192_usb_id_tbl[] = {
175 /* Realtek */
176 {USB_DEVICE(0x0bda, 0x8192)},
177 {USB_DEVICE(0x0bda, 0x8709)},
178 /* Corega */
179 {USB_DEVICE(0x07aa, 0x0043)},
180 /* Belkin */
181 {USB_DEVICE(0x050d, 0x805E)},
182 /* Sitecom */
183 {USB_DEVICE(0x0df6, 0x0031)},
184 /* EnGenius */
185 {USB_DEVICE(0x1740, 0x9201)},
186 /* Dlink */
187 {USB_DEVICE(0x2001, 0x3301)},
188 /* Zinwell */
189 {USB_DEVICE(0x5a57, 0x0290)},
190 //92SU
191 {USB_DEVICE(0x0bda, 0x8172)},
192 {}
193};
194
195MODULE_LICENSE("GPL");
5f53d8ca 196MODULE_VERSION("V 1.1");
5f53d8ca
JC		 197MODULE_DEVICE_TABLE(usb, rtl8192_usb_id_tbl);
198MODULE_DESCRIPTION("Linux driver for Realtek RTL8192 USB WiFi cards");
199
200static char* ifname = "wlan%d";
201#if 0
202static int hwseqnum = 0;
203static int hwwep = 0;
204#endif
205static int hwwep = 1; //default use hw. set 0 to use software security
206static int channels = 0x3fff;
207
208
209
5f53d8ca
JC		 210module_param(ifname, charp, S_IRUGO|S_IWUSR );
211//module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
212module_param(hwwep,int, S_IRUGO|S_IWUSR);
213module_param(channels,int, S_IRUGO|S_IWUSR);
5f53d8ca
JC		 214
215MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default");
216//MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
217MODULE_PARM_DESC(hwwep," Try to use hardware security support. ");
218MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
219
5f53d8ca
JC		 220static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
221 const struct usb_device_id *id);
222static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf);
5f53d8ca
JC		 223
224static struct usb_driver rtl8192_usb_driver = {
5f53d8ca
JC		 225 .name = RTL819xU_MODULE_NAME, /* Driver name */
226 .id_table = rtl8192_usb_id_tbl, /* PCI_ID table */
227 .probe = rtl8192_usb_probe, /* probe fn */
228 .disconnect = rtl8192_usb_disconnect, /* remove fn */
5f53d8ca
JC		 229#ifdef CONFIG_RTL8192_PM
230 .suspend = rtl8192U_suspend, /* PM suspend fn */
231 .resume = rtl8192U_resume, /* PM resume fn */
5f53d8ca 232 .reset_resume = rtl8192U_resume, /* PM reset resume fn */
5f53d8ca
JC		 233#else
234 .suspend = NULL, /* PM suspend fn */
235 .resume = NULL, /* PM resume fn */
5f53d8ca
JC		 236 .reset_resume = NULL, /* PM reset resume fn */
237#endif
5f53d8ca
JC		 238};
239
240
241#ifdef RTL8192SU
242static void rtl8192SU_read_eeprom_info(struct net_device *dev);
243short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
244void rtl8192SU_rx_nomal(struct sk_buff* skb);
245void rtl8192SU_rx_cmd(struct sk_buff *skb);
246bool rtl8192SU_adapter_start(struct net_device *dev);
247short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
248void rtl8192SU_link_change(struct net_device *dev);
249void InitialGain8192S(struct net_device *dev,u8 Operation);
250void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
251
252struct rtl819x_ops rtl8192su_ops = {
253 .nic_type = NIC_8192SU,
254 .rtl819x_read_eeprom_info = rtl8192SU_read_eeprom_info,
255 .rtl819x_tx = rtl8192SU_tx,
256 .rtl819x_tx_cmd = rtl8192SU_tx_cmd,
257 .rtl819x_rx_nomal = rtl8192SU_rx_nomal,
258 .rtl819x_rx_cmd = rtl8192SU_rx_cmd,
259 .rtl819x_adapter_start = rtl8192SU_adapter_start,
260 .rtl819x_link_change = rtl8192SU_link_change,
261 .rtl819x_initial_gain = InitialGain8192S,
262 .rtl819x_query_rxdesc_status = rtl8192SU_query_rxdesc_status,
263};
264#else
265static void rtl8192_read_eeprom_info(struct net_device *dev);
266short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
267void rtl8192_rx_nomal(struct sk_buff* skb);
268void rtl8192_rx_cmd(struct sk_buff *skb);
269bool rtl8192_adapter_start(struct net_device *dev);
270short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
271void rtl8192_link_change(struct net_device *dev);
272void InitialGain819xUsb(struct net_device *dev,u8 Operation);
273void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
274
275struct rtl819x_ops rtl8192u_ops = {
276 .nic_type = NIC_8192U,
277 .rtl819x_read_eeprom_info = rtl8192_read_eeprom_info,
278 .rtl819x_tx = rtl8192_tx,
279 .rtl819x_tx_cmd = rtl819xU_tx_cmd,
280 .rtl819x_rx_nomal = rtl8192_rx_nomal,
281 .rtl819x_rx_cmd = rtl8192_rx_cmd,
282 .rtl819x_adapter_start = rtl8192_adapter_start,
283 .rtl819x_link_change = rtl8192_link_change,
284 .rtl819x_initial_gain = InitialGain819xUsb,
285 .rtl819x_query_rxdesc_status = query_rxdesc_status,
286};
287#endif
288
289#ifdef ENABLE_DOT11D
290
291typedef struct _CHANNEL_LIST
292{
293 u8 Channel[32];
294 u8 Len;
295}CHANNEL_LIST, *PCHANNEL_LIST;
296
297static CHANNEL_LIST ChannelPlan[] = {
298 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
299 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
300 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
301 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI.
302 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
303 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK
304 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1
305 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel.
306 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC
307 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC
308 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
309};
310
311static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv)
312{
313 int i, max_chan=-1, min_chan=-1;
314 struct ieee80211_device* ieee = priv->ieee80211;
315 switch (channel_plan)
316 {
317 case COUNTRY_CODE_FCC:
318 case COUNTRY_CODE_IC:
319 case COUNTRY_CODE_ETSI:
320 case COUNTRY_CODE_SPAIN:
321 case COUNTRY_CODE_FRANCE:
322 case COUNTRY_CODE_MKK:
323 case COUNTRY_CODE_MKK1:
324 case COUNTRY_CODE_ISRAEL:
325 case COUNTRY_CODE_TELEC:
326 case COUNTRY_CODE_MIC:
327 {
328 Dot11d_Init(ieee);
329 ieee->bGlobalDomain = false;
330 //acturally 8225 & 8256 rf chip only support B,G,24N mode
331 if ((priv->rf_chip == RF_8225) || (priv->rf_chip == RF_8256) || (priv->rf_chip == RF_6052))
332 {
333 min_chan = 1;
334 max_chan = 14;
335 }
336 else
337 {
338 RT_TRACE(COMP_ERR, "unknown rf chip, can't set channel map in function:%s()\n", __FUNCTION__);
339 }
340 if (ChannelPlan[channel_plan].Len != 0){
341 // Clear old channel map
342 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
343 // Set new channel map
344 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
345 {
346 if (ChannelPlan[channel_plan].Channel[i] < min_chan || ChannelPlan[channel_plan].Channel[i] > max_chan)
347 break;
348 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
349 }
350 }
351 break;
352 }
353 case COUNTRY_CODE_GLOBAL_DOMAIN:
354 {
355 GET_DOT11D_INFO(ieee)->bEnabled = 0;//this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain settings.
356 Dot11d_Reset(ieee);
357 ieee->bGlobalDomain = true;
358 break;
359 }
360 default:
361 break;
362 }
363 return;
364}
365#endif
366
367#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
368
369#ifdef RTL8192SU
370#define rx_hal_is_cck_rate(_pDesc)\
371 ((_pDesc->RxMCS == DESC92S_RATE1M ||\
372 _pDesc->RxMCS == DESC92S_RATE2M ||\
373 _pDesc->RxMCS == DESC92S_RATE5_5M ||\
374 _pDesc->RxMCS == DESC92S_RATE11M) &&\
375 !_pDesc->RxHT)
376
377#define tx_hal_is_cck_rate(_DataRate)\
378 ( _DataRate == MGN_1M ||\
379 _DataRate == MGN_2M ||\
380 _DataRate == MGN_5_5M ||\
381 _DataRate == MGN_11M )
382
383#else
384#define rx_hal_is_cck_rate(_pdrvinfo)\
385 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
386 _pdrvinfo->RxRate == DESC90_RATE2M ||\
387 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
388 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
389 !_pdrvinfo->RxHT)
390#endif
391
392
393
394void CamResetAllEntry(struct net_device *dev)
395{
396#if 1
397 u32 ulcommand = 0;
398 //2004/02/11 In static WEP, OID_ADD_KEY or OID_ADD_WEP are set before STA associate to AP.
399 // However, ResetKey is called on OID_802_11_INFRASTRUCTURE_MODE and MlmeAssociateRequest
400 // In this condition, Cam can not be reset because upper layer will not set this static key again.
401 //if(Adapter->EncAlgorithm == WEP_Encryption)
402 // return;
403//debug
404 //DbgPrint("========================================\n");
405 //DbgPrint(" Call ResetAllEntry \n");
406 //DbgPrint("========================================\n\n");
407 ulcommand |= BIT31|BIT30;
408 write_nic_dword(dev, RWCAM, ulcommand);
409#else
410 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
411 CAM_mark_invalid(dev, ucIndex);
412 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
413 CAM_empty_entry(dev, ucIndex);
414#endif
415
416}
417
418
419void write_cam(struct net_device *dev, u8 addr, u32 data)
420{
421 write_nic_dword(dev, WCAMI, data);
422 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) );
423}
424
425u32 read_cam(struct net_device *dev, u8 addr)
426{
427 write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) );
428 return read_nic_dword(dev, 0xa8);
429}
430
431void write_nic_byte_E(struct net_device *dev, int indx, u8 data)
432{
433 int status;
434 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
435 struct usb_device *udev = priv->udev;
436
437 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
438 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
439 indx|0xfe00, 0, &data, 1, HZ / 2);
440
441 if (status < 0)
442 {
443 printk("write_nic_byte_E TimeOut! status:%d\n", status);
444 }
445}
446
447u8 read_nic_byte_E(struct net_device *dev, int indx)
448{
449 int status;
450 u8 data;
451 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
452 struct usb_device *udev = priv->udev;
453
454 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
455 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
456 indx|0xfe00, 0, &data, 1, HZ / 2);
457
458 if (status < 0)
459 {
460 printk("read_nic_byte_E TimeOut! status:%d\n", status);
461 }
462
463 return data;
464}
465//as 92U has extend page from 4 to 16, so modify functions below.
466void write_nic_byte(struct net_device *dev, int indx, u8 data)
467{
468 int status;
469
470 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
471 struct usb_device *udev = priv->udev;
472
473 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
474 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
475#ifdef RTL8192SU
476 indx, 0, &data, 1, HZ / 2);
477#else
478 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
479#endif
480
481 if (status < 0)
482 {
483 printk("write_nic_byte TimeOut! status:%d\n", status);
484 }
485
486
487}
488
489
490void write_nic_word(struct net_device *dev, int indx, u16 data)
491{
492
493 int status;
494
495 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
496 struct usb_device *udev = priv->udev;
497
498 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
499 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
500#ifdef RTL8192SU
501 indx, 0, &data, 2, HZ / 2);
502#else
503 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2);
504#endif
505
506 if (status < 0)
507 {
508 printk("write_nic_word TimeOut! status:%d\n", status);
509 }
510
511}
512
513
514void write_nic_dword(struct net_device *dev, int indx, u32 data)
515{
516
517 int status;
518
519 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
520 struct usb_device *udev = priv->udev;
521
522 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
523 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
524#ifdef RTL8192SU
525 indx, 0, &data, 4, HZ / 2);
526#else
527 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2);
528#endif
529
530
531 if (status < 0)
532 {
533 printk("write_nic_dword TimeOut! status:%d\n", status);
534 }
535
536}
537
538
539
540u8 read_nic_byte(struct net_device *dev, int indx)
541{
542 u8 data;
543 int status;
544 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
545 struct usb_device *udev = priv->udev;
546
547 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
548 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
549#ifdef RTL8192SU
550 indx, 0, &data, 1, HZ / 2);
551#else
552 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
553#endif
554
555 if (status < 0)
556 {
557 printk("read_nic_byte TimeOut! status:%d\n", status);
558 }
559
560 return data;
561}
562
563
564
565u16 read_nic_word(struct net_device *dev, int indx)
566{
567 u16 data;
568 int status;
569 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
570 struct usb_device *udev = priv->udev;
571
572 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
573 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
574#ifdef RTL8192SU
575 indx, 0, &data, 2, HZ / 2);
576#else
577 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2);
578#endif
579
580 if (status < 0)
581 {
582 printk("read_nic_word TimeOut! status:%d\n", status);
583 }
584
585
586 return data;
587}
588
589u16 read_nic_word_E(struct net_device *dev, int indx)
590{
591 u16 data;
592 int status;
593 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
594 struct usb_device *udev = priv->udev;
595
596 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
597 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
598 indx|0xfe00, 0, &data, 2, HZ / 2);
599
600 if (status < 0)
601 {
602 printk("read_nic_word TimeOut! status:%d\n", status);
603 }
604
605
606 return data;
607}
608
609u32 read_nic_dword(struct net_device *dev, int indx)
610{
611 u32 data;
612 int status;
613// int result;
614
615 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
616 struct usb_device *udev = priv->udev;
617
618 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
619 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
620#ifdef RTL8192SU
621 indx, 0, &data, 4, HZ / 2);
622#else
623 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2);
624#endif
625// if(0 != result) {
626// printk(KERN_WARNING "read size of data = %d\, date = %d\n", result, data);
627// }
628
629 if (status < 0)
630 {
631 printk("read_nic_dword TimeOut! status:%d\n", status);
632 if(status == -ENODEV) {
633 priv->usb_error = true;
634 }
635 }
636
637
638
639 return data;
640}
641
642
643//u8 read_phy_cck(struct net_device *dev, u8 adr);
644//u8 read_phy_ofdm(struct net_device *dev, u8 adr);
645/* this might still called in what was the PHY rtl8185/rtl8192 common code
646 * plans are to possibilty turn it again in one common code...
647 */
648inline void force_pci_posting(struct net_device *dev)
649{
650}
651
652
653static struct net_device_stats *rtl8192_stats(struct net_device *dev);
654void rtl8192_commit(struct net_device *dev);
655//void rtl8192_restart(struct net_device *dev);
5f53d8ca
JC		 656void rtl8192_restart(struct work_struct *work);
657//void rtl8192_rq_tx_ack(struct work_struct *work);
5f53d8ca
JC		 658
659void watch_dog_timer_callback(unsigned long data);
660
661/****************************************************************************
662 -----------------------------PROCFS STUFF-------------------------
663*****************************************************************************/
664
665static struct proc_dir_entry *rtl8192_proc = NULL;
666
667
668
669static int proc_get_stats_ap(char *page, char **start,
670 off_t offset, int count,
671 int *eof, void *data)
672{
673 struct net_device *dev = data;
674 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
675 struct ieee80211_device *ieee = priv->ieee80211;
676 struct ieee80211_network *target;
677
678 int len = 0;
679
680 list_for_each_entry(target, &ieee->network_list, list) {
681
682 len += snprintf(page + len, count - len,
683 "%s ", target->ssid);
684
685 if(target->wpa_ie_len>0 || target->rsn_ie_len>0){
686 len += snprintf(page + len, count - len,
687 "WPA\n");
688 }
689 else{
690 len += snprintf(page + len, count - len,
691 "non_WPA\n");
692 }
693
694 }
695
696 *eof = 1;
697 return len;
698}
699
700#ifdef RTL8192SU
701static int proc_get_registers(char *page, char **start,
702 off_t offset, int count,
703 int *eof, void *data)
704{
705 struct net_device *dev = data;
706// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
707
708 int len = 0;
709 int i,n,page0,page1,page2;
710
711 int max=0xff;
712 page0 = 0x000;
713 page1 = 0x100;
714 page2 = 0x800;
715
716 /* This dump the current register page */
717 if(!IS_BB_REG_OFFSET_92S(page0)){
718 len += snprintf(page + len, count - len,
719 "\n####################page %x##################\n ", (page0>>8));
720 for(n=0;n<=max;)
721 {
722 len += snprintf(page + len, count - len,
723 "\nD: %2x > ",n);
724 for(i=0;i<16 && n<=max;i++,n++)
725 len += snprintf(page + len, count - len,
726 "%2.2x ",read_nic_byte(dev,(page0|n)));
727 }
728 }else{
729 len += snprintf(page + len, count - len,
730 "\n####################page %x##################\n ", (page0>>8));
731 for(n=0;n<=max;)
732 {
733 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
734 for(i=0;i<4 && n<=max;n+=4,i++)
735 len += snprintf(page + len, count - len,
736 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
737 }
738 }
739 len += snprintf(page + len, count - len,"\n");
740 *eof = 1;
741 return len;
742
743}
744static int proc_get_registers_1(char *page, char **start,
745 off_t offset, int count,
746 int *eof, void *data)
747{
748 struct net_device *dev = data;
749// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
750
751 int len = 0;
752 int i,n,page0;
753
754 int max=0xff;
755 page0 = 0x100;
756
757 /* This dump the current register page */
758 len += snprintf(page + len, count - len,
759 "\n####################page %x##################\n ", (page0>>8));
760 for(n=0;n<=max;)
761 {
762 len += snprintf(page + len, count - len,
763 "\nD: %2x > ",n);
764 for(i=0;i<16 && n<=max;i++,n++)
765 len += snprintf(page + len, count - len,
766 "%2.2x ",read_nic_byte(dev,(page0|n)));
767 }
768 len += snprintf(page + len, count - len,"\n");
769 *eof = 1;
770 return len;
771
772}
773static int proc_get_registers_2(char *page, char **start,
774 off_t offset, int count,
775 int *eof, void *data)
776{
777 struct net_device *dev = data;
778// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
779
780 int len = 0;
781 int i,n,page0;
782
783 int max=0xff;
784 page0 = 0x200;
785
786 /* This dump the current register page */
787 len += snprintf(page + len, count - len,
788 "\n####################page %x##################\n ", (page0>>8));
789 for(n=0;n<=max;)
790 {
791 len += snprintf(page + len, count - len,
792 "\nD: %2x > ",n);
793 for(i=0;i<16 && n<=max;i++,n++)
794 len += snprintf(page + len, count - len,
795 "%2.2x ",read_nic_byte(dev,(page0|n)));
796 }
797 len += snprintf(page + len, count - len,"\n");
798 *eof = 1;
799 return len;
800
801}
802static int proc_get_registers_8(char *page, char **start,
803 off_t offset, int count,
804 int *eof, void *data)
805{
806 struct net_device *dev = data;
807
808 int len = 0;
809 int i,n,page0;
810
811 int max=0xff;
812 page0 = 0x800;
813
814 /* This dump the current register page */
815 len += snprintf(page + len, count - len,
816 "\n####################page %x##################\n ", (page0>>8));
817 for(n=0;n<=max;)
818 {
819 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
820 for(i=0;i<4 && n<=max;n+=4,i++)
821 len += snprintf(page + len, count - len,
822 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
823 }
824 len += snprintf(page + len, count - len,"\n");
825 *eof = 1;
826 return len;
827
828 }
829static int proc_get_registers_9(char *page, char **start,
830 off_t offset, int count,
831 int *eof, void *data)
832{
833 struct net_device *dev = data;
834// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
835
836 int len = 0;
837 int i,n,page0;
838
839 int max=0xff;
840 page0 = 0x900;
841
842 /* This dump the current register page */
843 len += snprintf(page + len, count - len,
844 "\n####################page %x##################\n ", (page0>>8));
845 for(n=0;n<=max;)
846 {
847 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
848 for(i=0;i<4 && n<=max;n+=4,i++)
849 len += snprintf(page + len, count - len,
850 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
851 }
852 len += snprintf(page + len, count - len,"\n");
853 *eof = 1;
854 return len;
855}
856static int proc_get_registers_a(char *page, char **start,
857 off_t offset, int count,
858 int *eof, void *data)
859{
860 struct net_device *dev = data;
861// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
862
863 int len = 0;
864 int i,n,page0;
865
866 int max=0xff;
867 page0 = 0xa00;
868
869 /* This dump the current register page */
870 len += snprintf(page + len, count - len,
871 "\n####################page %x##################\n ", (page0>>8));
872 for(n=0;n<=max;)
873 {
874 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
875 for(i=0;i<4 && n<=max;n+=4,i++)
876 len += snprintf(page + len, count - len,
877 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
878 }
879 len += snprintf(page + len, count - len,"\n");
880 *eof = 1;
881 return len;
882}
883static int proc_get_registers_b(char *page, char **start,
884 off_t offset, int count,
885 int *eof, void *data)
886{
887 struct net_device *dev = data;
888// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
889
890 int len = 0;
891 int i,n,page0;
892
893 int max=0xff;
894 page0 = 0xb00;
895
896 /* This dump the current register page */
897 len += snprintf(page + len, count - len,
898 "\n####################page %x##################\n ", (page0>>8));
899 for(n=0;n<=max;)
900 {
901 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
902 for(i=0;i<4 && n<=max;n+=4,i++)
903 len += snprintf(page + len, count - len,
904 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
905 }
906 len += snprintf(page + len, count - len,"\n");
907 *eof = 1;
908 return len;
909 }
910static int proc_get_registers_c(char *page, char **start,
911 off_t offset, int count,
912 int *eof, void *data)
913{
914 struct net_device *dev = data;
915// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
916
917 int len = 0;
918 int i,n,page0;
919
920 int max=0xff;
921 page0 = 0xc00;
922
923 /* This dump the current register page */
924 len += snprintf(page + len, count - len,
925 "\n####################page %x##################\n ", (page0>>8));
926 for(n=0;n<=max;)
927 {
928 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
929 for(i=0;i<4 && n<=max;n+=4,i++)
930 len += snprintf(page + len, count - len,
931 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
932 }
933 len += snprintf(page + len, count - len,"\n");
934 *eof = 1;
935 return len;
936}
937static int proc_get_registers_d(char *page, char **start,
938 off_t offset, int count,
939 int *eof, void *data)
940{
941 struct net_device *dev = data;
942// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
943
944 int len = 0;
945 int i,n,page0;
946
947 int max=0xff;
948 page0 = 0xd00;
949
950 /* This dump the current register page */
951 len += snprintf(page + len, count - len,
952 "\n####################page %x##################\n ", (page0>>8));
953 for(n=0;n<=max;)
954 {
955 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
956 for(i=0;i<4 && n<=max;n+=4,i++)
957 len += snprintf(page + len, count - len,
958 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
959 }
960 len += snprintf(page + len, count - len,"\n");
961 *eof = 1;
962 return len;
963}
964static int proc_get_registers_e(char *page, char **start,
965 off_t offset, int count,
966 int *eof, void *data)
967{
968 struct net_device *dev = data;
969// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
970
971 int len = 0;
972 int i,n,page0;
973
974 int max=0xff;
975 page0 = 0xe00;
976
977 /* This dump the current register page */
978 len += snprintf(page + len, count - len,
979 "\n####################page %x##################\n ", (page0>>8));
980 for(n=0;n<=max;)
981 {
982 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
983 for(i=0;i<4 && n<=max;n+=4,i++)
984 len += snprintf(page + len, count - len,
985 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
986 }
987 len += snprintf(page + len, count - len,"\n");
988 *eof = 1;
989 return len;
990}
991#else
992static int proc_get_registers(char *page, char **start,
993 off_t offset, int count,
994 int *eof, void *data)
995{
996 struct net_device *dev = data;
997// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
998
999 int len = 0;
1000 int i,n;
1001
1002 int max=0xff;
1003
1004 /* This dump the current register page */
1005len += snprintf(page + len, count - len,
1006 "\n####################page 0##################\n ");
1007
1008 for(n=0;n<=max;)
1009 {
1010 //printk( "\nD: %2x> ", n);
1011 len += snprintf(page + len, count - len,
1012 "\nD: %2x > ",n);
1013
1014 for(i=0;i<16 && n<=max;i++,n++)
1015 len += snprintf(page + len, count - len,
1016 "%2x ",read_nic_byte(dev,0x000|n));
1017
1018 // printk("%2x ",read_nic_byte(dev,n));
1019 }
1020#if 1
1021len += snprintf(page + len, count - len,
1022 "\n####################page 1##################\n ");
1023 for(n=0;n<=max;)
1024 {
1025 //printk( "\nD: %2x> ", n);
1026 len += snprintf(page + len, count - len,
1027 "\nD: %2x > ",n);
1028
1029 for(i=0;i<16 && n<=max;i++,n++)
1030 len += snprintf(page + len, count - len,
1031 "%2x ",read_nic_byte(dev,0x100|n));
1032
1033 // printk("%2x ",read_nic_byte(dev,n));
1034 }
1035len += snprintf(page + len, count - len,
1036 "\n####################page 3##################\n ");
1037 for(n=0;n<=max;)
1038 {
1039 //printk( "\nD: %2x> ", n);
1040 len += snprintf(page + len, count - len,
1041 "\nD: %2x > ",n);
1042
1043 for(i=0;i<16 && n<=max;i++,n++)
1044 len += snprintf(page + len, count - len,
1045 "%2x ",read_nic_byte(dev,0x300|n));
1046
1047 // printk("%2x ",read_nic_byte(dev,n));
1048 }
1049
1050#endif
1051
1052 len += snprintf(page + len, count - len,"\n");
1053 *eof = 1;
1054 return len;
1055
1056}
1057#endif
1058
1059#if 0
1060static int proc_get_cck_reg(char *page, char **start,
1061 off_t offset, int count,
1062 int *eof, void *data)
1063{
1064 struct net_device *dev = data;
1065// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1066
1067 int len = 0;
1068 int i,n;
1069
1070 int max = 0x5F;
1071
1072 /* This dump the current register page */
1073 for(n=0;n<=max;)
1074 {
1075 //printk( "\nD: %2x> ", n);
1076 len += snprintf(page + len, count - len,
1077 "\nD: %2x > ",n);
1078
1079 for(i=0;i<16 && n<=max;i++,n++)
1080 len += snprintf(page + len, count - len,
1081 "%2x ",read_phy_cck(dev,n));
1082
1083 // printk("%2x ",read_nic_byte(dev,n));
1084 }
1085 len += snprintf(page + len, count - len,"\n");
1086
1087
1088 *eof = 1;
1089 return len;
1090}
1091
1092#endif
1093
1094#if 0
1095static int proc_get_ofdm_reg(char *page, char **start,
1096 off_t offset, int count,
1097 int *eof, void *data)
1098{
1099 struct net_device *dev = data;
1100// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1101
1102 int len = 0;
1103 int i,n;
1104
1105 //int max=0xff;
1106 int max = 0x40;
1107
1108 /* This dump the current register page */
1109 for(n=0;n<=max;)
1110 {
1111 //printk( "\nD: %2x> ", n);
1112 len += snprintf(page + len, count - len,
1113 "\nD: %2x > ",n);
1114
1115 for(i=0;i<16 && n<=max;i++,n++)
1116 len += snprintf(page + len, count - len,
1117 "%2x ",read_phy_ofdm(dev,n));
1118
1119 // printk("%2x ",read_nic_byte(dev,n));
1120 }
1121 len += snprintf(page + len, count - len,"\n");
1122
1123
1124
1125 *eof = 1;
1126 return len;
1127}
1128
1129#endif
1130
1131#if 0
1132static int proc_get_stats_hw(char *page, char **start,
1133 off_t offset, int count,
1134 int *eof, void *data)
1135{
1136 struct net_device *dev = data;
1137 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1138
1139 int len = 0;
1140
1141 len += snprintf(page + len, count - len,
1142 "NIC int: %lu\n"
1143 "Total int: %lu\n",
1144 priv->stats.ints,
1145 priv->stats.shints);
1146
1147 *eof = 1;
1148 return len;
1149}
1150#endif
1151
1152static int proc_get_stats_tx(char *page, char **start,
1153 off_t offset, int count,
1154 int *eof, void *data)
1155{
1156 struct net_device *dev = data;
1157 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1158
1159 int len = 0;
1160
1161 len += snprintf(page + len, count - len,
1162 "TX VI priority ok int: %lu\n"
1163 "TX VI priority error int: %lu\n"
1164 "TX VO priority ok int: %lu\n"
1165 "TX VO priority error int: %lu\n"
1166 "TX BE priority ok int: %lu\n"
1167 "TX BE priority error int: %lu\n"
1168 "TX BK priority ok int: %lu\n"
1169 "TX BK priority error int: %lu\n"
1170 "TX MANAGE priority ok int: %lu\n"
1171 "TX MANAGE priority error int: %lu\n"
1172 "TX BEACON priority ok int: %lu\n"
1173 "TX BEACON priority error int: %lu\n"
1174// "TX high priority ok int: %lu\n"
1175// "TX high priority failed error int: %lu\n"
1176 "TX queue resume: %lu\n"
1177 "TX queue stopped?: %d\n"
1178 "TX fifo overflow: %lu\n"
1179// "TX beacon: %lu\n"
1180 "TX VI queue: %d\n"
1181 "TX VO queue: %d\n"
1182 "TX BE queue: %d\n"
1183 "TX BK queue: %d\n"
1184// "TX HW queue: %d\n"
1185 "TX VI dropped: %lu\n"
1186 "TX VO dropped: %lu\n"
1187 "TX BE dropped: %lu\n"
1188 "TX BK dropped: %lu\n"
1189 "TX total data packets %lu\n",
1190// "TX beacon aborted: %lu\n",
1191 priv->stats.txviokint,
1192 priv->stats.txvierr,
1193 priv->stats.txvookint,
1194 priv->stats.txvoerr,
1195 priv->stats.txbeokint,
1196 priv->stats.txbeerr,
1197 priv->stats.txbkokint,
1198 priv->stats.txbkerr,
1199 priv->stats.txmanageokint,
1200 priv->stats.txmanageerr,
1201 priv->stats.txbeaconokint,
1202 priv->stats.txbeaconerr,
1203// priv->stats.txhpokint,
1204// priv->stats.txhperr,
1205 priv->stats.txresumed,
1206 netif_queue_stopped(dev),
1207 priv->stats.txoverflow,
1208// priv->stats.txbeacon,
1209 atomic_read(&(priv->tx_pending[VI_PRIORITY])),
1210 atomic_read(&(priv->tx_pending[VO_PRIORITY])),
1211 atomic_read(&(priv->tx_pending[BE_PRIORITY])),
1212 atomic_read(&(priv->tx_pending[BK_PRIORITY])),
1213// read_nic_byte(dev, TXFIFOCOUNT),
1214 priv->stats.txvidrop,
1215 priv->stats.txvodrop,
1216 priv->stats.txbedrop,
1217 priv->stats.txbkdrop,
1218 priv->stats.txdatapkt
1219// priv->stats.txbeaconerr
1220 );
1221
1222 *eof = 1;
1223 return len;
1224}
1225
1226
1227
1228static int proc_get_stats_rx(char *page, char **start,
1229 off_t offset, int count,
1230 int *eof, void *data)
1231{
1232 struct net_device *dev = data;
1233 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1234
1235 int len = 0;
1236
1237 len += snprintf(page + len, count - len,
1238 "RX packets: %lu\n"
1239 "RX urb status error: %lu\n"
1240 "RX invalid urb error: %lu\n",
1241 priv->stats.rxoktotal,
1242 priv->stats.rxstaterr,
1243 priv->stats.rxurberr);
1244
1245 *eof = 1;
1246 return len;
1247}
1248#if 0
1249#if WIRELESS_EXT >= 12 && WIRELESS_EXT < 17
1250
1251static struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev)
1252{
1253 struct r8192_priv *priv = ieee80211_priv(dev);
1254
1255 return &priv->wstats;
1256}
1257#endif
1258#endif
1259void rtl8192_proc_module_init(void)
1260{
1261 RT_TRACE(COMP_INIT, "Initializing proc filesystem");
5f53d8ca 1262 rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, init_net.proc_net);
5f53d8ca
JC		 1263}
1264
1265
1266void rtl8192_proc_module_remove(void)
1267{
5f53d8ca 1268 remove_proc_entry(RTL819xU_MODULE_NAME, init_net.proc_net);
5f53d8ca
JC		 1269}
1270
1271
1272void rtl8192_proc_remove_one(struct net_device *dev)
1273{
1274 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1275
1276
1277 if (priv->dir_dev) {
1278 // remove_proc_entry("stats-hw", priv->dir_dev);
1279 remove_proc_entry("stats-tx", priv->dir_dev);
1280 remove_proc_entry("stats-rx", priv->dir_dev);
1281 // remove_proc_entry("stats-ieee", priv->dir_dev);
1282 remove_proc_entry("stats-ap", priv->dir_dev);
1283 remove_proc_entry("registers", priv->dir_dev);
1284 remove_proc_entry("registers-1", priv->dir_dev);
1285 remove_proc_entry("registers-2", priv->dir_dev);
1286 remove_proc_entry("registers-8", priv->dir_dev);
1287 remove_proc_entry("registers-9", priv->dir_dev);
1288 remove_proc_entry("registers-a", priv->dir_dev);
1289 remove_proc_entry("registers-b", priv->dir_dev);
1290 remove_proc_entry("registers-c", priv->dir_dev);
1291 remove_proc_entry("registers-d", priv->dir_dev);
1292 remove_proc_entry("registers-e", priv->dir_dev);
1293 // remove_proc_entry("cck-registers",priv->dir_dev);
1294 // remove_proc_entry("ofdm-registers",priv->dir_dev);
1295 //remove_proc_entry(dev->name, rtl8192_proc);
1296 remove_proc_entry("wlan0", rtl8192_proc);
1297 priv->dir_dev = NULL;
1298 }
1299}
1300
1301
1302void rtl8192_proc_init_one(struct net_device *dev)
1303{
1304 struct proc_dir_entry *e;
1305 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1306 priv->dir_dev = create_proc_entry(dev->name,
1307 S_IFDIR | S_IRUGO | S_IXUGO,
1308 rtl8192_proc);
1309 if (!priv->dir_dev) {
1310 RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n",
1311 dev->name);
1312 return;
1313 }
1314 #if 0
1315 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
1316 priv->dir_dev, proc_get_stats_hw, dev);
1317
1318 if (!e) {
1319 DMESGE("Unable to initialize "
1320 "/proc/net/rtl8192/%s/stats-hw\n",
1321 dev->name);
1322 }
1323 #endif
1324 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
1325 priv->dir_dev, proc_get_stats_rx, dev);
1326
1327 if (!e) {
1328 RT_TRACE(COMP_ERR,"Unable to initialize "
1329 "/proc/net/rtl8192/%s/stats-rx\n",
1330 dev->name);
1331 }
1332
1333
1334 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
1335 priv->dir_dev, proc_get_stats_tx, dev);
1336
1337 if (!e) {
1338 RT_TRACE(COMP_ERR, "Unable to initialize "
1339 "/proc/net/rtl8192/%s/stats-tx\n",
1340 dev->name);
1341 }
1342 #if 0
1343 e = create_proc_read_entry("stats-ieee", S_IFREG | S_IRUGO,
1344 priv->dir_dev, proc_get_stats_ieee, dev);
1345
1346 if (!e) {
1347 DMESGE("Unable to initialize "
1348 "/proc/net/rtl8192/%s/stats-ieee\n",
1349 dev->name);
1350 }
1351
1352 #endif
1353
1354 e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO,
1355 priv->dir_dev, proc_get_stats_ap, dev);
1356
1357 if (!e) {
1358 RT_TRACE(COMP_ERR, "Unable to initialize "
1359 "/proc/net/rtl8192/%s/stats-ap\n",
1360 dev->name);
1361 }
1362
1363 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
1364 priv->dir_dev, proc_get_registers, dev);
1365 if (!e) {
1366 RT_TRACE(COMP_ERR, "Unable to initialize "
1367 "/proc/net/rtl8192/%s/registers\n",
1368 dev->name);
1369 }
1370#ifdef RTL8192SU
1371 e = create_proc_read_entry("registers-1", S_IFREG | S_IRUGO,
1372 priv->dir_dev, proc_get_registers_1, dev);
1373 if (!e) {
1374 RT_TRACE(COMP_ERR, "Unable to initialize "
1375 "/proc/net/rtl8192/%s/registers-1\n",
1376 dev->name);
1377 }
1378 e = create_proc_read_entry("registers-2", S_IFREG | S_IRUGO,
1379 priv->dir_dev, proc_get_registers_2, dev);
1380 if (!e) {
1381 RT_TRACE(COMP_ERR, "Unable to initialize "
1382 "/proc/net/rtl8192/%s/registers-2\n",
1383 dev->name);
1384 }
1385 e = create_proc_read_entry("registers-8", S_IFREG | S_IRUGO,
1386 priv->dir_dev, proc_get_registers_8, dev);
1387 if (!e) {
1388 RT_TRACE(COMP_ERR, "Unable to initialize "
1389 "/proc/net/rtl8192/%s/registers-8\n",
1390 dev->name);
1391 }
1392 e = create_proc_read_entry("registers-9", S_IFREG | S_IRUGO,
1393 priv->dir_dev, proc_get_registers_9, dev);
1394 if (!e) {
1395 RT_TRACE(COMP_ERR, "Unable to initialize "
1396 "/proc/net/rtl8192/%s/registers-9\n",
1397 dev->name);
1398 }
1399 e = create_proc_read_entry("registers-a", S_IFREG | S_IRUGO,
1400 priv->dir_dev, proc_get_registers_a, dev);
1401 if (!e) {
1402 RT_TRACE(COMP_ERR, "Unable to initialize "
1403 "/proc/net/rtl8192/%s/registers-a\n",
1404 dev->name);
1405 }
1406 e = create_proc_read_entry("registers-b", S_IFREG | S_IRUGO,
1407 priv->dir_dev, proc_get_registers_b, dev);
1408 if (!e) {
1409 RT_TRACE(COMP_ERR, "Unable to initialize "
1410 "/proc/net/rtl8192/%s/registers-b\n",
1411 dev->name);
1412 }
1413 e = create_proc_read_entry("registers-c", S_IFREG | S_IRUGO,
1414 priv->dir_dev, proc_get_registers_c, dev);
1415 if (!e) {
1416 RT_TRACE(COMP_ERR, "Unable to initialize "
1417 "/proc/net/rtl8192/%s/registers-c\n",
1418 dev->name);
1419 }
1420 e = create_proc_read_entry("registers-d", S_IFREG | S_IRUGO,
1421 priv->dir_dev, proc_get_registers_d, dev);
1422 if (!e) {
1423 RT_TRACE(COMP_ERR, "Unable to initialize "
1424 "/proc/net/rtl8192/%s/registers-d\n",
1425 dev->name);
1426 }
1427 e = create_proc_read_entry("registers-e", S_IFREG | S_IRUGO,
1428 priv->dir_dev, proc_get_registers_e, dev);
1429 if (!e) {
1430 RT_TRACE(COMP_ERR, "Unable to initialize "
1431 "/proc/net/rtl8192/%s/registers-e\n",
1432 dev->name);
1433 }
1434#endif
1435#if 0
1436 e = create_proc_read_entry("cck-registers", S_IFREG | S_IRUGO,
1437 priv->dir_dev, proc_get_cck_reg, dev);
1438 if (!e) {
1439 RT_TRACE(COMP_ERR, "Unable to initialize "
1440 "/proc/net/rtl8192/%s/cck-registers\n",
1441 dev->name);
1442 }
1443
1444 e = create_proc_read_entry("ofdm-registers", S_IFREG | S_IRUGO,
1445 priv->dir_dev, proc_get_ofdm_reg, dev);
1446 if (!e) {
1447 RT_TRACE(COMP_ERR, "Unable to initialize "
1448 "/proc/net/rtl8192/%s/ofdm-registers\n",
1449 dev->name);
1450 }
1451#endif
1452}
1453/****************************************************************************
1454 -----------------------------MISC STUFF-------------------------
1455*****************************************************************************/
1456
1457/* this is only for debugging */
1458void print_buffer(u32 *buffer, int len)
1459{
1460 int i;
1461 u8 *buf =(u8*)buffer;
1462
1463 printk("ASCII BUFFER DUMP (len: %x):\n",len);
1464
1465 for(i=0;i<len;i++)
1466 printk("%c",buf[i]);
1467
1468 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
1469
1470 for(i=0;i<len;i++)
1471 printk("%x",buf[i]);
1472
1473 printk("\n");
1474}
1475
1476//short check_nic_enough_desc(struct net_device *dev, priority_t priority)
1477short check_nic_enough_desc(struct net_device *dev,int queue_index)
1478{
1479 struct r8192_priv *priv = ieee80211_priv(dev);
1480 int used = atomic_read(&priv->tx_pending[queue_index]);
1481
1482 return (used < MAX_TX_URB);
1483}
1484
1485void tx_timeout(struct net_device *dev)
1486{
1487 struct r8192_priv *priv = ieee80211_priv(dev);
1488 //rtl8192_commit(dev);
1489
5f53d8ca 1490 schedule_work(&priv->reset_wq);
5f53d8ca
JC		 1491 //DMESG("TXTIMEOUT");
1492}
1493
1494
1495/* this is only for debug */
1496void dump_eprom(struct net_device *dev)
1497{
1498 int i;
1499 for(i=0; i<63; i++)
1500 RT_TRACE(COMP_EPROM, "EEPROM addr %x : %x", i, eprom_read(dev,i));
1501}
1502
1503/* this is only for debug */
1504void rtl8192_dump_reg(struct net_device *dev)
1505{
1506 int i;
1507 int n;
1508 int max=0x1ff;
1509
1510 RT_TRACE(COMP_PHY, "Dumping NIC register map");
1511
1512 for(n=0;n<=max;)
1513 {
1514 printk( "\nD: %2x> ", n);
1515 for(i=0;i<16 && n<=max;i++,n++)
1516 printk("%2x ",read_nic_byte(dev,n));
1517 }
1518 printk("\n");
1519}
1520
1521/****************************************************************************
1522 ------------------------------HW STUFF---------------------------
1523*****************************************************************************/
1524
1525#if 0
1526void rtl8192_irq_enable(struct net_device *dev)
1527{
1528 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1529 //priv->irq_enabled = 1;
1530/*
1531 write_nic_word(dev,INTA_MASK,INTA_RXOK | INTA_RXDESCERR | INTA_RXOVERFLOW |\
1532 INTA_TXOVERFLOW | INTA_HIPRIORITYDESCERR | INTA_HIPRIORITYDESCOK |\
1533 INTA_NORMPRIORITYDESCERR | INTA_NORMPRIORITYDESCOK |\
1534 INTA_LOWPRIORITYDESCERR | INTA_LOWPRIORITYDESCOK | INTA_TIMEOUT);
1535*/
1536 write_nic_word(dev,INTA_MASK, priv->irq_mask);
1537}
1538
1539
1540void rtl8192_irq_disable(struct net_device *dev)
1541{
1542// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1543
1544 write_nic_word(dev,INTA_MASK,0);
1545 force_pci_posting(dev);
1546// priv->irq_enabled = 0;
1547}
1548#endif
1549
1550void rtl8192_set_mode(struct net_device *dev,int mode)
1551{
1552 u8 ecmd;
1553 ecmd=read_nic_byte(dev, EPROM_CMD);
1554 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
1555 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
1556 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
1557 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
1558 write_nic_byte(dev, EPROM_CMD, ecmd);
1559}
1560
1561
1562void rtl8192_update_msr(struct net_device *dev)
1563{
1564 struct r8192_priv *priv = ieee80211_priv(dev);
1565 u8 msr;
1566
1567 msr = read_nic_byte(dev, MSR);
1568 msr &= ~ MSR_LINK_MASK;
1569
1570 /* do not change in link_state != WLAN_LINK_ASSOCIATED.
1571 * msr must be updated if the state is ASSOCIATING.
1572 * this is intentional and make sense for ad-hoc and
1573 * master (see the create BSS/IBSS func)
1574 */
1575 if (priv->ieee80211->state == IEEE80211_LINKED){
1576
1577 if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
1578 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
1579 else if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1580 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
1581 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
1582 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
1583
1584 }else
1585 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
1586
1587 write_nic_byte(dev, MSR, msr);
1588}
1589
1590void rtl8192_set_chan(struct net_device *dev,short ch)
1591{
1592 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1593// u32 tx;
1594 RT_TRACE(COMP_CH, "=====>%s()====ch:%d\n", __FUNCTION__, ch);
1595 //printk("=====>%s()====ch:%d\n", __FUNCTION__, ch);
1596 priv->chan=ch;
1597 #if 0
1598 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC ||
1599 priv->ieee80211->iw_mode == IW_MODE_MASTER){
1600
1601 priv->ieee80211->link_state = WLAN_LINK_ASSOCIATED;
1602 priv->ieee80211->master_chan = ch;
1603 rtl8192_update_beacon_ch(dev);
1604 }
1605 #endif
1606
1607 /* this hack should avoid frame TX during channel setting*/
1608
1609
1610// tx = read_nic_dword(dev,TX_CONF);
1611// tx &= ~TX_LOOPBACK_MASK;
1612
1613#ifndef LOOP_TEST
1614// write_nic_dword(dev,TX_CONF, tx |( TX_LOOPBACK_MAC<<TX_LOOPBACK_SHIFT));
1615
1616 //need to implement rf set channel here WB
1617
1618 if (priv->rf_set_chan)
1619 priv->rf_set_chan(dev,priv->chan);
1620 mdelay(10);
1621// write_nic_dword(dev,TX_CONF,tx | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT));
1622#endif
1623}
1624
5f53d8ca 1625static void rtl8192_rx_isr(struct urb *urb);
5f53d8ca
JC		 1626
1627u32 get_rxpacket_shiftbytes_819xusb(struct ieee80211_rx_stats *pstats)
1628{
1629
1630#ifdef USB_RX_AGGREGATION_SUPPORT
1631 if (pstats->bisrxaggrsubframe)
1632 return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize
1633 + pstats->RxBufShift + 8);
1634 else
1635#endif
1636 return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize
1637 + pstats->RxBufShift);
1638
1639}
1640static int rtl8192_rx_initiate(struct net_device*dev)
1641{
1642 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1643 struct urb *entry;
1644 struct sk_buff *skb;
1645 struct rtl8192_rx_info *info;
1646
1647 /* nomal packet rx procedure */
1648 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB) {
1649 skb = __dev_alloc_skb(RX_URB_SIZE, GFP_KERNEL);
1650 if (!skb)
1651 break;
5f53d8ca 1652 entry = usb_alloc_urb(0, GFP_KERNEL);
5f53d8ca
JC		 1653 if (!entry) {
1654 kfree_skb(skb);
1655 break;
1656 }
1657// printk("nomal packet IN request!\n");
1658 usb_fill_bulk_urb(entry, priv->udev,
1659 usb_rcvbulkpipe(priv->udev, 3), skb->tail,
1660 RX_URB_SIZE, rtl8192_rx_isr, skb);
1661 info = (struct rtl8192_rx_info *) skb->cb;
1662 info->urb = entry;
1663 info->dev = dev;
1664 info->out_pipe = 3; //denote rx normal packet queue
1665 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1666 usb_submit_urb(entry, GFP_KERNEL);
5f53d8ca
JC		 1667 }
1668
1669 /* command packet rx procedure */
1670 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB + 3) {
1671// printk("command packet IN request!\n");
1672 skb = __dev_alloc_skb(RX_URB_SIZE ,GFP_KERNEL);
1673 if (!skb)
1674 break;
5f53d8ca 1675 entry = usb_alloc_urb(0, GFP_KERNEL);
5f53d8ca
JC		 1676 if (!entry) {
1677 kfree_skb(skb);
1678 break;
1679 }
1680 usb_fill_bulk_urb(entry, priv->udev,
1681 usb_rcvbulkpipe(priv->udev, 9), skb->tail,
1682 RX_URB_SIZE, rtl8192_rx_isr, skb);
1683 info = (struct rtl8192_rx_info *) skb->cb;
1684 info->urb = entry;
1685 info->dev = dev;
1686 info->out_pipe = 9; //denote rx cmd packet queue
1687 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1688 usb_submit_urb(entry, GFP_KERNEL);
5f53d8ca
JC		 1689 }
1690
1691 return 0;
1692}
1693
1694void rtl8192_set_rxconf(struct net_device *dev)
1695{
1696 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1697 u32 rxconf;
1698
1699 rxconf=read_nic_dword(dev,RCR);
1700 rxconf = rxconf &~ MAC_FILTER_MASK;
1701 rxconf = rxconf | RCR_AMF;
1702 rxconf = rxconf | RCR_ADF;
1703 rxconf = rxconf | RCR_AB;
1704 rxconf = rxconf | RCR_AM;
1705 //rxconf = rxconf | RCR_ACF;
1706
1707 if (dev->flags & IFF_PROMISC) {DMESG ("NIC in promisc mode");}
1708
1709 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1710 dev->flags & IFF_PROMISC){
1711 rxconf = rxconf | RCR_AAP;
1712 } /*else if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
1713 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
1714 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
1715 }*/else{
1716 rxconf = rxconf | RCR_APM;
1717 rxconf = rxconf | RCR_CBSSID;
1718 }
1719
1720
1721 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1722 rxconf = rxconf | RCR_AICV;
1723 rxconf = rxconf | RCR_APWRMGT;
1724 }
1725
1726 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1727 rxconf = rxconf | RCR_ACRC32;
1728
1729
1730 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
1731 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
1732 rxconf = rxconf &~ MAX_RX_DMA_MASK;
1733 rxconf = rxconf | ((u32)7<<RCR_MXDMA_OFFSET);
1734
1735// rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
1736 rxconf = rxconf | RCR_ONLYERLPKT;
1737
1738// rxconf = rxconf &~ RCR_CS_MASK;
1739// rxconf = rxconf | (1<<RCR_CS_SHIFT);
1740
1741 write_nic_dword(dev, RCR, rxconf);
1742
1743 #ifdef DEBUG_RX
1744 DMESG("rxconf: %x %x",rxconf ,read_nic_dword(dev,RCR));
1745 #endif
1746}
1747//wait to be removed
1748void rtl8192_rx_enable(struct net_device *dev)
1749{
1750 //u8 cmd;
1751
1752 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1753
1754 rtl8192_rx_initiate(dev);
1755
1756// rtl8192_set_rxconf(dev);
1757#if 0
1758 if(NIC_8187 == priv->card_8187) {
1759 cmd=read_nic_byte(dev,CMD);
1760 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
1761 }
1762 else {
1763 //write_nic_dword(dev, RX_CONF, priv->ReceiveConfig);
1764 }
1765#endif
1766}
1767
1768
1769void rtl8192_tx_enable(struct net_device *dev)
1770{
1771#if 0
1772 u8 cmd;
1773 u8 byte;
1774 u32 txconf;
1775 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1776 //test loopback
1777 // priv->TransmitConfig |= (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1778 if(NIC_8187B == priv->card_8187){
1779 write_nic_dword(dev, TX_CONF, priv->TransmitConfig);
1780 byte = read_nic_byte(dev, MSR);
1781 byte |= MSR_LINK_ENEDCA;
1782 write_nic_byte(dev, MSR, byte);
1783 } else {
1784 byte = read_nic_byte(dev,CW_CONF);
1785 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
1786 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
1787 write_nic_byte(dev, CW_CONF, byte);
1788
1789 byte = read_nic_byte(dev, TX_AGC_CTL);
1790 byte &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
1791 byte &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
1792 byte &= ~(1<<TX_AGC_CTL_FEEDBACK_ANT);
1793 write_nic_byte(dev, TX_AGC_CTL, byte);
1794
1795 txconf= read_nic_dword(dev,TX_CONF);
1796
1797
1798 txconf = txconf &~ TX_LOOPBACK_MASK;
1799
1800#ifndef LOOP_TEST
1801 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT);
1802#else
1803 txconf = txconf | (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1804#endif
1805 txconf = txconf &~ TCR_SRL_MASK;
1806 txconf = txconf &~ TCR_LRL_MASK;
1807
1808 txconf = txconf | (priv->retry_data<<TX_LRLRETRY_SHIFT); // long
1809 txconf = txconf | (priv->retry_rts<<TX_SRLRETRY_SHIFT); // short
1810
1811 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
1812
1813 txconf = txconf &~ TCR_MXDMA_MASK;
1814 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
1815
1816 txconf = txconf | TCR_DISReqQsize;
1817 txconf = txconf | TCR_DISCW;
1818 txconf = txconf &~ TCR_SWPLCPLEN;
1819
1820 txconf=txconf | (1<<TX_NOICV_SHIFT);
1821
1822 write_nic_dword(dev,TX_CONF,txconf);
1823
1824#ifdef DEBUG_TX
1825 DMESG("txconf: %x %x",txconf,read_nic_dword(dev,TX_CONF));
1826#endif
1827
1828 cmd=read_nic_byte(dev,CMD);
1829 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1830 }
1831#endif
1832}
1833
1834#if 0
1835void rtl8192_beacon_tx_enable(struct net_device *dev)
1836{
1837 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1838 priv->dma_poll_mask &=~(1<<TX_DMA_STOP_BEACON_SHIFT);
1839 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1840 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1841 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1842}
1843
1844
1845void rtl8192_
1846_disable(struct net_device *dev)
1847{
1848 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1849 priv->dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
1850 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1851 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1852 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1853}
1854
1855#endif
1856
1857
1858void rtl8192_rtx_disable(struct net_device *dev)
1859{
1860 u8 cmd;
1861 struct r8192_priv *priv = ieee80211_priv(dev);
1862 struct sk_buff *skb;
1863 struct rtl8192_rx_info *info;
1864
1865 cmd=read_nic_byte(dev,CMDR);
1866 write_nic_byte(dev, CMDR, cmd &~ \
1867 (CR_TE|CR_RE));
1868 force_pci_posting(dev);
1869 mdelay(10);
1870
1871 while ((skb = __skb_dequeue(&priv->rx_queue))) {
1872 info = (struct rtl8192_rx_info *) skb->cb;
1873 if (!info->urb)
1874 continue;
1875
1876 usb_kill_urb(info->urb);
1877 kfree_skb(skb);
1878 }
1879
1880 if (skb_queue_len(&priv->skb_queue)) {
1881 printk(KERN_WARNING "skb_queue not empty\n");
1882 }
1883
1884 skb_queue_purge(&priv->skb_queue);
1885 return;
1886}
1887
1888
1889int alloc_tx_beacon_desc_ring(struct net_device *dev, int count)
1890{
1891 #if 0
1892 int i;
1893 u32 *tmp;
1894 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1895
1896 priv->txbeaconring = (u32*)pci_alloc_consistent(priv->pdev,
1897 sizeof(u32)*8*count,
1898 &priv->txbeaconringdma);
1899 if (!priv->txbeaconring) return -1;
1900 for (tmp=priv->txbeaconring,i=0;i<count;i++){
1901 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1902 /*
1903 *(tmp+2) = (u32)dma_tmp;
1904 *(tmp+3) = bufsize;
1905 */
1906 if(i+1<count)
1907 *(tmp+4) = (u32)priv->txbeaconringdma+((i+1)*8*4);
1908 else
1909 *(tmp+4) = (u32)priv->txbeaconringdma;
1910
1911 tmp=tmp+8;
1912 }
1913 #endif
1914 return 0;
1915}
1916
1917#if 0
1918void rtl8192_reset(struct net_device *dev)
1919{
1920
1921 //struct r8192_priv *priv = ieee80211_priv(dev);
1922 //u8 cr;
1923
1924
1925 /* make sure the analog power is on before
1926 * reset, otherwise reset may fail
1927 */
1928#if 0
1929 if(NIC_8187 == priv->card_8187) {
1930 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1931 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1932 rtl8192_irq_disable(dev);
1933 mdelay(200);
1934 write_nic_byte_E(dev,0x18,0x10);
1935 write_nic_byte_E(dev,0x18,0x11);
1936 write_nic_byte_E(dev,0x18,0x00);
1937 mdelay(200);
1938 }
1939#endif
1940 printk("=====>reset?\n");
1941#if 0
1942 cr=read_nic_byte(dev,CMD);
1943 cr = cr & 2;
1944 cr = cr | (1<<CMD_RST_SHIFT);
1945 write_nic_byte(dev,CMD,cr);
1946
1947 force_pci_posting(dev);
1948
1949 mdelay(200);
1950
1951 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1952 RT_TRACE(COMP_ERR, "Card reset timeout!\n");
1953 else
1954 RT_TRACE(COMP_DOWN, "Card successfully reset\n");
1955#endif
1956#if 0
1957 if(NIC_8187 == priv->card_8187) {
1958
1959 printk("This is RTL8187 Reset procedure\n");
1960 rtl8192_set_mode(dev,EPROM_CMD_LOAD);
1961 force_pci_posting(dev);
1962 mdelay(200);
1963
1964 /* after the eeprom load cycle, make sure we have
1965 * correct anaparams
1966 */
1967 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1968 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1969 }
1970 else
1971#endif
1972 printk("This is RTL8187B Reset procedure\n");
1973
1974}
1975#endif
1976inline u16 ieeerate2rtlrate(int rate)
1977{
1978 switch(rate){
1979 case 10:
1980 return 0;
1981 case 20:
1982 return 1;
1983 case 55:
1984 return 2;
1985 case 110:
1986 return 3;
1987 case 60:
1988 return 4;
1989 case 90:
1990 return 5;
1991 case 120:
1992 return 6;
1993 case 180:
1994 return 7;
1995 case 240:
1996 return 8;
1997 case 360:
1998 return 9;
1999 case 480:
2000 return 10;
2001 case 540:
2002 return 11;
2003 default:
2004 return 3;
2005
2006 }
2007}
2008static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540};
2009inline u16 rtl8192_rate2rate(short rate)
2010{
2011 if (rate >11) return 0;
2012 return rtl_rate[rate];
2013}
2014
5f53d8ca 2015static void rtl8192_rx_isr(struct urb *urb)
5f53d8ca
JC		 2016{
2017 struct sk_buff *skb = (struct sk_buff *) urb->context;
2018 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
2019 struct net_device *dev = info->dev;
2020 struct r8192_priv *priv = ieee80211_priv(dev);
2021 int out_pipe = info->out_pipe;
2022 int err;
2023 if(!priv->up)
2024 return;
2025 if (unlikely(urb->status)) {
2026 info->urb = NULL;
2027 priv->stats.rxstaterr++;
2028 priv->ieee80211->stats.rx_errors++;
2029 usb_free_urb(urb);
2030 // printk("%s():rx status err\n",__FUNCTION__);
2031 return;
2032 }
1ec9e48d 2033
5f53d8ca 2034 skb_unlink(skb, &priv->rx_queue);
5f53d8ca
JC		 2035 skb_put(skb, urb->actual_length);
2036
2037 skb_queue_tail(&priv->skb_queue, skb);
2038 tasklet_schedule(&priv->irq_rx_tasklet);
2039
2040 skb = dev_alloc_skb(RX_URB_SIZE);
2041 if (unlikely(!skb)) {
2042 usb_free_urb(urb);
2043 printk("%s():can,t alloc skb\n",__FUNCTION__);
2044 /* TODO check rx queue length and refill *somewhere* */
2045 return;
2046 }
2047
2048 usb_fill_bulk_urb(urb, priv->udev,
2049 usb_rcvbulkpipe(priv->udev, out_pipe), skb->tail,
2050 RX_URB_SIZE, rtl8192_rx_isr, skb);
2051
2052 info = (struct rtl8192_rx_info *) skb->cb;
2053 info->urb = urb;
2054 info->dev = dev;
2055 info->out_pipe = out_pipe;
2056
2057 urb->transfer_buffer = skb->tail;
2058 urb->context = skb;
2059 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 2060 err = usb_submit_urb(urb, GFP_ATOMIC);
5f53d8ca
JC		 2061 if(err && err != EPERM)
2062 printk("can not submit rxurb, err is %x,URB status is %x\n",err,urb->status);
2063}
2064
2065u32
2066rtl819xusb_rx_command_packet(
2067 struct net_device *dev,
2068 struct ieee80211_rx_stats *pstats
2069 )
2070{
2071 u32 status;
2072
2073 //RT_TRACE(COMP_RECV, DBG_TRACE, ("---> RxCommandPacketHandle819xUsb()\n"));
2074
2075 status = cmpk_message_handle_rx(dev, pstats);
2076 if (status)
2077 {
2078 DMESG("rxcommandpackethandle819xusb: It is a command packet\n");
2079 }
2080 else
2081 {
2082 //RT_TRACE(COMP_RECV, DBG_TRACE, ("RxCommandPacketHandle819xUsb: It is not a command packet\n"));
2083 }
2084
2085 //RT_TRACE(COMP_RECV, DBG_TRACE, ("<--- RxCommandPacketHandle819xUsb()\n"));
2086 return status;
2087}
2088
2089#if 0
2090void rtl8192_tx_queues_stop(struct net_device *dev)
2091{
2092 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2093 u8 dma_poll_mask = (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2094 dma_poll_mask |= (1<<TX_DMA_STOP_HIPRIORITY_SHIFT);
2095 dma_poll_mask |= (1<<TX_DMA_STOP_NORMPRIORITY_SHIFT);
2096 dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
2097
2098 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2099 write_nic_byte(dev,TX_DMA_POLLING,dma_poll_mask);
2100 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2101}
2102#endif
2103
2104void rtl8192_data_hard_stop(struct net_device *dev)
2105{
2106 //FIXME !!
2107 #if 0
2108 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2109 priv->dma_poll_mask |= (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2110 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2111 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
2112 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2113 #endif
2114}
2115
2116
2117void rtl8192_data_hard_resume(struct net_device *dev)
2118{
2119 // FIXME !!
2120 #if 0
2121 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2122 priv->dma_poll_mask &= ~(1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2123 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2124 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
2125 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2126 #endif
2127}
2128
2129/* this function TX data frames when the ieee80211 stack requires this.
2130 * It checks also if we need to stop the ieee tx queue, eventually do it
2131 */
2132void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate)
2133{
2134 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2135 int ret;
2136 unsigned long flags;
2137 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2138 u8 queue_index = tcb_desc->queue_index;
2139
2140 /* shall not be referred by command packet */
2141 assert(queue_index != TXCMD_QUEUE);
2142
2143 spin_lock_irqsave(&priv->tx_lock,flags);
2144
2145 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
2146// tcb_desc->RATRIndex = 7;
2147// tcb_desc->bTxDisableRateFallBack = 1;
2148// tcb_desc->bTxUseDriverAssingedRate = 1;
2149 tcb_desc->bTxEnableFwCalcDur = 1;
2150 skb_push(skb, priv->ieee80211->tx_headroom);
2151 ret = priv->ops->rtl819x_tx(dev, skb);
2152
2153 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2154 //priv->ieee80211->stats.tx_packets++;
2155
2156 spin_unlock_irqrestore(&priv->tx_lock,flags);
2157
2158// return ret;
2159 return;
2160}
2161
2162/* This is a rough attempt to TX a frame
2163 * This is called by the ieee 80211 stack to TX management frames.
2164 * If the ring is full packet are dropped (for data frame the queue
2165 * is stopped before this can happen).
2166 */
2167int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
2168{
2169 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2170 int ret;
2171 unsigned long flags;
2172 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2173 u8 queue_index = tcb_desc->queue_index;
2174
2175
2176 spin_lock_irqsave(&priv->tx_lock,flags);
2177
2178 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
2179 if(queue_index == TXCMD_QUEUE) {
2180 skb_push(skb, USB_HWDESC_HEADER_LEN);
2181 priv->ops->rtl819x_tx_cmd(dev, skb);
2182 ret = 1;
2183 spin_unlock_irqrestore(&priv->tx_lock,flags);
2184 return ret;
2185 } else {
2186 skb_push(skb, priv->ieee80211->tx_headroom);
2187 ret = priv->ops->rtl819x_tx(dev, skb);
2188 }
2189
2190 spin_unlock_irqrestore(&priv->tx_lock,flags);
2191
2192 return ret;
2193}
2194
2195
2196void rtl8192_try_wake_queue(struct net_device *dev, int pri);
2197
2198#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
2199u16 DrvAggr_PaddingAdd(struct net_device *dev, struct sk_buff *skb)
2200{
2201 u16 PaddingNum = 256 - ((skb->len + TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES) % 256);
2202 return (PaddingNum&0xff);
2203}
2204
2205u8 MRateToHwRate8190Pci(u8 rate);
2206u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc);
2207u8 MapHwQueueToFirmwareQueue(u8 QueueID);
2208struct sk_buff *DrvAggr_Aggregation(struct net_device *dev, struct ieee80211_drv_agg_txb *pSendList)
2209{
5f53d8ca 2210 struct ieee80211_device *ieee = netdev_priv(dev);
5f53d8ca
JC		 2211 struct r8192_priv *priv = ieee80211_priv(dev);
2212 cb_desc *tcb_desc = NULL;
2213 u8 i;
2214 u32 TotalLength;
2215 struct sk_buff *skb;
2216 struct sk_buff *agg_skb;
2217 tx_desc_819x_usb_aggr_subframe *tx_agg_desc = NULL;
2218 tx_fwinfo_819x_usb *tx_fwinfo = NULL;
2219
2220 //
2221 // Local variable initialization.
2222 //
2223 /* first skb initialization */
2224 skb = pSendList->tx_agg_frames[0];
2225 TotalLength = skb->len;
2226
2227 /* Get the total aggregation length including the padding space and
2228 * sub frame header.
2229 */
2230 for(i = 1; i < pSendList->nr_drv_agg_frames; i++) {
2231 TotalLength += DrvAggr_PaddingAdd(dev, skb);
2232 skb = pSendList->tx_agg_frames[i];
2233 TotalLength += (skb->len + TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES);
2234 }
2235
2236 /* allocate skb to contain the aggregated packets */
2237 agg_skb = dev_alloc_skb(TotalLength + ieee->tx_headroom);
2238 memset(agg_skb->data, 0, agg_skb->len);
2239 skb_reserve(agg_skb, ieee->tx_headroom);
2240
2241// RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb));
2242 /* reserve info for first subframe Tx descriptor to be set in the tx function */
2243 skb = pSendList->tx_agg_frames[0];
2244 tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2245 tcb_desc->drv_agg_enable = 1;
2246 tcb_desc->pkt_size = skb->len;
2247 tcb_desc->DrvAggrNum = pSendList->nr_drv_agg_frames;
2248 printk("DrvAggNum = %d\n", tcb_desc->DrvAggrNum);
2249// RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb));
2250// printk("========>skb->data ======> \n");
2251// RT_DEBUG_DATA(COMP_SEND, skb->data, skb->len);
2252 memcpy(agg_skb->cb, skb->cb, sizeof(skb->cb));
2253 memcpy(skb_put(agg_skb,skb->len),skb->data,skb->len);
2254
2255 for(i = 1; i < pSendList->nr_drv_agg_frames; i++) {
2256 /* push the next sub frame to be 256 byte aline */
2257 skb_put(agg_skb,DrvAggr_PaddingAdd(dev,skb));
2258
2259 /* Subframe drv Tx descriptor and firmware info setting */
2260 skb = pSendList->tx_agg_frames[i];
2261 tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2262 tx_agg_desc = (tx_desc_819x_usb_aggr_subframe *)agg_skb->tail;
2263 tx_fwinfo = (tx_fwinfo_819x_usb *)(agg_skb->tail + sizeof(tx_desc_819x_usb_aggr_subframe));
2264
2265 memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
2266 /* DWORD 0 */
2267 tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0;
2268 tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
2269 tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
2270 tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc);
2271 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
2272 tx_fwinfo->AllowAggregation = 1;
2273 /* DWORD 1 */
2274 tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
2275 tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
2276 } else {
2277 tx_fwinfo->AllowAggregation = 0;
2278 /* DWORD 1 */
2279 tx_fwinfo->RxMF = 0;
2280 tx_fwinfo->RxAMD = 0;
2281 }
2282
2283 /* Protection mode related */
2284 tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0;
2285 tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0;
2286 tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0;
2287 tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0;
2288 tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
2289 tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0;
2290 tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0;
2291 tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
2292 (tcb_desc->bRTSUseShortGI?1:0);
2293
2294 /* Set Bandwidth and sub-channel settings. */
2295 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2296 {
2297 if(tcb_desc->bPacketBW) {
2298 tx_fwinfo->TxBandwidth = 1;
2299 tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
2300 } else {
2301 tx_fwinfo->TxBandwidth = 0;
2302 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
2303 }
2304 } else {
2305 tx_fwinfo->TxBandwidth = 0;
2306 tx_fwinfo->TxSubCarrier = 0;
2307 }
2308
2309 /* Fill Tx descriptor */
2310 memset(tx_agg_desc, 0, sizeof(tx_desc_819x_usb_aggr_subframe));
2311 /* DWORD 0 */
2312 //tx_agg_desc->LINIP = 0;
2313 //tx_agg_desc->CmdInit = 1;
2314 tx_agg_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8;
2315 /* already raw data, need not to substract header length */
2316 tx_agg_desc->PktSize = skb->len & 0xffff;
2317
2318 /*DWORD 1*/
2319 tx_agg_desc->SecCAMID= 0;
2320 tx_agg_desc->RATid = tcb_desc->RATRIndex;
2321#if 0
2322 /* Fill security related */
2323 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
2324 {
2325 EncAlg = SecGetEncryptionOverhead(
2326 Adapter,
2327 &EncryptionMPDUHeadOverhead,
2328 &EncryptionMPDUTailOverhead,
2329 NULL,
2330 NULL,
2331 FALSE,
2332 FALSE);
2333 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
2334 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
2335 MPDUOverhead = EncryptionMPDUTailOverhead;
2336 tx_agg_desc->NoEnc = 0;
2337 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_agg_desc->SecCAMID,tx_agg_desc->SecDescAssign,EncAlg));
2338 //CamDumpAll(Adapter);
2339 }
2340 else
2341#endif
2342 {
2343 //MPDUOverhead = 0;
2344 tx_agg_desc->NoEnc = 1;
2345 }
2346#if 0
2347 switch(EncAlg){
2348 case NO_Encryption:
2349 tx_agg_desc->SecType = 0x0;
2350 break;
2351 case WEP40_Encryption:
2352 case WEP104_Encryption:
2353 tx_agg_desc->SecType = 0x1;
2354 break;
2355 case TKIP_Encryption:
2356 tx_agg_desc->SecType = 0x2;
2357 break;
2358 case AESCCMP_Encryption:
2359 tx_agg_desc->SecType = 0x3;
2360 break;
2361 default:
2362 tx_agg_desc->SecType = 0x0;
2363 break;
2364 }
2365#else
2366 tx_agg_desc->SecType = 0x0;
2367#endif
2368
2369 if (tcb_desc->bHwSec) {
2370 switch (priv->ieee80211->pairwise_key_type)
2371 {
2372 case KEY_TYPE_WEP40:
2373 case KEY_TYPE_WEP104:
2374 tx_agg_desc->SecType = 0x1;
2375 tx_agg_desc->NoEnc = 0;
2376 break;
2377 case KEY_TYPE_TKIP:
2378 tx_agg_desc->SecType = 0x2;
2379 tx_agg_desc->NoEnc = 0;
2380 break;
2381 case KEY_TYPE_CCMP:
2382 tx_agg_desc->SecType = 0x3;
2383 tx_agg_desc->NoEnc = 0;
2384 break;
2385 case KEY_TYPE_NA:
2386 tx_agg_desc->SecType = 0x0;
2387 tx_agg_desc->NoEnc = 1;
2388 break;
2389 }
2390 }
2391
2392 tx_agg_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
2393 tx_agg_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);
2394
2395 tx_agg_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
2396 tx_agg_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
2397
2398 tx_agg_desc->OWN = 1;
2399
2400 //DWORD 2
2401 /* According windows driver, it seems that there no need to fill this field */
2402 //tx_agg_desc->TxBufferSize= (u32)(skb->len - USB_HWDESC_HEADER_LEN);
2403
2404 /* to fill next packet */
2405 skb_put(agg_skb,TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES);
2406 memcpy(skb_put(agg_skb,skb->len),skb->data,skb->len);
2407 }
2408
2409 for(i = 0; i < pSendList->nr_drv_agg_frames; i++) {
2410 dev_kfree_skb_any(pSendList->tx_agg_frames[i]);
2411 }
2412
2413 return agg_skb;
2414}
2415
2416/* NOTE:
2417 This function return a list of PTCB which is proper to be aggregate with the input TCB.
2418 If no proper TCB is found to do aggregation, SendList will only contain the input TCB.
2419*/
2420u8 DrvAggr_GetAggregatibleList(struct net_device *dev, struct sk_buff *skb,
2421 struct ieee80211_drv_agg_txb *pSendList)
2422{
5f53d8ca 2423 struct ieee80211_device *ieee = netdev_priv(dev);
5f53d8ca
JC		 2424 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
2425 u16 nMaxAggrNum = pHTInfo->UsbTxAggrNum;
2426 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2427 u8 QueueID = tcb_desc->queue_index;
2428
2429 do {
2430 pSendList->tx_agg_frames[pSendList->nr_drv_agg_frames++] = skb;
2431 if(pSendList->nr_drv_agg_frames >= nMaxAggrNum) {
2432 break;
2433 }
2434
2435 } while((skb = skb_dequeue(&ieee->skb_drv_aggQ[QueueID])));
2436
2437 RT_TRACE(COMP_AMSDU, "DrvAggr_GetAggregatibleList, nAggrTcbNum = %d \n", pSendList->nr_drv_agg_frames);
2438 return pSendList->nr_drv_agg_frames;
2439}
2440#endif
2441
5f53d8ca 2442static void rtl8192_tx_isr(struct urb *tx_urb)
5f53d8ca
JC		 2443{
2444 struct sk_buff *skb = (struct sk_buff*)tx_urb->context;
2445 struct net_device *dev = NULL;
2446 struct r8192_priv *priv = NULL;
2447 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2448 u8 queue_index = tcb_desc->queue_index;
2449// bool bToSend0Byte;
2450// u16 BufLen = skb->len;
2451
2452 memcpy(&dev,(struct net_device*)(skb->cb),sizeof(struct net_device*));
2453 priv = ieee80211_priv(dev);
2454
2455 if(tcb_desc->queue_index != TXCMD_QUEUE) {
2456 if(tx_urb->status == 0) {
2457 // dev->trans_start = jiffies;
2458 // As act as station mode, destion shall be unicast address.
2459 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2460 //priv->ieee80211->stats.tx_packets++;
2461 priv->stats.txoktotal++;
2462 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
2463 priv->stats.txbytesunicast += (skb->len - priv->ieee80211->tx_headroom);
2464 } else {
2465 priv->ieee80211->stats.tx_errors++;
2466 //priv->stats.txmanageerr++;
2467 /* TODO */
2468 }
2469 }
2470
2471 /* free skb and tx_urb */
2472 if(skb != NULL) {
2473 dev_kfree_skb_any(skb);
2474 usb_free_urb(tx_urb);
2475 atomic_dec(&priv->tx_pending[queue_index]);
2476 }
2477
2478#if 0 //we need to send zero byte packet just after 512 byte(64 byte)packet is transmitted, or we will halt. It will greatly reduced available page in FW, and ruin our throughput. WB 2008.08.27
2479 if(BufLen > 0 && ((BufLen % 512 == 0)||(BufLen % 64 == 0))) {
2480 bToSend0Byte = true;
2481 }
2482
2483 bToSend0Byte = false;
2484 //
2485 // Note that, we at most handle 1 MPDU to send here, either
2486 // fragment or MPDU in wait queue.
2487 //
2488 if(!bToSend0Byte)
2489#endif
2490 {
2491 //
2492 // Handle HW Beacon:
2493 // We had transfer our beacon frame to host controler at this moment.
2494 //
2495#if 0
2496 if(tcb_desc->tx_queue == BEACON_QUEUE)
2497 {
2498 priv->bSendingBeacon = FALSE;
2499 }
2500#endif
2501 //
2502 // Caution:
2503 // Handling the wait queue of command packets.
2504 // For Tx command packets, we must not do TCB fragment because it is not handled right now.
2505 // We must cut the packets to match the size of TX_CMD_PKT before we send it.
2506 //
2507 if (queue_index == MGNT_QUEUE){
2508 if (priv->ieee80211->ack_tx_to_ieee){
2509 if (rtl8192_is_tx_queue_empty(dev)){
2510 priv->ieee80211->ack_tx_to_ieee = 0;
2511 ieee80211_ps_tx_ack(priv->ieee80211, 1);
2512 }
2513 }
2514 }
2515 /* Handle MPDU in wait queue. */
2516 if(queue_index != BEACON_QUEUE) {
2517 /* Don't send data frame during scanning.*/
2518 if((skb_queue_len(&priv->ieee80211->skb_waitQ[queue_index]) != 0)&&\
2519 (!(priv->ieee80211->queue_stop))) {
2520 if(NULL != (skb = skb_dequeue(&(priv->ieee80211->skb_waitQ[queue_index]))))
2521 priv->ieee80211->softmac_hard_start_xmit(skb, dev);
2522
2523 return; //modified by david to avoid further processing AMSDU
2524 }
2525#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
2526 else if ((skb_queue_len(&priv->ieee80211->skb_drv_aggQ[queue_index])!= 0)&&\
2527 (!(priv->ieee80211->queue_stop))) {
2528 // Tx Driver Aggregation process
2529 /* The driver will aggregation the packets according to the following stets
2530 * 1. check whether there's tx irq available, for it's a completion return
2531 * function, it should contain enough tx irq;
2532 * 2. check pakcet type;
2533 * 3. intialize sendlist, check whether the to-be send packet no greater than 1
2534 * 4. aggregation the packets, and fill firmware info and tx desc to it, etc.
2535 * 5. check whehter the packet could be sent, otherwise just insert to wait head
2536 * */
2537 skb = skb_dequeue(&priv->ieee80211->skb_drv_aggQ[queue_index]);
2538 if(!check_nic_enough_desc(dev, queue_index)) {
2539 skb_queue_head(&(priv->ieee80211->skb_drv_aggQ[queue_index]), skb);
2540 return;
2541 }
2542
2543 {
2544 /*TODO*/
2545 /*
2546 u8* pHeader = skb->data;
2547
2548 if(IsMgntQosData(pHeader) ||
2549 IsMgntQData_Ack(pHeader) ||
2550 IsMgntQData_Poll(pHeader) ||
2551 IsMgntQData_Poll_Ack(pHeader)
2552 )
2553 */
2554 {
2555 struct ieee80211_drv_agg_txb SendList;
2556
2557 memset(&SendList, 0, sizeof(struct ieee80211_drv_agg_txb));
2558 if(DrvAggr_GetAggregatibleList(dev, skb, &SendList) > 1) {
2559 skb = DrvAggr_Aggregation(dev, &SendList);
2560
2561#if 0
2562 printk("=============>to send aggregated packet!\n");
2563 RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb));
2564 printk("\n=================skb->len = %d\n", skb->len);
2565 RT_DEBUG_DATA(COMP_SEND, skb->data, skb->len);
2566#endif
2567 }
2568 }
2569 priv->ieee80211->softmac_hard_start_xmit(skb, dev);
2570 }
2571 }
2572#endif
2573 }
2574 }
2575
2576#if 0
2577 else
2578 {
2579 RT_TRACE( COMP_SEND,"HalUsbOutComplete(%d): bToSend0Byte.\n", PipeIndex);
2580
2581 //
2582 // In this case, we don't return skb now.
2583 // It will be returned when the 0-byte request completed.
2584 //
2585
2586 //
2587 // Bulk out an 0-byte padding transfer.
2588 //
2589 HalUsbOut0Byte(pAdapter, PipeIndex, skb);
2590 }
2591
2592#endif
2593}
2594
2595void rtl8192_beacon_stop(struct net_device *dev)
2596{
2597 u8 msr, msrm, msr2;
2598 struct r8192_priv *priv = ieee80211_priv(dev);
2599
2600 msr = read_nic_byte(dev, MSR);
2601 msrm = msr & MSR_LINK_MASK;
2602 msr2 = msr & ~MSR_LINK_MASK;
2603
2604 if(NIC_8192U == priv->card_8192) {
2605 usb_kill_urb(priv->rx_urb[MAX_RX_URB]);
2606 }
2607 if ((msrm == (MSR_LINK_ADHOC<<MSR_LINK_SHIFT) ||
2608 (msrm == (MSR_LINK_MASTER<<MSR_LINK_SHIFT)))){
2609 write_nic_byte(dev, MSR, msr2 | MSR_LINK_NONE);
2610 write_nic_byte(dev, MSR, msr);
2611 }
2612}
2613
2614void rtl8192_config_rate(struct net_device* dev, u16* rate_config)
2615{
2616 struct r8192_priv *priv = ieee80211_priv(dev);
2617 struct ieee80211_network *net;
2618 u8 i=0, basic_rate = 0;
2619 net = & priv->ieee80211->current_network;
2620
2621 for (i=0; i<net->rates_len; i++)
2622 {
2623 basic_rate = net->rates[i]&0x7f;
2624 switch(basic_rate)
2625 {
2626 case MGN_1M: *rate_config |= RRSR_1M; break;
2627 case MGN_2M: *rate_config |= RRSR_2M; break;
2628 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2629 case MGN_11M: *rate_config |= RRSR_11M; break;
2630 case MGN_6M: *rate_config |= RRSR_6M; break;
2631 case MGN_9M: *rate_config |= RRSR_9M; break;
2632 case MGN_12M: *rate_config |= RRSR_12M; break;
2633 case MGN_18M: *rate_config |= RRSR_18M; break;
2634 case MGN_24M: *rate_config |= RRSR_24M; break;
2635 case MGN_36M: *rate_config |= RRSR_36M; break;
2636 case MGN_48M: *rate_config |= RRSR_48M; break;
2637 case MGN_54M: *rate_config |= RRSR_54M; break;
2638 }
2639 }
2640 for (i=0; i<net->rates_ex_len; i++)
2641 {
2642 basic_rate = net->rates_ex[i]&0x7f;
2643 switch(basic_rate)
2644 {
2645 case MGN_1M: *rate_config |= RRSR_1M; break;
2646 case MGN_2M: *rate_config |= RRSR_2M; break;
2647 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2648 case MGN_11M: *rate_config |= RRSR_11M; break;
2649 case MGN_6M: *rate_config |= RRSR_6M; break;
2650 case MGN_9M: *rate_config |= RRSR_9M; break;
2651 case MGN_12M: *rate_config |= RRSR_12M; break;
2652 case MGN_18M: *rate_config |= RRSR_18M; break;
2653 case MGN_24M: *rate_config |= RRSR_24M; break;
2654 case MGN_36M: *rate_config |= RRSR_36M; break;
2655 case MGN_48M: *rate_config |= RRSR_48M; break;
2656 case MGN_54M: *rate_config |= RRSR_54M; break;
2657 }
2658 }
2659}
2660
2661
2662#define SHORT_SLOT_TIME 9
2663#define NON_SHORT_SLOT_TIME 20
2664
2665void rtl8192_update_cap(struct net_device* dev, u16 cap)
2666{
2667 //u32 tmp = 0;
2668 struct r8192_priv *priv = ieee80211_priv(dev);
2669 struct ieee80211_network *net = &priv->ieee80211->current_network;
2670 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
2671
2672 //LZM MOD 090303 HW_VAR_ACK_PREAMBLE
2673#ifdef RTL8192SU
2674 if(0)
2675 {
2676 u8 tmp = 0;
2677 tmp = ((priv->nCur40MhzPrimeSC) << 5);
2678 if (priv->short_preamble)
2679 tmp |= 0x80;
2680 write_nic_byte(dev, RRSR+2, tmp);
2681 }
2682#else
2683 {
2684 u32 tmp = 0;
2685 tmp = priv->basic_rate;
2686 if (priv->short_preamble)
2687 tmp |= BRSR_AckShortPmb;
2688 write_nic_dword(dev, RRSR, tmp);
2689 }
2690#endif
2691
2692 if (net->mode & (IEEE_G|IEEE_N_24G))
2693 {
2694 u8 slot_time = 0;
2695 if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime))
2696 {//short slot time
2697 slot_time = SHORT_SLOT_TIME;
2698 }
2699 else //long slot time
2700 slot_time = NON_SHORT_SLOT_TIME;
2701 priv->slot_time = slot_time;
2702 write_nic_byte(dev, SLOT_TIME, slot_time);
2703 }
2704
2705}
2706void rtl8192_net_update(struct net_device *dev)
2707{
2708
2709 struct r8192_priv *priv = ieee80211_priv(dev);
2710 struct ieee80211_network *net;
2711 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
2712 u16 rate_config = 0;
2713 net = & priv->ieee80211->current_network;
2714
2715 rtl8192_config_rate(dev, &rate_config);
2716 priv->basic_rate = rate_config &= 0x15f;
2717
2718 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
2719 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
2720 //for(i=0;i<ETH_ALEN;i++)
2721 // write_nic_byte(dev,BSSID+i,net->bssid[i]);
2722
2723 rtl8192_update_msr(dev);
2724// rtl8192_update_cap(dev, net->capability);
2725 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
2726 {
2727 write_nic_word(dev, ATIMWND, 2);
2728 write_nic_word(dev, BCN_DMATIME, 1023);
2729 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
2730// write_nic_word(dev, BcnIntTime, 100);
2731 write_nic_word(dev, BCN_DRV_EARLY_INT, 1);
2732 write_nic_byte(dev, BCN_ERR_THRESH, 100);
2733 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
2734 // TODO: BcnIFS may required to be changed on ASIC
2735 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
2736
2737 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
2738 }
2739
2740
2741
2742}
2743
2744//temporary hw beacon is not used any more.
2745//open it when necessary
2746#if 1
2747void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate)
2748{
2749
2750#if 0
2751 struct r8192_priv *priv = ieee80211_priv(dev);
2752 struct sk_buff *skb;
2753 int i = 0;
2754 //u8 cr;
2755
2756 rtl8192_net_update(dev);
2757
2758 skb = ieee80211_get_beacon(priv->ieee80211);
2759 if(!skb){
2760 DMESG("not enought memory for allocating beacon");
2761 return;
2762 }
2763
2764
2765 write_nic_byte(dev, BQREQ, read_nic_byte(dev, BQREQ) | (1<<7));
2766
2767 i=0;
2768 //while(!read_nic_byte(dev,BQREQ & (1<<7)))
2769 while( (read_nic_byte(dev, BQREQ) & (1<<7)) == 0 )
2770 {
2771 msleep_interruptible_rtl(HZ/2);
2772 if(i++ > 10){
2773 DMESGW("get stuck to wait HW beacon to be ready");
2774 return ;
2775 }
2776 }
2777 skb->cb[0] = NORM_PRIORITY;
2778 skb->cb[1] = 0; //morefragment = 0
2779 skb->cb[2] = ieeerate2rtlrate(tx_rate);
2780
2781 rtl8192_tx(dev,skb);
2782
2783#endif
2784}
2785#endif
2786inline u8 rtl8192_IsWirelessBMode(u16 rate)
2787{
2788 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
2789 return 1;
2790 else return 0;
2791}
2792
2793u16 N_DBPSOfRate(u16 DataRate);
2794
2795u16 ComputeTxTime(
2796 u16 FrameLength,
2797 u16 DataRate,
2798 u8 bManagementFrame,
2799 u8 bShortPreamble
2800)
2801{
2802 u16 FrameTime;
2803 u16 N_DBPS;
2804 u16 Ceiling;
2805
2806 if( rtl8192_IsWirelessBMode(DataRate) )
2807 {
2808 if( bManagementFrame || !bShortPreamble || DataRate == 10 )
2809 { // long preamble
2810 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
2811 }
2812 else
2813 { // Short preamble
2814 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
2815 }
2816 if( ( FrameLength*8 % (DataRate/10) ) != 0 ) //Get the Ceilling
2817 FrameTime ++;
2818 } else { //802.11g DSSS-OFDM PLCP length field calculation.
2819 N_DBPS = N_DBPSOfRate(DataRate);
2820 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
2821 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
2822 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
2823 }
2824 return FrameTime;
2825}
2826
2827u16 N_DBPSOfRate(u16 DataRate)
2828{
2829 u16 N_DBPS = 24;
2830
2831 switch(DataRate)
2832 {
2833 case 60:
2834 N_DBPS = 24;
2835 break;
2836
2837 case 90:
2838 N_DBPS = 36;
2839 break;
2840
2841 case 120:
2842 N_DBPS = 48;
2843 break;
2844
2845 case 180:
2846 N_DBPS = 72;
2847 break;
2848
2849 case 240:
2850 N_DBPS = 96;
2851 break;
2852
2853 case 360:
2854 N_DBPS = 144;
2855 break;
2856
2857 case 480:
2858 N_DBPS = 192;
2859 break;
2860
2861 case 540:
2862 N_DBPS = 216;
2863 break;
2864
2865 default:
2866 break;
2867 }
2868
2869 return N_DBPS;
2870}
2871
2872void rtl819xU_cmd_isr(struct urb *tx_cmd_urb, struct pt_regs *regs)
2873{
2874#if 0
2875 struct net_device *dev = (struct net_device*)tx_cmd_urb->context;
2876 struct r8192_priv *priv = ieee80211_priv(dev);
2877 int last_init_packet = 0;
2878 u8 *ptr_cmd_buf;
2879 u16 cmd_buf_len;
2880
2881 if(tx_cmd_urb->status != 0) {
2882 priv->pFirmware.firmware_seg_index = 0; //only begin transter, should it can be set to 1
2883 }
2884
2885 /* Free the urb and the corresponding buf for common Tx cmd packet, or
2886 * last segment of each firmware img.
2887 */
2888 if((priv->pFirmware.firmware_seg_index == 0) ||(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum)) {
2889 priv->pFirmware.firmware_seg_index = 0;//only begin transter, should it can be set to 1
2890 } else {
2891 /* prepare for last transfer */
2892 /* update some infomation for */
2893 /* last segment of the firmware img need indicate to device */
2894 priv->pFirmware.firmware_seg_index++;
2895 if(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum) {
2896 last_init_packet = 1;
2897 }
2898
2899 cmd_buf_len = priv->pFirmware.firmware_seg_container[priv->pFirmware.firmware_seg_index-1].seg_size;
2900 ptr_cmd_buf = priv->pFfirmware.firmware_seg_container[priv->pFfirmware.firmware_seg_index-1].seg_ptr;
2901 rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT);
2902 }
2903
2904 kfree(tx_cmd_urb->transfer_buffer);
2905#endif
2906 usb_free_urb(tx_cmd_urb);
2907}
2908
2909unsigned int txqueue2outpipe(struct r8192_priv* priv,unsigned int tx_queue) {
2910
2911 if(tx_queue >= 9)
2912 {
2913 RT_TRACE(COMP_ERR,"%s():Unknown queue ID!!!\n",__FUNCTION__);
2914 return 0x04;
2915 }
2916 return priv->txqueue_to_outpipemap[tx_queue];
2917}
2918
2919#ifdef RTL8192SU
2920short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
2921{
2922 struct r8192_priv *priv = ieee80211_priv(dev);
2923 int status;
2924 struct urb *tx_urb;
2925 unsigned int idx_pipe;
2926 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
2927 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2928 u8 queue_index = tcb_desc->queue_index;
2929 u32 PktSize = 0;
2930
2931 //printk("\n %s::::::::::::::::::::::queue_index = %d\n",__FUNCTION__, queue_index);
2932 atomic_inc(&priv->tx_pending[queue_index]);
2933
5f53d8ca 2934 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2935 if(!tx_urb){
2936 dev_kfree_skb(skb);
2937 return -ENOMEM;
2938 }
2939
2940 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
2941
2942 /* Tx descriptor ought to be set according to the skb->cb */
2943 pdesc->LINIP = tcb_desc->bLastIniPkt;
2944 PktSize = (u16)(skb->len - USB_HWDESC_HEADER_LEN);
2945 pdesc->PktSize = PktSize;
2946 //printk("PKTSize = %d %x\n",pdesc->PktSize,pdesc->PktSize);
2947 //----------------------------------------------------------------------------
2948 // Fill up USB_OUT_CONTEXT.
2949 //----------------------------------------------------------------------------
2950 // Get index to out pipe from specified QueueID.
2951 idx_pipe = txqueue2outpipe(priv,queue_index);
2952 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,queue_index,priv->RtOutPipes[idx_pipe]);
2953
2954#ifdef JOHN_DUMP_TXDESC
2955 int i;
2956 printk("Len = %d\n", skb->len);
2957 for (i = 0; i < 8; i++)
2958 printk("%2.2x ", *((u8*)skb->data+i));
2959 printk("\n");
2960#endif
2961
2962 usb_fill_bulk_urb(tx_urb,
2963 priv->udev,
2964 usb_sndbulkpipe(priv->udev,priv->RtOutPipes[idx_pipe]),
2965 skb->data,
2966 skb->len,
2967 rtl8192_tx_isr,
2968 skb);
2969
5f53d8ca 2970 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 2971 if (!status){
2972 return 0;
2973 }else{
2974 printk("Error TX CMD URB, error %d",
2975 status);
2976 return -1;
2977 }
2978}
2979#else
2980short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
2981{
2982 struct r8192_priv *priv = ieee80211_priv(dev);
2983 //u8 *tx;
2984 int status;
2985 struct urb *tx_urb;
2986 //int urb_buf_len;
2987 unsigned int idx_pipe;
2988 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
2989 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2990 u8 queue_index = tcb_desc->queue_index;
2991
2992 //printk("\n %s::queue_index = %d\n",__FUNCTION__, queue_index);
2993 atomic_inc(&priv->tx_pending[queue_index]);
1ec9e48d 2994
5f53d8ca 2995 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2996 if(!tx_urb){
2997 dev_kfree_skb(skb);
2998 return -ENOMEM;
2999 }
3000
3001 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
3002 /* Tx descriptor ought to be set according to the skb->cb */
3003 pdesc->FirstSeg = 1;//bFirstSeg;
3004 pdesc->LastSeg = 1;//bLastSeg;
3005 pdesc->CmdInit = tcb_desc->bCmdOrInit;
3006 pdesc->TxBufferSize = tcb_desc->txbuf_size;
3007 pdesc->OWN = 1;
3008 pdesc->LINIP = tcb_desc->bLastIniPkt;
3009
3010 //----------------------------------------------------------------------------
3011 // Fill up USB_OUT_CONTEXT.
3012 //----------------------------------------------------------------------------
3013 // Get index to out pipe from specified QueueID.
3014#ifndef USE_ONE_PIPE
3015 idx_pipe = txqueue2outpipe(priv,queue_index);
3016#else
3017 idx_pipe = 0x04;
3018#endif
3019#ifdef JOHN_DUMP_TXDESC
3020 int i;
3021 printk("<Tx descriptor>--rate %x---",rate);
3022 for (i = 0; i < 8; i++)
3023 printk("%8x ", tx[i]);
3024 printk("\n");
3025#endif
3026 usb_fill_bulk_urb(tx_urb,priv->udev, usb_sndbulkpipe(priv->udev,idx_pipe), \
3027 skb->data, skb->len, rtl8192_tx_isr, skb);
3028
5f53d8ca 3029 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 3030 if (!status){
3031 return 0;
3032 }else{
3033 DMESGE("Error TX CMD URB, error %d",
3034 status);
3035 return -1;
3036 }
3037}
3038#endif
3039
3040/*
3041 * Mapping Software/Hardware descriptor queue id to "Queue Select Field"
3042 * in TxFwInfo data structure
3043 * 2006.10.30 by Emily
3044 *
3045 * \param QUEUEID Software Queue
3046*/
3047u8 MapHwQueueToFirmwareQueue(u8 QueueID)
3048{
3049 u8 QueueSelect = 0x0; //defualt set to
3050
3051 switch(QueueID) {
3052 case BE_QUEUE:
3053 QueueSelect = QSLT_BE; //or QSelect = pTcb->priority;
3054 break;
3055
3056 case BK_QUEUE:
3057 QueueSelect = QSLT_BK; //or QSelect = pTcb->priority;
3058 break;
3059
3060 case VO_QUEUE:
3061 QueueSelect = QSLT_VO; //or QSelect = pTcb->priority;
3062 break;
3063
3064 case VI_QUEUE:
3065 QueueSelect = QSLT_VI; //or QSelect = pTcb->priority;
3066 break;
3067 case MGNT_QUEUE:
3068 QueueSelect = QSLT_MGNT;
3069 break;
3070
3071 case BEACON_QUEUE:
3072 QueueSelect = QSLT_BEACON;
3073 break;
3074
3075 // TODO: 2006.10.30 mark other queue selection until we verify it is OK
3076 // TODO: Remove Assertions
3077//#if (RTL819X_FPGA_VER & RTL819X_FPGA_GUANGAN_070502)
3078 case TXCMD_QUEUE:
3079 QueueSelect = QSLT_CMD;
3080 break;
3081//#endif
3082 case HIGH_QUEUE:
3083 QueueSelect = QSLT_HIGH;
3084 break;
3085
3086 default:
3087 RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID);
3088 break;
3089 }
3090 return QueueSelect;
3091}
3092
3093#ifdef RTL8192SU
3094u8 MRateToHwRate8190Pci(u8 rate)
3095{
3096 u8 ret = DESC92S_RATE1M;
3097
3098 switch(rate)
3099 {
3100 // CCK and OFDM non-HT rates
3101 case MGN_1M: ret = DESC92S_RATE1M; break;
3102 case MGN_2M: ret = DESC92S_RATE2M; break;
3103 case MGN_5_5M: ret = DESC92S_RATE5_5M; break;
3104 case MGN_11M: ret = DESC92S_RATE11M; break;
3105 case MGN_6M: ret = DESC92S_RATE6M; break;
3106 case MGN_9M: ret = DESC92S_RATE9M; break;
3107 case MGN_12M: ret = DESC92S_RATE12M; break;
3108 case MGN_18M: ret = DESC92S_RATE18M; break;
3109 case MGN_24M: ret = DESC92S_RATE24M; break;
3110 case MGN_36M: ret = DESC92S_RATE36M; break;
3111 case MGN_48M: ret = DESC92S_RATE48M; break;
3112 case MGN_54M: ret = DESC92S_RATE54M; break;
3113
3114 // HT rates since here
3115 case MGN_MCS0: ret = DESC92S_RATEMCS0; break;
3116 case MGN_MCS1: ret = DESC92S_RATEMCS1; break;
3117 case MGN_MCS2: ret = DESC92S_RATEMCS2; break;
3118 case MGN_MCS3: ret = DESC92S_RATEMCS3; break;
3119 case MGN_MCS4: ret = DESC92S_RATEMCS4; break;
3120 case MGN_MCS5: ret = DESC92S_RATEMCS5; break;
3121 case MGN_MCS6: ret = DESC92S_RATEMCS6; break;
3122 case MGN_MCS7: ret = DESC92S_RATEMCS7; break;
3123 case MGN_MCS8: ret = DESC92S_RATEMCS8; break;
3124 case MGN_MCS9: ret = DESC92S_RATEMCS9; break;
3125 case MGN_MCS10: ret = DESC92S_RATEMCS10; break;
3126 case MGN_MCS11: ret = DESC92S_RATEMCS11; break;
3127 case MGN_MCS12: ret = DESC92S_RATEMCS12; break;
3128 case MGN_MCS13: ret = DESC92S_RATEMCS13; break;
3129 case MGN_MCS14: ret = DESC92S_RATEMCS14; break;
3130 case MGN_MCS15: ret = DESC92S_RATEMCS15; break;
3131
3132 // Set the highest SG rate
3133 case MGN_MCS0_SG:
3134 case MGN_MCS1_SG:
3135 case MGN_MCS2_SG:
3136 case MGN_MCS3_SG:
3137 case MGN_MCS4_SG:
3138 case MGN_MCS5_SG:
3139 case MGN_MCS6_SG:
3140 case MGN_MCS7_SG:
3141 case MGN_MCS8_SG:
3142 case MGN_MCS9_SG:
3143 case MGN_MCS10_SG:
3144 case MGN_MCS11_SG:
3145 case MGN_MCS12_SG:
3146 case MGN_MCS13_SG:
3147 case MGN_MCS14_SG:
3148 case MGN_MCS15_SG:
3149 {
3150 ret = DESC92S_RATEMCS15_SG;
3151 break;
3152 }
3153
3154 default: break;
3155 }
3156 return ret;
3157}
3158#else
3159u8 MRateToHwRate8190Pci(u8 rate)
3160{
3161 u8 ret = DESC90_RATE1M;
3162
3163 switch(rate) {
3164 case MGN_1M: ret = DESC90_RATE1M; break;
3165 case MGN_2M: ret = DESC90_RATE2M; break;
3166 case MGN_5_5M: ret = DESC90_RATE5_5M; break;
3167 case MGN_11M: ret = DESC90_RATE11M; break;
3168 case MGN_6M: ret = DESC90_RATE6M; break;
3169 case MGN_9M: ret = DESC90_RATE9M; break;
3170 case MGN_12M: ret = DESC90_RATE12M; break;
3171 case MGN_18M: ret = DESC90_RATE18M; break;
3172 case MGN_24M: ret = DESC90_RATE24M; break;
3173 case MGN_36M: ret = DESC90_RATE36M; break;
3174 case MGN_48M: ret = DESC90_RATE48M; break;
3175 case MGN_54M: ret = DESC90_RATE54M; break;
3176
3177 // HT rate since here
3178 case MGN_MCS0: ret = DESC90_RATEMCS0; break;
3179 case MGN_MCS1: ret = DESC90_RATEMCS1; break;
3180 case MGN_MCS2: ret = DESC90_RATEMCS2; break;
3181 case MGN_MCS3: ret = DESC90_RATEMCS3; break;
3182 case MGN_MCS4: ret = DESC90_RATEMCS4; break;
3183 case MGN_MCS5: ret = DESC90_RATEMCS5; break;
3184 case MGN_MCS6: ret = DESC90_RATEMCS6; break;
3185 case MGN_MCS7: ret = DESC90_RATEMCS7; break;
3186 case MGN_MCS8: ret = DESC90_RATEMCS8; break;
3187 case MGN_MCS9: ret = DESC90_RATEMCS9; break;
3188 case MGN_MCS10: ret = DESC90_RATEMCS10; break;
3189 case MGN_MCS11: ret = DESC90_RATEMCS11; break;
3190 case MGN_MCS12: ret = DESC90_RATEMCS12; break;
3191 case MGN_MCS13: ret = DESC90_RATEMCS13; break;
3192 case MGN_MCS14: ret = DESC90_RATEMCS14; break;
3193 case MGN_MCS15: ret = DESC90_RATEMCS15; break;
3194 case (0x80|0x20): ret = DESC90_RATEMCS32; break;
3195
3196 default: break;
3197 }
3198 return ret;
3199}
3200#endif
3201
3202u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc)
3203{
3204 u8 tmp_Short;
3205
3206 tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0);
3207
3208 if(TxHT==1 && TxRate != DESC90_RATEMCS15)
3209 tmp_Short = 0;
3210
3211 return tmp_Short;
3212}
3213
5f53d8ca 3214static void tx_zero_isr(struct urb *tx_urb)
5f53d8ca
JC		 3215{
3216 return;
3217}
3218
3219
3220#ifdef RTL8192SU
3221/*
3222 * The tx procedure is just as following, skb->cb will contain all the following
3223 *information: * priority, morefrag, rate, &dev.
3224 * */
3225 // <Note> Buffer format for 8192S Usb bulk out:
3226//
3227// --------------------------------------------------
3228// | 8192S Usb Tx Desc | 802_11_MAC_header | data |
3229// --------------------------------------------------
3230// | 32 bytes | 24 bytes |0-2318 bytes|
3231// --------------------------------------------------
3232// |<------------ BufferLen ------------------------->|
3233
3234short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb)
3235{
3236 struct r8192_priv *priv = ieee80211_priv(dev);
3237 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3238 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
3239 //tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);//92su del
3240 struct usb_device *udev = priv->udev;
3241 int pend;
3242 int status;
3243 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
3244 //int urb_len;
3245 unsigned int idx_pipe;
3246 u16 MPDUOverhead = 0;
3247 //RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
3248
3249#if 0
3250 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
3251 RT_ENC_ALG EncAlg = NO_Encryption;
3252#endif
3253
3254
3255 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
3256 /* we are locked here so the two atomic_read and inc are executed
3257 * without interleaves * !!! For debug purpose */
3258 if( pend > MAX_TX_URB){
3259 switch (tcb_desc->queue_index) {
3260 case VO_PRIORITY:
3261 priv->stats.txvodrop++;
3262 break;
3263 case VI_PRIORITY:
3264 priv->stats.txvidrop++;
3265 break;
3266 case BE_PRIORITY:
3267 priv->stats.txbedrop++;
3268 break;
3269 default://BK_PRIORITY
3270 priv->stats.txbkdrop++;
3271 break;
3272 }
3273 printk("To discard skb packet!\n");
3274 dev_kfree_skb_any(skb);
3275 return -1;
3276 }
3277
5f53d8ca 3278 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3279 if(!tx_urb){
3280 dev_kfree_skb_any(skb);
3281 return -ENOMEM;
3282 }
3283
3284 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3285
3286
3287#if RTL8192SU_FPGA_UNSPECIFIED_NETWORK
3288 if(IsQoSDataFrame(skb->data))
3289 {
3290 tcb_desc->bAMPDUEnable = TRUE;
3291 tx_desc->NonQos = 0;
3292 }
3293 else
3294 tcb_desc->bAMPDUEnable = FALSE;
3295
3296 tcb_desc->bPacketBW = TRUE;
3297 priv->CurrentChannelBW = HT_CHANNEL_WIDTH_20_40;
3298#endif
3299
3300#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
3301 tx_desc->NonQos = (IsQoSDataFrame(skb->data)==TRUE)? 0:1;
3302#endif
3303
3304 /* Fill Tx descriptor */
3305 //memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
3306
3307 // This part can just fill to the first descriptor of the frame.
3308 /* DWORD 0 */
3309 tx_desc->TxHT = (tcb_desc->data_rate&0x80)?1:0;
3310
3311#ifdef RTL8192SU_DISABLE_CCK_RATE
3312 if(tx_hal_is_cck_rate(tcb_desc->data_rate))
3313 tcb_desc->data_rate = MGN_6M;
3314#endif
3315
3316 tx_desc->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
3317 //tx_desc->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
3318 tx_desc->TxShort = QueryIsShort(tx_desc->TxHT, tx_desc->TxRate, tcb_desc);
3319
3320
3321 // Aggregation related
3322 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
3323 tx_desc->AllowAggregation = 1;
3324 /* DWORD 1 */
3325 //tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
3326 //tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
3327 } else {
3328 tx_desc->AllowAggregation = 0;
3329 /* DWORD 1 */
3330 //tx_fwinfo->RxMF = 0;
3331 //tx_fwinfo->RxAMD = 0;
3332 }
3333
3334 //
3335 // <Roger_Notes> For AMPDU case, we must insert SSN into TX_DESC,
3336 // FW according as this SSN to do necessary packet retry.
3337 // 2008.06.06.
3338 //
3339 {
3340 u8 *pSeq;
3341 u16 Temp;
3342 //pSeq = (u8 *)(VirtualAddress+USB_HWDESC_HEADER_LEN + FRAME_OFFSET_SEQUENCE);
3343 pSeq = (u8 *)(skb->data+USB_HWDESC_HEADER_LEN + 22);
3344 Temp = pSeq[0];
3345 Temp <<= 12;
3346 Temp |= (*(u16 *)pSeq)>>4;
3347 tx_desc->Seq = Temp;
3348 }
3349
3350 /* Protection mode related */
3351 tx_desc->RTSEn = (tcb_desc->bRTSEnable)?1:0;
3352 tx_desc->CTS2Self = (tcb_desc->bCTSEnable)?1:0;
3353 tx_desc->RTSSTBC = (tcb_desc->bRTSSTBC)?1:0;
3354 tx_desc->RTSHT = (tcb_desc->rts_rate&0x80)?1:0;
3355 tx_desc->RTSRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
3356 tx_desc->RTSSubcarrier = (tx_desc->RTSHT==0)?(tcb_desc->RTSSC):0;
3357 tx_desc->RTSBW = (tx_desc->RTSHT==1)?((tcb_desc->bRTSBW)?1:0):0;
3358 tx_desc->RTSShort = (tx_desc->RTSHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
3359 (tcb_desc->bRTSUseShortGI?1:0);
3360 //LZM 090219
3361 tx_desc->DisRTSFB = 0;
3362 tx_desc->RTSRateFBLmt = 0xf;
3363
3364 // <Roger_EXP> 2008.09.22. We disable RTS rate fallback temporarily.
3365 //tx_desc->DisRTSFB = 0x01;
3366
3367 /* Set Bandwidth and sub-channel settings. */
3368 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
3369 {
3370 if(tcb_desc->bPacketBW) {
3371 tx_desc->TxBandwidth = 1;
3372 tx_desc->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
3373 } else {
3374 tx_desc->TxBandwidth = 0;
3375 tx_desc->TxSubCarrier = priv->nCur40MhzPrimeSC;
3376 }
3377 } else {
3378 tx_desc->TxBandwidth = 0;
3379 tx_desc->TxSubCarrier = 0;
3380 }
3381
3382#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3383 if (tcb_desc->drv_agg_enable)
3384 {
3385 //tx_desc->Tx_INFO_RSVD = (tcb_desc->DrvAggrNum & 0x1f) << 1; //92su del
3386 }
3387#endif
3388
3389 //memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3390 /* DWORD 0 */
3391 tx_desc->LINIP = 0;
3392 //tx_desc->CmdInit = 1; //92su del
3393 tx_desc->Offset = USB_HWDESC_HEADER_LEN;
3394
3395#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3396 if (tcb_desc->drv_agg_enable) {
3397 tx_desc->PktSize = tcb_desc->pkt_size;//FIXLZM
3398 } else
3399#endif
3400 {
3401 tx_desc->PktSize = (skb->len - USB_HWDESC_HEADER_LEN) & 0xffff;
3402 }
3403
3404 /*DWORD 1*/
3405 //tx_desc->SecCAMID= 0;//92su del
3406 tx_desc->RaBRSRID= tcb_desc->RATRIndex;
3407//#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE
3408#if 0//LZM 090219
3409 tx_desc->RaBRSRID= 1;
3410#endif
3411
3412#if 0
3413 /* Fill security related */
3414 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
3415 {
3416 EncAlg = SecGetEncryptionOverhead(
3417 Adapter,
3418 &EncryptionMPDUHeadOverhead,
3419 &EncryptionMPDUTailOverhead,
3420 NULL,
3421 NULL,
3422 FALSE,
3423 FALSE);
3424 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
3425 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
3426 MPDUOverhead = EncryptionMPDUTailOverhead;
3427 tx_desc->NoEnc = 0;
3428 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
3429 //CamDumpAll(Adapter);
3430 }
3431 else
3432#endif
3433 {
3434 MPDUOverhead = 0;
3435 //tx_desc->NoEnc = 1;//92su del
3436 }
3437#if 0
3438 switch(EncAlg){
3439 case NO_Encryption:
3440 tx_desc->SecType = 0x0;
3441 break;
3442 case WEP40_Encryption:
3443 case WEP104_Encryption:
3444 tx_desc->SecType = 0x1;
3445 break;
3446 case TKIP_Encryption:
3447 tx_desc->SecType = 0x2;
3448 break;
3449 case AESCCMP_Encryption:
3450 tx_desc->SecType = 0x3;
3451 break;
3452 default:
3453 tx_desc->SecType = 0x0;
3454 break;
3455 }
3456#else
3457 tx_desc->SecType = 0x0;
3458#endif
3459 if (tcb_desc->bHwSec)
3460 {
3461 switch (priv->ieee80211->pairwise_key_type)
3462 {
3463 case KEY_TYPE_WEP40:
3464 case KEY_TYPE_WEP104:
3465 tx_desc->SecType = 0x1;
3466 //tx_desc->NoEnc = 0;//92su del
3467 break;
3468 case KEY_TYPE_TKIP:
3469 tx_desc->SecType = 0x2;
3470 //tx_desc->NoEnc = 0;//92su del
3471 break;
3472 case KEY_TYPE_CCMP:
3473 tx_desc->SecType = 0x3;
3474 //tx_desc->NoEnc = 0;//92su del
3475 break;
3476 case KEY_TYPE_NA:
3477 tx_desc->SecType = 0x0;
3478 //tx_desc->NoEnc = 1;//92su del
3479 break;
3480 default:
3481 tx_desc->SecType = 0x0;
3482 //tx_desc->NoEnc = 1;//92su del
3483 break;
3484 }
3485 }
3486
3487 //tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);//92su del
3488
3489
3490 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
3491 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
3492 tx_desc->DataRateFBLmt = 0x1F;// Alwasy enable all rate fallback range
3493
3494 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
3495
3496
3497 /* Fill fields that are required to be initialized in all of the descriptors */
3498 //DWORD 0
3499#if 0
3500 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
3501 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
3502#else
3503 tx_desc->FirstSeg = 1;
3504 tx_desc->LastSeg = 1;
3505#endif
3506 tx_desc->OWN = 1;
3507
3508#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3509 if (tcb_desc->drv_agg_enable) {
3510 tx_desc->TxBufferSize = tcb_desc->pkt_size + sizeof(tx_fwinfo_819x_usb);
3511 } else
3512#endif
3513 {
3514 //DWORD 2
3515 //tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
3516 tx_desc->TxBufferSize = (u32)(skb->len);//92su mod FIXLZM
3517 }
3518
3519#if 0
3520 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(1)TxFillDescriptor8192SUsb(): DataRate(%#x)\n", pTcb->DataRate));
3521 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(2)TxFillDescriptor8192SUsb(): bTxUseDriverAssingedRate(%#x)\n", pTcb->bTxUseDriverAssingedRate));
3522 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(3)TxFillDescriptor8192SUsb(): bAMPDUEnable(%d)\n", pTcb->bAMPDUEnable));
3523 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(4)TxFillDescriptor8192SUsb(): bRTSEnable(%d)\n", pTcb->bRTSEnable));
3524 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(5)TxFillDescriptor8192SUsb(): RTSRate(%#x)\n", pTcb->RTSRate));
3525 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(6)TxFillDescriptor8192SUsb(): bCTSEnable(%d)\n", pTcb->bCTSEnable));
3526 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(7)TxFillDescriptor8192SUsb(): bUseShortGI(%d)\n", pTcb->bUseShortGI));
3527 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(8)TxFillDescriptor8192SUsb(): bPacketBW(%d)\n", pTcb->bPacketBW));
3528 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(9)TxFillDescriptor8192SUsb(): CurrentChannelBW(%d)\n", pHalData->CurrentChannelBW));
3529 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(10)TxFillDescriptor8192SUsb(): bTxDisableRateFallBack(%d)\n", pTcb->bTxDisableRateFallBack));
3530 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(11)TxFillDescriptor8192SUsb(): RATRIndex(%d)\n", pTcb->RATRIndex));
3531#endif
3532
3533 /* Get index to out pipe from specified QueueID */
3534 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
3535 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,tcb_desc->queue_index,priv->RtOutPipes[idx_pipe]);
3536
3537 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
3538 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
3539
3540 /* To submit bulk urb */
3541 usb_fill_bulk_urb(tx_urb,
3542 udev,
3543 usb_sndbulkpipe(udev,priv->RtOutPipes[idx_pipe]),
3544 skb->data,
3545 skb->len, rtl8192_tx_isr, skb);
3546
5f53d8ca 3547 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 3548 if (!status){
3549//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
3550 bool bSend0Byte = false;
3551 u8 zero = 0;
3552 if(udev->speed == USB_SPEED_HIGH)
3553 {
3554 if (skb->len > 0 && skb->len % 512 == 0)
3555 bSend0Byte = true;
3556 }
3557 else
3558 {
3559 if (skb->len > 0 && skb->len % 64 == 0)
3560 bSend0Byte = true;
3561 }
3562 if (bSend0Byte)
3563 {
3564#if 1
5f53d8ca 3565 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3566 if(!tx_urb_zero){
3567 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
3568 return -ENOMEM;
3569 }
3570 usb_fill_bulk_urb(tx_urb_zero,udev,
3571 usb_sndbulkpipe(udev,idx_pipe), &zero,
3572 0, tx_zero_isr, dev);
5f53d8ca 3573 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
5f53d8ca
JC		 3574 if (status){
3575 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
3576 return -1;
3577 }
3578#endif
3579 }
3580 dev->trans_start = jiffies;
3581 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
3582 return 0;
3583 }else{
3584 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
3585 status);
3586 return -1;
3587 }
3588}
3589#else
3590
3591/*
3592 * The tx procedure is just as following,
3593 * skb->cb will contain all the following information,
3594 * priority, morefrag, rate, &dev.
3595 * */
3596short rtl8192_tx(struct net_device *dev, struct sk_buff* skb)
3597{
3598 struct r8192_priv *priv = ieee80211_priv(dev);
3599 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3600 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
3601 tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);
3602 struct usb_device *udev = priv->udev;
3603 int pend;
3604 int status;
3605 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
3606 //int urb_len;
3607 unsigned int idx_pipe;
3608// RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
3609#if 0
3610 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
3611 RT_ENC_ALG EncAlg = NO_Encryption;
3612#endif
3613// printk("=============> %s\n", __FUNCTION__);
3614 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
3615 /* we are locked here so the two atomic_read and inc are executed
3616 * without interleaves
3617 * !!! For debug purpose
3618 */
3619 if( pend > MAX_TX_URB){
3620#if 0
3621 switch (tcb_desc->queue_index) {
3622 case VO_PRIORITY:
3623 priv->stats.txvodrop++;
3624 break;
3625 case VI_PRIORITY:
3626 priv->stats.txvidrop++;
3627 break;
3628 case BE_PRIORITY:
3629 priv->stats.txbedrop++;
3630 break;
3631 default://BK_PRIORITY
3632 priv->stats.txbkdrop++;
3633 break;
3634 }
3635#endif
3636 printk("To discard skb packet!\n");
3637 dev_kfree_skb_any(skb);
3638 return -1;
3639 }
3640
5f53d8ca 3641 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3642 if(!tx_urb){
3643 dev_kfree_skb_any(skb);
3644 return -ENOMEM;
3645 }
3646
3647 /* Fill Tx firmware info */
3648 memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
3649 /* DWORD 0 */
3650 tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0;
3651 tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
3652 tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
3653 tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc);
3654 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
3655 tx_fwinfo->AllowAggregation = 1;
3656 /* DWORD 1 */
3657 tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
3658 tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
3659 } else {
3660 tx_fwinfo->AllowAggregation = 0;
3661 /* DWORD 1 */
3662 tx_fwinfo->RxMF = 0;
3663 tx_fwinfo->RxAMD = 0;
3664 }
3665
3666 /* Protection mode related */
3667 tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0;
3668 tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0;
3669 tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0;
3670 tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0;
3671 tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
3672 tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0;
3673 tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0;
3674 tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
3675 (tcb_desc->bRTSUseShortGI?1:0);
3676
3677 /* Set Bandwidth and sub-channel settings. */
3678 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
3679 {
3680 if(tcb_desc->bPacketBW) {
3681 tx_fwinfo->TxBandwidth = 1;
3682 tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
3683 } else {
3684 tx_fwinfo->TxBandwidth = 0;
3685 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
3686 }
3687 } else {
3688 tx_fwinfo->TxBandwidth = 0;
3689 tx_fwinfo->TxSubCarrier = 0;
3690 }
3691
3692#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3693 if (tcb_desc->drv_agg_enable)
3694 {
3695 tx_fwinfo->Tx_INFO_RSVD = (tcb_desc->DrvAggrNum & 0x1f) << 1;
3696 }
3697#endif
3698 /* Fill Tx descriptor */
3699 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3700 /* DWORD 0 */
3701 tx_desc->LINIP = 0;
3702 tx_desc->CmdInit = 1;
3703 tx_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8;
3704
3705#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3706 if (tcb_desc->drv_agg_enable) {
3707 tx_desc->PktSize = tcb_desc->pkt_size;
3708 } else
3709#endif
3710 {
3711 tx_desc->PktSize = (skb->len - TX_PACKET_SHIFT_BYTES) & 0xffff;
3712 }
3713
3714 /*DWORD 1*/
3715 tx_desc->SecCAMID= 0;
3716 tx_desc->RATid = tcb_desc->RATRIndex;
3717#if 0
3718 /* Fill security related */
3719 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
3720 {
3721 EncAlg = SecGetEncryptionOverhead(
3722 Adapter,
3723 &EncryptionMPDUHeadOverhead,
3724 &EncryptionMPDUTailOverhead,
3725 NULL,
3726 NULL,
3727 FALSE,
3728 FALSE);
3729 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
3730 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
3731 MPDUOverhead = EncryptionMPDUTailOverhead;
3732 tx_desc->NoEnc = 0;
3733 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
3734 //CamDumpAll(Adapter);
3735 }
3736 else
3737#endif
3738 {
3739 //MPDUOverhead = 0;
3740 tx_desc->NoEnc = 1;
3741 }
3742#if 0
3743 switch(EncAlg){
3744 case NO_Encryption:
3745 tx_desc->SecType = 0x0;
3746 break;
3747 case WEP40_Encryption:
3748 case WEP104_Encryption:
3749 tx_desc->SecType = 0x1;
3750 break;
3751 case TKIP_Encryption:
3752 tx_desc->SecType = 0x2;
3753 break;
3754 case AESCCMP_Encryption:
3755 tx_desc->SecType = 0x3;
3756 break;
3757 default:
3758 tx_desc->SecType = 0x0;
3759 break;
3760 }
3761#else
3762 tx_desc->SecType = 0x0;
3763#endif
3764 if (tcb_desc->bHwSec)
3765 {
3766 switch (priv->ieee80211->pairwise_key_type)
3767 {
3768 case KEY_TYPE_WEP40:
3769 case KEY_TYPE_WEP104:
3770 tx_desc->SecType = 0x1;
3771 tx_desc->NoEnc = 0;
3772 break;
3773 case KEY_TYPE_TKIP:
3774 tx_desc->SecType = 0x2;
3775 tx_desc->NoEnc = 0;
3776 break;
3777 case KEY_TYPE_CCMP:
3778 tx_desc->SecType = 0x3;
3779 tx_desc->NoEnc = 0;
3780 break;
3781 case KEY_TYPE_NA:
3782 tx_desc->SecType = 0x0;
3783 tx_desc->NoEnc = 1;
3784 break;
3785 }
3786 }
3787
3788 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
3789 tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);
3790
3791 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
3792 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
3793
3794 /* Fill fields that are required to be initialized in all of the descriptors */
3795 //DWORD 0
3796#if 0
3797 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
3798 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
3799#else
3800 tx_desc->FirstSeg = 1;
3801 tx_desc->LastSeg = 1;
3802#endif
3803 tx_desc->OWN = 1;
3804
3805#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3806 if (tcb_desc->drv_agg_enable) {
3807 tx_desc->TxBufferSize = tcb_desc->pkt_size + sizeof(tx_fwinfo_819x_usb);
3808 } else
3809#endif
3810 {
3811 //DWORD 2
3812 tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
3813 }
3814 /* Get index to out pipe from specified QueueID */
3815#ifndef USE_ONE_PIPE
3816 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
3817#else
3818 idx_pipe = 0x5;
3819#endif
3820
3821 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
3822 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
3823
3824 /* To submit bulk urb */
3825 usb_fill_bulk_urb(tx_urb,udev,
3826 usb_sndbulkpipe(udev,idx_pipe), skb->data,
3827 skb->len, rtl8192_tx_isr, skb);
3828
5f53d8ca 3829 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 3830 if (!status){
3831//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
3832 bool bSend0Byte = false;
3833 u8 zero = 0;
3834 if(udev->speed == USB_SPEED_HIGH)
3835 {
3836 if (skb->len > 0 && skb->len % 512 == 0)
3837 bSend0Byte = true;
3838 }
3839 else
3840 {
3841 if (skb->len > 0 && skb->len % 64 == 0)
3842 bSend0Byte = true;
3843 }
3844 if (bSend0Byte)
3845 {
3846#if 1
5f53d8ca 3847 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 3848 if(!tx_urb_zero){
3849 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
3850 return -ENOMEM;
3851 }
3852 usb_fill_bulk_urb(tx_urb_zero,udev,
3853 usb_sndbulkpipe(udev,idx_pipe), &zero,
3854 0, tx_zero_isr, dev);
5f53d8ca 3855 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
5f53d8ca
JC		 3856 if (status){
3857 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
3858 return -1;
3859 }
3860#endif
3861 }
3862 dev->trans_start = jiffies;
3863 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
3864 return 0;
3865 }else{
3866 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
3867 status);
3868 return -1;
3869 }
3870}
3871#endif
3872
3873#if 0
3874void rtl8192_set_rate(struct net_device *dev)
3875{
3876 int i;
3877 u16 word;
3878 int basic_rate,min_rr_rate,max_rr_rate;
3879
3880// struct r8192_priv *priv = ieee80211_priv(dev);
3881
3882 //if (ieee80211_is_54g(priv->ieee80211->current_network) &&
3883// priv->ieee80211->state == IEEE80211_LINKED){
3884 basic_rate = ieeerate2rtlrate(240);
3885 min_rr_rate = ieeerate2rtlrate(60);
3886 max_rr_rate = ieeerate2rtlrate(240);
3887
3888//
3889// }else{
3890// basic_rate = ieeerate2rtlrate(20);
3891// min_rr_rate = ieeerate2rtlrate(10);
3892// max_rr_rate = ieeerate2rtlrate(110);
3893// }
3894
3895 write_nic_byte(dev, RESP_RATE,
3896 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3897
3898 //word = read_nic_word(dev, BRSR);
3899 word = read_nic_word(dev, BRSR_8187);
3900 word &= ~BRSR_MBR_8185;
3901
3902
3903 for(i=0;i<=basic_rate;i++)
3904 word |= (1<<i);
3905
3906 //write_nic_word(dev, BRSR, word);
3907 write_nic_word(dev, BRSR_8187, word);
3908 //DMESG("RR:%x BRSR: %x", read_nic_byte(dev,RESP_RATE), read_nic_word(dev,BRSR));
3909}
3910#endif
3911
3912
3913#ifdef RTL8192SU
3914void rtl8192SU_net_update(struct net_device *dev)
3915{
3916
3917 struct r8192_priv *priv = ieee80211_priv(dev);
3918 struct ieee80211_device* ieee = priv->ieee80211;
3919 struct ieee80211_network *net = &priv->ieee80211->current_network;
3920 //u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
3921 u16 rate_config = 0;
3922 u32 regTmp = 0;
3923 u8 rateIndex = 0;
3924 u8 retrylimit = 0x30;
3925 u16 cap = net->capability;
3926
3927 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
3928
3929//HW_VAR_BASIC_RATE
3930 //update Basic rate: RR, BRSR
3931 rtl8192_config_rate(dev, &rate_config); //HalSetBrateCfg
3932
3933#ifdef RTL8192SU_DISABLE_CCK_RATE
3934 priv->basic_rate = rate_config = rate_config & 0x150; // Disable CCK 11M, 5.5M, 2M, and 1M rates.
3935#else
3936 priv->basic_rate = rate_config = rate_config & 0x15f;
3937#endif
3938
3939 // Set RRSR rate table.
3940 write_nic_byte(dev, RRSR, rate_config&0xff);
3941 write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff);
3942
3943 // Set RTS initial rate
3944 while(rate_config > 0x1)
3945 {
3946 rate_config = (rate_config>> 1);
3947 rateIndex++;
3948 }
3949 write_nic_byte(dev, INIRTSMCS_SEL, rateIndex);
3950//HW_VAR_BASIC_RATE
3951
3952 //set ack preample
3953 regTmp = (priv->nCur40MhzPrimeSC) << 5;
3954 if (priv->short_preamble)
3955 regTmp |= 0x80;
3956 write_nic_byte(dev, RRSR+2, regTmp);
3957
3958 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
3959 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
3960
3961 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
3962 //2008.10.24 added by tynli for beacon changed.
3963 PHY_SetBeaconHwReg( dev, net->beacon_interval);
3964
3965 rtl8192_update_cap(dev, cap);
3966
3967 if (ieee->iw_mode == IW_MODE_ADHOC){
3968 retrylimit = 7;
3969 //we should enable ibss interrupt here, but disable it temporarily
3970 if (0){
3971 priv->irq_mask |= (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3972 //rtl8192_irq_disable(dev);
3973 //rtl8192_irq_enable(dev);
3974 }
3975 }
3976 else{
3977 if (0){
3978 priv->irq_mask &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3979 //rtl8192_irq_disable(dev);
3980 //rtl8192_irq_enable(dev);
3981 }
3982 }
3983
3984 priv->ShortRetryLimit = priv->LongRetryLimit = retrylimit;
3985
3986 write_nic_word(dev, RETRY_LIMIT,
3987 retrylimit << RETRY_LIMIT_SHORT_SHIFT | \
3988 retrylimit << RETRY_LIMIT_LONG_SHIFT);
3989}
3990
3991void rtl8192SU_update_ratr_table(struct net_device* dev)
3992{
3993 struct r8192_priv* priv = ieee80211_priv(dev);
3994 struct ieee80211_device* ieee = priv->ieee80211;
3995 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
3996 //struct ieee80211_network *net = &ieee->current_network;
3997 u32 ratr_value = 0;
3998
3999 u8 rate_index = 0;
4000 int WirelessMode = ieee->mode;
4001 u8 MimoPs = ieee->pHTInfo->PeerMimoPs;
4002
4003 u8 bNMode = 0;
4004
4005 rtl8192_config_rate(dev, (u16*)(&ratr_value));
4006 ratr_value |= (*(u16*)(pMcsRate)) << 12;
4007
4008 //switch (ieee->mode)
4009 switch (WirelessMode)
4010 {
4011 case IEEE_A:
4012 ratr_value &= 0x00000FF0;
4013 break;
4014 case IEEE_B:
4015 ratr_value &= 0x0000000D;
4016 break;
4017 case IEEE_G:
4018 ratr_value &= 0x00000FF5;
4019 break;
4020 case IEEE_N_24G:
4021 case IEEE_N_5G:
4022 {
4023 bNMode = 1;
4024
4025 if (MimoPs == 0) //MIMO_PS_STATIC
4026 {
4027 ratr_value &= 0x0007F005;
4028 }
4029 else
4030 { // MCS rate only => for 11N mode.
4031 u32 ratr_mask;
4032
4033 // 1T2R or 1T1R, Spatial Stream 2 should be disabled
4034 if ( priv->rf_type == RF_1T2R ||
4035 priv->rf_type == RF_1T1R ||
4036 (ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_2SS) )
4037 ratr_mask = 0x000ff005;
4038 else
4039 ratr_mask = 0x0f0ff005;
4040
4041 if((ieee->pHTInfo->bCurTxBW40MHz) &&
4042 !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ))
4043 ratr_mask |= 0x00000010; // Set 6MBps
4044
4045 // Select rates for rate adaptive mechanism.
4046 ratr_value &= ratr_mask;
4047 }
4048 }
4049 break;
4050 default:
4051 if(0)
4052 {
4053 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
4054 {
4055 ratr_value &= 0x000ff0f5;
4056 }
4057 else
4058 {
4059 ratr_value &= 0x0f0ff0f5;
4060 }
4061 }
4062 //printk("====>%s(), mode is not correct:%x\n", __FUNCTION__, ieee->mode);
4063 break;
4064 }
4065
4066#ifdef RTL8192SU_DISABLE_CCK_RATE
4067 ratr_value &= 0x0FFFFFF0;
4068#else
4069 ratr_value &= 0x0FFFFFFF;
4070#endif
4071
4072 // Get MAX MCS available.
4073 if ( (bNMode && ((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0)) &&
4074 ((ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI40MHz) ||
4075 (!ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI20MHz)))
4076 {
4077 u8 shortGI_rate = 0;
4078 u32 tmp_ratr_value = 0;
4079 ratr_value |= 0x10000000;//???
4080 tmp_ratr_value = (ratr_value>>12);
4081 for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--)
4082 {
4083 if((1<<shortGI_rate) & tmp_ratr_value)
4084 break;
4085 }
4086 shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate);
4087 write_nic_byte(dev, SG_RATE, shortGI_rate);
4088 //printk("==>SG_RATE:%x\n", read_nic_byte(dev, SG_RATE));
4089 }
4090 write_nic_dword(dev, ARFR0+rate_index*4, ratr_value);
4091 printk("=============>ARFR0+rate_index*4:%#x\n", ratr_value);
4092
4093 //2 UFWP
4094 if (ratr_value & 0xfffff000){
4095 //printk("===>set to N mode\n");
4096 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_N);
4097 }
4098 else {
4099 //printk("===>set to B/G mode\n");
4100 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_BG);
4101 }
4102}
4103
4104void rtl8192SU_link_change(struct net_device *dev)
4105{
4106 struct r8192_priv *priv = ieee80211_priv(dev);
4107 struct ieee80211_device* ieee = priv->ieee80211;
4108 //unsigned long flags;
4109 u32 reg = 0;
4110
4111 printk("=====>%s 1\n", __func__);
4112 reg = read_nic_dword(dev, RCR);
4113
4114 if (ieee->state == IEEE80211_LINKED)
4115 {
4116
4117 rtl8192SU_net_update(dev);
4118 rtl8192SU_update_ratr_table(dev);
4119 ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE);
4120 priv->ReceiveConfig = reg |= RCR_CBSSID;
4121
4122 }else{
4123 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
4124
4125 }
4126
4127 write_nic_dword(dev, RCR, reg);
4128 rtl8192_update_msr(dev);
4129
4130 printk("<=====%s 2\n", __func__);
4131}
4132#else
4133extern void rtl8192_update_ratr_table(struct net_device* dev);
4134void rtl8192_link_change(struct net_device *dev)
4135{
4136// int i;
4137
4138 struct r8192_priv *priv = ieee80211_priv(dev);
4139 struct ieee80211_device* ieee = priv->ieee80211;
4140 //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval);
4141 if (ieee->state == IEEE80211_LINKED)
4142 {
4143 rtl8192_net_update(dev);
4144 rtl8192_update_ratr_table(dev);
4145#if 1
4146 //add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08
4147 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
4148 EnableHWSecurityConfig8192(dev);
4149#endif
4150 }
4151 /*update timing params*/
4152// RT_TRACE(COMP_CH, "========>%s(), chan:%d\n", __FUNCTION__, priv->chan);
4153// rtl8192_set_chan(dev, priv->chan);
4154 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
4155 {
4156 u32 reg = 0;
4157 reg = read_nic_dword(dev, RCR);
4158 if (priv->ieee80211->state == IEEE80211_LINKED)
4159 priv->ReceiveConfig = reg |= RCR_CBSSID;
4160 else
4161 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
4162 write_nic_dword(dev, RCR, reg);
4163 }
4164
4165// rtl8192_set_rxconf(dev);
4166}
4167#endif
4168
4169static struct ieee80211_qos_parameters def_qos_parameters = {
4170 {3,3,3,3},/* cw_min */
4171 {7,7,7,7},/* cw_max */
4172 {2,2,2,2},/* aifs */
4173 {0,0,0,0},/* flags */
4174 {0,0,0,0} /* tx_op_limit */
4175};
4176
4177
5f53d8ca
JC		 4178void rtl8192_update_beacon(struct work_struct * work)
4179{
4180 struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work);
4181 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 4182 struct ieee80211_device* ieee = priv->ieee80211;
4183 struct ieee80211_network* net = &ieee->current_network;
4184
4185 if (ieee->pHTInfo->bCurrentHTSupport)
4186 HTUpdateSelfAndPeerSetting(ieee, net);
4187 ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime;
4188 // Joseph test for turbo mode with AP
4189 ieee->pHTInfo->RT2RT_HT_Mode = net->bssht.RT2RT_HT_Mode;
4190 rtl8192_update_cap(dev, net->capability);
4191}
4192/*
4193* background support to run QoS activate functionality
4194*/
4195int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO};
1ec9e48d 4196
5f53d8ca
JC		 4197void rtl8192_qos_activate(struct work_struct * work)
4198{
4199 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
4200 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 4201 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
4202 u8 mode = priv->ieee80211->current_network.mode;
4203 //u32 size = sizeof(struct ieee80211_qos_parameters);
4204 u8 u1bAIFS;
4205 u32 u4bAcParam;
4206 int i;
4207
4208 if (priv == NULL)
4209 return;
4210
5f53d8ca 4211 mutex_lock(&priv->mutex);
1ec9e48d 4212
5f53d8ca
JC		 4213 if(priv->ieee80211->state != IEEE80211_LINKED)
4214 goto success;
4215 RT_TRACE(COMP_QOS,"qos active process with associate response received\n");
4216 /* It better set slot time at first */
4217 /* For we just support b/g mode at present, let the slot time at 9/20 selection */
4218 /* update the ac parameter to related registers */
4219 for(i = 0; i < QOS_QUEUE_NUM; i++) {
4220 //Mode G/A: slotTimeTimer = 9; Mode B: 20
4221 u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
4222 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
4223 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
4224 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
4225 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
4226
4227 write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
4228 //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4322);
4229 }
4230
4231success:
5f53d8ca 4232 mutex_unlock(&priv->mutex);
5f53d8ca
JC		 4233}
4234
4235static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv,
4236 int active_network,
4237 struct ieee80211_network *network)
4238{
4239 int ret = 0;
4240 u32 size = sizeof(struct ieee80211_qos_parameters);
4241
4242 if(priv->ieee80211->state !=IEEE80211_LINKED)
4243 return ret;
4244
4245 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
4246 return ret;
4247
4248 if (network->flags & NETWORK_HAS_QOS_MASK) {
4249 if (active_network &&
4250 (network->flags & NETWORK_HAS_QOS_PARAMETERS))
4251 network->qos_data.active = network->qos_data.supported;
4252
4253 if ((network->qos_data.active == 1) && (active_network == 1) &&
4254 (network->flags & NETWORK_HAS_QOS_PARAMETERS) &&
4255 (network->qos_data.old_param_count !=
4256 network->qos_data.param_count)) {
4257 network->qos_data.old_param_count =
4258 network->qos_data.param_count;
5f53d8ca 4259 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 4260 RT_TRACE (COMP_QOS, "QoS parameters change call "
4261 "qos_activate\n");
4262 }
4263 } else {
4264 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
4265 &def_qos_parameters, size);
4266
4267 if ((network->qos_data.active == 1) && (active_network == 1)) {
5f53d8ca 4268 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 4269 RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate \n");
4270 }
4271 network->qos_data.active = 0;
4272 network->qos_data.supported = 0;
4273 }
4274
4275 return 0;
4276}
4277
4278/* handle manage frame frame beacon and probe response */
4279static int rtl8192_handle_beacon(struct net_device * dev,
4280 struct ieee80211_beacon * beacon,
4281 struct ieee80211_network * network)
4282{
4283 struct r8192_priv *priv = ieee80211_priv(dev);
4284
4285 rtl8192_qos_handle_probe_response(priv,1,network);
5f53d8ca 4286 queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0);
5f53d8ca 4287
5f53d8ca
JC		 4288 return 0;
4289
4290}
4291
4292/*
4293* handling the beaconing responses. if we get different QoS setting
4294* off the network from the associated setting, adjust the QoS
4295* setting
4296*/
4297static int rtl8192_qos_association_resp(struct r8192_priv *priv,
4298 struct ieee80211_network *network)
4299{
4300 int ret = 0;
4301 unsigned long flags;
4302 u32 size = sizeof(struct ieee80211_qos_parameters);
4303 int set_qos_param = 0;
4304
4305 if ((priv == NULL) || (network == NULL))
4306 return ret;
4307
4308 if(priv->ieee80211->state !=IEEE80211_LINKED)
4309 return ret;
4310
4311 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
4312 return ret;
4313
4314 spin_lock_irqsave(&priv->ieee80211->lock, flags);
4315 if(network->flags & NETWORK_HAS_QOS_PARAMETERS) {
4316 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
4317 &network->qos_data.parameters,\
4318 sizeof(struct ieee80211_qos_parameters));
4319 priv->ieee80211->current_network.qos_data.active = 1;
4320#if 0
4321 if((priv->ieee80211->current_network.qos_data.param_count != \
4322 network->qos_data.param_count))
4323#endif
4324 {
4325 set_qos_param = 1;
4326 /* update qos parameter for current network */
4327 priv->ieee80211->current_network.qos_data.old_param_count = \
4328 priv->ieee80211->current_network.qos_data.param_count;
4329 priv->ieee80211->current_network.qos_data.param_count = \
4330 network->qos_data.param_count;
4331 }
4332 } else {
4333 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
4334 &def_qos_parameters, size);
4335 priv->ieee80211->current_network.qos_data.active = 0;
4336 priv->ieee80211->current_network.qos_data.supported = 0;
4337 set_qos_param = 1;
4338 }
4339
4340 spin_unlock_irqrestore(&priv->ieee80211->lock, flags);
4341
4342 RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n",__FUNCTION__,network->flags ,priv->ieee80211->current_network.qos_data.active);
4343 if (set_qos_param == 1)
5f53d8ca 4344 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 4345
4346 return ret;
4347}
4348
4349
4350static int rtl8192_handle_assoc_response(struct net_device *dev,
4351 struct ieee80211_assoc_response_frame *resp,
4352 struct ieee80211_network *network)
4353{
4354 struct r8192_priv *priv = ieee80211_priv(dev);
4355 rtl8192_qos_association_resp(priv, network);
4356 return 0;
4357}
4358
4359
4360void rtl8192_update_ratr_table(struct net_device* dev)
4361 // POCTET_STRING posLegacyRate,
4362 // u8* pMcsRate)
4363 // PRT_WLAN_STA pEntry)
4364{
4365 struct r8192_priv* priv = ieee80211_priv(dev);
4366 struct ieee80211_device* ieee = priv->ieee80211;
4367 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
4368 //struct ieee80211_network *net = &ieee->current_network;
4369 u32 ratr_value = 0;
4370 u8 rate_index = 0;
4371 rtl8192_config_rate(dev, (u16*)(&ratr_value));
4372 ratr_value |= (*(u16*)(pMcsRate)) << 12;
4373// switch (net->mode)
4374 switch (ieee->mode)
4375 {
4376 case IEEE_A:
4377 ratr_value &= 0x00000FF0;
4378 break;
4379 case IEEE_B:
4380 ratr_value &= 0x0000000F;
4381 break;
4382 case IEEE_G:
4383 ratr_value &= 0x00000FF7;
4384 break;
4385 case IEEE_N_24G:
4386 case IEEE_N_5G:
4387 if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC
4388 ratr_value &= 0x0007F007;
4389 else{
4390 if (priv->rf_type == RF_1T2R)
4391 ratr_value &= 0x000FF007;
4392 else
4393 ratr_value &= 0x0F81F007;
4394 }
4395 break;
4396 default:
4397 break;
4398 }
4399 ratr_value &= 0x0FFFFFFF;
4400 if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){
4401 ratr_value |= 0x80000000;
4402 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
4403 ratr_value |= 0x80000000;
4404 }
4405 write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
4406 write_nic_byte(dev, UFWP, 1);
4407}
4408
4409static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04};
4410static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04};
4411bool GetNmodeSupportBySecCfg8192(struct net_device*dev)
4412{
4413#if 1
4414 struct r8192_priv* priv = ieee80211_priv(dev);
4415 struct ieee80211_device* ieee = priv->ieee80211;
4416 struct ieee80211_network * network = &ieee->current_network;
4417 int wpa_ie_len= ieee->wpa_ie_len;
4418 struct ieee80211_crypt_data* crypt;
4419 int encrypt;
4420#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
4421 return TRUE;
4422#endif
4423
4424 crypt = ieee->crypt[ieee->tx_keyidx];
4425 //we use connecting AP's capability instead of only security config on our driver to distinguish whether it should use N mode or G mode
4426 encrypt = (network->capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && (0 == strcmp(crypt->ops->name,"WEP")));
4427
4428 /* simply judge */
4429 if(encrypt && (wpa_ie_len == 0)) {
4430 /* wep encryption, no N mode setting */
4431 return false;
4432// } else if((wpa_ie_len != 0)&&(memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) {
4433 } else if((wpa_ie_len != 0)) {
4434 /* parse pairwise key type */
4435 //if((pairwisekey = WEP40)||(pairwisekey = WEP104)||(pairwisekey = TKIP))
4436 if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4))))
4437 return true;
4438 else
4439 return false;
4440 } else {
4441 return true;
4442 }
4443
4444#if 0
4445 //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate.
4446 //We can't force in G mode if Pairwie key is AES and group key is TKIP
4447 if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) ||
4448 (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) ||
4449 (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption))
4450 {
4451 return false;
4452 }
4453 else
4454 return true;
4455#endif
4456 return true;
4457#endif
4458}
4459
4460bool GetHalfNmodeSupportByAPs819xUsb(struct net_device* dev)
4461{
4462 bool Reval;
4463 struct r8192_priv* priv = ieee80211_priv(dev);
4464 struct ieee80211_device* ieee = priv->ieee80211;
4465
4466// Added by Roger, 2008.08.29.
4467#ifdef RTL8192SU
4468 return false;
4469#endif
4470
4471 if(ieee->bHalfWirelessN24GMode == true)
4472 Reval = true;
4473 else
4474 Reval = false;
4475
4476 return Reval;
4477}
4478
4479void rtl8192_refresh_supportrate(struct r8192_priv* priv)
4480{
4481 struct ieee80211_device* ieee = priv->ieee80211;
4482 //we donot consider set support rate for ABG mode, only HT MCS rate is set here.
4483 if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G)
4484 {
4485 memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
4486 //RT_DEBUG_DATA(COMP_INIT, ieee->RegHTSuppRateSet, 16);
4487 //RT_DEBUG_DATA(COMP_INIT, ieee->Regdot11HTOperationalRateSet, 16);
4488 }
4489 else
4490 memset(ieee->Regdot11HTOperationalRateSet, 0, 16);
4491 return;
4492}
4493
4494u8 rtl8192_getSupportedWireleeMode(struct net_device*dev)
4495{
4496 struct r8192_priv *priv = ieee80211_priv(dev);
4497 u8 ret = 0;
4498 switch(priv->rf_chip)
4499 {
4500 case RF_8225:
4501 case RF_8256:
4502 case RF_PSEUDO_11N:
4503 case RF_6052:
4504 ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B);
4505 break;
4506 case RF_8258:
4507 ret = (WIRELESS_MODE_A|WIRELESS_MODE_N_5G);
4508 break;
4509 default:
4510 ret = WIRELESS_MODE_B;
4511 break;
4512 }
4513 return ret;
4514}
4515void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode)
4516{
4517 struct r8192_priv *priv = ieee80211_priv(dev);
4518 u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev);
4519
4520#if 1
4521 if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0))
4522 {
4523 if(bSupportMode & WIRELESS_MODE_N_24G)
4524 {
4525 wireless_mode = WIRELESS_MODE_N_24G;
4526 }
4527 else if(bSupportMode & WIRELESS_MODE_N_5G)
4528 {
4529 wireless_mode = WIRELESS_MODE_N_5G;
4530 }
4531 else if((bSupportMode & WIRELESS_MODE_A))
4532 {
4533 wireless_mode = WIRELESS_MODE_A;
4534 }
4535 else if((bSupportMode & WIRELESS_MODE_G))
4536 {
4537 wireless_mode = WIRELESS_MODE_G;
4538 }
4539 else if((bSupportMode & WIRELESS_MODE_B))
4540 {
4541 wireless_mode = WIRELESS_MODE_B;
4542 }
4543 else{
4544 RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode);
4545 wireless_mode = WIRELESS_MODE_B;
4546 }
4547 }
4548#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA
4549 ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting );
4550#endif
4551#ifdef RTL8192SU
4552 //LZM 090306 usb crash here, mark it temp
4553 //write_nic_word(dev, SIFS_OFDM, 0x0e0e);
4554#endif
4555 priv->ieee80211->mode = wireless_mode;
4556
4557 if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G))
4558 priv->ieee80211->pHTInfo->bEnableHT = 1;
4559 else
4560 priv->ieee80211->pHTInfo->bEnableHT = 0;
4561 RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode);
4562 rtl8192_refresh_supportrate(priv);
4563#endif
4564
4565}
4566
4567
4568short rtl8192_is_tx_queue_empty(struct net_device *dev)
4569{
4570 int i=0;
4571 struct r8192_priv *priv = ieee80211_priv(dev);
4572 //struct ieee80211_device* ieee = priv->ieee80211;
4573 for (i=0; i<=MGNT_QUEUE; i++)
4574 {
4575 if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) )
4576 continue;
4577 if (atomic_read(&priv->tx_pending[i]))
4578 {
4579 printk("===>tx queue is not empty:%d, %d\n", i, atomic_read(&priv->tx_pending[i]));
4580 return 0;
4581 }
4582 }
4583 return 1;
4584}
4585#if 0
4586void rtl8192_rq_tx_ack(struct net_device *dev)
4587{
4588 struct r8192_priv *priv = ieee80211_priv(dev);
4589 priv->ieee80211->ack_tx_to_ieee = 1;
4590}
4591#endif
4592void rtl8192_hw_sleep_down(struct net_device *dev)
4593{
4594 RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__);
4595#ifdef TODO
4596// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
4597#endif
4598}
1ec9e48d 4599
5f53d8ca
JC		 4600void rtl8192_hw_sleep_wq (struct work_struct *work)
4601{
4602// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4603// struct ieee80211_device * ieee = (struct ieee80211_device*)
4604// container_of(work, struct ieee80211_device, watch_dog_wq);
4605 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4606 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
4607 struct net_device *dev = ieee->dev;
1ec9e48d 4608
5f53d8ca
JC		 4609 //printk("=========>%s()\n", __FUNCTION__);
4610 rtl8192_hw_sleep_down(dev);
4611}
4612// printk("dev is %d\n",dev);
4613// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__);
4614void rtl8192_hw_wakeup(struct net_device* dev)
4615{
4616// u32 flags = 0;
4617
4618// spin_lock_irqsave(&priv->ps_lock,flags);
4619 RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__);
4620#ifdef TODO
4621// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
4622#endif
4623 //FIXME: will we send package stored while nic is sleep?
4624// spin_unlock_irqrestore(&priv->ps_lock,flags);
4625}
1ec9e48d 4626
5f53d8ca
JC		 4627void rtl8192_hw_wakeup_wq (struct work_struct *work)
4628{
4629// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4630// struct ieee80211_device * ieee = (struct ieee80211_device*)
4631// container_of(work, struct ieee80211_device, watch_dog_wq);
4632 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4633 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
4634 struct net_device *dev = ieee->dev;
5f53d8ca 4635
1ec9e48d 4636 rtl8192_hw_wakeup(dev);
5f53d8ca
JC		 4637}
4638
4639#define MIN_SLEEP_TIME 50
4640#define MAX_SLEEP_TIME 10000
4641void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl)
4642{
4643
4644 struct r8192_priv *priv = ieee80211_priv(dev);
4645
4646 u32 rb = jiffies;
4647 unsigned long flags;
4648
4649 spin_lock_irqsave(&priv->ps_lock,flags);
4650
4651 /* Writing HW register with 0 equals to disable
4652 * the timer, that is not really what we want
4653 */
4654 tl -= MSECS(4+16+7);
4655
4656 //if(tl == 0) tl = 1;
4657
4658 /* FIXME HACK FIXME HACK */
4659// force_pci_posting(dev);
4660 //mdelay(1);
4661
4662// rb = read_nic_dword(dev, TSFTR);
4663
4664 /* If the interval in witch we are requested to sleep is too
4665 * short then give up and remain awake
4666 */
4667 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
4668 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
4669 spin_unlock_irqrestore(&priv->ps_lock,flags);
4670 printk("too short to sleep\n");
4671 return;
4672 }
4673
4674// write_nic_dword(dev, TimerInt, tl);
4675// rb = read_nic_dword(dev, TSFTR);
4676 {
4677 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
4678 // if (tl<rb)
4679
5f53d8ca 4680 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
5f53d8ca
JC		 4681 }
4682 /* if we suspect the TimerInt is gone beyond tl
4683 * while setting it, then give up
4684 */
4685#if 1
4686 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
4687 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
4688 printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME));
4689 spin_unlock_irqrestore(&priv->ps_lock,flags);
4690 return;
4691 }
4692#endif
4693// if(priv->rf_sleep)
4694// priv->rf_sleep(dev);
4695
4696 //printk("<=========%s()\n", __FUNCTION__);
5f53d8ca 4697 queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0);
1ec9e48d 4698
5f53d8ca
JC		 4699 spin_unlock_irqrestore(&priv->ps_lock,flags);
4700}
4701//init priv variables here. only non_zero value should be initialized here.
4702static void rtl8192_init_priv_variable(struct net_device* dev)
4703{
4704 struct r8192_priv *priv = ieee80211_priv(dev);
4705 u8 i;
4706 priv->card_8192 = NIC_8192U;
4707 priv->chan = 1; //set to channel 1
4708 priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO
4709 priv->ieee80211->iw_mode = IW_MODE_INFRA;
4710 priv->ieee80211->ieee_up=0;
4711 priv->retry_rts = DEFAULT_RETRY_RTS;
4712 priv->retry_data = DEFAULT_RETRY_DATA;
4713 priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD;
4714 priv->ieee80211->rate = 110; //11 mbps
4715 priv->ieee80211->short_slot = 1;
4716 priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
4717 priv->CckPwEnl = 6;
4718 //for silent reset
4719 priv->IrpPendingCount = 1;
4720 priv->ResetProgress = RESET_TYPE_NORESET;
4721 priv->bForcedSilentReset = 0;
4722 priv->bDisableNormalResetCheck = false;
4723 priv->force_reset = false;
4724
4725 priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available.
4726 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
4727 priv->ieee80211->iw_mode = IW_MODE_INFRA;
4728 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
4729 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
4730 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE |
4731 IEEE_SOFTMAC_BEACONS;//added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE;
4732
4733 priv->ieee80211->active_scan = 1;
4734 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION;
4735 priv->ieee80211->host_encrypt = 1;
4736 priv->ieee80211->host_decrypt = 1;
4737 priv->ieee80211->start_send_beacons = NULL;//rtl819xusb_beacon_tx;//-by amy 080604
4738 priv->ieee80211->stop_send_beacons = NULL;//rtl8192_beacon_stop;//-by amy 080604
4739 priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit;
4740 priv->ieee80211->set_chan = rtl8192_set_chan;
4741 priv->ieee80211->link_change = priv->ops->rtl819x_link_change;
4742 priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit;
4743 priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop;
4744 priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume;
4745 priv->ieee80211->init_wmmparam_flag = 0;
4746 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
4747 priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc;
4748 priv->ieee80211->tx_headroom = TX_PACKET_SHIFT_BYTES;
4749 priv->ieee80211->qos_support = 1;
4750
4751 //added by WB
4752// priv->ieee80211->SwChnlByTimerHandler = rtl8192_phy_SwChnl;
4753 priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode;
4754 priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response;
4755 priv->ieee80211->handle_beacon = rtl8192_handle_beacon;
4756 //for LPS
4757 priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup;
4758// priv->ieee80211->ps_request_tx_ack = rtl8192_rq_tx_ack;
4759 priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep;
4760 priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty;
4761 //added by david
4762 priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8192;
4763 priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xUsb;
4764 priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode;
4765 //added by amy
4766 priv->ieee80211->InitialGainHandler = priv->ops->rtl819x_initial_gain;
4767 priv->card_type = USB;
4768
4769#ifdef RTL8192SU
4770//1 RTL8192SU/
4771 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
4772 priv->ieee80211->SetFwCmdHandler = HalSetFwCmd8192S;
4773 priv->bRFSiOrPi = 0;//o=si,1=pi;
4774 //lzm add
4775 priv->bInHctTest = false;
4776
4777 priv->MidHighPwrTHR_L1 = 0x3B;
4778 priv->MidHighPwrTHR_L2 = 0x40;
4779
4780 if(priv->bInHctTest)
4781 {
4782 priv->ShortRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
4783 priv->LongRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
4784 }
4785 else
4786 {
4787 priv->ShortRetryLimit = HAL_RETRY_LIMIT_INFRA;
4788 priv->LongRetryLimit = HAL_RETRY_LIMIT_INFRA;
4789 }
4790
4791 priv->SetFwCmdInProgress = false; //is set FW CMD in Progress? 92S only
4792 priv->CurrentFwCmdIO = 0;
4793
4794 priv->MinSpaceCfg = 0;
4795
4796 priv->EarlyRxThreshold = 7;
4797 priv->enable_gpio0 = 0;
4798 priv->TransmitConfig =
4799 ((u32)TCR_MXDMA_2048<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
4800 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit
4801 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
4802 (false ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
4803 if(priv->bInHctTest)
4804 priv->ReceiveConfig = //priv->CSMethod |
4805 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
4806 RCR_ACF |RCR_APPFCS| //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
4807 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
4808 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
4809 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
4810 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
4811 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
4812 (priv->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
4813 else
4814 priv->ReceiveConfig = //priv->CSMethod |
4815 RCR_AMF | RCR_ADF | RCR_AB |
4816 RCR_AM | RCR_APM |RCR_AAP |RCR_ADD3|RCR_APP_ICV|
4817 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
4818 RCR_APP_MIC | RCR_APPFCS;
4819
4820 // <Roger_EXP> 2008.06.16.
4821 priv->IntrMask = (u16)(IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \
4822 IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \
4823 IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW | \
4824 IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
4825
4826//1 End
4827
4828#else
4829
4830#ifdef TO_DO_LIST
4831 if(Adapter->bInHctTest)
4832 {
4833 pHalData->ShortRetryLimit = 7;
4834 pHalData->LongRetryLimit = 7;
4835 }
4836#endif
4837 {
4838 priv->ShortRetryLimit = 0x30;
4839 priv->LongRetryLimit = 0x30;
4840 }
4841 priv->EarlyRxThreshold = 7;
4842 priv->enable_gpio0 = 0;
4843 priv->TransmitConfig =
4844 // TCR_DurProcMode | //for RTL8185B, duration setting by HW
4845 //? TCR_DISReqQsize |
4846 (TCR_MXDMA_2048<<TCR_MXDMA_OFFSET)| // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
4847 (priv->ShortRetryLimit<<TCR_SRL_OFFSET)| // Short retry limit
4848 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
4849 (false ? TCR_SAT: 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
4850#ifdef TO_DO_LIST
4851 if(Adapter->bInHctTest)
4852 pHalData->ReceiveConfig = pHalData->CSMethod |
4853 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
4854 //guangan200710
4855 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
4856 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
4857 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
4858 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
4859 (pHalData->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
4860 (pHalData->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
4861 else
4862
4863#endif
4864 priv->ReceiveConfig =
4865 RCR_AMF | RCR_ADF | //accept management/data
4866 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
4867 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
4868 //RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
4869 ((u32)7<<RCR_MXDMA_OFFSET)| // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
4870 (priv->EarlyRxThreshold<<RX_FIFO_THRESHOLD_SHIFT) | // Rx FIFO Threshold, 7: No Rx threshold.
4871 (priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0);
4872#endif
4873
4874 priv->AcmControl = 0;
4875 priv->pFirmware = (rt_firmware*)vmalloc(sizeof(rt_firmware));
4876 if (priv->pFirmware)
4877 memset(priv->pFirmware, 0, sizeof(rt_firmware));
4878
4879 /* rx related queue */
4880 skb_queue_head_init(&priv->rx_queue);
4881 skb_queue_head_init(&priv->skb_queue);
4882
4883 /* Tx related queue */
4884 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
4885 skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]);
4886 }
4887 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
4888 skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]);
4889 }
4890 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
4891 skb_queue_head_init(&priv->ieee80211->skb_drv_aggQ [i]);
4892 }
4893 priv->rf_set_chan = rtl8192_phy_SwChnl;
4894}
4895
4896//init lock here
4897static void rtl8192_init_priv_lock(struct r8192_priv* priv)
4898{
4899 spin_lock_init(&priv->tx_lock);
4900 spin_lock_init(&priv->irq_lock);//added by thomas
4901 //spin_lock_init(&priv->rf_lock);//use rf_sem, or will crash in some OS.
4902 sema_init(&priv->wx_sem,1);
4903 sema_init(&priv->rf_sem,1);
4904 spin_lock_init(&priv->ps_lock);
5f53d8ca 4905 mutex_init(&priv->mutex);
5f53d8ca
JC		 4906}
4907
5f53d8ca 4908extern void rtl819x_watchdog_wqcallback(struct work_struct *work);
5f53d8ca
JC		 4909
4910void rtl8192_irq_rx_tasklet(struct r8192_priv *priv);
4911//init tasklet and wait_queue here. only 2.6 above kernel is considered
4912#define DRV_NAME "wlan0"
4913static void rtl8192_init_priv_task(struct net_device* dev)
4914{
4915 struct r8192_priv *priv = ieee80211_priv(dev);
4916
5f53d8ca
JC		 4917#ifdef PF_SYNCTHREAD
4918 priv->priv_wq = create_workqueue(DRV_NAME,0);
4919#else
4920 priv->priv_wq = create_workqueue(DRV_NAME);
4921#endif
5f53d8ca 4922
5f53d8ca
JC		 4923 INIT_WORK(&priv->reset_wq, rtl8192_restart);
4924
4925 //INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog);
4926 INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback);
4927 INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback);
4928// INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
4929 INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback);
4930 INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon);
4931 INIT_DELAYED_WORK(&priv->initialgain_operate_wq, InitialGainOperateWorkItemCallBack);
4932 //INIT_WORK(&priv->SwChnlWorkItem, rtl8192_SwChnl_WorkItem);
4933 //INIT_WORK(&priv->SetBWModeWorkItem, rtl8192_SetBWModeWorkItem);
4934 INIT_WORK(&priv->qos_activate, rtl8192_qos_activate);
4935 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq);
4936 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq);
4937
5f53d8ca
JC		 4938 tasklet_init(&priv->irq_rx_tasklet,
4939 (void(*)(unsigned long))rtl8192_irq_rx_tasklet,
4940 (unsigned long)priv);
4941}
4942
4943static void rtl8192_get_eeprom_size(struct net_device* dev)
4944{
4945 u16 curCR = 0;
4946 struct r8192_priv *priv = ieee80211_priv(dev);
4947 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
4948 curCR = read_nic_word_E(dev,EPROM_CMD);
4949 RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR);
4950 //whether need I consider BIT5?
4951 priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46;
4952 RT_TRACE(COMP_EPROM, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype);
4953}
4954
4955//used to swap endian. as ntohl & htonl are not neccessary to swap endian, so use this instead.
4956static inline u16 endian_swap(u16* data)
4957{
4958 u16 tmp = *data;
4959 *data = (tmp >> 8) | (tmp << 8);
4960 return *data;
4961}
4962
4963#ifdef RTL8192SU
4964u8 rtl8192SU_UsbOptionToEndPointNumber(u8 UsbOption)
4965{
4966 u8 nEndPoint = 0;
4967 switch(UsbOption)
4968 {
4969 case 0:
4970 nEndPoint = 6;
4971 break;
4972 case 1:
4973 nEndPoint = 11;
4974 break;
4975 case 2:
4976 nEndPoint = 4;
4977 break;
4978 default:
4979 RT_TRACE(COMP_INIT, "UsbOptionToEndPointNumber(): Invalid UsbOption(%#x)\n", UsbOption);
4980 break;
4981 }
4982 return nEndPoint;
4983}
4984
4985u8 rtl8192SU_BoardTypeToRFtype(struct net_device* dev, u8 Boardtype)
4986{
4987 u8 RFtype = RF_1T2R;
4988
4989 switch(Boardtype)
4990 {
4991 case 0:
4992 RFtype = RF_1T1R;
4993 break;
4994 case 1:
4995 RFtype = RF_1T2R;
4996 break;
4997 case 2:
4998 RFtype = RF_2T2R;
4999 break;
5000 case 3:
5001 RFtype = RF_2T2R_GREEN;
5002 break;
5003 default:
5004 break;
5005 }
5006
5007 return RFtype;
5008}
5009
5010//
5011// Description:
5012// Config HW adapter information into initial value.
5013//
5014// Assumption:
5015// 1. After Auto load fail(i.e, check CR9346 fail)
5016//
5017// Created by Roger, 2008.10.21.
5018//
5019void
5020rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
5021{
5022 struct r8192_priv *priv = ieee80211_priv(dev);
5023 //u16 i,usValue;
5024 //u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5025 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
5026 int i;
5027
5028 RT_TRACE(COMP_INIT, "====> ConfigAdapterInfo8192SForAutoLoadFail\n");
5029
5030 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5031 //PlatformStallExecution(10000);
5032 mdelay(10);
5033 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
5034
5035 //RT_ASSERT(priv->AutoloadFailFlag==TRUE, ("ReadAdapterInfo8192SEEPROM(): AutoloadFailFlag !=TRUE\n"));
5036
5037 // Initialize IC Version && Channel Plan
5038 priv->eeprom_vid = 0;
5039 priv->eeprom_pid = 0;
5040 priv->card_8192_version = 0;
5041 priv->eeprom_ChannelPlan = 0;
5042 priv->eeprom_CustomerID = 0;
5043 priv->eeprom_SubCustomerID = 0;
5044 priv->bIgnoreDiffRateTxPowerOffset = false;
5045
5046 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5047 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5048 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5049 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5050 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5051 RT_TRACE(COMP_INIT, "IgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
5052
5053
5054
5055 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5056 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5057
5058 for(i=0; i<5; i++)
5059 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
5060
5061 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("EFUSE USB PHY Param: \n"), priv->EEPROMUsbPhyParam, 5);
5062
5063 {
5064 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5065 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5066 u8 i;
5067
5068 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5069
5070 for(i = 0; i < 6; i++)
5071 dev->dev_addr[i] = sMacAddr[i];
5072 }
5073 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
5074 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5075 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5076
5077 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
5078 dev->dev_addr[0], dev->dev_addr[1],
5079 dev->dev_addr[2], dev->dev_addr[3],
5080 dev->dev_addr[4], dev->dev_addr[5]);
5081
5082 priv->EEPROMBoardType = EEPROM_Default_BoardType;
5083 priv->rf_type = RF_1T2R; //RF_2T2R
5084 priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
5085 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5086 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5087 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5088 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5089 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5090 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5091
5092
5093#ifdef EEPROM_OLD_FORMAT_SUPPORT
5094 for(i=0; i<6; i++)
5095 {
5096 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5097 }
5098
5099 for(i=0; i<14; i++)
5100 {
5101 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5102 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5103 }
5104
5105 //
5106 // Update HAL variables.
5107 //
5108 memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
5109 memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
5110 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), priv->TxPowerLevelCCK, 14);
5111 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), priv->TxPowerLevelOFDM24G, 14);
5112#else
5113
5114 for (rf_path = 0; rf_path < 2; rf_path++)
5115 {
5116 for (i = 0; i < 3; i++)
5117 {
5118 // Read CCK RF A & B Tx power
5119 priv->RfCckChnlAreaTxPwr[rf_path][i] =
5120 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
5121 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
5122 (u8)(EEPROM_Default_TxPower & 0xff);
5123 }
5124 }
5125
5126 for (i = 0; i < 3; i++)
5127 {
5128 //RT_TRACE((COMP_EFUSE), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5129 //priv->RfCckChnlAreaTxPwr[rf_path][i]);
5130 //RT_TRACE((COMP_EFUSE), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5131 //priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
5132 //RT_TRACE((COMP_EFUSE), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5133 //priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
5134 }
5135
5136 // Assign dedicated channel tx power
5137 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
5138 {
5139 if (i < 3) // Cjanel 1-3
5140 index = 0;
5141 else if (i < 9) // Channel 4-9
5142 index = 1;
5143 else // Channel 10-14
5144 index = 2;
5145
5146 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
5147 priv->RfTxPwrLevelCck[rf_path][i] =
5148 priv->RfCckChnlAreaTxPwr[rf_path][index];
5149 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
5150 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
5151 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
5152 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
5153 }
5154
5155 for(i=0; i<14; i++)
5156 {
5157 //RT_TRACE((COMP_EFUSE), "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
5158 //rf_path, i, priv->RfTxPwrLevelCck[0][i],
5159 //priv->RfTxPwrLevelOfdm1T[0][i] ,
5160 //priv->RfTxPwrLevelOfdm2T[0][i] );
5161 }
5162#endif
5163
5164 //
5165 // Update remained HAL variables.
5166 //
5167 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5168 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;//new
5169 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
5170 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit0~3
5171 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit4~7
5172 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit12~15
5173 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5174 priv->LedStrategy = SW_LED_MODE0;
5175
5176 init_rate_adaptive(dev);
5177
5178 RT_TRACE(COMP_INIT, "<==== ConfigAdapterInfo8192SForAutoLoadFail\n");
5179
5180}
5181
5182#if 0
5183static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
5184{
5185 u16 EEPROMId = 0;
5186 u8 bLoad_From_EEPOM = false;
5187 struct r8192_priv *priv = ieee80211_priv(dev);
5188 u16 tmpValue = 0;
5189 u8 tmpBuffer[30];
5190 int i;
5191
5192 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
5193
5194
5195 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5196 udelay(10000);
5197 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
5198
5199
5200 EEPROMId = eprom_read(dev, 0); //first read EEPROM ID out;
5201 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", EEPROMId);
5202
5203 if (EEPROMId != RTL8190_EEPROM_ID)
5204 {
5205 priv->AutoloadFailFlag = true;
5206 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", EEPROMId, RTL8190_EEPROM_ID);
5207 }
5208 else
5209 {
5210 priv->AutoloadFailFlag = false;
5211 bLoad_From_EEPOM = true;
5212 }
5213
5214 if (bLoad_From_EEPOM)
5215 {
5216 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
5217 priv->eeprom_vid = endian_swap(&tmpValue);
5218 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
5219
5220 // Version ID, Channel plan
5221 tmpValue = eprom_read(dev, (EEPROM_Version>>1));
5222 //pHalData->card_8192_version = (VERSION_8192S)((usValue&0x00ff));
5223 priv->eeprom_ChannelPlan =(tmpValue&0xff00)>>8;
5224 priv->bTXPowerDataReadFromEEPORM = true;
5225
5226 // Customer ID, 0x00 and 0xff are reserved for Realtek.
5227 tmpValue = eprom_read(dev, (u16)(EEPROM_CustomID>>1)) ;
5228 priv->eeprom_CustomerID = (u8)( tmpValue & 0xff);
5229 priv->eeprom_SubCustomerID = (u8)((tmpValue & 0xff00)>>8);
5230 }
5231 else
5232 {
5233 priv->eeprom_vid = 0;
5234 priv->eeprom_pid = 0;
5235 //priv->card_8192_version = VERSION_8192SU_A;
5236 priv->eeprom_ChannelPlan = 0;
5237 priv->eeprom_CustomerID = 0;
5238 priv->eeprom_SubCustomerID = 0;
5239 }
5240 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
5241 //set channelplan from eeprom
5242 priv->ChannelPlan = priv->eeprom_ChannelPlan;// FIXLZM
5243
5244 RT_TRACE(COMP_INIT, "EEPROMId = 0x%4x\n", EEPROMId);
5245 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5246 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5247 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
5248 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5249 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5250 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5251
5252 // Read USB optional function.
5253 if(bLoad_From_EEPOM)
5254 {
5255 tmpValue = eprom_read(dev, (EEPROM_USB_OPTIONAL>>1));
5256 priv->EEPROMUsbOption = (u8)(tmpValue&0xff);
5257 }
5258 else
5259 {
5260 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5261 }
5262
5263 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5264
5265
5266 if (bLoad_From_EEPOM)
5267 {
5268 int i;
5269 for (i=0; i<6; i+=2)
5270 {
5271 u16 tmp = 0;
5272 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
5273 *(u16*)(&dev->dev_addr[i]) = tmp;
5274 }
5275 }
5276 else
5277 {
5278 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5279 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5280 u8 i;
5281
5282 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5283
5284 for(i = 0; i < 6; i++)
5285 dev->dev_addr[i] = sMacAddr[i];
5286
5287 //memcpy(dev->dev_addr, sMacAddr, 6);
5288 //should I set IDR0 here?
5289 }
5290 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5291 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5292 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
5293
5294 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
5295#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
5296 priv->rf_chip = RF_6052;
5297 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
5298 //priv->card_8192_version = VERSION_8192SU_A; //Over write for temporally experiment. 2008.10.16. By Roger.
5299#else
5300 priv->rf_chip = RF_8256;
5301#endif
5302
5303 {
5304#if 0
5305 if(bLoad_From_EEPOM)
5306 {
5307 tempval = (ReadEEprom(Adapter, (EEPROM_RFInd_PowerDiff>>1))) & 0xff;
5308 if (tempval&0x80) //RF-indication, bit[7]
5309 pHalData->RF_Type = RF_1T2R;
5310 else
5311 pHalData->RF_Type = RF_2T4R;
5312 }
5313#endif
5314
5315 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
5316 RT_TRACE(COMP_INIT, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff);
5317
5318
5319 //
5320 // Read antenna tx power offset of B/C/D to A from EEPROM
5321 // and read ThermalMeter from EEPROM
5322 //
5323 if(bLoad_From_EEPOM)
5324 {
5325 tmpValue = eprom_read(dev, (EEPROM_PwDiff>>1));
5326 priv->EEPROMPwDiff = tmpValue&0x00ff;
5327 priv->EEPROMThermalMeter = (tmpValue&0xff00)>>8;
5328 }
5329 else
5330 {
5331 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
5332 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5333 }
5334 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
5335 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5336
5337 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5338
5339
5340 // Read CrystalCap from EEPROM
5341 if(bLoad_From_EEPOM)
5342 {
5343 priv->EEPROMCrystalCap =(u8) (((eprom_read(dev, (EEPROM_CrystalCap>>1)))&0xf000)>>12);
5344 }
5345 else
5346 {
5347 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5348 }
5349 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
5350
5351
5352 //if(pHalData->EEPROM_Def_Ver == 0) // old eeprom definition
5353 {
5354
5355 //
5356 // Get Tx Power Base.//===>
5357 //
5358 if(bLoad_From_EEPOM)
5359 {
5360 priv->EEPROMTxPwrBase =(u8) ((eprom_read(dev, (EEPROM_TxPowerBase>>1)))&0xff);
5361 }
5362 else
5363 {
5364 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5365 }
5366
5367 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
5368
5369 //
5370 // Get CustomerID(Boad Type)
5371 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
5372 // Others: Reserved. Default is 0x2: RTL8192SU.
5373 //
5374 if(bLoad_From_EEPOM)
5375 {
5376 tmpValue = eprom_read(dev, (u16) (EEPROM_BoardType>>1));
5377 priv->EEPROMBoardType = (u8)(tmpValue&0xff);
5378 }
5379 else
5380 {
5381 priv->EEPROMBoardType = EEPROM_Default_BoardType;
5382 }
5383
5384 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
5385
5386#ifdef EEPROM_OLD_FORMAT_SUPPORT
5387
5388 //
5389 // Buffer TxPwIdx(i.e., from offset 0x58~0x75, total 30Bytes)
5390 //
5391 if(bLoad_From_EEPOM)
5392 {
5393 for(i = 0; i < 30; i += 2)
5394 {
5395 tmpValue = eprom_read(dev, (u16) ((EEPROM_TxPowerBase+i)>>1));
5396 *((u16 *)(&tmpBuffer[i])) = tmpValue;
5397 }
5398 }
5399
5400 //
5401 // Update CCK, OFDM Tx Power Index from above buffer.
5402 //
5403 if(bLoad_From_EEPOM)
5404 {
5405 for(i=0; i<14; i++)
5406 {
5407 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)tmpBuffer[i+1];
5408 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)tmpBuffer[i+15];
5409 }
5410
5411 }
5412 else
5413 {
5414 for(i=0; i<14; i++)
5415 {
5416 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5417 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5418 }
5419 }
5420
5421 for(i=0; i<14; i++)
5422 {
5423 RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK24G[i]);
5424 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]);
5425 }
5426#else
5427 // Please add code in the section!!!!
5428 // And merge tx power difference section.
5429#endif
5430
5431 //
5432 // Get TSSI value for each path.
5433 //
5434 if(bLoad_From_EEPOM)
5435 {
5436 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_A)>>1));
5437 priv->EEPROMTSSI_A = (u8)((tmpValue&0xff00)>>8);
5438 }
5439 else
5440 { // Default setting for Empty EEPROM
5441 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5442 }
5443
5444 if(bLoad_From_EEPOM)
5445 {
5446 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_B)>>1));
5447 priv->EEPROMTSSI_B = (u8)(tmpValue&0xff);
5448 priv->EEPROMTxPwrTkMode = (u8)((tmpValue&0xff00)>>8);
5449 }
5450 else
5451 { // Default setting for Empty EEPROM
5452 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5453 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5454 }
5455
5456 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5457 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5458
5459#ifdef EEPROM_OLD_FORMAT_SUPPORT
5460 //
5461 // Get HT 2T Path A and B Power Index.
5462 //
5463 if(bLoad_From_EEPOM)
5464 {
5465 for(i = 0; i < 6; i += 2)
5466 {
5467 tmpValue = eprom_read(dev, (u16) ((EEPROM_HT2T_CH1_A+i)>>1));
5468 *((u16*)(&priv->EEPROMHT2T_TxPwr[i])) = tmpValue;
5469 }
5470 }
5471 else
5472 { // Default setting for Empty EEPROM
5473 for(i=0; i<6; i++)
5474 {
5475 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5476 }
5477 }
5478
5479 for(i=0; i<6; i++)
5480 {
5481 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", i, priv->EEPROMHT2T_TxPwr[i]);
5482 }
5483#else
5484
5485#endif
5486 }
5487
5488#ifdef EEPROM_OLD_FORMAT_SUPPORT
5489 //
5490 // Update HAL variables.
5491 //
5492 for(i=0; i<14; i++)
5493 {
5494 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
5495 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
5496 }
5497#else
5498
5499#endif
5500 priv->TxPowerDiff = priv->EEPROMPwDiff;
5501 // Antenna B gain offset to antenna A, bit0~3
5502 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
5503 // Antenna C gain offset to antenna A, bit4~7
5504 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
5505 // CrystalCap, bit12~15
5506 priv->CrystalCap = priv->EEPROMCrystalCap;
5507 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5508 // 92U does not enable TX power tracking.
5509 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
5510 }
5511
5512 priv->LedStrategy = SW_LED_MODE0;
5513
5514 if(priv->rf_type == RF_1T2R)
5515 {
5516 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
5517 }
5518 else
5519 {
5520 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
5521 }
5522
5523 // 2008/01/16 MH We can only know RF type in the function. So we have to init
5524 // DIG RATR table again.
5525 init_rate_adaptive(dev);
5526 //we need init DIG RATR table here again.
5527
5528 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
5529 return;
5530}
5531
5532//
5533// Description:
5534// 1. Read HW adapter information by E-Fuse.
5535// 2. Refered from SD1 Richard.
5536//
5537// Assumption:
5538// 1. Boot from E-Fuse and CR9346 regiser has verified.
5539// 2. PASSIVE_LEVEL (USB interface)
5540//
5541// Created by Roger, 2008.10.21.
5542//
5543void
5544rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
5545{
5546 struct r8192_priv *priv = ieee80211_priv(dev);
5547 u16 i,usValue;
5548 u16 EEPROMId;
5549 u8 readbyte;
5550 u8 OFDMTxPwr[14];
5551 u8 CCKTxPwr[14];
5552 u8 HT2T_TxPwr[6];
5553 u8 UsbPhyParam[5];
5554 u8 hwinfo[HWSET_MAX_SIZE_92S];
5555
5556
5557 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SEFuse\n");
5558
5559 //
5560 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
5561 // from suspend mode.
5562 // 2008.10.21.
5563 //
5564 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5565 //PlatformStallExecution(10000);
5566 mdelay(10);
5567 write_nic_byte(dev, SYS_FUNC_EN+1, 0x40);
5568 write_nic_byte(dev, SYS_FUNC_EN+1, 0x50);
5569
5570 readbyte = read_nic_byte(dev, EFUSE_TEST+3);
5571 write_nic_byte(dev, EFUSE_TEST+3, (readbyte | 0x80));
5572 write_nic_byte(dev, EFUSE_TEST+3, 0x72);
5573 write_nic_byte(dev, EFUSE_CLK, 0x03);
5574
5575 //
5576 // Dump EFUSe at init time for later use
5577 //
5578 // Read EFUSE real map to shadow!!
5579 EFUSE_ShadowMapUpdate(dev);
5580
5581 memcpy(hwinfo, (void*)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
5582 //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("MAP \n"), hwinfo, HWSET_MAX_SIZE_92S);
5583
5584 //
5585 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
5586 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
5587 // 2008.10.21.
5588 //
5589 ReadEFuse(dev, 0, 2, (unsigned char*) &EEPROMId);
5590
5591 if( EEPROMId != RTL8190_EEPROM_ID )
5592 {
5593 RT_TRACE(COMP_INIT, "EEPROM ID(%#x) is invalid!!\n", EEPROMId);
5594 priv->AutoloadFailFlag=true;
5595 }
5596 else
5597 {
5598 priv->AutoloadFailFlag=false;
5599 }
5600
5601 // Read IC Version && Channel Plan
5602 if(!priv->AutoloadFailFlag)
5603 {
5604
5605 // VID, PID
5606 ReadEFuse(dev, EEPROM_VID, 2, (unsigned char*) &priv->eeprom_vid);
5607 ReadEFuse(dev, EEPROM_PID, 2, (unsigned char*) &priv->eeprom_pid);
5608
5609 // Version ID, Channel plan
5610 ReadEFuse(dev, EEPROM_Version, 2, (unsigned char*) &usValue);
5611 //pHalData->VersionID = (VERSION_8192S)(usValue&0x00ff);
5612 priv->eeprom_ChannelPlan = (usValue&0xff00>>8);
5613 priv->bTXPowerDataReadFromEEPORM = true;
5614
5615 // Customer ID, 0x00 and 0xff are reserved for Realtek.
5616 ReadEFuse(dev, EEPROM_CustomID, 2, (unsigned char*) &usValue);
5617 priv->eeprom_CustomerID = (u8)( usValue & 0xff);
5618 priv->eeprom_SubCustomerID = (u8)((usValue & 0xff00)>>8);
5619 }
5620 else
5621 {
5622 priv->eeprom_vid = 0;
5623 priv->eeprom_pid = 0;
5624 priv->eeprom_ChannelPlan = 0;
5625 priv->eeprom_CustomerID = 0;
5626 priv->eeprom_SubCustomerID = 0;
5627 }
5628
5629 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
5630 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5631 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5632 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
5633 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5634 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5635 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5636
5637
5638 // Read USB optional function.
5639 if(!priv->AutoloadFailFlag)
5640 {
5641 ReadEFuse(dev, EEPROM_USB_OPTIONAL, 1, (unsigned char*) &priv->EEPROMUsbOption);
5642 }
5643 else
5644 {
5645 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5646 }
5647
5648 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5649
5650
5651 // Read USB PHY parameters.
5652 if(!priv->AutoloadFailFlag)
5653 {
5654 ReadEFuse(dev, EEPROM_USB_PHY_PARA1, 5, (unsigned char*)UsbPhyParam);
5655 for(i=0; i<5; i++)
5656 {
5657 priv->EEPROMUsbPhyParam[i] = UsbPhyParam[i];
5658 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
5659 }
5660 }
5661 else
5662 {
5663 for(i=0; i<5; i++)
5664 {
5665 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
5666 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
5667 }
5668 }
5669
5670
5671 //Read Permanent MAC address
5672 if(!priv->AutoloadFailFlag)
5673 {
5674 u8 macaddr[6] = {0x00, 0xe1, 0x86, 0x4c, 0x92, 0x00};
5675
5676 ReadEFuse(dev, EEPROM_NODE_ADDRESS_BYTE_0, 6, (unsigned char*)macaddr);
5677 for(i=0; i<6; i++)
5678 dev->dev_addr[i] = macaddr[i];
5679 }
5680 else
5681 {//Auto load fail
5682
5683 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5684 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5685 u8 i;
5686
5687 //if(!Adapter->bInHctTest)
5688 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5689
5690 for(i = 0; i < 6; i++)
5691 dev->dev_addr[i] = sMacAddr[i];
5692 }
5693
5694 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
5695 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5696 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5697
5698 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
5699 dev->dev_addr[0], dev->dev_addr[1],
5700 dev->dev_addr[2], dev->dev_addr[3],
5701 dev->dev_addr[4], dev->dev_addr[5]);
5702
5703 // 2007/11/15 MH For RTL8192USB we assign as 1T2R now.
5704 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; // default : 1T2R
5705
5706#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
5707 priv->rf_chip = RF_6052;
5708 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
5709#else
5710 priv->rf_chip = RF_8256;
5711#endif
5712
5713 {
5714 //
5715 // Read antenna tx power offset of B/C/D to A from EEPROM
5716 // and read ThermalMeter from EEPROM
5717 //
5718 if(!priv->AutoloadFailFlag)
5719 {
5720 ReadEFuse(dev, EEPROM_PwDiff, 2, (unsigned char*) &usValue);
5721 priv->EEPROMPwDiff = usValue&0x00ff;
5722 priv->EEPROMThermalMeter = (usValue&0xff00)>>8;
5723 }
5724 else
5725 {
5726 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
5727 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5728 }
5729
5730 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
5731 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5732
5733 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5734
5735 //
5736 // Read Tx Power gain offset of legacy OFDM to HT rate.
5737 // Read CrystalCap from EEPROM
5738 //
5739 if(!priv->AutoloadFailFlag)
5740 {
5741 ReadEFuse(dev, EEPROM_CrystalCap, 1, (unsigned char*) &usValue);
5742 priv->EEPROMCrystalCap = (u8)((usValue&0xf0)>>4);
5743 }
5744 else
5745 {
5746 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5747 }
5748
5749 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
5750
5751 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
5752 RT_TRACE(COMP_INIT, "TxPowerDiff = %d\n", priv->EEPROMTxPowerDiff);
5753
5754
5755 //
5756 // Get Tx Power Base.
5757 //
5758 if(!priv->AutoloadFailFlag)
5759 {
5760 ReadEFuse(dev, EEPROM_TxPowerBase, 1, (unsigned char*) &priv->EEPROMTxPwrBase );
5761 }
5762 else
5763 {
5764 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5765 }
5766
5767 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
5768
5769 //
5770 // Get CustomerID(Boad Type)
5771 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
5772 // Others: Reserved. Default is 0x2: RTL8192SU.
5773 //
5774 if(!priv->AutoloadFailFlag)
5775 {
5776 ReadEFuse(dev, EEPROM_BoardType, 1, (unsigned char*) &priv->EEPROMBoardType );
5777 }
5778 else
5779 {
5780 priv->EEPROMBoardType = EEPROM_Default_BoardType;
5781 }
5782
5783 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
5784
5785 //if(pHalData->EEPROM_Def_Ver == 0)
5786 {
5787#ifdef EEPROM_OLD_FORMAT_SUPPORT
5788 //
5789 // Get CCK Tx Power Index.
5790 //
5791 if(!priv->AutoloadFailFlag)
5792 {
5793 ReadEFuse(dev, EEPROM_TxPwIndex_CCK_24G, 14, (unsigned char*)CCKTxPwr);
5794 for(i=0; i<14; i++)
5795 {
5796 RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, CCKTxPwr[i]);
5797 priv->EEPROMTxPowerLevelCCK24G[i] = CCKTxPwr[i];
5798 }
5799 }
5800 else
5801 { // Default setting for Empty EEPROM
5802 for(i=0; i<14; i++)
5803 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5804 }
5805
5806 //
5807 // Get OFDM Tx Power Index.
5808 //
5809 if(!priv->AutoloadFailFlag)
5810 {
5811 ReadEFuse(dev, EEPROM_TxPwIndex_OFDM_24G, 14, (unsigned char*)OFDMTxPwr);
5812 for(i=0; i<14; i++)
5813 {
5814 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, OFDMTxPwr[i]);
5815 priv->EEPROMTxPowerLevelOFDM24G[i] = OFDMTxPwr[i];
5816 }
5817 }
5818 else
5819 { // Default setting for Empty EEPROM
5820 usValue = 0x10;
5821 for(i=0; i<14; i++)
5822 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)usValue;
5823 }
5824#else
5825 // Please add code in the section!!!!
5826 // And merge tx power difference section.
5827#endif
5828
5829 //
5830 // Get TSSI value for each path.
5831 //
5832 if(!priv->AutoloadFailFlag)
5833 {
5834 ReadEFuse(dev, EEPROM_TSSI_A, 2, (unsigned char*)&usValue);
5835 priv->EEPROMTSSI_A = (u8)(usValue&0xff);
5836 priv->EEPROMTSSI_B = (u8)((usValue&0xff00)>>8);
5837 }
5838 else
5839 { // Default setting for Empty EEPROM
5840 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5841 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5842 }
5843
5844 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n",
5845 priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5846
5847 //
5848 // Get Tx Power tracking mode.
5849 //
5850 if(!priv->AutoloadFailFlag)
5851 {
5852 ReadEFuse(dev, EEPROM_TxPwTkMode, 1, (unsigned char*)&priv->EEPROMTxPwrTkMode);
5853 }
5854 else
5855 { // Default setting for Empty EEPROM
5856 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5857 }
5858
5859 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5860
5861
5862 // TODO: The following HT 2T Path A and B Power Index should be updated.!! Added by Roger, 2008.20.23.
5863
5864 //
5865 // Get HT 2T Path A and B Power Index.
5866 //
5867 if(!priv->AutoloadFailFlag)
5868 {
5869 ReadEFuse(dev, EEPROM_HT2T_CH1_A, 6, (unsigned char*)HT2T_TxPwr);
5870 for(i=0; i<6; i++)
5871 {
5872 priv->EEPROMHT2T_TxPwr[i] = HT2T_TxPwr[i];
5873 }
5874 }
5875 else
5876 { // Default setting for Empty EEPROM
5877 for(i=0; i<6; i++)
5878 {
5879 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5880 }
5881 }
5882
5883 for(i=0; i<6; i++)
5884 {
5885 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n",
5886 i, priv->EEPROMHT2T_TxPwr[i]);
5887 }
5888 }
5889
5890#ifdef EEPROM_OLD_FORMAT_SUPPORT
5891 //
5892 // Update HAL variables.
5893 //
5894 for(i=0; i<14; i++)
5895 {
5896 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
5897 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
5898 }
5899#else
5900
5901#endif
5902 priv->TxPowerDiff = priv->EEPROMPwDiff;
5903 // Antenna B gain offset to antenna A, bit0~3
5904 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
5905 // Antenna C gain offset to antenna A, bit4~7
5906 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
5907 // CrystalCap, bit12~15
5908 priv->CrystalCap = priv->EEPROMCrystalCap;
5909 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5910 // 92U does not enable TX power tracking.
5911 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
5912 }
5913
5914 priv->LedStrategy = SW_LED_MODE0;
5915
5916 init_rate_adaptive(dev);
5917
5918 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SEFuse\n");
5919
5920}
5921#endif
5922
5923//
5924// Description:
5925// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
5926//
5927// Assumption:
5928// 1. CR9346 regiser has verified.
5929// 2. PASSIVE_LEVEL (USB interface)
5930//
5931// Created by Roger, 2008.10.21.
5932//
5933void
5934rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
5935{
5936 struct r8192_priv *priv = ieee80211_priv(dev);
5937 u16 i,usValue;
5938 u8 tmpU1b, tempval;
5939 u16 EEPROMId;
5940 u8 hwinfo[HWSET_MAX_SIZE_92S];
5941 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
5942
5943
5944 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
5945
5946 //
5947 // <Roger_Note> The following operation are prevent Efuse leakage by turn on 2.5V.
5948 // 2008.11.25.
5949 //
5950 tmpU1b = read_nic_byte(dev, EFUSE_TEST+3);
5951 write_nic_byte(dev, EFUSE_TEST+3, tmpU1b|0x80);
5952 //PlatformStallExecution(1000);
5953 mdelay(10);
5954 write_nic_byte(dev, EFUSE_TEST+3, (tmpU1b&(~BIT7)));
5955
5956 // Retrieve Chip version.
5957 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
5958 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
5959
5960 switch(priv->card_8192_version)
5961 {
5962 case 0:
5963 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_ACUT.\n");
5964 break;
5965 case 1:
5966 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_BCUT.\n");
5967 break;
5968 case 2:
5969 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_CCUT.\n");
5970 break;
5971 default:
5972 RT_TRACE(COMP_INIT, "Unknown Chip Version!!\n");
5973 priv->card_8192_version = VERSION_8192S_BCUT;
5974 break;
5975 }
5976
5977 //if (IS_BOOT_FROM_EEPROM(Adapter))
5978 if(priv->EepromOrEfuse)
5979 { // Read frin EEPROM
5980 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5981 //PlatformStallExecution(10000);
5982 mdelay(10);
5983 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
5984 // Read all Content from EEPROM or EFUSE.
5985 for(i = 0; i < HWSET_MAX_SIZE_92S; i += 2)
5986 {
5987 usValue = eprom_read(dev, (u16) (i>>1));
5988 *((u16*)(&hwinfo[i])) = usValue;
5989 }
5990 }
5991 else if (!(priv->EepromOrEfuse))
5992 { // Read from EFUSE
5993
5994 //
5995 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
5996 // from suspend mode.
5997 // 2008.10.21.
5998 //
5999 //PlatformEFIOWrite1Byte(Adapter, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
6000 //PlatformStallExecution(10000);
6001 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x40);
6002 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x50);
6003
6004 //tmpU1b = PlatformEFIORead1Byte(Adapter, EFUSE_TEST+3);
6005 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, (tmpU1b | 0x80));
6006 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, 0x72);
6007 //PlatformEFIOWrite1Byte(Adapter, EFUSE_CLK, 0x03);
6008
6009 // Read EFUSE real map to shadow.
6010 EFUSE_ShadowMapUpdate(dev);
6011 memcpy(hwinfo, &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
6012 }
6013 else
6014 {
6015 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SUsb(): Invalid boot type!!\n");
6016 }
6017
6018 //YJ,test,090106
6019 //dump_buf(hwinfo,HWSET_MAX_SIZE_92S);
6020 //
6021 // <Roger_Notes> The following are EFUSE/EEPROM independent operations!!
6022 //
6023 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("MAP: \n"), hwinfo, HWSET_MAX_SIZE_92S);
6024
6025 //
6026 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
6027 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
6028 // 2008.10.21.
6029 //
6030 EEPROMId = *((u16 *)&hwinfo[0]);
6031
6032 if( EEPROMId != RTL8190_EEPROM_ID )
6033 {
6034 RT_TRACE(COMP_INIT, "ID(%#x) is invalid!!\n", EEPROMId);
6035 priv->bTXPowerDataReadFromEEPORM = FALSE;
6036 priv->AutoloadFailFlag=TRUE;
6037 }
6038 else
6039 {
6040 priv->AutoloadFailFlag=FALSE;
6041#if RTL8192SU_USE_PARAM_TXPWR
6042 priv->bTXPowerDataReadFromEEPORM = FALSE;
6043#else
6044 priv->bTXPowerDataReadFromEEPORM = TRUE;
6045#endif
6046
6047 }
6048 // Read IC Version && Channel Plan
6049 if(!priv->AutoloadFailFlag)
6050 {
6051 // VID, PID
6052 priv->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
6053 priv->eeprom_pid = *(u16 *)&hwinfo[EEPROM_PID];
6054 priv->bIgnoreDiffRateTxPowerOffset = false; //cosa for test
6055
6056
6057 // EEPROM Version ID, Channel plan
6058 priv->EEPROMVersion = *(u8 *)&hwinfo[EEPROM_Version];
6059 priv->eeprom_ChannelPlan = *(u8 *)&hwinfo[EEPROM_ChannelPlan];
6060
6061 // Customer ID, 0x00 and 0xff are reserved for Realtek.
6062 priv->eeprom_CustomerID = *(u8 *)&hwinfo[EEPROM_CustomID];
6063 priv->eeprom_SubCustomerID = *(u8 *)&hwinfo[EEPROM_SubCustomID];
6064 }
6065 else
6066 {
6067 //priv->eeprom_vid = 0;
6068 //priv->eeprom_pid = 0;
6069 //priv->EEPROMVersion = 0;
6070 //priv->eeprom_ChannelPlan = 0;
6071 //priv->eeprom_CustomerID = 0;
6072 //priv->eeprom_SubCustomerID = 0;
6073
6074 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
6075 return;
6076 }
6077
6078
6079 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
6080 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
6081 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
6082 RT_TRACE(COMP_INIT, "EEPROM Version ID: 0x%2x\n", priv->EEPROMVersion);
6083 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
6084 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
6085 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
6086 RT_TRACE(COMP_INIT, "bIgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
6087
6088
6089 // Read USB optional function.
6090 if(!priv->AutoloadFailFlag)
6091 {
6092 priv->EEPROMUsbOption = *(u8 *)&hwinfo[EEPROM_USB_OPTIONAL];
6093 }
6094 else
6095 {
6096 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
6097 }
6098
6099
6100 priv->EEPROMUsbEndPointNumber = rtl8192SU_UsbOptionToEndPointNumber((priv->EEPROMUsbOption&EEPROM_EP_NUMBER)>>3);
6101
6102 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
6103 RT_TRACE(COMP_INIT, "EndPoint Number = %#x\n", priv->EEPROMUsbEndPointNumber);
6104
6105#ifdef TO_DO_LIST
6106 //
6107 // Decide CustomerID according to VID/DID or EEPROM
6108 //
6109 switch(pHalData->EEPROMCustomerID)
6110 {
6111 case EEPROM_CID_ALPHA:
6112 pMgntInfo->CustomerID = RT_CID_819x_ALPHA;
6113 break;
6114
6115 case EEPROM_CID_CAMEO:
6116 pMgntInfo->CustomerID = RT_CID_819x_CAMEO;
6117 break;
6118
6119 case EEPROM_CID_SITECOM:
6120 pMgntInfo->CustomerID = RT_CID_819x_Sitecom;
6121 RT_TRACE(COMP_INIT, DBG_LOUD, ("CustomerID = 0x%4x\n", pMgntInfo->CustomerID));
6122
6123 break;
6124
6125 case EEPROM_CID_WHQL:
6126 Adapter->bInHctTest = TRUE;
6127
6128 pMgntInfo->bSupportTurboMode = FALSE;
6129 pMgntInfo->bAutoTurboBy8186 = FALSE;
6130
6131 pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
6132 pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
6133 pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
6134 pMgntInfo->keepAliveLevel = 0;
6135 break;
6136
6137 default:
6138 pMgntInfo->CustomerID = RT_CID_DEFAULT;
6139 break;
6140
6141 }
6142
6143 //
6144 // Led mode
6145 //
6146 switch(pMgntInfo->CustomerID)
6147 {
6148 case RT_CID_DEFAULT:
6149 case RT_CID_819x_ALPHA:
6150 pHalData->LedStrategy = SW_LED_MODE1;
6151 pHalData->bRegUseLed = TRUE;
6152 pHalData->SwLed1.bLedOn = TRUE;
6153 break;
6154 case RT_CID_819x_CAMEO:
6155 pHalData->LedStrategy = SW_LED_MODE1;
6156 pHalData->bRegUseLed = TRUE;
6157 break;
6158
6159 case RT_CID_819x_Sitecom:
6160 pHalData->LedStrategy = SW_LED_MODE2;
6161 pHalData->bRegUseLed = TRUE;
6162 break;
6163
6164 default:
6165 pHalData->LedStrategy = SW_LED_MODE0;
6166 break;
6167 }
6168#endif
6169
6170 // Read USB PHY parameters.
6171 for(i=0; i<5; i++)
6172 priv->EEPROMUsbPhyParam[i] = *(u8 *)&hwinfo[EEPROM_USB_PHY_PARA1+i];
6173
6174 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("USB PHY Param: \n"), pHalData->EEPROMUsbPhyParam, 5);
6175
6176
6177 //Read Permanent MAC address
6178 for(i=0; i<6; i++)
6179 dev->dev_addr[i] = *(u8 *)&hwinfo[EEPROM_NODE_ADDRESS_BYTE_0+i];
6180
6181 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
6182 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
6183 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
6184
6185 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
6186 dev->dev_addr[0], dev->dev_addr[1],
6187 dev->dev_addr[2], dev->dev_addr[3],
6188 dev->dev_addr[4], dev->dev_addr[5]);
6189
6190 //
6191 // Get CustomerID(Boad Type)
6192 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
6193 // Others: Reserved. Default is 0x2: RTL8192SU.
6194 //
6195 //if(!priv->AutoloadFailFlag)
6196 //{
6197 priv->EEPROMBoardType = *(u8 *)&hwinfo[EEPROM_BoardType];
6198 priv->rf_type = rtl8192SU_BoardTypeToRFtype(dev, priv->EEPROMBoardType);
6199 //}
6200 //else
6201 //{
6202 // priv->EEPROMBoardType = EEPROM_Default_BoardType;
6203 // priv->rf_type = RF_1T2R;
6204 //}
6205
6206#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
6207 priv->rf_chip = RF_6052;
6208#else
6209 priv->rf_chip = RF_8256;
6210#endif
6211
6212 priv->rf_chip = RF_6052;//lzm test
6213 RT_TRACE(COMP_INIT, "BoardType = 0x%2x\n", priv->EEPROMBoardType);
6214 RT_TRACE(COMP_INIT, "RF_Type = 0x%2x\n", priv->rf_type);
6215
6216 //
6217 // Read antenna tx power offset of B/C/D to A from EEPROM
6218 // and read ThermalMeter from EEPROM
6219 //
6220 //if(!priv->AutoloadFailFlag)
6221 {
6222 priv->EEPROMTxPowerDiff = *(u8 *)&hwinfo[EEPROM_PwDiff];
6223 priv->EEPROMThermalMeter = *(u8 *)&hwinfo[EEPROM_ThermalMeter];
6224 }
6225 //else
6226 //{
6227 // priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
6228 // priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
6229 //}
6230
6231 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMTxPowerDiff);
6232 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
6233
6234 //
6235 // Read Tx Power gain offset of legacy OFDM to HT rate.
6236 // Read CrystalCap from EEPROM
6237 //
6238 //if(!priv->AutoloadFailFlag)
6239 {
6240 priv->EEPROMCrystalCap = *(u8 *)&hwinfo[EEPROM_CrystalCap];
6241 }
6242 //else
6243 //{
6244 // priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
6245 //}
6246
6247 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
6248
6249 //
6250 // Get Tx Power Base.
6251 //
6252 //if(!priv->AutoloadFailFlag)
6253 {
6254 priv->EEPROMTxPwrBase = *(u8 *)&hwinfo[EEPROM_TxPowerBase];
6255 }
6256 //else
6257 //{
6258 // priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
6259 //}
6260
6261 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
6262
6263
6264 //
6265 // Get TSSI value for each path.
6266 //
6267 //if(!priv->AutoloadFailFlag)
6268 {
6269 priv->EEPROMTSSI_A = *(u8 *)&hwinfo[EEPROM_TSSI_A];
6270 priv->EEPROMTSSI_B = *(u8 *)&hwinfo[EEPROM_TSSI_B];
6271 }
6272 //else
6273 //{ // Default setting for Empty EEPROM
6274 // priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
6275 // priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
6276 //}
6277
6278 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
6279
6280 //
6281 // Get Tx Power tracking mode.
6282 //
6283 //if(!priv->AutoloadFailFlag)
6284 {
6285 priv->EEPROMTxPwrTkMode = *(u8 *)&hwinfo[EEPROM_TxPwTkMode];
6286 }
6287
6288 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
6289
6290
6291#ifdef EEPROM_OLD_FORMAT_SUPPORT
6292
6293 //
6294 // <Roger_Notes> The following settings are EFUSE version dependence.
6295 // So we need to adjust reading offset.
6296 // 2008.11.22.
6297 //
6298 {
6299 //
6300 // Get HT 2T Path A and B Power Index.
6301 //
6302 //if(!priv->AutoloadFailFlag)
6303 {
6304 for(i=0; i<6; i++)
6305 {
6306 priv->EEPROMHT2T_TxPwr[i] = *(u8 *)&hwinfo[EEPROM_HT2T_CH1_A+i];
6307 }
6308 }
6309
6310 //RT_PRINT_DATA(COMP_EFUSE, "HT2T TxPwr: \n"), pHalData->EEPROMHT2T_TxPwr, 6);
6311
6312 //
6313 // Get CCK and OFDM Tx Power Index.
6314 //
6315 //if(!priv->AutoloadFailFlag)
6316 {
6317 for(i=0; i<14; i++)
6318 {
6319 priv->EEPROMTxPowerLevelCCK24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_CCK_24G+i];
6320 priv->EEPROMTxPowerLevelOFDM24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_OFDM_24G+i];
6321 }
6322 }
6323
6324 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("CCK 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelCCK24G, 14);
6325 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("OFDM 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelOFDM24G, 14);
6326
6327 //
6328 // Update HAL variables.
6329 //
6330 memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
6331 memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
6332 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), pHalData->TxPowerLevelCCK, 14);
6333 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), pHalData->TxPowerLevelOFDM24G, 14);
6334
6335 }
6336#else // Support new version of EFUSE content, 2008.11.22.
6337 {
6338 //
6339 // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes)
6340 // Update CCK, OFDM (1T/2T)Tx Power Index from above buffer.
6341 //
6342
6343 //
6344 // Get Tx Power Level by Channel
6345 //
6346 //if(!priv->AutoloadFailFlag)
6347 {
6348 // Read Tx power of Channel 1 ~ 14 from EFUSE.
6349 // 92S suupport RF A & B
6350 for (rf_path = 0; rf_path < 2; rf_path++)
6351 {
6352 for (i = 0; i < 3; i++)
6353 {
6354 // Read CCK RF A & B Tx power
6355 priv->RfCckChnlAreaTxPwr[rf_path][i] =
6356 hwinfo[EEPROM_TxPwIndex+rf_path*3+i];
6357
6358 // Read OFDM RF A & B Tx power for 1T
6359 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
6360 hwinfo[EEPROM_TxPwIndex+6+rf_path*3+i];
6361
6362 // Read OFDM RF A & B Tx power for 2T
6363 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
6364 hwinfo[EEPROM_TxPwIndex+12+rf_path*3+i];
6365 }
6366 }
6367
6368 }
6369//
6370 // Update Tx Power HAL variables.
6371//
6372 for (rf_path = 0; rf_path < 2; rf_path++)
6373 {
6374 for (i = 0; i < 3; i++)
6375 {
6376 RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
6377 priv->RfCckChnlAreaTxPwr[rf_path][i]);
6378 RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
6379 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
6380 RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
6381 }
6382
6383 // Assign dedicated channel tx power
6384 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
6385 {
6386 if (i < 3) // Cjanel 1-3
6387 index = 0;
6388 else if (i < 9) // Channel 4-9
6389 index = 1;
6390 else // Channel 10-14
6391 index = 2;
6392
6393 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
6394 priv->RfTxPwrLevelCck[rf_path][i] =
6395 priv->RfCckChnlAreaTxPwr[rf_path][index];
6396 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
6397 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
6398 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
6399 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
6400 if (rf_path == 0)
6401 {
6402 priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ;
6403 priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i];
6404 }
6405 }
6406
6407 for(i=0; i<14; i++)
6408 {
6409 RT_TRACE((COMP_INIT),
6410 "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
6411 rf_path, i, priv->RfTxPwrLevelCck[rf_path][i],
6412 priv->RfTxPwrLevelOfdm1T[rf_path][i] ,
6413 priv->RfTxPwrLevelOfdm2T[rf_path][i] );
6414 }
6415 }
6416 }
6417
6418 //
6419 // 2009/02/09 Cosa add for new EEPROM format
6420 //
6421 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
6422 {
6423 // Read tx power difference between HT OFDM 20/40 MHZ
6424 if (i < 3) // Cjanel 1-3
6425 index = 0;
6426 else if (i < 9) // Channel 4-9
6427 index = 1;
6428 else // Channel 10-14
6429 index = 2;
6430
6431 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF+index])&0xff;
6432 priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF);
6433 priv->TxPwrHt20Diff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
6434
6435 // Read OFDM<->HT tx power diff
6436 if (i < 3) // Cjanel 1-3
6437 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF])&0xff;
6438 else if (i < 9) // Channel 4-9
6439 tempval = (*(u8 *)&hwinfo[EEPROM_PwDiff])&0xff;
6440 else // Channel 10-14
6441 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+1])&0xff;
6442
6443 //cosa tempval = (*(u1Byte *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+index])&0xff;
6444 priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF);
6445 priv->TxPwrLegacyHtDiff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
6446
6447 //
6448 // Read Band Edge tx power offset and check if user enable the ability
6449 //
6450 // HT 40 band edge channel
6451 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE])&0xff;
6452 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
6453 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
6454 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+1])&0xff;
6455 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
6456 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
6457 // HT 20 band edge channel
6458 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+2])&0xff;
6459 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
6460 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
6461 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+3])&0xff;
6462 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
6463 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
6464 // OFDM band edge channel
6465 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+4])&0xff;
6466 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
6467 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
6468 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+5])&0xff;
6469 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
6470 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
6471
6472 priv->TxPwrbandEdgeFlag = (*(u8 *)&hwinfo[TX_PWR_BAND_EDGE_CHK]);
6473 }
6474
6475 for(i=0; i<14; i++)
6476 RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]);
6477 for(i=0; i<14; i++)
6478 RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][i]);
6479 for(i=0; i<14; i++)
6480 RT_TRACE(COMP_INIT, "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_B][i]);
6481 for(i=0; i<14; i++)
6482 RT_TRACE(COMP_INIT, "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_B][i]);
6483 RT_TRACE(COMP_INIT, "RF-A HT40 band-edge low/high power diff = 0x%x/0x%x\n",
6484 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0],
6485 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]);
6486 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT40 band-edge low/high power diff = 0x%x/0x%x\n",
6487 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0],
6488 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1]);
6489
6490 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A HT20 band-edge low/high power diff = 0x%x/0x%x\n",
6491 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0],
6492 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]);
6493 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT20 band-edge low/high power diff = 0x%x/0x%x\n",
6494 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0],
6495 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1]);
6496
6497 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A OFDM band-edge low/high power diff = 0x%x/0x%x\n",
6498 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0],
6499 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]);
6500 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B OFDM band-edge low/high power diff = 0x%x/0x%x\n",
6501 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0],
6502 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]);
6503 RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag);
6504#endif
6505
6506 //
6507 // Update remained HAL variables.
6508 //
6509 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
6510 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;
6511 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
6512 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit[3:0]
6513 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit[7:4]
6514 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit[15:12]
6515 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter&0x1f);// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
6516 priv->LedStrategy = SW_LED_MODE0;
6517
6518 init_rate_adaptive(dev);
6519
6520 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
6521
6522 //return RT_STATUS_SUCCESS;
6523}
6524
6525
6526//
6527// Description:
6528// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
6529//
6530// Assumption:
6531// 1. CR9346 regiser has verified.
6532// 2. PASSIVE_LEVEL (USB interface)
6533//
6534// Created by Roger, 2008.10.21.
6535//
6536static void rtl8192SU_read_eeprom_info(struct net_device *dev)
6537{
6538 struct r8192_priv *priv = ieee80211_priv(dev);
6539 u8 tmpU1b;
6540
6541 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
6542
6543 // Retrieve Chip version.
6544 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
6545 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
6546
6547 tmpU1b = read_nic_byte(dev, EPROM_CMD);//CR9346
6548
6549 // To check system boot selection.
6550 if (tmpU1b & CmdEERPOMSEL)
6551 {
6552 RT_TRACE(COMP_INIT, "Boot from EEPROM\n");
6553 priv->EepromOrEfuse = TRUE;
6554 }
6555 else
6556 {
6557 RT_TRACE(COMP_INIT, "Boot from EFUSE\n");
6558 priv->EepromOrEfuse = FALSE;
6559 }
6560
6561 // To check autoload success or not.
6562 if (tmpU1b & CmdEEPROM_En)
6563 {
6564 RT_TRACE(COMP_INIT, "Autoload OK!!\n");
6565 priv->AutoloadFailFlag=FALSE;
6566 rtl8192SU_ReadAdapterInfo8192SUsb(dev);//eeprom or e-fuse
6567 }
6568 else
6569 { // Auto load fail.
6570 RT_TRACE(COMP_INIT, "AutoLoad Fail reported from CR9346!!\n");
6571 priv->AutoloadFailFlag=TRUE;
6572 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
6573
6574 //if (IS_BOOT_FROM_EFUSE(Adapter))
6575 if(!priv->EepromOrEfuse)
6576 {
6577 RT_TRACE(COMP_INIT, "Update shadow map for EFuse future use!!\n");
6578 EFUSE_ShadowMapUpdate(dev);
6579 }
6580 }
6581#ifdef TO_DO_LIST
6582 if((priv->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
6583 {
6584 pMgntInfo->ChannelPlan = HalMapChannelPlan8192S(Adapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
6585 pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
6586 }
6587 else
6588 {
6589 pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
6590 }
6591
6592 switch(pMgntInfo->ChannelPlan)
6593 {
6594 case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
6595 {
6596 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
6597
6598 pDot11dInfo->bEnabled = TRUE;
6599 }
6600 RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
6601 break;
6602 }
6603
6604 RT_TRACE(COMP_INIT, DBG_LOUD, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
6605 RT_TRACE(COMP_INIT, DBG_LOUD, ("ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
6606
6607 RT_TRACE(COMP_INIT, DBG_LOUD, ("<==== ReadAdapterInfo8192S\n"));
6608#endif
6609
6610 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
6611
6612 //return RT_STATUS_SUCCESS;
6613}
6614#else
6615static void rtl8192_read_eeprom_info(struct net_device* dev)
6616{
6617 u16 wEPROM_ID = 0;
6618 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x02};
6619 u8 bLoad_From_EEPOM = false;
6620 struct r8192_priv *priv = ieee80211_priv(dev);
6621 u16 tmpValue = 0;
6622 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
6623 wEPROM_ID = eprom_read(dev, 0); //first read EEPROM ID out;
6624 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", wEPROM_ID);
6625
6626 if (wEPROM_ID != RTL8190_EEPROM_ID)
6627 {
6628 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", wEPROM_ID, RTL8190_EEPROM_ID);
6629 }
6630 else
6631 bLoad_From_EEPOM = true;
6632
6633 if (bLoad_From_EEPOM)
6634 {
6635 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
6636 priv->eeprom_vid = endian_swap(&tmpValue);
6637 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
6638 tmpValue = eprom_read(dev, (EEPROM_ChannelPlan>>1));
6639 priv->eeprom_ChannelPlan =((tmpValue&0xff00)>>8);
6640 priv->btxpowerdata_readfromEEPORM = true;
6641 priv->eeprom_CustomerID = eprom_read(dev, (EEPROM_Customer_ID>>1)) >>8;
6642 }
6643 else
6644 {
6645 priv->eeprom_vid = 0;
6646 priv->eeprom_pid = 0;
6647 priv->card_8192_version = VERSION_819xU_B;
6648 priv->eeprom_ChannelPlan = 0;
6649 priv->eeprom_CustomerID = 0;
6650 }
6651 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
6652 //set channelplan from eeprom
6653 priv->ChannelPlan = priv->eeprom_ChannelPlan;
6654 if (bLoad_From_EEPOM)
6655 {
6656 int i;
6657 for (i=0; i<6; i+=2)
6658 {
6659 u16 tmp = 0;
6660 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
6661 *(u16*)(&dev->dev_addr[i]) = tmp;
6662 }
6663 }
6664 else
6665 {
6666 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
6667 //should I set IDR0 here?
6668 }
6669 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
6670 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
6671 priv->rf_chip = RF_8256;
6672
6673 if (priv->card_8192_version == (u8)VERSION_819xU_A)
6674 {
6675 //read Tx power gain offset of legacy OFDM to HT rate
6676 if (bLoad_From_EEPOM)
6677 priv->EEPROMTxPowerDiff = (eprom_read(dev, (EEPROM_TxPowerDiff>>1))&0xff00) >> 8;
6678 else
6679 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPower;
6680 RT_TRACE(COMP_EPROM, "TxPowerDiff:%d\n", priv->EEPROMTxPowerDiff);
6681 //read ThermalMeter from EEPROM
6682 if (bLoad_From_EEPOM)
6683 priv->EEPROMThermalMeter = (u8)(eprom_read(dev, (EEPROM_ThermalMeter>>1))&0x00ff);
6684 else
6685 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
6686 RT_TRACE(COMP_EPROM, "ThermalMeter:%d\n", priv->EEPROMThermalMeter);
6687 //vivi, for tx power track
6688 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
6689 //read antenna tx power offset of B/C/D to A from EEPROM
6690 if (bLoad_From_EEPOM)
6691 priv->EEPROMPwDiff = (eprom_read(dev, (EEPROM_PwDiff>>1))&0x0f00)>>8;
6692 else
6693 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
6694 RT_TRACE(COMP_EPROM, "TxPwDiff:%d\n", priv->EEPROMPwDiff);
6695 // Read CrystalCap from EEPROM
6696 if (bLoad_From_EEPOM)
6697 priv->EEPROMCrystalCap = (eprom_read(dev, (EEPROM_CrystalCap>>1))&0x0f);
6698 else
6699 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
6700 RT_TRACE(COMP_EPROM, "CrystalCap = %d\n", priv->EEPROMCrystalCap);
6701 //get per-channel Tx power level
6702 if (bLoad_From_EEPOM)
6703 priv->EEPROM_Def_Ver = (eprom_read(dev, (EEPROM_TxPwIndex_Ver>>1))&0xff00)>>8;
6704 else
6705 priv->EEPROM_Def_Ver = 1;
6706 RT_TRACE(COMP_EPROM, "EEPROM_DEF_VER:%d\n", priv->EEPROM_Def_Ver);
6707 if (priv->EEPROM_Def_Ver == 0) //old eeprom definition
6708 {
6709 int i;
6710 if (bLoad_From_EEPOM)
6711 priv->EEPROMTxPowerLevelCCK = (eprom_read(dev, (EEPROM_TxPwIndex_CCK>>1))&0xff) >> 8;
6712 else
6713 priv->EEPROMTxPowerLevelCCK = 0x10;
6714 RT_TRACE(COMP_EPROM, "CCK Tx Power Levl: 0x%02x\n", priv->EEPROMTxPowerLevelCCK);
6715 for (i=0; i<3; i++)
6716 {
6717 if (bLoad_From_EEPOM)
6718 {
6719 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G+i)>>1);
6720 if (((EEPROM_TxPwIndex_OFDM_24G+i) % 2) == 0)
6721 tmpValue = tmpValue & 0x00ff;
6722 else
6723 tmpValue = (tmpValue & 0xff00) >> 8;
6724 }
6725 else
6726 tmpValue = 0x10;
6727 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8) tmpValue;
6728 RT_TRACE(COMP_EPROM, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK);
6729 }
6730 }//end if EEPROM_DEF_VER == 0
6731 else if (priv->EEPROM_Def_Ver == 1)
6732 {
6733 if (bLoad_From_EEPOM)
6734 {
6735 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1>>1));
6736 tmpValue = (tmpValue & 0xff00) >> 8;
6737 }
6738 else
6739 tmpValue = 0x10;
6740 priv->EEPROMTxPowerLevelCCK_V1[0] = (u8)tmpValue;
6741
6742 if (bLoad_From_EEPOM)
6743 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1 + 2)>>1);
6744 else
6745 tmpValue = 0x1010;
6746 *((u16*)(&priv->EEPROMTxPowerLevelCCK_V1[1])) = tmpValue;
6747 if (bLoad_From_EEPOM)
6748 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1>>1));
6749 else
6750 tmpValue = 0x1010;
6751 *((u16*)(&priv->EEPROMTxPowerLevelOFDM24G[0])) = tmpValue;
6752 if (bLoad_From_EEPOM)
6753 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1+2)>>1);
6754 else
6755 tmpValue = 0x10;
6756 priv->EEPROMTxPowerLevelOFDM24G[2] = (u8)tmpValue;
6757 }//endif EEPROM_Def_Ver == 1
6758
6759 //update HAL variables
6760 //
6761 {
6762 int i;
6763 for (i=0; i<14; i++)
6764 {
6765 if (i<=3)
6766 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[0];
6767 else if (i>=4 && i<=9)
6768 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[1];
6769 else
6770 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[2];
6771 }
6772
6773 for (i=0; i<14; i++)
6774 {
6775 if (priv->EEPROM_Def_Ver == 0)
6776 {
6777 if (i<=3)
6778 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[0] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]);
6779 else if (i>=4 && i<=9)
6780 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK;
6781 else
6782 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[2] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]);
6783 }
6784 else if (priv->EEPROM_Def_Ver == 1)
6785 {
6786 if (i<=3)
6787 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[0];
6788 else if (i>=4 && i<=9)
6789 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[1];
6790 else
6791 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[2];
6792 }
6793 }
6794 }//end update HAL variables
6795 priv->TxPowerDiff = priv->EEPROMPwDiff;
6796// Antenna B gain offset to antenna A, bit0~3
6797 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
6798 // Antenna C gain offset to antenna A, bit4~7
6799 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
6800 // CrystalCap, bit12~15
6801 priv->CrystalCap = priv->EEPROMCrystalCap;
6802 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
6803 // 92U does not enable TX power tracking.
6804 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
6805 }//end if VersionID == VERSION_819xU_A
6806
6807//added by vivi, for dlink led, 20080416
6808 switch(priv->eeprom_CustomerID)
6809 {
6810 case EEPROM_CID_RUNTOP:
6811 priv->CustomerID = RT_CID_819x_RUNTOP;
6812 break;
6813
6814 case EEPROM_CID_DLINK:
6815 priv->CustomerID = RT_CID_DLINK;
6816 break;
6817
6818 default:
6819 priv->CustomerID = RT_CID_DEFAULT;
6820 break;
6821
6822 }
6823
6824 switch(priv->CustomerID)
6825 {
6826 case RT_CID_819x_RUNTOP:
6827 priv->LedStrategy = SW_LED_MODE2;
6828 break;
6829
6830 case RT_CID_DLINK:
6831 priv->LedStrategy = SW_LED_MODE4;
6832 break;
6833
6834 default:
6835 priv->LedStrategy = SW_LED_MODE0;
6836 break;
6837
6838 }
6839
6840
6841 if(priv->rf_type == RF_1T2R)
6842 {
6843 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
6844 }
6845 else
6846 {
6847 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
6848 }
6849
6850 // 2008/01/16 MH We can only know RF type in the function. So we have to init
6851 // DIG RATR table again.
6852 init_rate_adaptive(dev);
6853 //we need init DIG RATR table here again.
6854
6855 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
6856 return;
6857}
6858#endif
6859
6860short rtl8192_get_channel_map(struct net_device * dev)
6861{
6862 struct r8192_priv *priv = ieee80211_priv(dev);
6863#ifdef ENABLE_DOT11D
6864 if(priv->ChannelPlan > COUNTRY_CODE_GLOBAL_DOMAIN){
6865 printk("rtl8180_init:Error channel plan! Set to default.\n");
6866 priv->ChannelPlan= 0;
6867 }
6868 RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan);
6869
6870 rtl819x_set_channel_map(priv->ChannelPlan, priv);
6871#else
6872 int ch,i;
6873 //Set Default Channel Plan
6874 if(!channels){
6875 DMESG("No channels, aborting");
6876 return -1;
6877 }
6878 ch=channels;
6879 priv->ChannelPlan= 0;//hikaru
6880 // set channels 1..14 allowed in given locale
6881 for (i=1; i<=14; i++) {
6882 (priv->ieee80211->channel_map)[i] = (u8)(ch & 0x01);
6883 ch >>= 1;
6884 }
6885#endif
6886 return 0;
6887}
6888
6889short rtl8192_init(struct net_device *dev)
6890{
6891
6892 struct r8192_priv *priv = ieee80211_priv(dev);
6893
6894#ifndef RTL8192SU
6895 memset(&(priv->stats),0,sizeof(struct Stats));
6896 memset(priv->txqueue_to_outpipemap,0,9);
6897#ifdef PIPE12
6898 {
6899 int i=0;
6900 u8 queuetopipe[]={3,2,1,0,4,8,7,6,5};
6901 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
6902/* for(i=0;i<9;i++)
6903 printk("%d ",priv->txqueue_to_outpipemap[i]);
6904 printk("\n");*/
6905 }
6906#else
6907 {
6908 u8 queuetopipe[]={3,2,1,0,4,4,0,4,4};
6909 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
6910/* for(i=0;i<9;i++)
6911 printk("%d ",priv->txqueue_to_outpipemap[i]);
6912 printk("\n");*/
6913 }
6914#endif
6915#endif
6916 rtl8192_init_priv_variable(dev);
6917 rtl8192_init_priv_lock(priv);
6918 rtl8192_init_priv_task(dev);
6919 rtl8192_get_eeprom_size(dev);
6920 priv->ops->rtl819x_read_eeprom_info(dev);
6921 rtl8192_get_channel_map(dev);
6922 init_hal_dm(dev);
6923 init_timer(&priv->watch_dog_timer);
6924 priv->watch_dog_timer.data = (unsigned long)dev;
6925 priv->watch_dog_timer.function = watch_dog_timer_callback;
6926
6927 //rtl8192_adapter_start(dev);
6928#ifdef DEBUG_EPROM
6929 dump_eprom(dev);
6930#endif
6931 return 0;
6932}
6933
6934/******************************************************************************
6935 *function: This function actually only set RRSR, RATR and BW_OPMODE registers
6936 * not to do all the hw config as its name says
6937 * input: net_device dev
6938 * output: none
6939 * return: none
6940 * notice: This part need to modified according to the rate set we filtered
6941 * ****************************************************************************/
6942void rtl8192_hwconfig(struct net_device* dev)
6943{
6944 u32 regRATR = 0, regRRSR = 0;
6945 u8 regBwOpMode = 0, regTmp = 0;
6946 struct r8192_priv *priv = ieee80211_priv(dev);
6947
6948// Set RRSR, RATR, and BW_OPMODE registers
6949 //
6950 switch(priv->ieee80211->mode)
6951 {
6952 case WIRELESS_MODE_B:
6953 regBwOpMode = BW_OPMODE_20MHZ;
6954 regRATR = RATE_ALL_CCK;
6955 regRRSR = RATE_ALL_CCK;
6956 break;
6957 case WIRELESS_MODE_A:
6958 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
6959 regRATR = RATE_ALL_OFDM_AG;
6960 regRRSR = RATE_ALL_OFDM_AG;
6961 break;
6962 case WIRELESS_MODE_G:
6963 regBwOpMode = BW_OPMODE_20MHZ;
6964 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6965 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6966 break;
6967 case WIRELESS_MODE_AUTO:
6968#ifdef TO_DO_LIST
6969 if (Adapter->bInHctTest)
6970 {
6971 regBwOpMode = BW_OPMODE_20MHZ;
6972 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6973 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6974 }
6975 else
6976#endif
6977 {
6978 regBwOpMode = BW_OPMODE_20MHZ;
6979 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6980 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6981 }
6982 break;
6983 case WIRELESS_MODE_N_24G:
6984 // It support CCK rate by default.
6985 // CCK rate will be filtered out only when associated AP does not support it.
6986 regBwOpMode = BW_OPMODE_20MHZ;
6987 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6988 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
6989 break;
6990 case WIRELESS_MODE_N_5G:
6991 regBwOpMode = BW_OPMODE_5G;
6992 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
6993 regRRSR = RATE_ALL_OFDM_AG;
6994 break;
6995 }
6996
6997 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
6998 {
6999 u32 ratr_value = 0;
7000 ratr_value = regRATR;
7001 if (priv->rf_type == RF_1T2R)
7002 {
7003 ratr_value &= ~(RATE_ALL_OFDM_2SS);
7004 }
7005 write_nic_dword(dev, RATR0, ratr_value);
7006 write_nic_byte(dev, UFWP, 1);
7007 }
7008 regTmp = read_nic_byte(dev, 0x313);
7009 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
7010 write_nic_dword(dev, RRSR, regRRSR);
7011
7012 //
7013 // Set Retry Limit here
7014 //
7015 write_nic_word(dev, RETRY_LIMIT,
7016 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | \
7017 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
7018 // Set Contention Window here
7019
7020 // Set Tx AGC
7021
7022 // Set Tx Antenna including Feedback control
7023
7024 // Set Auto Rate fallback control
7025
7026
7027}
7028
7029#ifdef RTL8192SU
7030#ifdef USB_RX_AGGREGATION_SUPPORT
7031u8 rtl8192SU_MapRxPageSizeToIdx(u16 RxPktSize )
7032{
7033 switch(RxPktSize)
7034 {
7035 case 64: return 0; break;
7036 case 128 : return 1; break;
7037 case 256: return 2; break;
7038 case 512: return 3; break;
7039 case 1024: return 4; break;
7040 default: return 0; // We use 64bytes in defult.
7041 }
7042}
7043#endif
7044
7045//
7046// Description:
7047// Initial HW relted registers.
7048//
7049// Assumption:
7050// Config RTL8192S USB MAC, we should config MAC before download FW.
7051//
7052// 2008.09.03, Added by Roger.
7053//
7054static void rtl8192SU_MacConfigBeforeFwDownloadASIC(struct net_device *dev)
7055{
7056 u8 tmpU1b;// i;
7057// u16 tmpU2b;
7058// u32 tmpU4b;
7059 u8 PollingCnt = 20;
7060
7061 RT_TRACE(COMP_INIT, "--->MacConfigBeforeFwDownloadASIC()\n");
7062
7063 //2MAC Initialization for power on sequence, Revised by Roger. 2008.09.03.
7064
7065 //
7066 //<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and
7067 // MAC I/O to solve FW download fail when system from resume sate.
7068 // 2008.11.04.
7069 //
7070 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
7071 if(tmpU1b & 0x80)
7072 {
7073 tmpU1b &= 0x3f;
7074 write_nic_byte(dev, SYS_CLKR+1, tmpU1b);
7075 }
7076 // Clear FW RPWM for FW control LPS. by tynli. 2009.02.23
7077 write_nic_byte(dev, RPWM, 0x0);
7078
7079 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7080 tmpU1b &= 0x73;
7081 write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b);
7082 udelay(1000);
7083
7084 //Revised POS, suggested by SD1 Alex, 2008.09.27.
7085 write_nic_byte(dev, SPS0_CTRL+1, 0x53);
7086 write_nic_byte(dev, SPS0_CTRL, 0x57);
7087
7088 //Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
7089 tmpU1b = read_nic_byte(dev, AFE_MISC);
7090 write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_BGEN|AFE_MBEN));
7091
7092 //Enable PLL Power (LDOA15V)
7093 tmpU1b = read_nic_byte(dev, LDOA15_CTRL);
7094 write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|LDA15_EN));
7095
7096 //Enable LDOV12D block
7097 tmpU1b = read_nic_byte(dev, LDOV12D_CTRL);
7098 write_nic_byte(dev, LDOV12D_CTRL, (tmpU1b|LDV12_EN));
7099
7100 //mpU1b = read_nic_byte(Adapter, SPS1_CTRL);
7101 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_LDEN));
7102
7103 //PlatformSleepUs(2000);
7104
7105 //Enable Switch Regulator Block
7106 //tmpU1b = read_nic_byte(Adapter, SPS1_CTRL);
7107 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_SWEN));
7108
7109 //write_nic_dword(Adapter, SPS1_CTRL, 0x00a7b267);
7110
7111 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
7112 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b|0x08));
7113
7114 //Engineer Packet CP test Enable
7115 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7116 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x20));
7117
7118 //Support 64k IMEM, suggested by SD1 Alex.
7119 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
7120 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b& 0x68));
7121
7122 //Enable AFE clock
7123 tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL+1);
7124 write_nic_byte(dev, AFE_XTAL_CTRL+1, (tmpU1b& 0xfb));
7125
7126 //Enable AFE PLL Macro Block
7127 tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL);
7128 write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|0x11));
7129
7130 //Attatch AFE PLL to MACTOP/BB/PCIe Digital
7131 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL);
7132 write_nic_byte(dev, SYS_ISO_CTRL, (tmpU1b&0xEE));
7133
7134 // Switch to 40M clock
7135 write_nic_byte(dev, SYS_CLKR, 0x00);
7136
7137 //SSC Disable
7138 tmpU1b = read_nic_byte(dev, SYS_CLKR);
7139 //write_nic_byte(dev, SYS_CLKR, (tmpU1b&0x5f));
7140 write_nic_byte(dev, SYS_CLKR, (tmpU1b|0xa0));
7141
7142 //Enable MAC clock
7143 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
7144 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x18));
7145
7146 //Revised POS, suggested by SD1 Alex, 2008.09.27.
7147 write_nic_byte(dev, PMC_FSM, 0x02);
7148
7149 //Enable Core digital and enable IOREG R/W
7150 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7151 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x08));
7152
7153 //Enable REG_EN
7154 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7155 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x80));
7156
7157 //Switch the control path to FW
7158 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
7159 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x80)& 0xBF);
7160
7161 write_nic_byte(dev, CMDR, 0xFC);
7162 write_nic_byte(dev, CMDR+1, 0x37);
7163
7164 //Fix the RX FIFO issue(usb error), 970410
7165 tmpU1b = read_nic_byte_E(dev, 0x5c);
7166 write_nic_byte_E(dev, 0x5c, (tmpU1b|BIT7));
7167
7168 //For power save, used this in the bit file after 970621
7169 tmpU1b = read_nic_byte(dev, SYS_CLKR);
7170 write_nic_byte(dev, SYS_CLKR, tmpU1b&(~SYS_CPU_CLKSEL));
7171
7172 // Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16.
7173 write_nic_byte_E(dev, 0x1c, 0x80);
7174
7175 //
7176 // <Roger_EXP> To make sure that TxDMA can ready to download FW.
7177 // We should reset TxDMA if IMEM RPT was not ready.
7178 // Suggested by SD1 Alex. 2008.10.23.
7179 //
7180 do
7181 {
7182 tmpU1b = read_nic_byte(dev, TCR);
7183 if((tmpU1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
7184 break;
7185 //PlatformStallExecution(5);
7186 udelay(5);
7187 }while(PollingCnt--); // Delay 1ms
7188
7189 if(PollingCnt <= 0 )
7190 {
7191 RT_TRACE(COMP_INIT, "MacConfigBeforeFwDownloadASIC(): Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpU1b);
7192 tmpU1b = read_nic_byte(dev, CMDR);
7193 write_nic_byte(dev, CMDR, tmpU1b&(~TXDMA_EN));
7194 udelay(2);
7195 write_nic_byte(dev, CMDR, tmpU1b|TXDMA_EN);// Reset TxDMA
7196 }
7197
7198
7199 RT_TRACE(COMP_INIT, "<---MacConfigBeforeFwDownloadASIC()\n");
7200}
7201#ifdef USB_RX_AGGREGATION_SUPPORT
7202void rtl8192SU_HalUsbRxAggr8192SUsb(struct net_device *dev, bool Value)
7203{
7204 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7205 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;;
7206
7207
7208 //
7209 // <Roger_Notes> We decrease Rx page aggregated threshold in B/G mode.
7210 // 2008.10.29
7211 //
7212 if(priv->ieee80211->mode == WIRELESS_MODE_B || priv->ieee80211->mode == WIRELESS_MODE_G)
7213 {// Overwrite current settings to disable Rx Aggregation.
7214 Value = false;
7215 }
7216
7217 // Alway set Rx Aggregation to Disable if current platform is Win2K USB 1.1, by Emily
7218 //if(PLATFORM_LIMITED_RX_BUF_SIZE(Adapter))
7219 // Value = FALSE;
7220
7221 // Always set Rx Aggregation to Disable if connected AP is Realtek AP, by Joseph
7222 //if(pHTInfo->bCurrentRT2RTAggregation)
7223 // Value = FALSE;
7224
7225 // The RX aggregation may be enabled/disabled dynamically according current traffic stream.
7226 //Enable Rx aggregation if downlink traffic is busier than uplink traffic. by Guangan
7227 if(priv->bCurrentRxAggrEnable != Value)
7228 {
7229 priv->bCurrentRxAggrEnable = Value;
7230 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_USB_RX_AGGR, (pu1Byte)&pHalData->bCurrentRxAggrEnable);
7231 {
7232 //u8 Setting = ((pu1Byte)(val))[0];
7233 u8 Setting = priv->bCurrentRxAggrEnable
7234 u32 ulValue;
7235
7236 if(Setting==0)
7237 {
7238 //
7239 // <Roger_Notes> Reduce aggregated page threshold to 0x01 and set minimal threshold 0x0a.
7240 // i.e., disable Rx aggregation.
7241 //
7242 ulValue = 0x0001000a;
7243 }
7244 else
7245 {
7246 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
7247 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
7248
7249 if (priv->bForcedUsbRxAggr)
7250 {// Using forced settings.
7251 ulValue = priv->ForcedUsbRxAggrInfo;
7252 }
7253 else
7254 {// Using default settings.
7255
7256 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
7257 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
7258 }
7259 }
7260
7261 write_nic_byte(dev, RXDMA_AGG_PG_TH, (u8)((ulValue&0xff0000)>>16));
7262 write_nic_byte_E(dev, USB_RX_AGG_TIMEOUT, (u8)(ulValue&0xff));
7263
7264 priv->LastUsbRxAggrInfoSetting = ulValue;
7265
7266 RT_TRACE(COMP_HT|COMP_RECV, "Set HW_VAR_USB_RX_AGGR: ulValue(%#x)\n", ulValue);
7267 }
7268 RT_TRACE(COMP_RECV, "HalUsbRxAggr8192SUsb() : Set RxAggregation to %s\n", Value?"ON":"OFF");
7269 }
7270
7271}
7272#endif
7273
7274#ifdef USB_RX_AGGREGATION_SUPPORT
7275void rtl8192SU_HalUsbRxAggr8192SUsb(struct net_device *dev, bool Value)
7276{
7277 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7278 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;;
7279
7280
7281 //
7282 // <Roger_Notes> We decrease Rx page aggregated threshold in B/G mode.
7283 // 2008.10.29
7284 //
7285 if((priv->ieee80211->mode & WIRELESS_MODE_B) || (priv->ieee80211->mode & WIRELESS_MODE_G))
7286 {// Overwrite current settings to disable Rx Aggregation.
7287 Value = false;
7288 }
7289
7290 // Alway set Rx Aggregation to Disable if current platform is Win2K USB 1.1, by Emily
7291 //if(PLATFORM_LIMITED_RX_BUF_SIZE(Adapter))
7292 // Value = FALSE;
7293
7294 // Always set Rx Aggregation to Disable if connected AP is Realtek AP, by Joseph
7295 //if(pHTInfo->bCurrentRT2RTAggregation)
7296 // Value = FALSE;
7297
7298 // The RX aggregation may be enabled/disabled dynamically according current traffic stream.
7299 //Enable Rx aggregation if downlink traffic is busier than uplink traffic. by Guangan
7300 if(priv->bCurrentRxAggrEnable != Value)
7301 {
7302 priv->bCurrentRxAggrEnable = Value;
7303 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_USB_RX_AGGR, (pu1Byte)&pHalData->bCurrentRxAggrEnable);
7304 {
7305 //u8 Setting = ((pu1Byte)(val))[0];
7306 u8 Setting = priv->bCurrentRxAggrEnable
7307 u32 ulValue;
7308
7309 if(Setting==0)
7310 {
7311 //
7312 // <Roger_Notes> Reduce aggregated page threshold to 0x01 and set minimal threshold 0x0a.
7313 // i.e., disable Rx aggregation.
7314 //
7315 ulValue = 0x0001000a;
7316 }
7317 else
7318 {
7319 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
7320 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
7321
7322 if (priv->bForcedUsbRxAggr)
7323 {// Using forced settings.
7324 ulValue = priv->ForcedUsbRxAggrInfo;
7325 }
7326 else
7327 {// Using default settings.
7328
7329 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
7330 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
7331 }
7332 }
7333
7334 write_nic_byte(dev, RXDMA_AGG_PG_TH, (u8)((ulValue&0xff0000)>>16));
7335 write_nic_byte_E(dev, USB_RX_AGG_TIMEOUT, (u8)(ulValue&0xff));
7336
7337 priv->LastUsbRxAggrInfoSetting = ulValue;
7338
7339 RT_TRACE(COMP_HT|COMP_RECV, "Set HW_VAR_USB_RX_AGGR: ulValue(%#x)\n", ulValue);
7340 }
7341 RT_TRACE(COMP_RECV, "HalUsbRxAggr8192SUsb() : Set RxAggregation to %s\n", Value?"ON":"OFF");
7342 }
7343
7344}
7345
7346u8 rtl8192SU_MapRxPageSizeToIdx(u16 RxPktSize )
7347{
7348 switch(RxPktSize)
7349 {
7350 case 64: return 0; break;
7351 case 128 : return 1; break;
7352 case 256: return 2; break;
7353 case 512: return 3; break;
7354 case 1024: return 4; break;
7355 default: return 0; // We use 64bytes in defult.
7356 }
7357}
7358#endif
7359
7360#if 0
7361static void rtl8192SU_SetHwRegAmpduMinSpace(struct net_device *dev, u8 MinSpaceCfg)
7362{
7363 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7364 struct ieee80211_device* ieee = priv->ieee80211;
7365 u8 MinSpacingToSet;
7366 u8 SecMinSpace;
7367
7368#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE
7369 MinSpacingToSet = MinSpaceCfg;
7370 if(MinSpacingToSet <= 7)
7371 {
7372 switch(ieee->pairwise_key_type)
7373 {
7374 case KEY_TYPE_NA: SecMinSpace = 0; break;
7375 case KEY_TYPE_CCMP:
7376 case KEY_TYPE_WEP40:
7377 case KEY_TYPE_WEP104:
7378 case KEY_TYPE_TKIP: SecMinSpace = 6; break;
7379 default: SecMinSpace = 7; break;
7380 }
7381
7382 if(MinSpacingToSet < SecMinSpace)
7383 MinSpacingToSet = SecMinSpace;
7384 priv->MinSpaceCfg = ((priv->MinSpaceCfg&0xf8) |MinSpacingToSet);
7385 RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg);
7386 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
7387 }
7388
7389#else
7390 MinSpacingToSet = MinSpaceCfg;
7391 MinSpacingToSet &= 0x07; // We only care about bit[2:0]
7392 priv->MinSpaceCfg |= MinSpacingToSet;
7393 RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg);
7394 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);//FIXLZM
7395#endif
7396}
7397#endif
7398
7399//
7400// Description:
7401// Initial HW relted registers.
7402//
7403// Assumption:
7404// 1. This function is only invoked at driver intialization once.
7405// 2. PASSIVE LEVEL.
7406//
7407// 2008.06.10, Added by Roger.
7408//
7409static void rtl8192SU_MacConfigAfterFwDownload(struct net_device *dev)
7410{
7411 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7412 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
7413 //u8 tmpU1b, RxPageCfg, i;
7414 u16 tmpU2b;
7415 u8 tmpU1b;//, i;
7416
7417
7418 RT_TRACE(COMP_INIT, "--->MacConfigAfterFwDownload()\n");
7419
7420 // Enable Tx/Rx
7421 tmpU2b = (BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN|
7422 FW2HW_EN|RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN); //3
7423 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_COMMAND, &tmpU1b );
7424 write_nic_word(dev, CMDR, tmpU2b); //LZM REGISTER COM 090305
7425
7426 // Loopback mode or not
7427 priv->LoopbackMode = RTL8192SU_NO_LOOPBACK; // Set no loopback as default.
7428 if(priv->LoopbackMode == RTL8192SU_NO_LOOPBACK)
7429 tmpU1b = LBK_NORMAL;
7430 else if (priv->LoopbackMode == RTL8192SU_MAC_LOOPBACK )
7431 tmpU1b = LBK_MAC_DLB;
7432 else
7433 RT_TRACE(COMP_INIT, "Serious error: wrong loopback mode setting\n");
7434
7435 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_LBK_MODE, &tmpU1b);
7436 write_nic_byte(dev, LBKMD_SEL, tmpU1b);
7437
7438 // Set RCR
7439 write_nic_dword(dev, RCR, priv->ReceiveConfig);
7440 RT_TRACE(COMP_INIT, "MacConfigAfterFwDownload(): Current RCR settings(%#x)\n", priv->ReceiveConfig);
7441
7442
7443 // Set RQPN
7444 //
7445 // <Roger_Notes> 2008.08.18.
7446 // 6 endpoints:
7447 // (1) Page number on CMDQ is 0x03.
7448 // (2) Page number on BCNQ, HQ and MGTQ is 0.
7449 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
7450 // (4) Page number on PUBQ is 0xdd
7451 //
7452 // 11 endpoints:
7453 // (1) Page number on CMDQ is 0x00.
7454 // (2) Page number on BCNQ is 0x02, HQ and MGTQ are 0x03.
7455 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
7456 // (4) Page number on PUBQ is 0xd8
7457 //
7458 //write_nic_dword(Adapter, 0xa0, 0x07070707); //BKQ, BEQ, VIQ and VOQ
7459 //write_nic_byte(dev, 0xa4, 0x00); // HCCAQ
7460#if 0 //LZM 090219
7461#ifdef USE_SIX_USB_ENDPOINT
7462 //write_nic_dword(Adapter, 0xa5, 0x00000003); //CMDQ, MGTQ, HQ and BCNQ
7463 //write_nic_byte(dev, 0xa9, 0xdd); // PUBQ
7464 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
7465 write_nic_byte(dev, 0xab, tmpU1b|BIT7|BIT6);// reduce to 6 endpoints.
7466#else
7467 write_nic_dword(dev, 0xa5, 0x02030300); //CMDQ, MGTQ, HQ and BCNQ
7468 write_nic_byte(dev, 0xa9, 0xd8); // PUBQ
7469 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
7470 write_nic_byte(dev, 0xab, (tmpU1b&(~BIT6))|BIT7); // Disable reduced endpoint.
7471#endif
7472#endif
7473
7474#ifdef USB_RX_AGGREGATION_SUPPORT
7475 // Size of Tx/Rx packet buffer.
7476 tmpU1b = read_nic_byte(dev, PBP);
7477 RxPageCfg = rtl8192SU_MapRxPageSizeToIdx(priv->ieee80211->pHTInfo.UsbRxPageSize);
7478 write_nic_byte(dev, PBP, tmpU1b|RxPageCfg); // Set page size of Rx packet buffer to 128 bytes.
7479 tmpU1b = read_nic_byte(dev, RXDMA);
7480
7481 write_nic_byte(dev, RXDMA, tmpU1b|RXDMA_AGG_EN); // Rx aggregation enable.
7482 //PlatformIOWrite1Byte(Adapter, RXDMA_AGG_PG_TH, 0x14); // Set page size of RxDMA aggregation threshold, default: 20.
7483 //write_nic_byte(dev, RXDMA_AGG_PG_TH, 0x40); // By Scott's suggestion, 2008.09.30.//92su del
7484 //write_nic_byte(dev, USB_RX_AGG_TIMEOUT, RXDMA_AGG_TIMEOUT_17_4_MS); // Set aggregation time-out to 17ms/4.
7485 rtl8192SU_HalUsbRxAggr8192SUsb(dev, true);
7486#endif
7487
7488 // Fix the RX FIFO issue(USB error), Rivesed by Roger, 2008-06-14
7489 tmpU1b = read_nic_byte_E(dev, 0x5C);
7490 write_nic_byte_E(dev, 0x5C, tmpU1b|BIT7);
7491
7492 //
7493 // Revise USB PHY to solve the issue of Rx payload error, Rivesed by Roger, 2008-04-10
7494 // Suggest by SD1 Alex.
7495 //
7496 // <Roger_Notes> The following operation are ONLY for USB PHY test chip.
7497 // 2008.10.07.
7498 //
7499#if RTL8192SU_USB_PHY_TEST
7500 write_nic_byte(dev, 0x41,0xf4);
7501 write_nic_byte(dev, 0x40,0x00);
7502 write_nic_byte(dev, 0x42,0x00);
7503 write_nic_byte(dev, 0x42,0x01);
7504 write_nic_byte(dev, 0x40,0x0f);
7505 write_nic_byte(dev, 0x42,0x00);
7506 write_nic_byte(dev, 0x42,0x01);
7507#endif
7508
7509#if 0 //LZM 090219
7510 //
7511 // Suggested by SD1 Alex, 2008-06-14.
7512 //
7513 write_nic_byte(dev, TXOP_STALL_CTRL, 0x80);//NAV
7514
7515
7516 //
7517 // Set Data Auto Rate Fallback Retry Count register.
7518 //
7519 write_nic_dword(dev, DARFRC, 0x04010000);
7520 write_nic_dword(dev, DARFRC+4, 0x09070605);
7521 write_nic_dword(dev, RARFRC, 0x04010000);
7522 write_nic_dword(dev, RARFRC+4, 0x09070605);
7523
7524 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
7525 for (i = 0; i < 8; i++)
7526#ifdef RTL8192SU_DISABLE_CCK_RATE
7527 write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0);
7528#else
7529 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
7530#endif
7531
7532 //
7533 // Set driver info, we only accept PHY status now.
7534 //
7535 //write_nic_byte(dev, RXDRVINFO_SZ, 4);
7536
7537 //
7538 // Aggregation length limit. Revised by Roger. 2008.09.22.
7539 //
7540 write_nic_dword(dev, AGGLEN_LMT_L, 0x66666666); // Long GI
7541 write_nic_byte(dev, AGGLEN_LMT_H, 0x06); // Set AMPDU length to 12Kbytes for ShortGI case.
7542
7543 //
7544 // For Min Spacing configuration.
7545 //
7546 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AMPDU_MIN_SPACE, (u8*)(&Adapter->MgntInfo.MinSpaceCfg));
7547 rtl8192SU_SetHwRegAmpduMinSpace(dev,priv->MinSpaceCfg);
7548#endif
7549
7550 // For EFUSE init configuration.
7551 //if (IS_BOOT_FROM_EFUSE(Adapter)) // We may R/W EFUSE in EFUSE mode
7552 if (priv->bBootFromEfuse)
7553 {
7554 u8 tempval;
7555
7556 tempval = read_nic_byte(dev, SYS_ISO_CTRL+1);
7557 tempval &= 0xFE;
7558 write_nic_byte(dev, SYS_ISO_CTRL+1, tempval);
7559
7560 // Enable LDO 2.5V for write action
7561 //tempval = read_nic_byte(Adapter, EFUSE_TEST+3);
7562 //write_nic_byte(Adapter, EFUSE_TEST+3, (tempval | 0x80));
7563
7564 // Change Efuse Clock for write action
7565 //write_nic_byte(Adapter, EFUSE_CLK, 0x03);
7566
7567 // Change Program timing
7568 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);
7569 //printk("!!!!!!!!!!!!!!!!!!!!!%s: write 0x33 with 0x72\n",__FUNCTION__);
7570 RT_TRACE(COMP_INIT, "EFUSE CONFIG OK\n");
7571 }
7572
7573
7574 RT_TRACE(COMP_INIT, "<---MacConfigAfterFwDownload()\n");
7575}
7576
7577void rtl8192SU_HwConfigureRTL8192SUsb(struct net_device *dev)
7578{
7579
7580 struct r8192_priv *priv = ieee80211_priv(dev);
7581 u8 regBwOpMode = 0;
7582 u32 regRATR = 0, regRRSR = 0;
7583 u8 regTmp = 0;
7584 u32 i = 0;
7585
7586 //1 This part need to modified according to the rate set we filtered!!
7587 //
7588 // Set RRSR, RATR, and BW_OPMODE registers
7589 //
7590 switch(priv->ieee80211->mode)
7591 {
7592 case WIRELESS_MODE_B:
7593 regBwOpMode = BW_OPMODE_20MHZ;
7594 regRATR = RATE_ALL_CCK;
7595 regRRSR = RATE_ALL_CCK;
7596 break;
7597 case WIRELESS_MODE_A:
7598 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
7599 regRATR = RATE_ALL_OFDM_AG;
7600 regRRSR = RATE_ALL_OFDM_AG;
7601 break;
7602 case WIRELESS_MODE_G:
7603 regBwOpMode = BW_OPMODE_20MHZ;
7604 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7605 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7606 break;
7607 case WIRELESS_MODE_AUTO:
7608 if (priv->bInHctTest)
7609 {
7610 regBwOpMode = BW_OPMODE_20MHZ;
7611 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7612 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7613 }
7614 else
7615 {
7616 regBwOpMode = BW_OPMODE_20MHZ;
7617 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7618 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7619 }
7620 break;
7621 case WIRELESS_MODE_N_24G:
7622 // It support CCK rate by default.
7623 // CCK rate will be filtered out only when associated AP does not support it.
7624 regBwOpMode = BW_OPMODE_20MHZ;
7625 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7626 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7627 break;
7628 case WIRELESS_MODE_N_5G:
7629 regBwOpMode = BW_OPMODE_5G;
7630 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7631 regRRSR = RATE_ALL_OFDM_AG;
7632 break;
7633 }
7634
7635 //
7636 // <Roger_Notes> We disable CCK response rate until FIB CCK rate IC's back.
7637 // 2008.09.23.
7638 //
7639 regTmp = read_nic_byte(dev, INIRTSMCS_SEL);
7640#ifdef RTL8192SU_DISABLE_CCK_RATE
7641 regRRSR = ((regRRSR & 0x000ffff0)<<8) | regTmp;
7642#else
7643 regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp;
7644#endif
7645
7646 //
7647 // Update SIFS timing.
7648 //
7649 //priv->SifsTime = 0x0e0e0a0a;
7650 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SIFS, (pu1Byte)&pHalData->SifsTime);
7651 { u8 val[4] = {0x0e, 0x0e, 0x0a, 0x0a};
7652 // SIFS for CCK Data ACK
7653 write_nic_byte(dev, SIFS_CCK, val[0]);
7654 // SIFS for CCK consecutive tx like CTS data!
7655 write_nic_byte(dev, SIFS_CCK+1, val[1]);
7656
7657 // SIFS for OFDM Data ACK
7658 write_nic_byte(dev, SIFS_OFDM, val[2]);
7659 // SIFS for OFDM consecutive tx like CTS data!
7660 write_nic_byte(dev, SIFS_OFDM+1, val[3]);
7661 }
7662
7663 write_nic_dword(dev, INIRTSMCS_SEL, regRRSR);
7664 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
7665
7666 //
7667 // Suggested by SD1 Alex, 2008-06-14.
7668 //
7669 //PlatformEFIOWrite1Byte(Adapter, TXOP_STALL_CTRL, 0x80);//NAV to protect all TXOP.
7670
7671 //
7672 // Set Data Auto Rate Fallback Retry Count register.
7673 //
7674 write_nic_dword(dev, DARFRC, 0x02010000);
7675 write_nic_dword(dev, DARFRC+4, 0x06050403);
7676 write_nic_dword(dev, RARFRC, 0x02010000);
7677 write_nic_dword(dev, RARFRC+4, 0x06050403);
7678
7679 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
7680 for (i = 0; i < 8; i++)
7681#ifdef RTL8192SU_DISABLE_CCK_RATE
7682 write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0);
7683#else
7684 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
7685#endif
7686
7687 //
7688 // Aggregation length limit. Revised by Roger. 2008.09.22.
7689 //
7690 write_nic_byte(dev, AGGLEN_LMT_H, 0x0f); // Set AMPDU length to 12Kbytes for ShortGI case.
7691 write_nic_dword(dev, AGGLEN_LMT_L, 0xddd77442); // Long GI
7692 write_nic_dword(dev, AGGLEN_LMT_L+4, 0xfffdd772);
7693
7694 // Set NAV protection length
7695 write_nic_word(dev, NAV_PROT_LEN, 0x0080);
7696
7697 // Set TXOP stall control for several queue/HI/BCN/MGT/
7698 write_nic_byte(dev, TXOP_STALL_CTRL, 0x00); // NAV Protect next packet.
7699
7700 // Set MSDU lifetime.
7701 write_nic_byte(dev, MLT, 0x8f);
7702
7703 // Set CCK/OFDM SIFS
7704 write_nic_word(dev, SIFS_CCK, 0x0a0a); // CCK SIFS shall always be 10us.
7705 write_nic_word(dev, SIFS_OFDM, 0x0e0e);
7706
7707 write_nic_byte(dev, ACK_TIMEOUT, 0x40);
7708
7709 // CF-END Threshold
7710 write_nic_byte(dev, CFEND_TH, 0xFF);
7711
7712 //
7713 // For Min Spacing configuration.
7714 //
7715 switch(priv->rf_type)
7716 {
7717 case RF_1T2R:
7718 case RF_1T1R:
7719 RT_TRACE(COMP_INIT, "Initializeadapter: RF_Type%s\n", (priv->rf_type==RF_1T1R? "(1T1R)":"(1T2R)"));
7720 priv->MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
7721 break;
7722 case RF_2T2R:
7723 case RF_2T2R_GREEN:
7724 RT_TRACE(COMP_INIT, "Initializeadapter:RF_Type(2T2R)\n");
7725 priv->MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
7726 break;
7727 }
7728 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
7729
7730 //LZM 090219
7731 //
7732 // For Min Spacing configuration.
7733 //
7734 //priv->MinSpaceCfg = 0x00;
7735 //rtl8192SU_SetHwRegAmpduMinSpace(dev, priv->MinSpaceCfg);
7736}
7737
7738#endif
7739
7740#ifdef RTL8192SU
7741// Description: Initial HW relted registers.
7742//
7743// Assumption: This function is only invoked at driver intialization once.
7744//
7745// 2008.06.10, Added by Roger.
7746bool rtl8192SU_adapter_start(struct net_device *dev)
7747{
7748 struct r8192_priv *priv = ieee80211_priv(dev);
7749 //u32 dwRegRead = 0;
7750 //bool init_status = true;
7751 //u32 ulRegRead;
7752 bool rtStatus = true;
7753 //u8 PipeIndex;
7754 //u8 eRFPath, tmpU1b;
7755 u8 fw_download_times = 1;
7756
7757
7758 RT_TRACE(COMP_INIT, "--->InitializeAdapter8192SUsb()\n");
7759
7760 //pHalData->bGPIOChangeRF = FALSE;
7761
7762
7763 //
7764 // <Roger_Notes> 2008.06.15.
7765 //
7766 // Initialization Steps on RTL8192SU:
7767 // a. MAC initialization prior to sending down firmware code.
7768 // b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
7769 // c. MAC configuration after firmware has been download successfully.
7770 // d. Initialize BB related configurations.
7771 // e. Initialize RF related configurations.
7772 // f. Start to BulkIn transfer.
7773 //
7774
7775 //
7776 //a. MAC initialization prior to send down firmware code.
7777 //
7778start:
7779 rtl8192SU_MacConfigBeforeFwDownloadASIC(dev);
7780
7781 //
7782 //b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
7783 //
7784 rtStatus = FirmwareDownload92S(dev);
7785 if(rtStatus != true)
7786 {
7787 if(fw_download_times == 1){
7788 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed once, Download again!!\n");
7789 fw_download_times = fw_download_times + 1;
7790 goto start;
7791 }else{
7792 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed twice, end!!\n");
7793 goto end;
7794 }
7795 }
7796 //
7797 //c. MAC configuration after firmware has been download successfully.
7798 //
7799 rtl8192SU_MacConfigAfterFwDownload(dev);
7800
7801#if (RTL8192S_DISABLE_FW_DM == 1)
7802 write_nic_dword(dev, WFM5, FW_DM_DISABLE);
7803#endif
7804 //priv->bLbusEnable = TRUE;
7805 //if(priv->RegRfOff == TRUE)
7806 // priv->eRFPowerState = eRfOff;
7807
7808 // Save target channel
7809 // <Roger_Notes> Current Channel will be updated again later.
7810 //priv->CurrentChannel = Channel;
7811 rtStatus = PHY_MACConfig8192S(dev);//===>ok
7812 if(rtStatus != true)
7813 {
7814 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure MAC!!\n");
7815 goto end;
7816 }
7817 if (1){
7818 int i;
7819 for (i=0; i<4; i++)
7820 write_nic_dword(dev,WDCAPARA_ADD[i], 0x5e4322);
7821 write_nic_byte(dev,AcmHwCtrl, 0x01);
7822 }
7823
7824
7825 //
7826 //d. Initialize BB related configurations.
7827 //
7828
7829 rtStatus = PHY_BBConfig8192S(dev);//===>ok
7830 if(rtStatus != true)
7831 {
7832 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure BB!!\n");
7833 goto end;
7834 }
7835
7836 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);//===>ok
7837
7838 //
7839 // e. Initialize RF related configurations.
7840 //
7841 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
7842 priv->Rf_Mode = RF_OP_By_SW_3wire;
7843
7844 // For RF test only from Scott's suggestion
7845 //write_nic_byte(dev, 0x27, 0xDB);
7846 //write_nic_byte(dev, 0x1B, 0x07);
7847
7848
7849 write_nic_byte(dev, AFE_XTAL_CTRL+1, 0xDB);
7850
7851 // <Roger_Notes> The following IOs are configured for each RF modules.
7852 // Enable RF module and reset RF and SDM module. 2008.11.17.
7853 if(priv->card_8192_version == VERSION_8192S_ACUT)
7854 write_nic_byte(dev, SPS1_CTRL+3, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB)); // Fix A-Cut bug.
7855 else
7856 write_nic_byte(dev, RF_CTRL, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB));
7857
7858 rtStatus = PHY_RFConfig8192S(dev);//===>ok
7859 if(rtStatus != true)
7860 {
7861 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure RF!!\n");
7862 goto end;
7863 }
7864
7865
7866 // Set CCK and OFDM Block "ON"
7867 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
7868 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
7869
7870 //
7871 // Turn off Radio B while RF type is 1T1R by SD3 Wilsion's request.
7872 // Revised by Roger, 2008.12.18.
7873 //
7874 if(priv->rf_type == RF_1T1R)
7875 {
7876 // This is needed for PHY_REG after 20081219
7877 rtl8192_setBBreg(dev, rFPGA0_RFMOD, 0xff000000, 0x03);
7878 // This is needed for PHY_REG before 20081219
7879 //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x11);
7880 }
7881
7882#if (RTL8192SU_DISABLE_IQK==0)
7883 // For 1T2R IQK only currently.
7884 if (priv->card_8192_version == VERSION_8192S_BCUT)
7885 {
7886 PHY_IQCalibrateBcut(dev);
7887 }
7888 else if (priv->card_8192_version == VERSION_8192S_ACUT)
7889 {
7890 PHY_IQCalibrate(dev);
7891 }
7892#endif
7893
7894 //LZM 090219
7895 // Set CCK and OFDM Block "ON"
7896 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
7897 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
7898
7899
7900 //3//Get hardware version, do it in read eeprom?
7901 //GetHardwareVersion819xUsb(Adapter);
7902
7903 //3//
7904 //3 //Set Hardware
7905 //3//
7906 rtl8192SU_HwConfigureRTL8192SUsb(dev);//==>ok
7907
7908 //
7909 // <Roger_Notes> We set MAC address here if autoload was failed before,
7910 // otherwise IDR0 will NOT contain any value.
7911 //
7912 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
7913 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
7914 if(!priv->bInHctTest)
7915 {
7916 if(priv->ResetProgress == RESET_TYPE_NORESET)
7917 {
7918 //RT_TRACE(COMP_MLME, DBG_LOUD, ("Initializeadapter8192SUsb():RegWirelessMode(%#x) \n", Adapter->RegWirelessMode));
7919 //Adapter->HalFunc.SetWirelessModeHandler(Adapter, Adapter->RegWirelessMode);
7920 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);//===>ok
7921 }
7922 }
7923 else
7924 {
7925 priv->ieee80211->mode = WIRELESS_MODE_G;
7926 rtl8192_SetWirelessMode(dev, WIRELESS_MODE_G);
7927 }
7928
7929 //Security related.
7930 //-----------------------------------------------------------------------------
7931 // Set up security related. 070106, by rcnjko:
7932 // 1. Clear all H/W keys.
7933 // 2. Enable H/W encryption/decryption.
7934 //-----------------------------------------------------------------------------
7935 //CamResetAllEntry(Adapter);
7936 //Adapter->HalFunc.EnableHWSecCfgHandler(Adapter);
7937
7938 //SecClearAllKeys(Adapter);
7939 CamResetAllEntry(dev);
7940 //SecInit(Adapter);
7941 {
7942 u8 SECR_value = 0x0;
7943 SECR_value |= SCR_TxEncEnable;
7944 SECR_value |= SCR_RxDecEnable;
7945 SECR_value |= SCR_NoSKMC;
7946 write_nic_byte(dev, SECR, SECR_value);
7947 }
7948
7949#if 0
7950
7951 if(pHalData->VersionID == VERSION_8192SU_A)
7952 {
7953 // cosa add for tx power level initialization.
7954 GetTxPowerOriginalOffset(Adapter);
7955 SetTxPowerLevel819xUsb(Adapter, Channel);
7956 }
7957#endif
7958
7959
7960#ifdef TO_DO_LIST
7961
7962 //PHY_UpdateInitialGain(dev);
7963
7964 if(priv->RegRfOff == true)
7965 { // User disable RF via registry.
7966 u8 eRFPath = 0;
7967
7968 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RegRfOff ----------\n");
7969 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW);
7970 // Those action will be discard in MgntActSet_RF_State because off the same state
7971 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
7972 rtl8192_setBBreg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
7973 }
7974 else if(priv->RfOffReason > RF_CHANGE_BY_PS)
7975 { // H/W or S/W RF OFF before sleep.
7976 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RfOffReason(%d) ----------\n", priv->RfOffReason);
7977 MgntActSet_RF_State(dev, eRfOff, priv->RfOffReason);
7978 }
7979 else
7980 {
7981 priv->eRFPowerState = eRfOn;
7982 priv->RfOffReason = 0;
7983 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): RF is on ----------\n");
7984 }
7985
7986#endif
7987
7988
7989//
7990// f. Start to BulkIn transfer.
7991//
7992#ifdef TO_DO_LIST
7993
7994#ifndef UNDER_VISTA
7995 {
7996 u8 i;
7997 PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
7998
7999 for(PipeIndex=0; PipeIndex < MAX_RX_QUEUE; PipeIndex++)
8000 {
8001 if (PipeIndex == 0)
8002 {
8003 for(i=0; i<32; i++)
8004 HalUsbInMpdu(Adapter, PipeIndex);
8005 }
8006 else
8007 {
8008 //HalUsbInMpdu(Adapter, PipeIndex);
8009 //HalUsbInMpdu(Adapter, PipeIndex);
8010 //HalUsbInMpdu(Adapter, PipeIndex);
8011 }
8012 }
8013 PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
8014 }
8015#else
8016 // Joseph add to 819X code base for Vista USB platform.
8017 // This part may need to be add to Hal819xU code base. too.
8018 PlatformUsbEnableInPipes(Adapter);
8019#endif
8020
8021 RT_TRACE(COMP_INIT, "HighestOperaRate = %x\n", Adapter->MgntInfo.HighestOperaRate);
8022
8023 PlatformStartWorkItem( &(pHalData->RtUsbCheckForHangWorkItem) );
8024
8025 //
8026 // <Roger_EXP> The following configurations are for ASIC verification temporally.
8027 // 2008.07.10.
8028 //
8029
8030#endif
8031
8032 //
8033 // Read EEPROM TX power index and PHY_REG_PG.txt to capture correct
8034 // TX power index for different rate set.
8035 //
8036 //if(priv->card_8192_version >= VERSION_8192S_ACUT)
8037 {
8038 // Get original hw reg values
8039 PHY_GetHWRegOriginalValue(dev);
8040
8041 // Write correct tx power index//FIXLZM
8042 PHY_SetTxPowerLevel8192S(dev, priv->chan);
8043 }
8044
8045 {
8046 u8 tmpU1b = 0;
8047 // EEPROM R/W workaround
8048 tmpU1b = read_nic_byte(dev, MAC_PINMUX_CFG);
8049 write_nic_byte(dev, MAC_PINMUX_CFG, tmpU1b&(~GPIOMUX_EN));
8050 }
8051
8052//
8053//<Roger_Notes> 2008.08.19.
8054// We return status here for temporal FPGA verification, 2008.08.19.
8055
8056#ifdef RTL8192SU_FW_IQK
8057 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
8058 ChkFwCmdIoDone(dev);
8059#endif
8060
8061 //
8062 // <Roger_Notes> We enable high power mechanism after NIC initialized.
8063 // 2008.11.27.
8064 //
8065 write_nic_dword(dev, WFM5, FW_RA_RESET);
8066 ChkFwCmdIoDone(dev);
8067 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
8068 ChkFwCmdIoDone(dev);
8069 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
8070 ChkFwCmdIoDone(dev);
8071 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
8072
8073// <Roger_Notes> We return status here for temporal FPGA verification. 2008.05.12.
8074//
8075#if RTL8192SU_FPGA_UNSPECIFIED_NETWORK
8076 //
8077 // To send specific number of packets to verify MAC Lookback mode.
8078 //
8079 //SendRandomTxPkt(Adapter, 0); // Burst mode for verification.
8080 //rtStatus = RT_STATUS_FAILURE;
8081 rtStatus = true;
8082 goto end;
8083#endif
8084
8085// The following IO was for FPGA verification purpose. Added by Roger, 2008.09.11.
8086#if 0
8087 // 2008/08/19 MH From SD1 Jong, we must write some register for true PHY/MAC FPGA.
8088 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x30);
8089 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x30);
8090
8091 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
8092
8093 //write_nic_dword(Adapter, RCR, 0x817FF02F);
8094
8095 write_nic_dword(Adapter, rTxAGC_Mcs15_Mcs12, 0x06060606);
8096#endif
8097end:
8098return rtStatus;
8099}
8100
8101#else
8102
8103//InitializeAdapter and PhyCfg
8104bool rtl8192_adapter_start(struct net_device *dev)
8105{
8106 struct r8192_priv *priv = ieee80211_priv(dev);
8107 u32 dwRegRead = 0;
8108 bool init_status = true;
8109 RT_TRACE(COMP_INIT, "====>%s()\n", __FUNCTION__);
8110 priv->Rf_Mode = RF_OP_By_SW_3wire;
8111 //for ASIC power on sequence
8112 write_nic_byte_E(dev, 0x5f, 0x80);
8113 mdelay(50);
8114 write_nic_byte_E(dev, 0x5f, 0xf0);
8115 write_nic_byte_E(dev, 0x5d, 0x00);
8116 write_nic_byte_E(dev, 0x5e, 0x80);
8117 write_nic_byte(dev, 0x17, 0x37);
8118 mdelay(10);
8119//#ifdef TO_DO_LIST
8120 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
8121 //config CPUReset Register
8122 //Firmware Reset or not?
8123 dwRegRead = read_nic_dword(dev, CPU_GEN);
8124 if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
8125 dwRegRead |= CPU_GEN_SYSTEM_RESET; //do nothing here?
8126 else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
8127 dwRegRead |= CPU_GEN_FIRMWARE_RESET;
8128 else
8129 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
8130
8131 write_nic_dword(dev, CPU_GEN, dwRegRead);
8132 //mdelay(30);
8133 //config BB.
8134 rtl8192_BBConfig(dev);
8135
8136#if 1
8137 //Loopback mode or not
8138 priv->LoopbackMode = RTL819xU_NO_LOOPBACK;
8139// priv->LoopbackMode = RTL819xU_MAC_LOOPBACK;
8140
8141 dwRegRead = read_nic_dword(dev, CPU_GEN);
8142 if (priv->LoopbackMode == RTL819xU_NO_LOOPBACK)
8143 dwRegRead = ((dwRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
8144 else if (priv->LoopbackMode == RTL819xU_MAC_LOOPBACK)
8145 dwRegRead |= CPU_CCK_LOOPBACK;
8146 else
8147 RT_TRACE(COMP_ERR, "Serious error in %s(): wrong loopback mode setting(%d)\n", __FUNCTION__, priv->LoopbackMode);
8148
8149 write_nic_dword(dev, CPU_GEN, dwRegRead);
8150
8151 //after reset cpu, we need wait for a seconds to write in register.
8152 udelay(500);
8153
8154 //xiong add for new bitfile:usb suspend reset pin set to 1. //do we need?
8155 write_nic_byte_E(dev, 0x5f, (read_nic_byte_E(dev, 0x5f)|0x20));
8156
8157 //Set Hardware
8158 rtl8192_hwconfig(dev);
8159
8160 //turn on Tx/Rx
8161 write_nic_byte(dev, CMDR, CR_RE|CR_TE);
8162
8163 //set IDR0 here
8164 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
8165 write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
8166
8167 //set RCR
8168 write_nic_dword(dev, RCR, priv->ReceiveConfig);
8169
8170 //Initialize Number of Reserved Pages in Firmware Queue
8171 write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |\
8172 NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT | \
8173 NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT | \
8174 NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
8175 write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT |\
8176 NUM_OF_PAGE_IN_FW_QUEUE_CMD << RSVD_FW_QUEUE_PAGE_CMD_SHIFT);
8177 write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW| \
8178 NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT
8179// | NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT
8180 );
8181 write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
8182
8183 //Set AckTimeout
8184 // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
8185 write_nic_byte(dev, ACK_TIMEOUT, 0x30);
8186
8187// RT_TRACE(COMP_INIT, "%s():priv->ResetProgress is %d\n", __FUNCTION__,priv->ResetProgress);
8188 if(priv->ResetProgress == RESET_TYPE_NORESET)
8189 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);
8190 if(priv->ResetProgress == RESET_TYPE_NORESET){
8191 CamResetAllEntry(dev);
8192 {
8193 u8 SECR_value = 0x0;
8194 SECR_value |= SCR_TxEncEnable;
8195 SECR_value |= SCR_RxDecEnable;
8196 SECR_value |= SCR_NoSKMC;
8197 write_nic_byte(dev, SECR, SECR_value);
8198 }
8199 }
8200
8201 //Beacon related
8202 write_nic_word(dev, ATIMWND, 2);
8203 write_nic_word(dev, BCN_INTERVAL, 100);
8204
8205 {
8206#define DEFAULT_EDCA 0x005e4332
8207 int i;
8208 for (i=0; i<QOS_QUEUE_NUM; i++)
8209 write_nic_dword(dev, WDCAPARA_ADD[i], DEFAULT_EDCA);
8210 }
8211#ifdef USB_RX_AGGREGATION_SUPPORT
8212 //3 For usb rx firmware aggregation control
8213 if(priv->ResetProgress == RESET_TYPE_NORESET)
8214 {
8215 u32 ulValue;
8216 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
8217 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
8218 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
8219 /*
8220 * If usb rx firmware aggregation is enabled,
8221 * when anyone of three threshold conditions above is reached,
8222 * firmware will send aggregated packet to driver.
8223 */
8224 write_nic_dword(dev, 0x1a8, ulValue);
8225 priv->bCurrentRxAggrEnable = true;
8226 }
8227#endif
8228
8229 rtl8192_phy_configmac(dev);
8230
8231 if (priv->card_8192_version == (u8) VERSION_819xU_A)
8232 {
8233 rtl8192_phy_getTxPower(dev);
8234 rtl8192_phy_setTxPower(dev, priv->chan);
8235 }
8236
8237
8238 priv->usb_error = false;
8239 //Firmware download
8240 init_status = init_firmware(dev);
8241 if(!init_status)
8242 {
8243 RT_TRACE(COMP_ERR,"ERR!!! %s(): Firmware download is failed\n", __FUNCTION__);
8244 return init_status;
8245 }
8246 RT_TRACE(COMP_INIT, "%s():after firmware download\n", __FUNCTION__);
8247 //
8248#ifdef TO_DO_LIST
8249if(Adapter->ResetProgress == RESET_TYPE_NORESET)
8250 {
8251 if(pMgntInfo->RegRfOff == TRUE)
8252 { // User disable RF via registry.
8253 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RegRfOff ----------\n"));
8254 MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
8255 // Those action will be discard in MgntActSet_RF_State because off the same state
8256 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
8257 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
8258 }
8259 else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS)
8260 { // H/W or S/W RF OFF before sleep.
8261 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RfOffReason(%d) ----------\n", pMgntInfo->RfOffReason));
8262 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
8263 }
8264 else
8265 {
8266 pHalData->eRFPowerState = eRfOn;
8267 pMgntInfo->RfOffReason = 0;
8268 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): RF is on ----------\n"));
8269 }
8270 }
8271 else
8272 {
8273 if(pHalData->eRFPowerState == eRfOff)
8274 {
8275 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
8276 // Those action will be discard in MgntActSet_RF_State because off the same state
8277 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
8278 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
8279 }
8280 }
8281#endif
8282 //config RF.
8283 if(priv->ResetProgress == RESET_TYPE_NORESET){
8284 rtl8192_phy_RFConfig(dev);
8285 RT_TRACE(COMP_INIT, "%s():after phy RF config\n", __FUNCTION__);
8286 }
8287
8288
8289 if(priv->ieee80211->FwRWRF)
8290 // We can force firmware to do RF-R/W
8291 priv->Rf_Mode = RF_OP_By_FW;
8292 else
8293 priv->Rf_Mode = RF_OP_By_SW_3wire;
8294
8295
8296 rtl8192_phy_updateInitGain(dev);
8297 /*--set CCK and OFDM Block "ON"--*/
8298 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
8299 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
8300
8301 if(priv->ResetProgress == RESET_TYPE_NORESET)
8302 {
8303 //if D or C cut
8304 u8 tmpvalue = read_nic_byte(dev, 0x301);
8305 if(tmpvalue ==0x03)
8306 {
8307 priv->bDcut = TRUE;
8308 RT_TRACE(COMP_POWER_TRACKING, "D-cut\n");
8309 }
8310 else
8311 {
8312 priv->bDcut = FALSE;
8313 RT_TRACE(COMP_POWER_TRACKING, "C-cut\n");
8314 }
8315 dm_initialize_txpower_tracking(dev);
8316
8317 if(priv->bDcut == TRUE)
8318 {
8319 u32 i, TempCCk;
8320 u32 tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);
8321 // u32 tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);
8322 for(i = 0; i<TxBBGainTableLength; i++)
8323 {
8324 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
8325 {
8326 priv->rfa_txpowertrackingindex= (u8)i;
8327 priv->rfa_txpowertrackingindex_real= (u8)i;
8328 priv->rfa_txpowertracking_default= priv->rfa_txpowertrackingindex;
8329 break;
8330 }
8331 }
8332
8333 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
8334
8335 for(i=0 ; i<CCKTxBBGainTableLength ; i++)
8336 {
8337
8338 if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
8339 {
8340 priv->cck_present_attentuation_20Mdefault=(u8) i;
8341 break;
8342 }
8343 }
8344 priv->cck_present_attentuation_40Mdefault= 0;
8345 priv->cck_present_attentuation_difference= 0;
8346 priv->cck_present_attentuation = priv->cck_present_attentuation_20Mdefault;
8347
8348 // pMgntInfo->bTXPowerTracking = FALSE;//TEMPLY DISABLE
8349 }
8350 }
8351 write_nic_byte(dev, 0x87, 0x0);
8352
8353
8354#endif
8355 return init_status;
8356}
8357
8358#endif
8359/* this configures registers for beacon tx and enables it via
8360 * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might
8361 * be used to stop beacon transmission
8362 */
8363#if 0
8364void rtl8192_start_tx_beacon(struct net_device *dev)
8365{
8366 int i;
8367 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8368 u16 word;
8369 DMESG("Enabling beacon TX");
8370 //write_nic_byte(dev, TX_CONF,0xe6);// TX_CONF
8371 //rtl8192_init_beacon(dev);
8372 //set_nic_txring(dev);
8373// rtl8192_prepare_beacon(dev);
8374 rtl8192_irq_disable(dev);
8375// rtl8192_beacon_tx_enable(dev);
8376 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
8377 //write_nic_byte(dev,0x9d,0x20); //DMA Poll
8378 //write_nic_word(dev,0x7a,0);
8379 //write_nic_word(dev,0x7a,0x8000);
8380
8381
8382 word = read_nic_word(dev, BcnItv);
8383 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
8384 write_nic_word(dev, BcnItv, word);
8385
8386 write_nic_word(dev, AtimWnd,
8387 read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd);
8388
8389 word = read_nic_word(dev, BCN_INTR_ITV);
8390 word &= ~BCN_INTR_ITV_MASK;
8391
8392 //word |= priv->ieee80211->beacon_interval *
8393 // ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
8394 // FIXME:FIXME check if correct ^^ worked with 0x3e8;
8395
8396 write_nic_word(dev, BCN_INTR_ITV, word);
8397
8398 //write_nic_word(dev,0x2e,0xe002);
8399 //write_nic_dword(dev,0x30,0xb8c7832e);
8400 for(i=0; i<ETH_ALEN; i++)
8401 write_nic_byte(dev, BSSID+i, priv->ieee80211->beacon_cell_ssid[i]);
8402
8403// rtl8192_update_msr(dev);
8404
8405
8406 //write_nic_byte(dev,CONFIG4,3); /* !!!!!!!!!! */
8407
8408 rtl8192_set_mode(dev, EPROM_CMD_NORMAL);
8409
8410 rtl8192_irq_enable(dev);
8411
8412 /* VV !!!!!!!!!! VV*/
8413 /*
8414 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
8415 write_nic_byte(dev,0x9d,0x00);
8416 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
8417*/
8418}
8419#endif
8420/***************************************************************************
8421 -------------------------------NET STUFF---------------------------
8422***************************************************************************/
8423
8424static struct net_device_stats *rtl8192_stats(struct net_device *dev)
8425{
8426 struct r8192_priv *priv = ieee80211_priv(dev);
8427
8428 return &priv->ieee80211->stats;
8429}
8430
8431bool
8432HalTxCheckStuck819xUsb(
8433 struct net_device *dev
8434 )
8435{
8436 struct r8192_priv *priv = ieee80211_priv(dev);
8437 u16 RegTxCounter = read_nic_word(dev, 0x128);
8438 bool bStuck = FALSE;
8439 RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
8440 if(priv->TxCounter==RegTxCounter)
8441 bStuck = TRUE;
8442
8443 priv->TxCounter = RegTxCounter;
8444
8445 return bStuck;
8446}
8447
8448/*
8449* <Assumption: RT_TX_SPINLOCK is acquired.>
8450* First added: 2006.11.19 by emily
8451*/
8452RESET_TYPE
8453TxCheckStuck(struct net_device *dev)
8454{
8455 struct r8192_priv *priv = ieee80211_priv(dev);
8456 u8 QueueID;
8457// PRT_TCB pTcb;
8458// u8 ResetThreshold;
8459 bool bCheckFwTxCnt = false;
8460 //unsigned long flags;
8461
8462 //
8463 // Decide Stuch threshold according to current power save mode
8464 //
8465
8466// RT_TRACE(COMP_RESET, " ==> TxCheckStuck()\n");
8467// PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
8468// spin_lock_irqsave(&priv->ieee80211->lock,flags);
8469 for (QueueID = 0; QueueID<=BEACON_QUEUE;QueueID ++)
8470 {
8471 if(QueueID == TXCMD_QUEUE)
8472 continue;
8473#if 1
8474#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
8475 if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_drv_aggQ[QueueID]) == 0))
8476#else
8477 if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0))
8478#endif
8479 continue;
8480#endif
8481
8482 bCheckFwTxCnt = true;
8483 }
8484// PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
8485// spin_unlock_irqrestore(&priv->ieee80211->lock,flags);
8486// RT_TRACE(COMP_RESET,"bCheckFwTxCnt is %d\n",bCheckFwTxCnt);
8487#if 1
8488 if(bCheckFwTxCnt)
8489 {
8490 if(HalTxCheckStuck819xUsb(dev))
8491 {
8492 RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no Tx condition! \n");
8493 return RESET_TYPE_SILENT;
8494 }
8495 }
8496#endif
8497 return RESET_TYPE_NORESET;
8498}
8499
8500bool
8501HalRxCheckStuck819xUsb(struct net_device *dev)
8502{
8503 u16 RegRxCounter = read_nic_word(dev, 0x130);
8504 struct r8192_priv *priv = ieee80211_priv(dev);
8505 bool bStuck = FALSE;
8506//#ifdef RTL8192SU
8507
8508//#else
8509 static u8 rx_chk_cnt = 0;
8510 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
8511 // If rssi is small, we should check rx for long time because of bad rx.
8512 // or maybe it will continuous silent reset every 2 seconds.
8513 rx_chk_cnt++;
8514 if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5))
8515 {
8516 rx_chk_cnt = 0; //high rssi, check rx stuck right now.
8517 }
8518 else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) &&
8519 ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) ||
8520 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) )
8521 {
8522 if(rx_chk_cnt < 2)
8523 {
8524 return bStuck;
8525 }
8526 else
8527 {
8528 rx_chk_cnt = 0;
8529 }
8530 }
8531 else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) ||
8532 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) &&
8533 priv->undecorated_smoothed_pwdb >= VeryLowRSSI)
8534 {
8535 if(rx_chk_cnt < 4)
8536 {
8537 //DbgPrint("RSSI < %d && RSSI >= %d, no check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
8538 return bStuck;
8539 }
8540 else
8541 {
8542 rx_chk_cnt = 0;
8543 //DbgPrint("RSSI < %d && RSSI >= %d, check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
8544 }
8545 }
8546 else
8547 {
8548 if(rx_chk_cnt < 8)
8549 {
8550 //DbgPrint("RSSI <= %d, no check this time \n", VeryLowRSSI);
8551 return bStuck;
8552 }
8553 else
8554 {
8555 rx_chk_cnt = 0;
8556 //DbgPrint("RSSI <= %d, check this time \n", VeryLowRSSI);
8557 }
8558 }
8559//#endif
8560
8561 if(priv->RxCounter==RegRxCounter)
8562 bStuck = TRUE;
8563
8564 priv->RxCounter = RegRxCounter;
8565
8566 return bStuck;
8567}
8568
8569RESET_TYPE
8570RxCheckStuck(struct net_device *dev)
8571{
8572 struct r8192_priv *priv = ieee80211_priv(dev);
8573 //int i;
8574 bool bRxCheck = FALSE;
8575
8576// RT_TRACE(COMP_RESET," ==> RxCheckStuck()\n");
8577 //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
8578
8579 if(priv->IrpPendingCount > 1)
8580 bRxCheck = TRUE;
8581 //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
8582
8583// RT_TRACE(COMP_RESET,"bRxCheck is %d \n",bRxCheck);
8584 if(bRxCheck)
8585 {
8586 if(HalRxCheckStuck819xUsb(dev))
8587 {
8588 RT_TRACE(COMP_RESET, "RxStuck Condition\n");
8589 return RESET_TYPE_SILENT;
8590 }
8591 }
8592 return RESET_TYPE_NORESET;
8593}
8594
8595
8596/**
8597* This function is called by Checkforhang to check whether we should ask OS to reset driver
8598*
8599* \param pAdapter The adapter context for this miniport
8600*
8601* Note:NIC with USB interface sholud not call this function because we cannot scan descriptor
8602* to judge whether there is tx stuck.
8603* Note: This function may be required to be rewrite for Vista OS.
8604* <<<Assumption: Tx spinlock has been acquired >>>
8605*
8606* 8185 and 8185b does not implement this function. This is added by Emily at 2006.11.24
8607*/
8608RESET_TYPE
8609rtl819x_ifcheck_resetornot(struct net_device *dev)
8610{
8611 struct r8192_priv *priv = ieee80211_priv(dev);
8612 RESET_TYPE TxResetType = RESET_TYPE_NORESET;
8613 RESET_TYPE RxResetType = RESET_TYPE_NORESET;
8614 RT_RF_POWER_STATE rfState;
8615
8616#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
8617 return RESET_TYPE_NORESET;
8618#endif
8619
8620 rfState = priv->ieee80211->eRFPowerState;
8621
8622 TxResetType = TxCheckStuck(dev);
8623#if 1
8624 if( rfState != eRfOff ||
8625 /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/
8626 (priv->ieee80211->iw_mode != IW_MODE_ADHOC))
8627 {
8628 // If driver is in the status of firmware download failure , driver skips RF initialization and RF is
8629 // in turned off state. Driver should check whether Rx stuck and do silent reset. And
8630 // if driver is in firmware download failure status, driver should initialize RF in the following
8631 // silent reset procedure Emily, 2008.01.21
8632
8633 // Driver should not check RX stuck in IBSS mode because it is required to
8634 // set Check BSSID in order to send beacon, however, if check BSSID is
8635 // set, STA cannot hear any packet a all. Emily, 2008.04.12
8636 RxResetType = RxCheckStuck(dev);
8637 }
8638#endif
8639 if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL)
8640 return RESET_TYPE_NORMAL;
8641 else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT){
8642 RT_TRACE(COMP_RESET,"%s():silent reset\n",__FUNCTION__);
8643 return RESET_TYPE_SILENT;
8644 }
8645 else
8646 return RESET_TYPE_NORESET;
8647
8648}
8649
8650void rtl8192_cancel_deferred_work(struct r8192_priv* priv);
8651int _rtl8192_up(struct net_device *dev);
8652int rtl8192_close(struct net_device *dev);
8653
8654
8655
8656void
8657CamRestoreAllEntry( struct net_device *dev)
8658{
8659 u8 EntryId = 0;
8660 struct r8192_priv *priv = ieee80211_priv(dev);
8661 u8* MacAddr = priv->ieee80211->current_network.bssid;
8662
8663 static u8 CAM_CONST_ADDR[4][6] = {
8664 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
8665 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
8666 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
8667 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}};
8668 static u8 CAM_CONST_BROAD[] =
8669 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8670
8671 RT_TRACE(COMP_SEC, "CamRestoreAllEntry: \n");
8672
8673
8674 if ((priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP40)||
8675 (priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP104))
8676 {
8677
8678 for(EntryId=0; EntryId<4; EntryId++)
8679 {
8680 {
8681 MacAddr = CAM_CONST_ADDR[EntryId];
8682 setKey(dev,
8683 EntryId ,
8684 EntryId,
8685 priv->ieee80211->pairwise_key_type,
8686 MacAddr,
8687 0,
8688 NULL);
8689 }
8690 }
8691
8692 }
8693 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_TKIP)
8694 {
8695
8696 {
8697 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
8698 setKey(dev,
8699 4,
8700 0,
8701 priv->ieee80211->pairwise_key_type,
8702 (u8*)dev->dev_addr,
8703 0,
8704 NULL);
8705 else
8706 setKey(dev,
8707 4,
8708 0,
8709 priv->ieee80211->pairwise_key_type,
8710 MacAddr,
8711 0,
8712 NULL);
8713 }
8714 }
8715 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP)
8716 {
8717
8718 {
8719 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
8720 setKey(dev,
8721 4,
8722 0,
8723 priv->ieee80211->pairwise_key_type,
8724 (u8*)dev->dev_addr,
8725 0,
8726 NULL);
8727 else
8728 setKey(dev,
8729 4,
8730 0,
8731 priv->ieee80211->pairwise_key_type,
8732 MacAddr,
8733 0,
8734 NULL);
8735 }
8736 }
8737
8738
8739
8740 if(priv->ieee80211->group_key_type == KEY_TYPE_TKIP)
8741 {
8742 MacAddr = CAM_CONST_BROAD;
8743 for(EntryId=1 ; EntryId<4 ; EntryId++)
8744 {
8745 {
8746 setKey(dev,
8747 EntryId,
8748 EntryId,
8749 priv->ieee80211->group_key_type,
8750 MacAddr,
8751 0,
8752 NULL);
8753 }
8754 }
8755 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
8756 setKey(dev,
8757 0,
8758 0,
8759 priv->ieee80211->group_key_type,
8760 CAM_CONST_ADDR[0],
8761 0,
8762 NULL);
8763 }
8764 else if(priv->ieee80211->group_key_type == KEY_TYPE_CCMP)
8765 {
8766 MacAddr = CAM_CONST_BROAD;
8767 for(EntryId=1; EntryId<4 ; EntryId++)
8768 {
8769 {
8770 setKey(dev,
8771 EntryId ,
8772 EntryId,
8773 priv->ieee80211->group_key_type,
8774 MacAddr,
8775 0,
8776 NULL);
8777 }
8778 }
8779
8780 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
8781 setKey(dev,
8782 0 ,
8783 0,
8784 priv->ieee80211->group_key_type,
8785 CAM_CONST_ADDR[0],
8786 0,
8787 NULL);
8788 }
8789}
8790//////////////////////////////////////////////////////////////
8791// This function is used to fix Tx/Rx stop bug temporarily.
8792// This function will do "system reset" to NIC when Tx or Rx is stuck.
8793// The method checking Tx/Rx stuck of this function is supported by FW,
8794// which reports Tx and Rx counter to register 0x128 and 0x130.
8795//////////////////////////////////////////////////////////////
8796void
8797rtl819x_ifsilentreset(struct net_device *dev)
8798{
8799 //OCTET_STRING asocpdu;
8800 struct r8192_priv *priv = ieee80211_priv(dev);
8801 u8 reset_times = 0;
8802 int reset_status = 0;
8803 struct ieee80211_device *ieee = priv->ieee80211;
8804
8805
8806 // 2007.07.20. If we need to check CCK stop, please uncomment this line.
8807 //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter);
8808
8809 if(priv->ResetProgress==RESET_TYPE_NORESET)
8810 {
8811RESET_START:
8812
8813 RT_TRACE(COMP_RESET,"=========>Reset progress!! \n");
8814
8815 // Set the variable for reset.
8816 priv->ResetProgress = RESET_TYPE_SILENT;
8817// rtl8192_close(dev);
8818#if 1
8819 down(&priv->wx_sem);
8820 if(priv->up == 0)
8821 {
8822 RT_TRACE(COMP_ERR,"%s():the driver is not up! return\n",__FUNCTION__);
8823 up(&priv->wx_sem);
8824 return ;
8825 }
8826 priv->up = 0;
8827 RT_TRACE(COMP_RESET,"%s():======>start to down the driver\n",__FUNCTION__);
8828// if(!netif_queue_stopped(dev))
8829// netif_stop_queue(dev);
8830
8831 rtl8192_rtx_disable(dev);
8832 rtl8192_cancel_deferred_work(priv);
8833 deinit_hal_dm(dev);
8834 del_timer_sync(&priv->watch_dog_timer);
8835
8836 ieee->sync_scan_hurryup = 1;
8837 if(ieee->state == IEEE80211_LINKED)
8838 {
8839 down(&ieee->wx_sem);
8840 printk("ieee->state is IEEE80211_LINKED\n");
8841 ieee80211_stop_send_beacons(priv->ieee80211);
8842 del_timer_sync(&ieee->associate_timer);
5f53d8ca 8843 cancel_delayed_work(&ieee->associate_retry_wq);
5f53d8ca
JC		 8844 ieee80211_stop_scan(ieee);
8845 netif_carrier_off(dev);
8846 up(&ieee->wx_sem);
8847 }
8848 else{
8849 printk("ieee->state is NOT LINKED\n");
8850 ieee80211_softmac_stop_protocol(priv->ieee80211); }
8851 up(&priv->wx_sem);
8852 RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__);
8853 //rtl8192_irq_disable(dev);
8854 RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__);
8855 reset_status = _rtl8192_up(dev);
8856
8857 RT_TRACE(COMP_RESET,"%s():<===========up process is finished\n",__FUNCTION__);
8858 if(reset_status == -EAGAIN)
8859 {
8860 if(reset_times < 3)
8861 {
8862 reset_times++;
8863 goto RESET_START;
8864 }
8865 else
8866 {
8867 RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n", __FUNCTION__);
8868 }
8869 }
8870#endif
8871 ieee->is_silent_reset = 1;
8872#if 1
8873 EnableHWSecurityConfig8192(dev);
8874#if 1
8875 if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA)
8876 {
8877 ieee->set_chan(ieee->dev, ieee->current_network.channel);
8878
8879#if 1
5f53d8ca 8880 queue_work(ieee->wq, &ieee->associate_complete_wq);
5f53d8ca
JC		 8881#endif
8882
8883 }
8884 else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC)
8885 {
8886 ieee->set_chan(ieee->dev, ieee->current_network.channel);
8887 ieee->link_change(ieee->dev);
8888
8889 // notify_wx_assoc_event(ieee);
8890
8891 ieee80211_start_send_beacons(ieee);
8892
8893 if (ieee->data_hard_resume)
8894 ieee->data_hard_resume(ieee->dev);
8895 netif_carrier_on(ieee->dev);
8896 }
8897#endif
8898
8899 CamRestoreAllEntry(dev);
8900
8901 priv->ResetProgress = RESET_TYPE_NORESET;
8902 priv->reset_count++;
8903
8904 priv->bForcedSilentReset =false;
8905 priv->bResetInProgress = false;
8906
8907 // For test --> force write UFWP.
8908 write_nic_byte(dev, UFWP, 1);
8909 RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
8910#endif
8911 }
8912}
8913
8914void CAM_read_entry(
8915 struct net_device *dev,
8916 u32 iIndex
8917)
8918{
8919 u32 target_command=0;
8920 u32 target_content=0;
8921 u8 entry_i=0;
8922 u32 ulStatus;
8923 s32 i=100;
8924// printk("=======>start read CAM\n");
8925 for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
8926 {
8927 // polling bit, and No Write enable, and address
8928 target_command= entry_i+CAM_CONTENT_COUNT*iIndex;
8929 target_command= target_command | BIT31;
8930
8931 //Check polling bit is clear
8932// mdelay(1);
8933#if 1
8934 while((i--)>=0)
8935 {
8936 ulStatus = read_nic_dword(dev, RWCAM);
8937 if(ulStatus & BIT31){
8938 continue;
8939 }
8940 else{
8941 break;
8942 }
8943 }
8944#endif
8945 write_nic_dword(dev, RWCAM, target_command);
8946 RT_TRACE(COMP_SEC,"CAM_read_entry(): WRITE A0: %x \n",target_command);
8947 // printk("CAM_read_entry(): WRITE A0: %lx \n",target_command);
8948 target_content = read_nic_dword(dev, RCAMO);
8949 RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n",target_content);
8950 // printk("CAM_read_entry(): WRITE A8: %lx \n",target_content);
8951 }
8952 printk("\n");
8953}
8954
8955void rtl819x_update_rxcounts(
8956 struct r8192_priv *priv,
8957 u32* TotalRxBcnNum,
8958 u32* TotalRxDataNum
8959)
8960{
8961 u16 SlotIndex;
8962 u8 i;
8963
8964 *TotalRxBcnNum = 0;
8965 *TotalRxDataNum = 0;
8966
8967 SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum);
8968 priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod;
8969 priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod;
8970 for( i=0; i<priv->ieee80211->LinkDetectInfo.SlotNum; i++ ){
8971 *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i];
8972 *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i];
8973 }
8974}
8975
5f53d8ca
JC		 8976extern void rtl819x_watchdog_wqcallback(struct work_struct *work)
8977{
8978 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
8979 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq);
8980 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 8981 struct ieee80211_device* ieee = priv->ieee80211;
8982 RESET_TYPE ResetType = RESET_TYPE_NORESET;
8983 static u8 check_reset_cnt=0;
8984 bool bBusyTraffic = false;
8985
8986 if(!priv->up)
8987 return;
8988 hal_dm_watchdog(dev);
8989
8990 {//to get busy traffic condition
8991 if(ieee->state == IEEE80211_LINKED)
8992 {
8993 //windows mod 666 to 100.
8994 //if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 ||
8995 // ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) {
8996 if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 ||
8997 ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) {
8998 bBusyTraffic = true;
8999 }
9000 ieee->LinkDetectInfo.NumRxOkInPeriod = 0;
9001 ieee->LinkDetectInfo.NumTxOkInPeriod = 0;
9002 ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
9003 }
9004 }
9005 //added by amy for AP roaming
9006 {
9007 if(priv->ieee80211->state == IEEE80211_LINKED && priv->ieee80211->iw_mode == IW_MODE_INFRA)
9008 {
9009 u32 TotalRxBcnNum = 0;
9010 u32 TotalRxDataNum = 0;
9011
9012 rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum);
9013 if((TotalRxBcnNum+TotalRxDataNum) == 0)
9014 {
9015 #ifdef TODO
9016 if(rfState == eRfOff)
9017 RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__);
9018 #endif
9019 printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__);
9020 // Dot11d_Reset(dev);
9021 priv->ieee80211->state = IEEE80211_ASSOCIATING;
9022 notify_wx_assoc_event(priv->ieee80211);
9023 RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid);
9024 ieee->is_roaming = true;
9025 priv->ieee80211->link_change(dev);
5f53d8ca 9026 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
5f53d8ca
JC		 9027 }
9028 }
9029 priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod=0;
9030 priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod=0;
9031 }
9032// CAM_read_entry(dev,4);
9033 //check if reset the driver
9034 if(check_reset_cnt++ >= 3 && !ieee->is_roaming)
9035 {
9036 ResetType = rtl819x_ifcheck_resetornot(dev);
9037 check_reset_cnt = 3;
9038 //DbgPrint("Start to check silent reset\n");
9039 }
9040 // RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
9041#if 1
9042 if( (priv->force_reset) || (priv->ResetProgress==RESET_TYPE_NORESET &&
9043 (priv->bForcedSilentReset ||
9044 (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT)))) // This is control by OID set in Pomelo
9045 {
9046 RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
9047 rtl819x_ifsilentreset(dev);
9048 }
9049#endif
9050 priv->force_reset = false;
9051 priv->bForcedSilentReset = false;
9052 priv->bResetInProgress = false;
9053 RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n");
9054
9055}
9056
9057void watch_dog_timer_callback(unsigned long data)
9058{
9059 struct r8192_priv *priv = ieee80211_priv((struct net_device *) data);
9060 //printk("===============>watch_dog timer\n");
5f53d8ca 9061 queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq, 0);
5f53d8ca
JC		 9062 mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME));
9063#if 0
9064 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
9065 add_timer(&priv->watch_dog_timer);
9066#endif
9067}
9068int _rtl8192_up(struct net_device *dev)
9069{
9070 struct r8192_priv *priv = ieee80211_priv(dev);
9071 //int i;
9072 int init_status = 0;
9073 priv->up=1;
9074 priv->ieee80211->ieee_up=1;
9075 RT_TRACE(COMP_INIT, "Bringing up iface");
9076 init_status = priv->ops->rtl819x_adapter_start(dev);
9077 if(!init_status)
9078 {
9079 RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n", __FUNCTION__);
9080 priv->up=priv->ieee80211->ieee_up = 0;
9081 return -EAGAIN;
9082 }
9083 RT_TRACE(COMP_INIT, "start adapter finished\n");
9084 rtl8192_rx_enable(dev);
9085// rtl8192_tx_enable(dev);
9086 if(priv->ieee80211->state != IEEE80211_LINKED)
9087 ieee80211_softmac_start_protocol(priv->ieee80211);
9088 ieee80211_reset_queue(priv->ieee80211);
9089 watch_dog_timer_callback((unsigned long) dev);
9090 if(!netif_queue_stopped(dev))
9091 netif_start_queue(dev);
9092 else
9093 netif_wake_queue(dev);
9094
9095 /*
9096 * Make sure that drop_unencrypted is initialized as "0"
9097 * No packets will be sent in non-security mode if we had set drop_unencrypted.
9098 * ex, After kill wpa_supplicant process, make the driver up again.
9099 * drop_unencrypted remains as "1", which is set by wpa_supplicant. 2008/12/04.john
9100 */
9101 priv->ieee80211->drop_unencrypted = 0;
9102
9103 return 0;
9104}
9105
9106
9107int rtl8192_open(struct net_device *dev)
9108{
9109 struct r8192_priv *priv = ieee80211_priv(dev);
9110 int ret;
9111 down(&priv->wx_sem);
9112 ret = rtl8192_up(dev);
9113 up(&priv->wx_sem);
9114 return ret;
9115
9116}
9117
9118
9119int rtl8192_up(struct net_device *dev)
9120{
9121 struct r8192_priv *priv = ieee80211_priv(dev);
9122
9123 if (priv->up == 1) return -1;
9124
9125 return _rtl8192_up(dev);
9126}
9127
9128
9129int rtl8192_close(struct net_device *dev)
9130{
9131 struct r8192_priv *priv = ieee80211_priv(dev);
9132 int ret;
9133
9134 down(&priv->wx_sem);
9135
9136 ret = rtl8192_down(dev);
9137
9138 up(&priv->wx_sem);
9139
9140 return ret;
9141
9142}
9143
9144int rtl8192_down(struct net_device *dev)
9145{
9146 struct r8192_priv *priv = ieee80211_priv(dev);
9147 int i;
9148
9149 if (priv->up == 0) return -1;
9150
9151 priv->up=0;
9152 priv->ieee80211->ieee_up = 0;
9153 RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__);
9154/* FIXME */
9155 if (!netif_queue_stopped(dev))
9156 netif_stop_queue(dev);
9157
9158 rtl8192_rtx_disable(dev);
9159 //rtl8192_irq_disable(dev);
9160
9161 /* Tx related queue release */
9162 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
9163 skb_queue_purge(&priv->ieee80211->skb_waitQ [i]);
9164 }
9165 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
9166 skb_queue_purge(&priv->ieee80211->skb_aggQ [i]);
9167 }
9168
9169 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
9170 skb_queue_purge(&priv->ieee80211->skb_drv_aggQ [i]);
9171 }
9172
9173 //as cancel_delayed_work will del work->timer, so if work is not definedas struct delayed_work, it will corrupt
9174// flush_scheduled_work();
9175 rtl8192_cancel_deferred_work(priv);
9176 deinit_hal_dm(dev);
9177 del_timer_sync(&priv->watch_dog_timer);
9178
9179
9180 ieee80211_softmac_stop_protocol(priv->ieee80211);
9181 memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list));
9182 RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__);
9183
9184 return 0;
9185}
9186
9187
9188void rtl8192_commit(struct net_device *dev)
9189{
9190 struct r8192_priv *priv = ieee80211_priv(dev);
9191 int reset_status = 0;
9192 //u8 reset_times = 0;
9193 if (priv->up == 0) return ;
9194 priv->up = 0;
9195
9196 rtl8192_cancel_deferred_work(priv);
9197 del_timer_sync(&priv->watch_dog_timer);
9198 //cancel_delayed_work(&priv->SwChnlWorkItem);
9199
9200 ieee80211_softmac_stop_protocol(priv->ieee80211);
9201
9202 //rtl8192_irq_disable(dev);
9203 rtl8192_rtx_disable(dev);
9204 reset_status = _rtl8192_up(dev);
9205
9206}
9207
9208/*
9209void rtl8192_restart(struct net_device *dev)
9210{
9211 struct r8192_priv *priv = ieee80211_priv(dev);
9212*/
5f53d8ca
JC		 9213void rtl8192_restart(struct work_struct *work)
9214{
9215 struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq);
9216 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 9217
9218 down(&priv->wx_sem);
9219
9220 rtl8192_commit(dev);
9221
9222 up(&priv->wx_sem);
9223}
9224
9225static void r8192_set_multicast(struct net_device *dev)
9226{
9227 struct r8192_priv *priv = ieee80211_priv(dev);
9228 short promisc;
9229
9230 //down(&priv->wx_sem);
9231
9232 /* FIXME FIXME */
9233
9234 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
9235
9236 if (promisc != priv->promisc)
9237 // rtl8192_commit(dev);
9238
9239 priv->promisc = promisc;
9240
9241 //schedule_work(&priv->reset_wq);
9242 //up(&priv->wx_sem);
9243}
9244
9245
9246int r8192_set_mac_adr(struct net_device *dev, void *mac)
9247{
9248 struct r8192_priv *priv = ieee80211_priv(dev);
9249 struct sockaddr *addr = mac;
9250
9251 down(&priv->wx_sem);
9252
9253 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
9254
5f53d8ca 9255 schedule_work(&priv->reset_wq);
1ec9e48d 9256
5f53d8ca
JC		 9257 up(&priv->wx_sem);
9258
9259 return 0;
9260}
9261
9262/* based on ipw2200 driver */
9263int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
9264{
9265 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9266 struct iwreq *wrq = (struct iwreq *)rq;
9267 int ret=-1;
9268 struct ieee80211_device *ieee = priv->ieee80211;
9269 u32 key[4];
9270 u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
9271 u8 zero_addr[6] = {0};
9272 struct iw_point *p = &wrq->u.data;
9273 struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer;
9274
9275 down(&priv->wx_sem);
9276
9277
9278 if (p->length < sizeof(struct ieee_param) || !p->pointer){
9279 ret = -EINVAL;
9280 goto out;
9281 }
9282
9283 ipw = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL);
9284 if (ipw == NULL){
9285 ret = -ENOMEM;
9286 goto out;
9287 }
9288 if (copy_from_user(ipw, p->pointer, p->length)) {
9289 kfree(ipw);
9290 ret = -EFAULT;
9291 goto out;
9292 }
9293
9294 switch (cmd) {
9295 case RTL_IOCTL_WPA_SUPPLICANT:
9296 //parse here for HW security
9297 if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION)
9298 {
9299 if (ipw->u.crypt.set_tx)
9300 {
9301 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
9302 ieee->pairwise_key_type = KEY_TYPE_CCMP;
9303 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
9304 ieee->pairwise_key_type = KEY_TYPE_TKIP;
9305 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
9306 {
9307 if (ipw->u.crypt.key_len == 13)
9308 ieee->pairwise_key_type = KEY_TYPE_WEP104;
9309 else if (ipw->u.crypt.key_len == 5)
9310 ieee->pairwise_key_type = KEY_TYPE_WEP40;
9311 }
9312 else
9313 ieee->pairwise_key_type = KEY_TYPE_NA;
9314
9315 if (ieee->pairwise_key_type)
9316 {
9317 // FIXME:these two lines below just to fix ipw interface bug, that is, it will never set mode down to driver. So treat it as ADHOC mode, if no association procedure. WB. 2009.02.04
9318 if (memcmp(ieee->ap_mac_addr, zero_addr, 6) == 0)
9319 ieee->iw_mode = IW_MODE_ADHOC;
9320 memcpy((u8*)key, ipw->u.crypt.key, 16);
9321 EnableHWSecurityConfig8192(dev);
9322 //we fill both index entry and 4th entry for pairwise key as in IPW interface, adhoc will only get here, so we need index entry for its default key serching!
9323 //added by WB.
9324 setKey(dev, 4, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
9325 if (ieee->iw_mode == IW_MODE_ADHOC)
9326 setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
9327 }
9328 }
9329 else //if (ipw->u.crypt.idx) //group key use idx > 0
9330 {
9331 memcpy((u8*)key, ipw->u.crypt.key, 16);
9332 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
9333 ieee->group_key_type= KEY_TYPE_CCMP;
9334 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
9335 ieee->group_key_type = KEY_TYPE_TKIP;
9336 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
9337 {
9338 if (ipw->u.crypt.key_len == 13)
9339 ieee->group_key_type = KEY_TYPE_WEP104;
9340 else if (ipw->u.crypt.key_len == 5)
9341 ieee->group_key_type = KEY_TYPE_WEP40;
9342 }
9343 else
9344 ieee->group_key_type = KEY_TYPE_NA;
9345
9346 if (ieee->group_key_type)
9347 {
9348 setKey( dev,
9349 ipw->u.crypt.idx,
9350 ipw->u.crypt.idx, //KeyIndex
9351 ieee->group_key_type, //KeyType
9352 broadcast_addr, //MacAddr
9353 0, //DefaultKey
9354 key); //KeyContent
9355 }
9356 }
9357 }
9358#ifdef JOHN_HWSEC_DEBUG
9359 //john's test 0711
9360 printk("@@ wrq->u pointer = ");
9361 for(i=0;i<wrq->u.data.length;i++){
9362 if(i%10==0) printk("\n");
9363 printk( "%8x|", ((u32*)wrq->u.data.pointer)[i] );
9364 }
9365 printk("\n");
9366#endif /*JOHN_HWSEC_DEBUG*/
9367 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
9368 break;
9369
9370 default:
9371 ret = -EOPNOTSUPP;
9372 break;
9373 }
9374 kfree(ipw);
9375 ipw = NULL;
9376out:
9377 up(&priv->wx_sem);
9378 return ret;
9379}
9380
9381#ifdef RTL8192SU
9382u8 rtl8192SU_HwRateToMRate(bool bIsHT, u8 rate,bool bFirstAMPDU)
9383{
9384
9385 u8 ret_rate = 0x02;
9386
9387 if( bFirstAMPDU )
9388 {
9389 if(!bIsHT)
9390 {
9391 switch(rate)
9392 {
9393
9394 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
9395 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
9396 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
9397 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
9398 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
9399 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
9400 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
9401 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
9402 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
9403 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
9404 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
9405 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
9406
9407 default:
9408 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
9409 break;
9410 }
9411 }
9412 else
9413 {
9414 switch(rate)
9415 {
9416
9417 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
9418 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
9419 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
9420 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
9421 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
9422 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
9423 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
9424 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
9425 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
9426 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
9427 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
9428 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
9429 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
9430 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
9431 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
9432 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
9433 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
9434
9435 default:
9436 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
9437 break;
9438 }
9439
9440 }
9441 }
9442 else
9443 {
9444 switch(rate)
9445 {
9446
9447 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
9448 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
9449 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
9450 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
9451 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
9452 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
9453 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
9454 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
9455 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
9456 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
9457 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
9458 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
9459 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
9460 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
9461 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
9462 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
9463 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
9464 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
9465 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
9466 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
9467 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
9468 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
9469 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
9470 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
9471 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
9472 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
9473 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
9474 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
9475 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
9476
9477 default:
9478 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
9479 break;
9480 }
9481 }
9482 return ret_rate;
9483}
9484#endif
9485
9486u8 HwRateToMRate90(bool bIsHT, u8 rate)
9487{
9488 u8 ret_rate = 0xff;
9489
9490 if(!bIsHT) {
9491 switch(rate) {
9492 case DESC90_RATE1M: ret_rate = MGN_1M; break;
9493 case DESC90_RATE2M: ret_rate = MGN_2M; break;
9494 case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break;
9495 case DESC90_RATE11M: ret_rate = MGN_11M; break;
9496 case DESC90_RATE6M: ret_rate = MGN_6M; break;
9497 case DESC90_RATE9M: ret_rate = MGN_9M; break;
9498 case DESC90_RATE12M: ret_rate = MGN_12M; break;
9499 case DESC90_RATE18M: ret_rate = MGN_18M; break;
9500 case DESC90_RATE24M: ret_rate = MGN_24M; break;
9501 case DESC90_RATE36M: ret_rate = MGN_36M; break;
9502 case DESC90_RATE48M: ret_rate = MGN_48M; break;
9503 case DESC90_RATE54M: ret_rate = MGN_54M; break;
9504
9505 default:
9506 ret_rate = 0xff;
9507 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
9508 break;
9509 }
9510
9511 } else {
9512 switch(rate) {
9513 case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break;
9514 case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break;
9515 case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break;
9516 case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break;
9517 case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break;
9518 case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break;
9519 case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break;
9520 case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break;
9521 case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break;
9522 case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break;
9523 case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break;
9524 case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break;
9525 case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break;
9526 case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break;
9527 case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break;
9528 case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break;
9529 case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break;
9530
9531 default:
9532 ret_rate = 0xff;
9533 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT);
9534 break;
9535 }
9536 }
9537
9538 return ret_rate;
9539}
9540
9541/**
9542 * Function: UpdateRxPktTimeStamp
9543 * Overview: Recored down the TSF time stamp when receiving a packet
9544 *
9545 * Input:
9546 * PADAPTER Adapter
9547 * PRT_RFD pRfd,
9548 *
9549 * Output:
9550 * PRT_RFD pRfd
9551 * (pRfd->Status.TimeStampHigh is updated)
9552 * (pRfd->Status.TimeStampLow is updated)
9553 * Return:
9554 * None
9555 */
9556void UpdateRxPktTimeStamp8190 (struct net_device *dev, struct ieee80211_rx_stats *stats)
9557{
9558 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9559
9560 if(stats->bIsAMPDU && !stats->bFirstMPDU) {
9561 stats->mac_time[0] = priv->LastRxDescTSFLow;
9562 stats->mac_time[1] = priv->LastRxDescTSFHigh;
9563 } else {
9564 priv->LastRxDescTSFLow = stats->mac_time[0];
9565 priv->LastRxDescTSFHigh = stats->mac_time[1];
9566 }
9567}
9568
9569//by amy 080606
9570
9571long rtl819x_translate_todbm(u8 signal_strength_index )// 0-100 index.
9572{
9573 long signal_power; // in dBm.
9574
9575 // Translate to dBm (x=0.5y-95).
9576 signal_power = (long)((signal_strength_index + 1) >> 1);
9577 signal_power -= 95;
9578
9579 return signal_power;
9580}
9581
9582
9583/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
9584 be a local static. Otherwise, it may increase when we return from S3/S4. The
9585 value will be kept in memory or disk. We must delcare the value in adapter
9586 and it will be reinitialized when return from S3/S4. */
9587void rtl8192_process_phyinfo(struct r8192_priv * priv,u8* buffer, struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats)
9588{
9589 bool bcheck = false;
9590 u8 rfpath;
9591 u32 nspatial_stream, tmp_val;
9592 //u8 i;
9593 static u32 slide_rssi_index=0, slide_rssi_statistics=0;
9594 static u32 slide_evm_index=0, slide_evm_statistics=0;
9595 static u32 last_rssi=0, last_evm=0;
9596
9597 static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0;
9598 static u32 last_beacon_adc_pwdb=0;
9599
9600 struct ieee80211_hdr_3addr *hdr;
9601 u16 sc ;
9602 unsigned int frag,seq;
9603 hdr = (struct ieee80211_hdr_3addr *)buffer;
9604 sc = le16_to_cpu(hdr->seq_ctl);
9605 frag = WLAN_GET_SEQ_FRAG(sc);
9606 seq = WLAN_GET_SEQ_SEQ(sc);
9607 //cosa add 04292008 to record the sequence number
9608 pcurrent_stats->Seq_Num = seq;
9609 //
9610 // Check whether we should take the previous packet into accounting
9611 //
9612 if(!pprevious_stats->bIsAMPDU)
9613 {
9614 // if previous packet is not aggregated packet
9615 bcheck = true;
9616 }else
9617 {
9618 #if 0
9619 // if previous packet is aggregated packet, and current packet
9620 // (1) is not AMPDU
9621 // (2) is the first packet of one AMPDU
9622 // that means the previous packet is the last one aggregated packet
9623 if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU)
9624 bcheck = true;
9625 #endif
9626 }
9627
9628
9629 if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX)
9630 {
9631 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
9632 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
9633 priv->stats.slide_rssi_total -= last_rssi;
9634 }
9635 priv->stats.slide_rssi_total += pprevious_stats->SignalStrength;
9636
9637 priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength;
9638 if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
9639 slide_rssi_index = 0;
9640
9641 // <1> Showed on UI for user, in dbm
9642 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
9643 priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val);
9644 pcurrent_stats->rssi = priv->stats.signal_strength;
9645 //
9646 // If the previous packet does not match the criteria, neglect it
9647 //
9648 if(!pprevious_stats->bPacketMatchBSSID)
9649 {
9650 if(!pprevious_stats->bToSelfBA)
9651 return;
9652 }
9653
9654 if(!bcheck)
9655 return;
9656
9657
9658 //rtl8190_process_cck_rxpathsel(priv,pprevious_stats);//only rtl8190 supported
9659
9660 //
9661 // Check RSSI
9662 //
9663 priv->stats.num_process_phyinfo++;
9664
9665 /* record the general signal strength to the sliding window. */
9666
9667
9668 // <2> Showed on UI for engineering
9669 // hardware does not provide rssi information for each rf path in CCK
9670 if(!pprevious_stats->bIsCCK && (pprevious_stats->bPacketToSelf || pprevious_stats->bToSelfBA))
9671 {
9672 for (rfpath = RF90_PATH_A; rfpath < priv->NumTotalRFPath; rfpath++)
9673 {
9674 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath))
9675 continue;
9676
9677 //Fixed by Jacken 2008-03-20
9678 if(priv->stats.rx_rssi_percentage[rfpath] == 0)
9679 {
9680 priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath];
9681 //DbgPrint("MIMO RSSI initialize \n");
9682 }
9683 if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath])
9684 {
9685 priv->stats.rx_rssi_percentage[rfpath] =
9686 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
9687 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
9688 priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1;
9689 }
9690 else
9691 {
9692 priv->stats.rx_rssi_percentage[rfpath] =
9693 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
9694 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
9695 }
9696 RT_TRACE(COMP_DBG,"priv->stats.rx_rssi_percentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] );
9697 }
9698 }
9699
9700
9701 //
9702 // Check PWDB.
9703 //
9704 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
9705 pprevious_stats->bIsCCK? "CCK": "OFDM",
9706 pprevious_stats->RxPWDBAll);
9707
9708 if(pprevious_stats->bPacketBeacon)
9709 {
9710/* record the beacon pwdb to the sliding window. */
9711 if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX)
9712 {
9713 slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX;
9714 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index];
9715 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
9716 //DbgPrint("slide_beacon_adc_pwdb_index = %d, last_beacon_adc_pwdb = %d, Adapter->RxStats.Slide_Beacon_Total = %d\n",
9717 // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total);
9718 }
9719 priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll;
9720 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll;
9721 //DbgPrint("slide_beacon_adc_pwdb_index = %d, pPreviousRfd->Status.RxPWDBAll = %d\n", slide_beacon_adc_pwdb_index, pPreviousRfd->Status.RxPWDBAll);
9722 slide_beacon_adc_pwdb_index++;
9723 if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
9724 slide_beacon_adc_pwdb_index = 0;
9725 pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics;
9726 if(pprevious_stats->RxPWDBAll >= 3)
9727 pprevious_stats->RxPWDBAll -= 3;
9728 }
9729
9730 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
9731 pprevious_stats->bIsCCK? "CCK": "OFDM",
9732 pprevious_stats->RxPWDBAll);
9733
9734
9735 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
9736 {
9737 if(priv->undecorated_smoothed_pwdb < 0) // initialize
9738 {
9739 priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll;
9740 //DbgPrint("First pwdb initialize \n");
9741 }
9742#if 1
9743 if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb)
9744 {
9745 priv->undecorated_smoothed_pwdb =
9746 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
9747 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
9748 priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1;
9749 }
9750 else
9751 {
9752 priv->undecorated_smoothed_pwdb =
9753 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
9754 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
9755 }
9756#else
9757 //Fixed by Jacken 2008-03-20
9758 if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB)
9759 {
9760 pHalData->UndecoratedSmoothedPWDB =
9761 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
9762 pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1;
9763 }
9764 else
9765 {
9766 pHalData->UndecoratedSmoothedPWDB =
9767 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
9768 }
9769#endif
9770
9771 }
9772
9773 //
9774 // Check EVM
9775 //
9776 /* record the general EVM to the sliding window. */
9777 if(pprevious_stats->SignalQuality == 0)
9778 {
9779 }
9780 else
9781 {
9782 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){
9783 if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){
9784 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
9785 last_evm = priv->stats.slide_evm[slide_evm_index];
9786 priv->stats.slide_evm_total -= last_evm;
9787 }
9788
9789 priv->stats.slide_evm_total += pprevious_stats->SignalQuality;
9790
9791 priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality;
9792 if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
9793 slide_evm_index = 0;
9794
9795 // <1> Showed on UI for user, in percentage.
9796 tmp_val = priv->stats.slide_evm_total/slide_evm_statistics;
9797 priv->stats.signal_quality = tmp_val;
9798 //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality.
9799 priv->stats.last_signal_strength_inpercent = tmp_val;
9800 }
9801
9802 // <2> Showed on UI for engineering
9803 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
9804 {
9805 for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream
9806 {
9807 if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1)
9808 {
9809 if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize
9810 {
9811 priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream];
9812 }
9813 priv->stats.rx_evm_percentage[nspatial_stream] =
9814 ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) +
9815 (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor);
9816 }
9817 }
9818 }
9819 }
9820
9821
9822}
9823
9824/*-----------------------------------------------------------------------------
9825 * Function: rtl819x_query_rxpwrpercentage()
9826 *
9827 * Overview:
9828 *
9829 * Input: char antpower
9830 *
9831 * Output: NONE
9832 *
9833 * Return: 0-100 percentage
9834 *
9835 * Revised History:
9836 * When Who Remark
9837 * 05/26/2008 amy Create Version 0 porting from windows code.
9838 *
9839 *---------------------------------------------------------------------------*/
9840static u8 rtl819x_query_rxpwrpercentage(
9841 char antpower
9842 )
9843{
9844 if ((antpower <= -100) || (antpower >= 20))
9845 {
9846 return 0;
9847 }
9848 else if (antpower >= 0)
9849 {
9850 return 100;
9851 }
9852 else
9853 {
9854 return (100+antpower);
9855 }
9856
9857} /* QueryRxPwrPercentage */
9858
9859static u8
9860rtl819x_evm_dbtopercentage(
9861 char value
9862 )
9863{
9864 char ret_val;
9865
9866 ret_val = value;
9867
9868 if(ret_val >= 0)
9869 ret_val = 0;
9870 if(ret_val <= -33)
9871 ret_val = -33;
9872 ret_val = 0 - ret_val;
9873 ret_val*=3;
9874 if(ret_val == 99)
9875 ret_val = 100;
9876 return(ret_val);
9877}
9878//
9879// Description:
9880// We want good-looking for signal strength/quality
9881// 2007/7/19 01:09, by cosa.
9882//
9883long
9884rtl819x_signal_scale_mapping(
9885 long currsig
9886 )
9887{
9888 long retsig;
9889
9890 // Step 1. Scale mapping.
9891 if(currsig >= 61 && currsig <= 100)
9892 {
9893 retsig = 90 + ((currsig - 60) / 4);
9894 }
9895 else if(currsig >= 41 && currsig <= 60)
9896 {
9897 retsig = 78 + ((currsig - 40) / 2);
9898 }
9899 else if(currsig >= 31 && currsig <= 40)
9900 {
9901 retsig = 66 + (currsig - 30);
9902 }
9903 else if(currsig >= 21 && currsig <= 30)
9904 {
9905 retsig = 54 + (currsig - 20);
9906 }
9907 else if(currsig >= 5 && currsig <= 20)
9908 {
9909 retsig = 42 + (((currsig - 5) * 2) / 3);
9910 }
9911 else if(currsig == 4)
9912 {
9913 retsig = 36;
9914 }
9915 else if(currsig == 3)
9916 {
9917 retsig = 27;
9918 }
9919 else if(currsig == 2)
9920 {
9921 retsig = 18;
9922 }
9923 else if(currsig == 1)
9924 {
9925 retsig = 9;
9926 }
9927 else
9928 {
9929 retsig = currsig;
9930 }
9931
9932 return retsig;
9933}
9934
9935#ifdef RTL8192SU
9936/*-----------------------------------------------------------------------------
9937 * Function: QueryRxPhyStatus8192S()
9938 *
9939 * Overview:
9940 *
9941 * Input: NONE
9942 *
9943 * Output: NONE
9944 *
9945 * Return: NONE
9946 *
9947 * Revised History:
9948 * When Who Remark
9949 * 06/01/2007 MHC Create Version 0.
9950 * 06/05/2007 MHC Accordign to HW's new data sheet, we add CCK and OFDM
9951 * descriptor definition.
9952 * 07/04/2007 MHC According to Jerry and Bryant's document. We read
9953 * ir_isolation and ext_lna for RF's init value and use
9954 * to compensate RSSI after receiving packets.
9955 * 09/10/2008 MHC Modify name and PHY status field for 92SE.
9956 * 09/19/2008 MHC Add CCK/OFDM SS/SQ for 92S series.
9957 *
9958 *---------------------------------------------------------------------------*/
9959static void rtl8192SU_query_rxphystatus(
9960 struct r8192_priv * priv,
9961 struct ieee80211_rx_stats * pstats,
9962 rx_desc_819x_usb *pDesc,
9963 rx_drvinfo_819x_usb * pdrvinfo,
9964 struct ieee80211_rx_stats * precord_stats,
9965 bool bpacket_match_bssid,
9966 bool bpacket_toself,
9967 bool bPacketBeacon,
9968 bool bToSelfBA
9969 )
9970{
9971 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
9972 //PHY_STS_CCK_8192S_T *pCck_buf;
9973 phy_sts_cck_819xusb_t * pcck_buf;
9974 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
9975 //u8 *prxpkt;
9976 //u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
9977 u8 i, max_spatial_stream, rxsc_sgien_exflg;
9978 char rx_pwr[4], rx_pwr_all=0;
9979 //long rx_avg_pwr = 0;
9980 //char rx_snrX, rx_evmX;
9981 u8 evm, pwdb_all;
9982 u32 RSSI, total_rssi=0;//, total_evm=0;
9983// long signal_strength_index = 0;
9984 u8 is_cck_rate=0;
9985 u8 rf_rx_num = 0;
9986
9987
9988
9989 priv->stats.numqry_phystatus++;
9990
9991 is_cck_rate = rx_hal_is_cck_rate(pDesc);
9992
9993 // Record it for next packet processing
9994 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
9995 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
9996 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
9997 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
9998 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
9999 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
10000
10001#ifndef RTL8192SU
10002 phy_sts_ofdm_819xusb_t* pofdm_buf = NULL;
10003 prxpkt = (u8*)pdrvinfo;
10004
10005 /* Move pointer to the 16th bytes. Phy status start address. */
10006 prxpkt += sizeof(rx_drvinfo_819x_usb);
10007
10008 /* Initial the cck and ofdm buffer pointer */
10009 pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt;
10010 pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt;
10011#endif
10012
10013 pstats->RxMIMOSignalQuality[0] = -1;
10014 pstats->RxMIMOSignalQuality[1] = -1;
10015 precord_stats->RxMIMOSignalQuality[0] = -1;
10016 precord_stats->RxMIMOSignalQuality[1] = -1;
10017
10018 if(is_cck_rate)
10019 {
10020 u8 report;//, tmp_pwdb;
10021 //char cck_adc_pwdb[4];
10022
10023 // CCK Driver info Structure is not the same as OFDM packet.
10024 pcck_buf = (phy_sts_cck_819xusb_t *)pdrvinfo;
10025
10026 //
10027 // (1)Hardware does not provide RSSI for CCK
10028 //
10029
10030 //
10031 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10032 //
10033
10034 priv->stats.numqry_phystatusCCK++;
10035
10036 if(!priv->bCckHighPower)
10037 {
10038 report = pcck_buf->cck_agc_rpt & 0xc0;
10039 report = report>>6;
10040 switch(report)
10041 {
10042 //Fixed by Jacken from Bryant 2008-03-20
10043 //Original value is -38 , -26 , -14 , -2
10044 //Fixed value is -35 , -23 , -11 , 6
10045 case 0x3:
10046 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
10047 break;
10048 case 0x2:
10049 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
10050 break;
10051 case 0x1:
10052 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
10053 break;
10054 case 0x0:
10055 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);//6->8
10056 break;
10057 }
10058 }
10059 else
10060 {
10061 report = pdrvinfo->cfosho[0] & 0x60;
10062 report = report>>5;
10063 switch(report)
10064 {
10065 case 0x3:
10066 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10067 break;
10068 case 0x2:
10069 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
10070 break;
10071 case 0x1:
10072 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10073 break;
10074 case 0x0:
10075 rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;//6->-8
10076 break;
10077 }
10078 }
10079
10080 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);//check it
10081 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10082 //pstats->RecvSignalPower = pwdb_all;
10083 pstats->RecvSignalPower = rx_pwr_all;
10084
10085 //
10086 // (3) Get Signal Quality (EVM)
10087 //
10088 //if(bpacket_match_bssid)
10089 {
10090 u8 sq;
10091
10092 if(pstats->RxPWDBAll > 40)
10093 {
10094 sq = 100;
10095 }else
10096 {
10097 sq = pcck_buf->sq_rpt;
10098
10099 if(pcck_buf->sq_rpt > 64)
10100 sq = 0;
10101 else if (pcck_buf->sq_rpt < 20)
10102 sq = 100;
10103 else
10104 sq = ((64-sq) * 100) / 44;
10105 }
10106 pstats->SignalQuality = precord_stats->SignalQuality = sq;
10107 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
10108 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
10109 }
10110 }
10111 else
10112 {
10113 priv->stats.numqry_phystatusHT++;
10114
10115 // 2008/09/19 MH For 92S debug, RX RF path always enable!!
10116 priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = TRUE;
10117
10118 //
10119 // (1)Get RSSI for HT rate
10120 //
10121 //for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
10122 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
10123 {
10124 // 2008/01/30 MH we will judge RF RX path now.
10125 if (priv->brfpath_rxenable[i])
10126 rf_rx_num++;
10127 //else
10128 // continue;
10129
10130 //if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
10131 // continue;
10132
10133 //Fixed by Jacken from Bryant 2008-03-20
10134 //Original value is 106
10135 //rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
10136 rx_pwr[i] = ((pdrvinfo->gain_trsw[i]&0x3F)*2) - 110;
10137
10138 /* Translate DBM to percentage. */
10139 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); //check ok
10140 total_rssi += RSSI;
10141 RT_TRACE(COMP_RF, "RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI);
10142
10143 //Get Rx snr value in DB
10144 //tmp_rxsnr = pofdm_buf->rxsnr_X[i];
10145 //rx_snrX = (char)(tmp_rxsnr);
10146 //rx_snrX /= 2;
10147 //priv->stats.rxSNRdB[i] = (long)rx_snrX;
10148 priv->stats.rxSNRdB[i] = (long)(pdrvinfo->rxsnr[i]/2);
10149
10150 /* Translate DBM to percentage. */
10151 //RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
10152 //total_rssi += RSSI;
10153
10154 /* Record Signal Strength for next packet */
10155 //if(bpacket_match_bssid)
10156 {
10157 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
10158 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
10159 }
10160 }
10161
10162
10163 //
10164 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10165 //
10166 //Fixed by Jacken from Bryant 2008-03-20
10167 //Original value is 106
10168 //rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
10169 rx_pwr_all = (((pdrvinfo->pwdb_all ) >> 1 )& 0x7f) -106;
10170 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
10171
10172 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10173 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
10174 pstats->RecvSignalPower = rx_pwr_all;
10175
10176 //
10177 // (3)EVM of HT rate
10178 //
10179 //if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
10180 // pdrvinfo->RxRate<=DESC90_RATEMCS15)
10181 if(pDesc->RxHT && pDesc->RxMCS>=DESC92S_RATEMCS8 &&
10182 pDesc->RxMCS<=DESC92S_RATEMCS15)
10183 max_spatial_stream = 2; //both spatial stream make sense
10184 else
10185 max_spatial_stream = 1; //only spatial stream 1 makes sense
10186
10187 for(i=0; i<max_spatial_stream; i++)
10188 {
10189 //tmp_rxevm = pofdm_buf->rxevm_X[i];
10190 //rx_evmX = (char)(tmp_rxevm);
10191
10192 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
10193 // fill most significant bit to "zero" when doing shifting operation which may change a negative
10194 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
10195 //rx_evmX /= 2; //dbm
10196
10197 //evm = rtl819x_evm_dbtopercentage(rx_evmX);
10198 evm = rtl819x_evm_dbtopercentage( (pdrvinfo->rxevm[i] /*/ 2*/)); //dbm
10199 RT_TRACE(COMP_RF, "RXRATE=%x RXEVM=%x EVM=%s%d\n", pDesc->RxMCS, pdrvinfo->rxevm[i], "%", evm);
10200#if 0
10201 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100//=====>from here
10202#endif
10203
10204 //if(bpacket_match_bssid)
10205 {
10206 if(i==0) // Fill value in RFD, Get the first spatial stream only
10207 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
10208 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
10209 }
10210 }
10211
10212
10213 /* record rx statistics for debug */
10214 //rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
10215 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
10216 //if(pdrvinfo->BW) //40M channel
10217 if(pDesc->BW) //40M channel
10218 priv->stats.received_bwtype[1+pdrvinfo->rxsc]++;
10219 else //20M channel
10220 priv->stats.received_bwtype[0]++;
10221 }
10222
10223 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
10224 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
10225 if(is_cck_rate)
10226 {
10227 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;//check ok
10228
10229 }
10230 else
10231 {
10232 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
10233 // We can judge RX path number now.
10234 if (rf_rx_num != 0)
10235 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
10236 }
10237}/* QueryRxPhyStatus8192S */
10238#else
10239static void rtl8192_query_rxphystatus(
10240 struct r8192_priv * priv,
10241 struct ieee80211_rx_stats * pstats,
10242 rx_drvinfo_819x_usb * pdrvinfo,
10243 struct ieee80211_rx_stats * precord_stats,
10244 bool bpacket_match_bssid,
10245 bool bpacket_toself,
10246 bool bPacketBeacon,
10247 bool bToSelfBA
10248 )
10249{
10250 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
10251 phy_sts_ofdm_819xusb_t* pofdm_buf;
10252 phy_sts_cck_819xusb_t * pcck_buf;
10253 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
10254 u8 *prxpkt;
10255 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
10256 char rx_pwr[4], rx_pwr_all=0;
10257 //long rx_avg_pwr = 0;
10258 char rx_snrX, rx_evmX;
10259 u8 evm, pwdb_all;
10260 u32 RSSI, total_rssi=0;//, total_evm=0;
10261// long signal_strength_index = 0;
10262 u8 is_cck_rate=0;
10263 u8 rf_rx_num = 0;
10264
10265
10266 priv->stats.numqry_phystatus++;
10267
10268 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
10269
10270 // Record it for next packet processing
10271 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
10272 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
10273 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
10274 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
10275 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
10276 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
10277
10278 prxpkt = (u8*)pdrvinfo;
10279
10280 /* Move pointer to the 16th bytes. Phy status start address. */
10281 prxpkt += sizeof(rx_drvinfo_819x_usb);
10282
10283 /* Initial the cck and ofdm buffer pointer */
10284 pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt;
10285 pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt;
10286
10287 pstats->RxMIMOSignalQuality[0] = -1;
10288 pstats->RxMIMOSignalQuality[1] = -1;
10289 precord_stats->RxMIMOSignalQuality[0] = -1;
10290 precord_stats->RxMIMOSignalQuality[1] = -1;
10291
10292 if(is_cck_rate)
10293 {
10294 //
10295 // (1)Hardware does not provide RSSI for CCK
10296 //
10297
10298 //
10299 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10300 //
10301 u8 report;//, cck_agc_rpt;
10302
10303 priv->stats.numqry_phystatusCCK++;
10304
10305 if(!priv->bCckHighPower)
10306 {
10307 report = pcck_buf->cck_agc_rpt & 0xc0;
10308 report = report>>6;
10309 switch(report)
10310 {
10311 //Fixed by Jacken from Bryant 2008-03-20
10312 //Original value is -38 , -26 , -14 , -2
10313 //Fixed value is -35 , -23 , -11 , 6
10314 case 0x3:
10315 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
10316 break;
10317 case 0x2:
10318 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
10319 break;
10320 case 0x1:
10321 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
10322 break;
10323 case 0x0:
10324 rx_pwr_all = 6 - (pcck_buf->cck_agc_rpt & 0x3e);
10325 break;
10326 }
10327 }
10328 else
10329 {
10330 report = pcck_buf->cck_agc_rpt & 0x60;
10331 report = report>>5;
10332 switch(report)
10333 {
10334 case 0x3:
10335 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10336 break;
10337 case 0x2:
10338 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
10339 break;
10340 case 0x1:
10341 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10342 break;
10343 case 0x0:
10344 rx_pwr_all = 6 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10345 break;
10346 }
10347 }
10348
10349 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
10350 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10351 pstats->RecvSignalPower = pwdb_all;
10352
10353 //
10354 // (3) Get Signal Quality (EVM)
10355 //
10356 //if(bpacket_match_bssid)
10357 {
10358 u8 sq;
10359
10360 if(pstats->RxPWDBAll > 40)
10361 {
10362 sq = 100;
10363 }else
10364 {
10365 sq = pcck_buf->sq_rpt;
10366
10367 if(pcck_buf->sq_rpt > 64)
10368 sq = 0;
10369 else if (pcck_buf->sq_rpt < 20)
10370 sq = 100;
10371 else
10372 sq = ((64-sq) * 100) / 44;
10373 }
10374 pstats->SignalQuality = precord_stats->SignalQuality = sq;
10375 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
10376 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
10377 }
10378 }
10379 else
10380 {
10381 priv->stats.numqry_phystatusHT++;
10382 //
10383 // (1)Get RSSI for HT rate
10384 //
10385 for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
10386 {
10387 // 2008/01/30 MH we will judge RF RX path now.
10388 if (priv->brfpath_rxenable[i])
10389 rf_rx_num++;
10390 else
10391 continue;
10392
10393 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
10394 continue;
10395
10396 //Fixed by Jacken from Bryant 2008-03-20
10397 //Original value is 106
10398 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
10399
10400 //Get Rx snr value in DB
10401 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
10402 rx_snrX = (char)(tmp_rxsnr);
10403 //rx_snrX >>= 1;;
10404 rx_snrX /= 2;
10405 priv->stats.rxSNRdB[i] = (long)rx_snrX;
10406
10407 /* Translate DBM to percentage. */
10408 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
10409 total_rssi += RSSI;
10410
10411 /* Record Signal Strength for next packet */
10412 //if(bpacket_match_bssid)
10413 {
10414 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
10415 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
10416 }
10417 }
10418
10419
10420 //
10421 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10422 //
10423 //Fixed by Jacken from Bryant 2008-03-20
10424 //Original value is 106
10425 rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
10426 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
10427
10428 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10429 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
10430
10431 //
10432 // (3)EVM of HT rate
10433 //
10434 if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
10435 pdrvinfo->RxRate<=DESC90_RATEMCS15)
10436 max_spatial_stream = 2; //both spatial stream make sense
10437 else
10438 max_spatial_stream = 1; //only spatial stream 1 makes sense
10439
10440 for(i=0; i<max_spatial_stream; i++)
10441 {
10442 tmp_rxevm = pofdm_buf->rxevm_X[i];
10443 rx_evmX = (char)(tmp_rxevm);
10444
10445 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
10446 // fill most significant bit to "zero" when doing shifting operation which may change a negative
10447 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
10448 rx_evmX /= 2; //dbm
10449
10450 evm = rtl819x_evm_dbtopercentage(rx_evmX);
10451#if 0
10452 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100
10453#endif
10454 //if(bpacket_match_bssid)
10455 {
10456 if(i==0) // Fill value in RFD, Get the first spatial stream only
10457 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
10458 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
10459 }
10460 }
10461
10462
10463 /* record rx statistics for debug */
10464 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
10465 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
10466 if(pdrvinfo->BW) //40M channel
10467 priv->stats.received_bwtype[1+prxsc->rxsc]++;
10468 else //20M channel
10469 priv->stats.received_bwtype[0]++;
10470 }
10471
10472 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
10473 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
10474 if(is_cck_rate)
10475 {
10476 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;
10477
10478 }
10479 else
10480 {
10481 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
10482 // We can judge RX path number now.
10483 if (rf_rx_num != 0)
10484 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
10485 }
10486} /* QueryRxPhyStatus8190Pci */
10487#endif
10488
10489void
10490rtl8192_record_rxdesc_forlateruse(
10491 struct ieee80211_rx_stats * psrc_stats,
10492 struct ieee80211_rx_stats * ptarget_stats
10493)
10494{
10495 ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU;
10496 ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU;
10497 ptarget_stats->Seq_Num = psrc_stats->Seq_Num;
10498}
10499
10500#ifdef RTL8192SU
10501static void rtl8192SU_query_rxphystatus(
10502 struct r8192_priv * priv,
10503 struct ieee80211_rx_stats * pstats,
10504 rx_desc_819x_usb *pDesc,
10505 rx_drvinfo_819x_usb * pdrvinfo,
10506 struct ieee80211_rx_stats * precord_stats,
10507 bool bpacket_match_bssid,
10508 bool bpacket_toself,
10509 bool bPacketBeacon,
10510 bool bToSelfBA
10511 );
10512void rtl8192SU_TranslateRxSignalStuff(struct sk_buff *skb,
10513 struct ieee80211_rx_stats * pstats,
10514 rx_desc_819x_usb *pDesc,
10515 rx_drvinfo_819x_usb *pdrvinfo)
10516{
10517 // TODO: We must only check packet for current MAC address. Not finish
10518 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10519 struct net_device *dev=info->dev;
10520 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10521 bool bpacket_match_bssid, bpacket_toself;
10522 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
10523 static struct ieee80211_rx_stats previous_stats;
10524 struct ieee80211_hdr_3addr *hdr;//by amy
10525 u16 fc,type;
10526
10527 // Get Signal Quality for only RX data queue (but not command queue)
10528
10529 u8* tmp_buf;
10530 //u16 tmp_buf_len = 0;
10531 u8 *praddr;
10532
10533 /* Get MAC frame start address. */
10534 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
10535
10536 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
10537 fc = le16_to_cpu(hdr->frame_ctl);
10538 type = WLAN_FC_GET_TYPE(fc);
10539 praddr = hdr->addr1;
10540
10541 /* Check if the received packet is acceptabe. */
10542 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
10543 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
10544 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
10545 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
10546
10547#if 1//cosa
10548 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
10549 {
10550 bPacketBeacon = true;
10551 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10552 }
10553 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
10554 {
10555 if((eqMacAddr(praddr,dev->dev_addr)))
10556 bToSelfBA = true;
10557 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10558 }
10559
10560#endif
10561
10562
10563 if(bpacket_match_bssid)
10564 {
10565 priv->stats.numpacket_matchbssid++;
10566 }
10567 if(bpacket_toself){
10568 priv->stats.numpacket_toself++;
10569 }
10570 //
10571 // Process PHY information for previous packet (RSSI/PWDB/EVM)
10572 //
10573 // Because phy information is contained in the last packet of AMPDU only, so driver
10574 // should process phy information of previous packet
10575 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
10576 rtl8192SU_query_rxphystatus(priv, pstats, pDesc, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
10577 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
10578
10579}
10580#else
10581void TranslateRxSignalStuff819xUsb(struct sk_buff *skb,
10582 struct ieee80211_rx_stats * pstats,
10583 rx_drvinfo_819x_usb *pdrvinfo)
10584{
10585 // TODO: We must only check packet for current MAC address. Not finish
10586 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10587 struct net_device *dev=info->dev;
10588 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10589 bool bpacket_match_bssid, bpacket_toself;
10590 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
10591 static struct ieee80211_rx_stats previous_stats;
10592 struct ieee80211_hdr_3addr *hdr;//by amy
10593 u16 fc,type;
10594
10595 // Get Signal Quality for only RX data queue (but not command queue)
10596
10597 u8* tmp_buf;
10598 //u16 tmp_buf_len = 0;
10599 u8 *praddr;
10600
10601 /* Get MAC frame start address. */
10602 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
10603
10604 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
10605 fc = le16_to_cpu(hdr->frame_ctl);
10606 type = WLAN_FC_GET_TYPE(fc);
10607 praddr = hdr->addr1;
10608
10609 /* Check if the received packet is acceptabe. */
10610 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
10611 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
10612 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
10613 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
10614
10615#if 1//cosa
10616 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
10617 {
10618 bPacketBeacon = true;
10619 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10620 }
10621 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
10622 {
10623 if((eqMacAddr(praddr,dev->dev_addr)))
10624 bToSelfBA = true;
10625 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10626 }
10627
10628#endif
10629
10630
10631 if(bpacket_match_bssid)
10632 {
10633 priv->stats.numpacket_matchbssid++;
10634 }
10635 if(bpacket_toself){
10636 priv->stats.numpacket_toself++;
10637 }
10638 //
10639 // Process PHY information for previous packet (RSSI/PWDB/EVM)
10640 //
10641 // Because phy information is contained in the last packet of AMPDU only, so driver
10642 // should process phy information of previous packet
10643 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
10644 rtl8192_query_rxphystatus(priv, pstats, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
10645 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
10646
10647}
10648#endif
10649
10650/**
10651* Function: UpdateReceivedRateHistogramStatistics
10652* Overview: Recored down the received data rate
10653*
10654* Input:
10655* struct net_device *dev
10656* struct ieee80211_rx_stats *stats
10657*
10658* Output:
10659*
10660* (priv->stats.ReceivedRateHistogram[] is updated)
10661* Return:
10662* None
10663*/
10664void
10665UpdateReceivedRateHistogramStatistics8190(
10666 struct net_device *dev,
10667 struct ieee80211_rx_stats *stats
10668 )
10669{
10670 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10671 u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV
10672 u32 rateIndex;
10673 u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI
10674
10675
10676 if(stats->bCRC)
10677 rcvType = 2;
10678 else if(stats->bICV)
10679 rcvType = 3;
10680
10681 if(stats->bShortPreamble)
10682 preamble_guardinterval = 1;// short
10683 else
10684 preamble_guardinterval = 0;// long
10685
10686 switch(stats->rate)
10687 {
10688 //
10689 // CCK rate
10690 //
10691 case MGN_1M: rateIndex = 0; break;
10692 case MGN_2M: rateIndex = 1; break;
10693 case MGN_5_5M: rateIndex = 2; break;
10694 case MGN_11M: rateIndex = 3; break;
10695 //
10696 // Legacy OFDM rate
10697 //
10698 case MGN_6M: rateIndex = 4; break;
10699 case MGN_9M: rateIndex = 5; break;
10700 case MGN_12M: rateIndex = 6; break;
10701 case MGN_18M: rateIndex = 7; break;
10702 case MGN_24M: rateIndex = 8; break;
10703 case MGN_36M: rateIndex = 9; break;
10704 case MGN_48M: rateIndex = 10; break;
10705 case MGN_54M: rateIndex = 11; break;
10706 //
10707 // 11n High throughput rate
10708 //
10709 case MGN_MCS0: rateIndex = 12; break;
10710 case MGN_MCS1: rateIndex = 13; break;
10711 case MGN_MCS2: rateIndex = 14; break;
10712 case MGN_MCS3: rateIndex = 15; break;
10713 case MGN_MCS4: rateIndex = 16; break;
10714 case MGN_MCS5: rateIndex = 17; break;
10715 case MGN_MCS6: rateIndex = 18; break;
10716 case MGN_MCS7: rateIndex = 19; break;
10717 case MGN_MCS8: rateIndex = 20; break;
10718 case MGN_MCS9: rateIndex = 21; break;
10719 case MGN_MCS10: rateIndex = 22; break;
10720 case MGN_MCS11: rateIndex = 23; break;
10721 case MGN_MCS12: rateIndex = 24; break;
10722 case MGN_MCS13: rateIndex = 25; break;
10723 case MGN_MCS14: rateIndex = 26; break;
10724 case MGN_MCS15: rateIndex = 27; break;
10725 default: rateIndex = 28; break;
10726 }
10727 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
10728 priv->stats.received_rate_histogram[0][rateIndex]++; //total
10729 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
10730}
10731
10732#ifdef RTL8192SU
10733void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
10734{
10735 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10736 struct net_device *dev=info->dev;
10737 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10738 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
10739 rx_drvinfo_819x_usb *driver_info = NULL;
10740
10741 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
10742 //PHAL_DATA_8192SUSB pHalData = GET_HAL_DATA(Adapter);
10743 //pu1Byte pDesc = (pu1Byte)pDescIn;
10744 //PRX_DRIVER_INFO_8192S pDrvInfo;
10745
10746#ifdef USB_RX_AGGREGATION_SUPPORT//FIXLZM
10747 //if (bIsRxAggrSubframe)
10748 rx_desc_819x_usb_aggr_subframe *desc = (rx_desc_819x_usb_aggr_subframe *)skb->data;
10749 else
10750#endif
10751 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
10752
10753 if(0)
10754 {
10755 int m = 0;
10756 printk("========================");
10757 for(m=0; m<skb->len; m++){
10758 if((m%32) == 0)
10759 printk("\n");
10760 printk("%2x ",((u8*)skb->data)[m]);
10761 }
10762 printk("\n========================\n");
10763
10764 }
10765
10766
10767 //
10768 //Get Rx Descriptor Raw Information
10769 //
10770 stats->Length = desc->Length ;
10771 stats->RxDrvInfoSize = desc->RxDrvInfoSize*RX_DRV_INFO_SIZE_UNIT;
10772 stats->RxBufShift = (desc->Shift)&0x03;
10773 stats->bICV = desc->ICV;
10774 stats->bCRC = desc->CRC32;
10775 stats->bHwError = stats->bCRC|stats->bICV;
10776 stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet
10777 stats->bIsAMPDU = (desc->AMSDU==1);
10778 stats->bFirstMPDU = (desc->PAGGR==1) && (desc->FAGGR==1);
10779 stats->bShortPreamble = desc->SPLCP;
10780 stats->RxIs40MHzPacket = (desc->BW==1);
10781 stats->TimeStampLow = desc->TSFL;
10782
10783 if((desc->FAGGR==1) || (desc->PAGGR==1))
10784 {// Rx A-MPDU
10785 RT_TRACE(COMP_RXDESC, "FirstAGGR = %d, PartAggr = %d\n", desc->FAGGR, desc->PAGGR);
10786 }
10787//YJ,test,090310
10788if(stats->bHwError)
10789{
10790 if(stats->bICV)
10791 printk("%s: Receive ICV error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
10792 if(stats->bCRC)
10793 printk("%s: Receive CRC error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
10794}
10795
10796 if(IS_UNDER_11N_AES_MODE(priv->ieee80211))
10797 {
10798 // Always received ICV error packets in AES mode.
10799 // This fixed HW later MIC write bug.
10800 if(stats->bICV && !stats->bCRC)
10801 {
10802 stats->bICV = FALSE;
10803 stats->bHwError = FALSE;
10804 }
10805 }
10806
10807 // Transform HwRate to MRate
10808 if(!stats->bHwError)
10809 //stats->DataRate = HwRateToMRate(
10810 // (BOOLEAN)GET_RX_DESC_RXHT(pDesc),
10811 // (u1Byte)GET_RX_DESC_RXMCS(pDesc),
10812 // (BOOLEAN)GET_RX_DESC_PAGGR(pDesc));
10813 stats->rate = rtl8192SU_HwRateToMRate(desc->RxHT, desc->RxMCS, desc->PAGGR);
10814 else
10815 stats->rate = MGN_1M;
10816
10817 //
10818 // Collect Rx rate/AMPDU/TSFL
10819 //
10820 //UpdateRxdRateHistogramStatistics8192S(Adapter, pRfd);
10821 //UpdateRxAMPDUHistogramStatistics8192S(Adapter, pRfd);
10822 //UpdateRxPktTimeStamp8192S(Adapter, pRfd);
10823 UpdateReceivedRateHistogramStatistics8190(dev, stats);
10824 //UpdateRxAMPDUHistogramStatistics8192S(dev, stats); //FIXLZM
10825 UpdateRxPktTimeStamp8190(dev, stats);
10826
10827 //
10828 // Get PHY Status and RSVD parts.
10829 // <Roger_Notes> It only appears on last aggregated packet.
10830 //
10831 if (desc->PHYStatus)
10832 {
10833 //driver_info = (rx_drvinfo_819x_usb *)(skb->data + RX_DESC_SIZE + stats->RxBufShift);
10834 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
10835 stats->RxBufShift);
10836 if(0)
10837 {
10838 int m = 0;
10839 printk("========================\n");
10840 printk("RX_DESC_SIZE:%d, RxBufShift:%d, RxDrvInfoSize:%d\n",
10841 RX_DESC_SIZE, stats->RxBufShift, stats->RxDrvInfoSize);
10842 for(m=0; m<32; m++){
10843 printk("%2x ",((u8*)driver_info)[m]);
10844 }
10845 printk("\n========================\n");
10846
10847 }
10848
10849 }
10850
10851 //YJ,add,090107
10852 skb_pull(skb, sizeof(rx_desc_819x_usb));
10853 //YJ,add,090107,end
10854
10855 //
10856 // Get Total offset of MPDU Frame Body
10857 //
10858 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
10859 {
10860 stats->bShift = 1;
10861 //YJ,add,090107
10862 skb_pull(skb, stats->RxBufShift + stats->RxDrvInfoSize);
10863 //YJ,add,090107,end
10864 }
10865
10866 //
10867 // Get PHY Status and RSVD parts.
10868 // <Roger_Notes> It only appears on last aggregated packet.
10869 //
10870 if (desc->PHYStatus)
10871 {
10872 rtl8192SU_TranslateRxSignalStuff(skb, stats, desc, driver_info);
10873 }
10874}
10875#else
10876void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
10877{
10878 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10879 struct net_device *dev=info->dev;
10880 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10881 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
10882 rx_drvinfo_819x_usb *driver_info = NULL;
10883
10884 //
10885 //Get Rx Descriptor Information
10886 //
10887#ifdef USB_RX_AGGREGATION_SUPPORT
10888 if (bIsRxAggrSubframe)
10889 {
10890 rx_desc_819x_usb_aggr_subframe *desc = (rx_desc_819x_usb_aggr_subframe *)skb->data;
10891 stats->Length = desc->Length ;
10892 stats->RxDrvInfoSize = desc->RxDrvInfoSize;
10893 stats->RxBufShift = 0; //RxBufShift = 2 in RxDesc, but usb didn't shift bytes in fact.
10894 stats->bICV = desc->ICV;
10895 stats->bCRC = desc->CRC32;
10896 stats->bHwError = stats->bCRC|stats->bICV;
10897 stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet
10898 } else
10899#endif
10900 {
10901 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
10902
10903 stats->Length = desc->Length;
10904 stats->RxDrvInfoSize = desc->RxDrvInfoSize;
10905 stats->RxBufShift = 0;//desc->Shift&0x03;
10906 stats->bICV = desc->ICV;
10907 stats->bCRC = desc->CRC32;
10908 stats->bHwError = stats->bCRC|stats->bICV;
10909 //RTL8190 set this bit to indicate that Hw does not decrypt packet
10910 stats->Decrypted = !desc->SWDec;
10911 }
10912
10913 if((priv->ieee80211->pHTInfo->bCurrentHTSupport == true) && (priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP))
10914 {
10915 stats->bHwError = false;
10916 }
10917 else
10918 {
10919 stats->bHwError = stats->bCRC|stats->bICV;
10920 }
10921
10922 if(stats->Length < 24 || stats->Length > MAX_8192U_RX_SIZE)
10923 stats->bHwError |= 1;
10924 //
10925 //Get Driver Info
10926 //
10927 // TODO: Need to verify it on FGPA platform
10928 //Driver info are written to the RxBuffer following rx desc
10929 if (stats->RxDrvInfoSize != 0) {
10930 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
10931 stats->RxBufShift);
10932 /* unit: 0.5M */
10933 /* TODO */
10934 if(!stats->bHwError){
10935 u8 ret_rate;
10936 ret_rate = HwRateToMRate90(driver_info->RxHT, driver_info->RxRate);
10937 if(ret_rate == 0xff)
10938 {
10939 // Abnormal Case: Receive CRC OK packet with Rx descriptor indicating non supported rate.
10940 // Special Error Handling here, 2008.05.16, by Emily
10941
10942 stats->bHwError = 1;
10943 stats->rate = MGN_1M; //Set 1M rate by default
10944 }else
10945 {
10946 stats->rate = ret_rate;
10947 }
10948 }
10949 else
10950 stats->rate = 0x02;
10951
10952 stats->bShortPreamble = driver_info->SPLCP;
10953
10954
10955 UpdateReceivedRateHistogramStatistics8190(dev, stats);
10956
10957 stats->bIsAMPDU = (driver_info->PartAggr==1);
10958 stats->bFirstMPDU = (driver_info->PartAggr==1) && (driver_info->FirstAGGR==1);
10959#if 0
10960 // TODO: it is debug only. It should be disabled in released driver. 2007.1.12 by Joseph
10961 UpdateRxAMPDUHistogramStatistics8190(Adapter, pRfd);
10962#endif
10963 stats->TimeStampLow = driver_info->TSFL;
10964 // xiong mask it, 070514
10965 //pRfd->Status.TimeStampHigh = PlatformEFIORead4Byte(Adapter, TSFR+4);
10966 // stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
10967
10968 UpdateRxPktTimeStamp8190(dev, stats);
10969
10970 //
10971 // Rx A-MPDU
10972 //
10973 if(driver_info->FirstAGGR==1 || driver_info->PartAggr == 1)
10974 RT_TRACE(COMP_RXDESC, "driver_info->FirstAGGR = %d, driver_info->PartAggr = %d\n",
10975 driver_info->FirstAGGR, driver_info->PartAggr);
10976
10977 }
10978
10979 skb_pull(skb,sizeof(rx_desc_819x_usb));
10980 //
10981 // Get Total offset of MPDU Frame Body
10982 //
10983 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0) {
10984 stats->bShift = 1;
10985 skb_pull(skb,stats->RxBufShift + stats->RxDrvInfoSize);
10986 }
10987
10988#ifdef USB_RX_AGGREGATION_SUPPORT
10989 /* for the rx aggregated sub frame, the redundant space truelly contained in the packet */
10990 if(bIsRxAggrSubframe) {
10991 skb_pull(skb, 8);
10992 }
10993#endif
10994 /* for debug 2008.5.29 */
10995#if 0
10996 {
10997 int i;
10998 printk("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
10999 for(i = 0; i < skb->len; i++) {
11000 if(i % 10 == 0) printk("\n");
11001 printk("%02x ", skb->data[i]);
11002 }
11003 printk("\n<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
11004 }
11005#endif
11006
11007 //added by vivi, for MP, 20080108
11008 stats->RxIs40MHzPacket = driver_info->BW;
11009 if(stats->RxDrvInfoSize != 0)
11010 TranslateRxSignalStuff819xUsb(skb, stats, driver_info);
11011
11012}
11013#endif
11014
11015#ifdef RTL8192SU
11016#if 0
11017/*-----------------------------------------------------------------------------
11018 * Function: UpdateRxAMPDUHistogramStatistics8192S
11019 *
11020 * Overview: Recored down the received A-MPDU aggregation size and pkt number
11021 *
11022 * Input: Adapter
11023 *
11024 * Output: Adapter
11025 * (Adapter->RxStats.RxAMPDUSizeHistogram[] is updated)
11026 * (Adapter->RxStats.RxAMPDUNumHistogram[] is updated)
11027 *
11028 * Return: NONE
11029 *
11030 * Revised History:
11031 * When Who Remark
11032 * 09/18/2008 MHC Create Version 0.
11033 *
11034 *---------------------------------------------------------------------------*/
11035static void
11036UpdateRxAMPDUHistogramStatistics8192S(
11037 struct net_device *dev,
11038 struct ieee80211_rx_stats *stats
11039 )
11040{
11041 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
11042 u8 size_index;
11043 u8 num_index;
11044 u16 update_size = 0;
11045 u8 update_num = 0;
11046
11047 if(stats->bIsAMPDU)
11048 {
11049 if(stats->bFirstMPDU)
11050 {
11051 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
11052 {
11053 update_size = stats->nRxAMPDU_Size;
11054 update_num = stats->nRxAMPDU_AggrNum;
11055 }
11056 stats->nRxAMPDU_Size = stats->Length;
11057 stats->nRxAMPDU_AggrNum = 1;
11058 }
11059 else
11060 {
11061 stats->nRxAMPDU_Size += stats->Length;
11062 stats->nRxAMPDU_AggrNum++;
11063 }
11064 }
11065 else
11066 {
11067 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
11068 {
11069 update_size = stats->nRxAMPDU_Size;
11070 update_num = stats->nRxAMPDU_AggrNum;
11071 }
11072 stats->nRxAMPDU_Size = 0;
11073 stats->nRxAMPDU_AggrNum = 0;
11074 }
11075
11076 if(update_size!=0 && update_num!= 0)
11077 {
11078 if(update_size < 4096)
11079 size_index = 0;
11080 else if(update_size < 8192)
11081 size_index = 1;
11082 else if(update_size < 16384)
11083 size_index = 2;
11084 else if(update_size < 32768)
11085 size_index = 3;
11086 else if(update_size < 65536)
11087 size_index = 4;
11088 else
11089 {
11090 RT_TRACE(COMP_RXDESC,
11091 ("UpdateRxAMPDUHistogramStatistics8192S(): A-MPDU too large\n");
11092 }
11093
11094 Adapter->RxStats.RxAMPDUSizeHistogram[size_index]++;
11095
11096 if(update_num < 5)
11097 num_index = 0;
11098 else if(update_num < 10)
11099 num_index = 1;
11100 else if(update_num < 20)
11101 num_index = 2;
11102 else if(update_num < 40)
11103 num_index = 3;
11104 else
11105 num_index = 4;
11106
11107 Adapter->RxStats.RxAMPDUNumHistogram[num_index]++;
11108 }
11109} // UpdateRxAMPDUHistogramStatistics8192S
11110#endif
11111
11112#endif
11113
11114
11115#ifdef RTL8192SU
11116//
11117// Description:
11118// The strarting address of wireless lan header will shift 1 or 2 or 3 or "more" bytes for the following reason :
11119// (1) QoS control : shift 2 bytes
11120// (2) Mesh Network : shift 1 or 3 bytes
11121// (3) RxDriverInfo occupies the front parts of Rx Packets buffer(shift units is in 8Bytes)
11122//
11123// It is because Lextra CPU used by 8186 or 865x series assert exception if the statrting address
11124// of IP header is not double word alignment.
11125// This features is supported in 818xb and 8190 only, but not 818x.
11126//
11127// parameter: PRT_RFD, Pointer of Reeceive frame descriptor which is initialized according to
11128// Rx Descriptor
11129// return value: unsigned int, number of total shifted bytes
11130//
11131// Notes: 2008/06/28, created by Roger
11132//
11133u32 GetRxPacketShiftBytes8192SU(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
11134{
11135 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
11136
11137 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + Status->RxBufShift);
11138}
11139
11140void rtl8192SU_rx_nomal(struct sk_buff* skb)
11141{
11142 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11143 struct net_device *dev=info->dev;
11144 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11145 struct ieee80211_rx_stats stats = {
11146 .signal = 0,
11147 .noise = -98,
11148 .rate = 0,
11149 // .mac_time = jiffies,
11150 .freq = IEEE80211_24GHZ_BAND,
11151 };
11152 u32 rx_pkt_len = 0;
11153 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
11154 bool unicast_packet = false;
11155
11156#ifdef USB_RX_AGGREGATION_SUPPORT
11157 struct sk_buff *agg_skb = NULL;
11158 u32 TotalLength = 0;//Total packet length for all aggregated packets.
11159 u32 TempDWord = 0;
11160 u32 PacketLength = 0;// Per-packet length include size of RxDesc.
11161 u32 PacketOccupiedLendth = 0;
11162 u8 TempByte = 0;
11163 u32 PacketShiftBytes = 0;
11164 rx_desc_819x_usb_aggr_subframe *RxDescr = NULL;
11165 u8 PaddingBytes = 0;
11166 //add just for testing
11167 u8 testing;
11168
11169 u8 TotalAggPkt = 0;
11170 PRT_HIGH_THROUGHPUT pHTInfo =priv-> ieee80211->pHTInfo;
11171 u16 RxPageSize = pHTInfo->UsbRxPageSize;
11172
11173 stats->nTotalAggPkt = 0;
11174 //stats->bIsRxAggrSubframe = FALSE;
11175
11176#endif
11177 //printk("**********skb->len = %d\n", skb->len);
11178 /* 20 is for ps-poll */
11179 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
11180
11181 /* first packet should not contain Rx aggregation header */
11182 rtl8192SU_query_rxdesc_status(skb, &stats, false);
11183 /* TODO */
11184
11185 /* hardware related info */
11186#ifdef USB_RX_AGGREGATION_SUPPORT
11187 TotalAggPkt = stats->nTotalAggPkt;
11188 PacketLength = stats->Length + GetRxPacketShiftBytes8192SU(&stats, false);
11189
11190 agg_skb = skb;
11191 skb = dev_alloc_skb(PacketLength);
11192 memcpy(skb_put(skb,PacketLength),agg_skb->data,PacketLength);
11193#endif
11194 priv->stats.rxoktotal++; //YJ,test,090108
11195
11196 /* Process the MPDU recevied */
11197 skb_trim(skb, skb->len - 4/*sCrcLng*/);//FIXLZM
11198
11199 rx_pkt_len = skb->len;
11200 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11201 unicast_packet = false;
11202 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11203 //TODO
11204 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11205 //TODO
11206 }else {
11207 /* unicast packet */
11208 unicast_packet = true;
11209 }
11210
11211 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11212 dev_kfree_skb_any(skb);
11213 } else {
11214 // priv->stats.rxoktotal++; //YJ,test,090108
11215 if(unicast_packet) {
11216 priv->stats.rxbytesunicast += rx_pkt_len;
11217 }
11218 }
11219
11220 //up is firs pkt, follow is next and next
11221#ifdef USB_RX_AGGREGATION_SUPPORT
11222 //
11223 // The following operations are for processing Rx aggregated packets.
11224 //
11225 if(TotalAggPkt>0)
11226 TotalAggPkt--;
11227
11228 while ( TotalAggPkt>0 )
11229 {// More aggregated packets need to process.
11230
11231 u8 tmpCRC = 0, tmpICV = 0;
11232
11233 //Page size must align to multiple of 128-Bytes.
11234 if((PacketLength%RxPageSize) != 0)
11235 //PacketLength = ((PacketLength/RxPageSize)+1)*RxPageSize;
11236 PacketLength = ((PacketLength>>7)+1)*RxPageSize; // RxPageSize is 128bytes as default.
11237
11238 // Current total packet occupied length in this buffer.
11239 PacketOccupiedLendth += PacketLength;
11240
11241#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
11242 //if(PacketOccupiedLendth>pContext->BufLenUsed)
11243 if(PacketOccupiedLendth>skb->len)
11244 {
11245 RT_TRACE(COMP_RECV, "(1)HalUsbInMpduComplete8192SUsb(): pRtRfdStatus->Length(%#x)!!\n", stats->Length);
11246 RT_TRACE(COMP_RECV, "(1)HalUsbInMpduComplete8192SUsb(): Invalid PacketOccupiedLendth(%#x)!!, BufLenUsed(%#x)\n", PacketOccupiedLendth, stats->BufLenUsed);
11247 break;
11248 }
11249#endif
11250
11251 skb_pull(agg_skb, PacketLength);
11252
11253 //
11254 // Process the MPDU recevied.
11255 //
11256 //RT_TRACE(COMP_RECV,"%s:aggred pkt,total_len = %d\n",__FUNCTION__,agg_skb->len);
11257 RxDescr = (rx_desc_819x_usb_aggr_subframe *)(agg_skb->data);
11258
11259#if 0//92SU del
11260 tmpCRC = RxDescr->CRC32;
11261 tmpICV = RxDescr->ICV;
11262 memcpy(agg_skb->data, &agg_skb->data[44], 2);
11263 RxDescr->CRC32 = tmpCRC;
11264 RxDescr->ICV = tmpICV;
11265#endif
11266 memset(&stats, 0, sizeof(struct ieee80211_rx_stats));
11267 stats.signal = 0;
11268 stats.noise = -98;
11269 stats.rate = 0;
11270 stats.freq = IEEE80211_24GHZ_BAND;
11271
11272 rtl8192SU_query_rxdesc_status(agg_skb, &stats, true);
11273 //PacketLength = stats.Length;
11274 PacketLength = stats.Length + GetRxPacketShiftBytes8192SU(&stats, true);
11275
11276#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
11277 if((PacketOccupiedLendth+PacketLength)>skb->len)
11278 {
11279 RT_TRACE(COMP_RECV, "(2)HalUsbInMpduComplete8192SUsb(): Invalid PacketOccupiedLendth(%#x)+PacketLength(%#x)!!, BufLenUsed(%#x)\n",
11280 PacketOccupiedLendth, PacketLength, pContext->BufLenUsed);
11281 break;
11282 }
11283#endif
11284
11285 if(PacketLength > agg_skb->len) {
11286 break;
11287 }
11288
11289 /* Process the MPDU recevied */
11290 skb = dev_alloc_skb(PacketLength);
11291 memcpy(skb_put(skb,PacketLength),agg_skb->data, PacketLength);
11292 skb_trim(skb, skb->len - 4/*sCrcLng*/);
11293
11294 rx_pkt_len = skb->len;
11295 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11296 unicast_packet = false;
11297 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11298 //TODO
11299 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11300 //TODO
11301 }else {
11302 /* unicast packet */
11303 unicast_packet = true;
11304 }
11305 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11306 dev_kfree_skb_any(skb);
11307 } else {
11308 priv->stats.rxoktotal++;
11309 if(unicast_packet) {
11310 priv->stats.rxbytesunicast += rx_pkt_len;
11311 }
11312 }
11313
11314 TotalAggPkt--;
11315
11316 skb_pull(agg_skb, TempDWord);
11317 }
11318
11319 dev_kfree_skb(agg_skb);
11320#endif
11321 }
11322 else
11323 {
11324 priv->stats.rxurberr++;
11325 printk("actual_length:%d\n", skb->len);
11326 dev_kfree_skb_any(skb);
11327 }
11328
11329}
11330#else
11331u32 GetRxPacketShiftBytes819xUsb(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
11332{
11333#ifdef USB_RX_AGGREGATION_SUPPORT
11334 if (bIsRxAggrSubframe)
11335 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize
11336 + Status->RxBufShift + 8);
11337 else
11338#endif
11339 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize
11340 + Status->RxBufShift);
11341}
11342
11343void rtl8192_rx_nomal(struct sk_buff* skb)
11344{
11345 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11346 struct net_device *dev=info->dev;
11347 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11348 struct ieee80211_rx_stats stats = {
11349 .signal = 0,
11350 .noise = -98,
11351 .rate = 0,
11352 // .mac_time = jiffies,
11353 .freq = IEEE80211_24GHZ_BAND,
11354 };
11355 u32 rx_pkt_len = 0;
11356 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
11357 bool unicast_packet = false;
11358#ifdef USB_RX_AGGREGATION_SUPPORT
11359 struct sk_buff *agg_skb = NULL;
11360 u32 TotalLength = 0;
11361 u32 TempDWord = 0;
11362 u32 PacketLength = 0;
11363 u32 PacketOccupiedLendth = 0;
11364 u8 TempByte = 0;
11365 u32 PacketShiftBytes = 0;
11366 rx_desc_819x_usb_aggr_subframe *RxDescr = NULL;
11367 u8 PaddingBytes = 0;
11368 //add just for testing
11369 u8 testing;
11370
11371#endif
11372
11373 /* 20 is for ps-poll */
11374 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
11375#ifdef USB_RX_AGGREGATION_SUPPORT
11376 TempByte = *(skb->data + sizeof(rx_desc_819x_usb));
11377#endif
11378 /* first packet should not contain Rx aggregation header */
11379 query_rxdesc_status(skb, &stats, false);
11380 /* TODO */
11381 /* hardware related info */
11382#ifdef USB_RX_AGGREGATION_SUPPORT
11383 if (TempByte & BIT0) {
11384 agg_skb = skb;
11385 //TotalLength = agg_skb->len - 4; /*sCrcLng*/
11386 TotalLength = stats.Length - 4; /*sCrcLng*/
11387 //RT_TRACE(COMP_RECV, "%s:first aggregated packet!Length=%d\n",__FUNCTION__,TotalLength);
11388 /* though the head pointer has passed this position */
11389 TempDWord = *(u32 *)(agg_skb->data - 4);
11390 PacketLength = (u16)(TempDWord & 0x3FFF); /*sCrcLng*/
11391 skb = dev_alloc_skb(PacketLength);
11392 memcpy(skb_put(skb,PacketLength),agg_skb->data,PacketLength);
11393 PacketShiftBytes = GetRxPacketShiftBytes819xUsb(&stats, false);
11394 }
11395#endif
11396 /* Process the MPDU recevied */
11397 skb_trim(skb, skb->len - 4/*sCrcLng*/);
11398
11399 rx_pkt_len = skb->len;
11400 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11401 unicast_packet = false;
11402 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11403 //TODO
11404 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11405 //TODO
11406 }else {
11407 /* unicast packet */
11408 unicast_packet = true;
11409 }
11410
11411 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11412 dev_kfree_skb_any(skb);
11413 } else {
11414 priv->stats.rxoktotal++;
11415 if(unicast_packet) {
11416 priv->stats.rxbytesunicast += rx_pkt_len;
11417 }
11418 }
11419#ifdef USB_RX_AGGREGATION_SUPPORT
11420 testing = 1;
11421 // (PipeIndex == 0) && (TempByte & BIT0) => TotalLength > 0.
11422 if (TotalLength > 0) {
11423 PacketOccupiedLendth = PacketLength + (PacketShiftBytes + 8);
11424 if ((PacketOccupiedLendth & 0xFF) != 0)
11425 PacketOccupiedLendth = (PacketOccupiedLendth & 0xFFFFFF00) + 256;
11426 PacketOccupiedLendth -= 8;
11427 TempDWord = PacketOccupiedLendth - PacketShiftBytes; /*- PacketLength */
11428 if (agg_skb->len > TempDWord)
11429 skb_pull(agg_skb, TempDWord);
11430 else
11431 agg_skb->len = 0;
11432
11433 while (agg_skb->len>=GetRxPacketShiftBytes819xUsb(&stats, true)) {
11434 u8 tmpCRC = 0, tmpICV = 0;
11435 //RT_TRACE(COMP_RECV,"%s:aggred pkt,total_len = %d\n",__FUNCTION__,agg_skb->len);
11436 RxDescr = (rx_desc_819x_usb_aggr_subframe *)(agg_skb->data);
11437 tmpCRC = RxDescr->CRC32;
11438 tmpICV = RxDescr->ICV;
11439 memcpy(agg_skb->data, &agg_skb->data[44], 2);
11440 RxDescr->CRC32 = tmpCRC;
11441 RxDescr->ICV = tmpICV;
11442
11443 memset(&stats, 0, sizeof(struct ieee80211_rx_stats));
11444 stats.signal = 0;
11445 stats.noise = -98;
11446 stats.rate = 0;
11447 stats.freq = IEEE80211_24GHZ_BAND;
11448 query_rxdesc_status(agg_skb, &stats, true);
11449 PacketLength = stats.Length;
11450
11451 if(PacketLength > agg_skb->len) {
11452 break;
11453 }
11454 /* Process the MPDU recevied */
11455 skb = dev_alloc_skb(PacketLength);
11456 memcpy(skb_put(skb,PacketLength),agg_skb->data, PacketLength);
11457 skb_trim(skb, skb->len - 4/*sCrcLng*/);
11458
11459 rx_pkt_len = skb->len;
11460 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11461 unicast_packet = false;
11462 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11463 //TODO
11464 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11465 //TODO
11466 }else {
11467 /* unicast packet */
11468 unicast_packet = true;
11469 }
11470 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11471 dev_kfree_skb_any(skb);
11472 } else {
11473 priv->stats.rxoktotal++;
11474 if(unicast_packet) {
11475 priv->stats.rxbytesunicast += rx_pkt_len;
11476 }
11477 }
11478 /* should trim the packet which has been copied to target skb */
11479 skb_pull(agg_skb, PacketLength);
11480 PacketShiftBytes = GetRxPacketShiftBytes819xUsb(&stats, true);
11481 PacketOccupiedLendth = PacketLength + PacketShiftBytes;
11482 if ((PacketOccupiedLendth & 0xFF) != 0) {
11483 PaddingBytes = 256 - (PacketOccupiedLendth & 0xFF);
11484 if (agg_skb->len > PaddingBytes)
11485 skb_pull(agg_skb, PaddingBytes);
11486 else
11487 agg_skb->len = 0;
11488 }
11489 }
11490 dev_kfree_skb(agg_skb);
11491 }
11492#endif
11493 } else {
11494 priv->stats.rxurberr++;
11495 printk("actual_length:%d\n", skb->len);
11496 dev_kfree_skb_any(skb);
11497 }
11498
11499}
11500
11501#endif
11502
11503void
11504rtl819xusb_process_received_packet(
11505 struct net_device *dev,
11506 struct ieee80211_rx_stats *pstats
11507 )
11508{
11509// bool bfreerfd=false, bqueued=false;
11510 u8* frame;
11511 u16 frame_len=0;
11512 struct r8192_priv *priv = ieee80211_priv(dev);
11513// u8 index = 0;
11514// u8 TID = 0;
11515 //u16 seqnum = 0;
11516 //PRX_TS_RECORD pts = NULL;
11517
11518 // Get shifted bytes of Starting address of 802.11 header. 2006.09.28, by Emily
11519 //porting by amy 080508
11520 pstats->virtual_address += get_rxpacket_shiftbytes_819xusb(pstats);
11521 frame = pstats->virtual_address;
11522 frame_len = pstats->packetlength;
11523#ifdef TODO // by amy about HCT
11524 if(!Adapter->bInHctTest)
11525 CountRxErrStatistics(Adapter, pRfd);
11526#endif
11527 {
11528 #ifdef ENABLE_PS //by amy for adding ps function in future
11529 RT_RF_POWER_STATE rtState;
11530 // When RF is off, we should not count the packet for hw/sw synchronize
11531 // reason, ie. there may be a duration while sw switch is changed and hw
11532 // switch is being changed. 2006.12.04, by shien chang.
11533 Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (u8* )(&rtState));
11534 if (rtState == eRfOff)
11535 {
11536 return;
11537 }
11538 #endif
11539 priv->stats.rxframgment++;
11540
11541 }
11542#ifdef TODO
11543 RmMonitorSignalStrength(Adapter, pRfd);
11544#endif
11545 /* 2007/01/16 MH Add RX command packet handle here. */
11546 /* 2007/03/01 MH We have to release RFD and return if rx pkt is cmd pkt. */
11547 if (rtl819xusb_rx_command_packet(dev, pstats))
11548 {
11549 return;
11550 }
11551
11552#ifdef SW_CRC_CHECK
11553 SwCrcCheck();
11554#endif
11555
11556
11557}
11558
11559void query_rx_cmdpkt_desc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats)
11560{
11561// rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11562// struct net_device *dev=info->dev;
11563// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11564 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
11565// rx_drvinfo_819x_usb *driver_info;
11566
11567 //
11568 //Get Rx Descriptor Information
11569 //
11570 stats->virtual_address = (u8*)skb->data;
11571 stats->Length = desc->Length;
11572 stats->RxDrvInfoSize = 0;
11573 stats->RxBufShift = 0;
11574 stats->packetlength = stats->Length-scrclng;
11575 stats->fraglength = stats->packetlength;
11576 stats->fragoffset = 0;
11577 stats->ntotalfrag = 1;
11578}
11579
11580#ifdef RTL8192SU
11581void rtl8192SU_rx_cmd(struct sk_buff *skb)
11582{
11583 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11584 struct net_device *dev = info->dev;
11585
11586 /* TODO */
11587 struct ieee80211_rx_stats stats = {
11588 .signal = 0,
11589 .noise = -98,
11590 .rate = 0,
11591 // .mac_time = jiffies,
11592 .freq = IEEE80211_24GHZ_BAND,
11593 };
11594
11595 //
11596 // Check buffer length to determine if this is a valid MPDU.
11597 //
11598 if( (skb->len >= sizeof(rx_desc_819x_usb)) && (skb->len <= RX_URB_SIZE) )//&&
11599 //(pHalData->SwChnlInProgress == FALSE))
11600 {
11601 //
11602 // Collection information in Rx descriptor.
11603 //
11604#if 0
11605 pRxDesc = pContext->Buffer;
11606
11607 pRfd->Buffer.VirtualAddress = pContext->Buffer; // 061109, rcnjko, for multi-platform consideration..
11608
11609 pRtRfdStatus->Length = (u2Byte)GET_RX_DESC_PKT_LEN(pRxDesc);
11610 pRtRfdStatus->RxDrvInfoSize = 0;
11611 pRtRfdStatus->RxBufShift = 0;
11612
11613 pRfd->PacketLength = pRfd->Status.Length - sCrcLng;
11614 pRfd->FragLength = pRfd->PacketLength;
11615 pRfd->FragOffset = 0;
11616 pRfd->nTotalFrag = 1;
11617 pRfd->queue_id = PipeIndex;
11618#endif
11619 query_rx_cmdpkt_desc_status(skb,&stats);
11620 // this is to be done by amy 080508 prfd->queue_id = 1;
11621
11622 //
11623 // Process the MPDU recevied.
11624 //
11625 rtl819xusb_process_received_packet(dev,&stats);
11626
11627 dev_kfree_skb_any(skb);
11628 }
11629 else
11630 {
11631 //RTInsertTailListWithCnt(&pAdapter->RfdIdleQueue, &pRfd->List, &pAdapter->NumIdleRfd);
11632 //RT_ASSERT(pAdapter->NumIdleRfd <= pAdapter->NumRfd, ("HalUsbInCommandComplete8192SUsb(): Adapter->NumIdleRfd(%d)\n", pAdapter->NumIdleRfd));
11633 //RT_TRACE(COMP_RECV, DBG_LOUD, ("HalUsbInCommandComplete8192SUsb(): NOT enough Resources!! BufLenUsed(%d), NumIdleRfd(%d)\n",
11634 //pContext->BufLenUsed, pAdapter->NumIdleRfd));
11635 }
11636
11637 //
11638 // Reuse USB_IN_CONTEXT since we had finished processing the
11639 // buffer in USB_IN_CONTEXT.
11640 //
11641 //HalUsbReturnInContext(pAdapter, pContext);
11642
11643 //
11644 // Issue another bulk IN transfer.
11645 //
11646 //HalUsbInMpdu(pAdapter, PipeIndex);
11647
11648 RT_TRACE(COMP_RECV, "<--- HalUsbInCommandComplete8192SUsb()\n");
11649
11650}
11651#else
11652void rtl8192_rx_cmd(struct sk_buff *skb)
11653{
11654 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11655 struct net_device *dev = info->dev;
11656 //int ret;
11657// struct urb *rx_urb = info->urb;
11658 /* TODO */
11659 struct ieee80211_rx_stats stats = {
11660 .signal = 0,
11661 .noise = -98,
11662 .rate = 0,
11663 // .mac_time = jiffies,
11664 .freq = IEEE80211_24GHZ_BAND,
11665 };
11666
11667 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE))
11668 {
11669
11670 query_rx_cmdpkt_desc_status(skb,&stats);
11671 // this is to be done by amy 080508 prfd->queue_id = 1;
11672
11673
11674 //
11675 // Process the command packet received.
11676 //
11677
11678 rtl819xusb_process_received_packet(dev,&stats);
11679
11680 dev_kfree_skb_any(skb);
11681 }
11682 else
11683 ;
11684
11685
11686#if 0
11687 desc = (u32*)(skb->data);
11688 cmd = (desc[0] >> 30) & 0x03;
11689
11690 if(cmd == 0x00) {//beacon interrupt
11691 //send beacon packet
11692 skb = ieee80211_get_beacon(priv->ieee80211);
11693
11694 if(!skb){
11695 DMESG("not enought memory for allocating beacon");
11696 return;
11697 }
11698 skb->cb[0] = BEACON_PRIORITY;
11699 skb->cb[1] = 0;
11700 skb->cb[2] = ieeerate2rtlrate(priv->ieee80211->basic_rate);
11701 ret = rtl8192_tx(dev, skb);
11702
11703 if( ret != 0 ){
11704 printk(KERN_ALERT "tx beacon packet error : %d !\n", ret);
11705 }
11706 dev_kfree_skb_any(skb);
11707 } else {//0x00
11708 //{ log the device information
11709 // At present, It is not implemented just now.
11710 //}
11711 }
11712#endif
11713}
11714#endif
11715
11716void rtl8192_irq_rx_tasklet(struct r8192_priv *priv)
11717{
11718 struct sk_buff *skb;
11719 struct rtl8192_rx_info *info;
11720
11721 while (NULL != (skb = skb_dequeue(&priv->skb_queue))) {
11722 info = (struct rtl8192_rx_info *)skb->cb;
11723 switch (info->out_pipe) {
11724 /* Nomal packet pipe */
11725 case 3:
11726 //RT_TRACE(COMP_RECV, "normal in-pipe index(%d)\n",info->out_pipe);
11727 priv->IrpPendingCount--;
11728 priv->ops->rtl819x_rx_nomal(skb);
11729 break;
11730
11731 /* Command packet pipe */
11732 case 9:
11733 RT_TRACE(COMP_RECV, "command in-pipe index(%d)\n",\
11734 info->out_pipe);
11735 priv->ops->rtl819x_rx_cmd(skb);
11736 break;
11737
11738 default: /* should never get here! */
11739 RT_TRACE(COMP_ERR, "Unknown in-pipe index(%d)\n",\
11740 info->out_pipe);
11741 dev_kfree_skb(skb);
11742 break;
11743
11744 }
11745 }
11746}
11747
11748
11749
11750/****************************************************************************
11751 ---------------------------- USB_STUFF---------------------------
11752*****************************************************************************/
5f53d8ca
JC		 11753//LZM Merge from windows HalUsbSetQueuePipeMapping8192SUsb 090319
11754static void HalUsbSetQueuePipeMapping8192SUsb(struct usb_interface *intf, struct net_device *dev)
11755{
11756 struct r8192_priv *priv = ieee80211_priv(dev);
11757 struct usb_host_interface *iface_desc;
11758 struct usb_endpoint_descriptor *endpoint;
11759 u8 i = 0;
11760
11761 priv->ep_in_num = 0;
11762 priv->ep_out_num = 0;
11763 memset(priv->RtOutPipes,0,16);
11764 memset(priv->RtInPipes,0,16);
11765
11766#ifndef USE_ONE_PIPE
11767 iface_desc = intf->cur_altsetting;
11768 priv->ep_num = iface_desc->desc.bNumEndpoints;
11769
11770 for (i = 0; i < priv->ep_num; ++i) {
11771 endpoint = &iface_desc->endpoint[i].desc;
5f53d8ca
JC		 11772 if (usb_endpoint_is_bulk_in(endpoint)) {
11773 priv->RtInPipes[priv->ep_in_num] = usb_endpoint_num(endpoint);
11774 priv->ep_in_num ++;
11775 //printk("in_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
11776 } else if (usb_endpoint_is_bulk_out(endpoint)) {
11777 priv->RtOutPipes[priv->ep_out_num] = usb_endpoint_num(endpoint);
11778 priv->ep_out_num ++;
11779 //printk("out_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
11780 }
5f53d8ca
JC		 11781 }
11782 {
11783 memset(priv->txqueue_to_outpipemap,0,9);
11784 if (priv->ep_num == 6) {
11785 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
11786 u8 queuetopipe[] = {3, 2, 1, 0, 4, 4, 4, 4, 4};
11787
11788 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
11789 } else if (priv->ep_num == 4) {
11790 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
11791 u8 queuetopipe[] = {1, 1, 0, 0, 2, 2, 2, 2, 2};
11792
11793 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
11794 } else if (priv->ep_num > 9) {
11795 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
11796 u8 queuetopipe[] = {3, 2, 1, 0, 4, 8, 7, 6, 5};
11797
11798 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
11799 } else {//use sigle pipe
11800 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
11801 u8 queuetopipe[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
11802 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
11803 }
11804 }
11805 printk("==>ep_num:%d, in_ep_num:%d, out_ep_num:%d\n", priv->ep_num, priv->ep_in_num, priv->ep_out_num);
11806
11807 printk("==>RtInPipes:");
11808 for(i=0; i < priv->ep_in_num; i++)
11809 printk("%d ", priv->RtInPipes[i]);
11810 printk("\n");
11811
11812 printk("==>RtOutPipes:");
11813 for(i=0; i < priv->ep_out_num; i++)
11814 printk("%d ", priv->RtOutPipes[i]);
11815 printk("\n");
11816
11817 printk("==>txqueue_to_outpipemap for BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON:\n");
11818 for(i=0; i < 9; i++)
11819 printk("%d ", priv->txqueue_to_outpipemap[i]);
11820 printk("\n");
11821#else
11822 {
11823 memset(priv->txqueue_to_outpipemap,0,9);
11824 memset(priv->RtOutPipes,4,16);//all use endpoint 4 for out
11825 }
11826#endif
11827
11828 return;
11829}
5f53d8ca 11830
77b92881
BZ		 11831static const struct net_device_ops rtl8192_netdev_ops = {
11832 .ndo_open = rtl8192_open,
11833 .ndo_stop = rtl8192_close,
11834 .ndo_get_stats = rtl8192_stats,
11835 .ndo_tx_timeout = tx_timeout,
11836 .ndo_do_ioctl = rtl8192_ioctl,
11837 .ndo_set_multicast_list = r8192_set_multicast,
11838 .ndo_set_mac_address = r8192_set_mac_adr,
11839 .ndo_validate_addr = eth_validate_addr,
11840 .ndo_change_mtu = eth_change_mtu,
ce9c010c 11841 .ndo_start_xmit = rtl8192_ieee80211_xmit,
77b92881
BZ		 11842};
11843
5f53d8ca
JC		 11844static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
11845 const struct usb_device_id *id)
5f53d8ca
JC		 11846{
11847// unsigned long ioaddr = 0;
11848 struct net_device *dev = NULL;
11849 struct r8192_priv *priv= NULL;
5f53d8ca 11850 struct usb_device *udev = interface_to_usbdev(intf);
1ec9e48d 11851
5f53d8ca
JC		 11852 RT_TRACE(COMP_INIT, "Oops: i'm coming\n");
11853
11854 dev = alloc_ieee80211(sizeof(struct r8192_priv));
11855
5f53d8ca
JC		 11856 usb_set_intfdata(intf, dev);
11857 SET_NETDEV_DEV(dev, &intf->dev);
5f53d8ca 11858 priv = ieee80211_priv(dev);
5f53d8ca 11859 priv->ieee80211 = netdev_priv(dev);
5f53d8ca
JC		 11860 priv->udev=udev;
11861
11862#ifdef RTL8192SU
5f53d8ca 11863 HalUsbSetQueuePipeMapping8192SUsb(intf, dev);
5f53d8ca
JC		 11864#endif
11865
11866#ifdef RTL8192SU
11867 //printk("===============>NIC 8192SU\n");
11868 priv->ops = &rtl8192su_ops;
11869#else
11870 //printk("===============>NIC 8192U\n");
11871 priv->ops = &rtl8192u_ops;
11872#endif
11873
77b92881 11874 dev->netdev_ops = &rtl8192_netdev_ops;
5f53d8ca
JC		 11875
11876 //DMESG("Oops: i'm coming\n");
11877#if WIRELESS_EXT >= 12
11878#if WIRELESS_EXT < 17
11879 dev->get_wireless_stats = r8192_get_wireless_stats;
11880#endif
11881 dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def;
11882#endif
11883 dev->type=ARPHRD_ETHER;
11884
11885 dev->watchdog_timeo = HZ*3; //modified by john, 0805
11886
11887 if (dev_alloc_name(dev, ifname) < 0){
11888 RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n");
11889 ifname = "wlan%d";
11890 dev_alloc_name(dev, ifname);
11891 }
11892
11893 RT_TRACE(COMP_INIT, "Driver probe completed1\n");
11894#if 1
11895 if(rtl8192_init(dev)!=0){
11896 RT_TRACE(COMP_ERR, "Initialization failed");
11897 goto fail;
11898 }
11899#endif
11900 netif_carrier_off(dev);
11901 netif_stop_queue(dev);
11902
11903 register_netdev(dev);
11904 RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name);
11905 rtl8192_proc_init_one(dev);
11906
11907
11908 RT_TRACE(COMP_INIT, "Driver probe completed\n");
5f53d8ca 11909 return 0;
5f53d8ca
JC		 11910fail:
11911 free_ieee80211(dev);
11912
11913 RT_TRACE(COMP_ERR, "wlan driver load failed\n");
5f53d8ca 11914 return -ENODEV;
5f53d8ca
JC		 11915}
11916
11917//detach all the work and timer structure declared or inititialize in r8192U_init function.
11918void rtl8192_cancel_deferred_work(struct r8192_priv* priv)
11919{
5f53d8ca
JC		 11920 cancel_work_sync(&priv->reset_wq);
11921 cancel_work_sync(&priv->qos_activate);
11922 cancel_delayed_work(&priv->watch_dog_wq);
11923 cancel_delayed_work(&priv->update_beacon_wq);
11924 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
11925 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
11926 //cancel_work_sync(&priv->SetBWModeWorkItem);
11927 //cancel_work_sync(&priv->SwChnlWorkItem);
5f53d8ca
JC		 11928}
11929
5f53d8ca 11930static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf)
5f53d8ca 11931{
5f53d8ca 11932 struct net_device *dev = usb_get_intfdata(intf);
5f53d8ca
JC		 11933 struct r8192_priv *priv = ieee80211_priv(dev);
11934 if(dev){
11935
11936 unregister_netdev(dev);
11937
11938 RT_TRACE(COMP_DOWN, "=============>wlan driver to be removed\n");
11939 rtl8192_proc_remove_one(dev);
11940
11941 rtl8192_down(dev);
11942 if (priv->pFirmware)
11943 {
11944 vfree(priv->pFirmware);
11945 priv->pFirmware = NULL;
11946 }
11947 // priv->rf_close(dev);
11948// rtl8192_SetRFPowerState(dev, eRfOff);
5f53d8ca 11949 destroy_workqueue(priv->priv_wq);
5f53d8ca
JC		 11950 //rtl8192_irq_disable(dev);
11951 //rtl8192_reset(dev);
11952 mdelay(10);
11953
11954 }
11955 free_ieee80211(dev);
11956 RT_TRACE(COMP_DOWN, "wlan driver removed\n");
11957}
11958
11959static int __init rtl8192_usb_module_init(void)
11960{
11961 printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n");
11962 printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n");
11963 RT_TRACE(COMP_INIT, "Initializing module");
11964 RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT);
11965 rtl8192_proc_module_init();
11966 return usb_register(&rtl8192_usb_driver);
11967}
11968
11969
11970static void __exit rtl8192_usb_module_exit(void)
11971{
11972 usb_deregister(&rtl8192_usb_driver);
11973
11974 RT_TRACE(COMP_DOWN, "Exiting");
11975 rtl8192_proc_module_remove();
11976}
11977
11978
11979void rtl8192_try_wake_queue(struct net_device *dev, int pri)
11980{
11981 unsigned long flags;
11982 short enough_desc;
11983 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11984
11985 spin_lock_irqsave(&priv->tx_lock,flags);
11986 enough_desc = check_nic_enough_desc(dev,pri);
11987 spin_unlock_irqrestore(&priv->tx_lock,flags);
11988
11989 if(enough_desc)
11990 ieee80211_wake_queue(priv->ieee80211);
11991}
11992
11993#if 0
11994void DisableHWSecurityConfig8192SUsb(struct net_device *dev)
11995{
11996 u8 SECR_value = 0x0;
11997 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
11998}
11999#endif
12000
12001void EnableHWSecurityConfig8192(struct net_device *dev)
12002{
12003 u8 SECR_value = 0x0;
12004 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
12005 struct ieee80211_device* ieee = priv->ieee80211;
12006
12007 SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;
12008#if 1
12009 if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2))
12010 {
12011 SECR_value |= SCR_RxUseDK;
12012 SECR_value |= SCR_TxUseDK;
12013 }
12014 else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP)))
12015 {
12016 SECR_value |= SCR_RxUseDK;
12017 SECR_value |= SCR_TxUseDK;
12018 }
12019#endif
12020 //add HWSec active enable here.
12021//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4
12022
12023 ieee->hwsec_active = 1;
12024
12025 if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off
12026 {
12027 ieee->hwsec_active = 0;
12028 SECR_value &= ~SCR_RxDecEnable;
12029 }
12030
12031 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, \
12032 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
12033 {
12034 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
12035 }
12036}
12037
12038
12039void setKey( struct net_device *dev,
12040 u8 EntryNo,
12041 u8 KeyIndex,
12042 u16 KeyType,
12043 u8 *MacAddr,
12044 u8 DefaultKey,
12045 u32 *KeyContent )
12046{
12047 u32 TargetCommand = 0;
12048 u32 TargetContent = 0;
12049 u16 usConfig = 0;
12050 u8 i;
12051 if (EntryNo >= TOTAL_CAM_ENTRY)
12052 RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n");
12053
12054 RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr));
12055
12056 if (DefaultKey)
12057 usConfig |= BIT15 | (KeyType<<2);
12058 else
12059 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
12060// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex;
12061
12062
12063 for(i=0 ; i<CAM_CONTENT_COUNT; i++){
12064 TargetCommand = i+CAM_CONTENT_COUNT*EntryNo;
12065 TargetCommand |= BIT31|BIT16;
12066
12067 if(i==0){//MAC|Config
12068 TargetContent = (u32)(*(MacAddr+0)) << 16|
12069 (u32)(*(MacAddr+1)) << 24|
12070 (u32)usConfig;
12071
12072 write_nic_dword(dev, WCAMI, TargetContent);
12073 write_nic_dword(dev, RWCAM, TargetCommand);
12074 // printk("setkey cam =%8x\n", read_cam(dev, i+6*EntryNo));
12075 }
12076 else if(i==1){//MAC
12077 TargetContent = (u32)(*(MacAddr+2)) |
12078 (u32)(*(MacAddr+3)) << 8|
12079 (u32)(*(MacAddr+4)) << 16|
12080 (u32)(*(MacAddr+5)) << 24;
12081 write_nic_dword(dev, WCAMI, TargetContent);
12082 write_nic_dword(dev, RWCAM, TargetCommand);
12083 }
12084 else {
12085 //Key Material
12086 if(KeyContent !=NULL){
12087 write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) );
12088 write_nic_dword(dev, RWCAM, TargetCommand);
12089 }
12090 }
12091 }
12092
12093}
12094
12095/***************************************************************************
12096 ------------------- module init / exit stubs ----------------
12097****************************************************************************/
12098module_init(rtl8192_usb_module_init);
12099module_exit(rtl8192_usb_module_exit);
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