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Staging: rtl8187se: cleanup r8180_pm.c
[net-next-2.6.git] / drivers / staging / rtl8187se / r8180_core.c
CommitLineData
c8d86be3
GKH		 1/*
2 This is part of rtl818x pci OpenSource driver - v 0.1
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public License)
5
6 Parts of this driver are based on the GPL part of the official
7 Realtek driver.
8
9 Parts of this driver are based on the rtl8180 driver skeleton
10 from Patric Schenke & Andres Salomon.
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
13
14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
15
16 RSSI calc function from 'The Deuce'
17
18 Some ideas borrowed from the 8139too.c driver included in linux kernel.
19
20 We (I?) want to thanks the Authors of those projecs and also the
21 Ndiswrapper's project Authors.
22
23 A big big thanks goes also to Realtek corp. for their help in my attempt to
24 add RTL8185 and RTL8225 support, and to David Young also.
25*/
26
c8d86be3 27#undef RX_DONT_PASS_UL
c8d86be3 28#undef DUMMY_RX
c8d86be3 29
c8d86be3
GKH		 30#include <linux/syscalls.h>
31//#include <linux/fcntl.h>
32//#include <asm/uaccess.h>
33#include "r8180_hw.h"
34#include "r8180.h"
c8d86be3 35#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
c8d86be3
GKH		 36#include "r8180_93cx6.h" /* Card EEPROM */
37#include "r8180_wx.h"
38#include "r8180_dm.h"
39
c8d86be3 40#include "r8180_pm.h"
c8d86be3 41
fd9b8d6e 42#include "ieee80211/dot11d.h"
c8d86be3 43
c8d86be3
GKH		 44#ifndef PCI_VENDOR_ID_BELKIN
45 #define PCI_VENDOR_ID_BELKIN 0x1799
46#endif
47#ifndef PCI_VENDOR_ID_DLINK
48 #define PCI_VENDOR_ID_DLINK 0x1186
49#endif
50
51static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = {
52 {
53 .vendor = PCI_VENDOR_ID_REALTEK,
54// .device = 0x8180,
55 .device = 0x8199,
56 .subvendor = PCI_ANY_ID,
57 .subdevice = PCI_ANY_ID,
58 .driver_data = 0,
59 },
c8d86be3
GKH		 60 {
61 .vendor = 0,
62 .device = 0,
63 .subvendor = 0,
64 .subdevice = 0,
65 .driver_data = 0,
66 }
67};
68
69
70static char* ifname = "wlan%d";
71static int hwseqnum = 0;
72//static char* ifname = "ath%d";
73static int hwwep = 0;
74static int channels = 0x3fff;
75
76#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
77#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
78MODULE_LICENSE("GPL");
79MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
80MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
81MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards");
82
83
84
85/*
86MODULE_PARM(ifname, "s");
87MODULE_PARM_DESC(devname," Net interface name, wlan%d=default");
88
89MODULE_PARM(hwseqnum,"i");
90MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
91
92MODULE_PARM(hwwep,"i");
93MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
94
95MODULE_PARM(channels,"i");
96MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
97*/
98
c8d86be3
GKH		 99module_param(ifname, charp, S_IRUGO|S_IWUSR );
100module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
101module_param(hwwep,int, S_IRUGO|S_IWUSR);
102module_param(channels,int, S_IRUGO|S_IWUSR);
c8d86be3
GKH		 103
104MODULE_PARM_DESC(devname," Net interface name, wlan%d=default");
105//MODULE_PARM_DESC(devname," Net interface name, ath%d=default");
106MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
107MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
108MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
109
110
111static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
112 const struct pci_device_id *id);
113
114static void __devexit rtl8180_pci_remove(struct pci_dev *pdev);
115
116static void rtl8180_shutdown (struct pci_dev *pdev)
117{
118 struct net_device *dev = pci_get_drvdata(pdev);
727ae303
AB		 119 if (dev->netdev_ops->ndo_stop)
120 dev->netdev_ops->ndo_stop(dev);
c8d86be3
GKH		 121 pci_disable_device(pdev);
122}
123
124static struct pci_driver rtl8180_pci_driver = {
125 .name = RTL8180_MODULE_NAME, /* Driver name */
126 .id_table = rtl8180_pci_id_tbl, /* PCI_ID table */
127 .probe = rtl8180_pci_probe, /* probe fn */
128 .remove = __devexit_p(rtl8180_pci_remove),/* remove fn */
c8d86be3
GKH		 129 .suspend = rtl8180_suspend, /* PM suspend fn */
130 .resume = rtl8180_resume, /* PM resume fn */
c8d86be3
GKH		 131 .shutdown = rtl8180_shutdown,
132};
133
134
135
c8d86be3
GKH		 136
137u8 read_nic_byte(struct net_device *dev, int x)
138{
139 return 0xff&readb((u8*)dev->mem_start +x);
140}
141
142u32 read_nic_dword(struct net_device *dev, int x)
143{
144 return readl((u8*)dev->mem_start +x);
145}
146
147u16 read_nic_word(struct net_device *dev, int x)
148{
149 return readw((u8*)dev->mem_start +x);
150}
151
152void write_nic_byte(struct net_device *dev, int x,u8 y)
153{
154 writeb(y,(u8*)dev->mem_start +x);
155 udelay(20);
156}
157
158void write_nic_dword(struct net_device *dev, int x,u32 y)
159{
160 writel(y,(u8*)dev->mem_start +x);
161 udelay(20);
162}
163
164void write_nic_word(struct net_device *dev, int x,u16 y)
165{
166 writew(y,(u8*)dev->mem_start +x);
167 udelay(20);
168}
169
c8d86be3
GKH		 170
171
172
173
174
175inline void force_pci_posting(struct net_device *dev)
176{
177 read_nic_byte(dev,EPROM_CMD);
c8d86be3 178 mb();
c8d86be3
GKH		 179}
180
181
182irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs);
183void set_nic_rxring(struct net_device *dev);
184void set_nic_txring(struct net_device *dev);
185static struct net_device_stats *rtl8180_stats(struct net_device *dev);
186void rtl8180_commit(struct net_device *dev);
187void rtl8180_start_tx_beacon(struct net_device *dev);
188
189/****************************************************************************
190 -----------------------------PROCFS STUFF-------------------------
191*****************************************************************************/
192
193static struct proc_dir_entry *rtl8180_proc = NULL;
194
195static int proc_get_registers(char *page, char **start,
196 off_t offset, int count,
197 int *eof, void *data)
198{
199 struct net_device *dev = data;
200// struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
201
202 int len = 0;
203 int i,n;
204
205 int max=0xff;
206
207 /* This dump the current register page */
208 for(n=0;n<=max;)
209 {
210 //printk( "\nD: %2x> ", n);
211 len += snprintf(page + len, count - len,
212 "\nD: %2x > ",n);
213
214 for(i=0;i<16 && n<=max;i++,n++)
215 len += snprintf(page + len, count - len,
216 "%2x ",read_nic_byte(dev,n));
217
218 // printk("%2x ",read_nic_byte(dev,n));
219 }
220 len += snprintf(page + len, count - len,"\n");
221
222
223
224 *eof = 1;
225 return len;
226
227}
228
229int get_curr_tx_free_desc(struct net_device *dev, int priority);
230
231static int proc_get_stats_hw(char *page, char **start,
232 off_t offset, int count,
233 int *eof, void *data)
234{
235 //struct net_device *dev = data;
236 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
237
238 int len = 0;
c8d86be3 239
c8d86be3
GKH		 240 *eof = 1;
241 return len;
242}
243
244
245static int proc_get_stats_rx(char *page, char **start,
246 off_t offset, int count,
247 int *eof, void *data)
248{
249 struct net_device *dev = data;
250 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
251
252 int len = 0;
253
254 len += snprintf(page + len, count - len,
255 /* "RX descriptor not available: %lu\n"
256 "RX incomplete (missing last descriptor): %lu\n"
257 "RX not data: %lu\n"
258 //"RX descriptor pointer reset: %lu\n"
259 "RX descriptor pointer lost: %lu\n"
260 //"RX pointer workaround: %lu\n"
261 "RX error int: %lu\n"
262 "RX fifo overflow: %lu\n"
263 "RX int: %lu\n"
264 "RX packet: %lu\n"
265 "RX bytes: %lu\n"
266 "RX DMA fail: %lu\n",
267 priv->stats.rxrdu,
268 priv->stats.rxnolast,
269 priv->stats.rxnodata,
270 //priv->stats.rxreset,
271 priv->stats.rxnopointer,
272 //priv->stats.rxwrkaround,
273 priv->stats.rxerr,
274 priv->stats.rxoverflow,
275 priv->stats.rxint,
276 priv->ieee80211->stats.rx_packets,
277 priv->ieee80211->stats.rx_bytes,
278 priv->stats.rxdmafail */
279 "RX OK: %lu\n"
280 "RX Retry: %lu\n"
281 "RX CRC Error(0-500): %lu\n"
282 "RX CRC Error(500-1000): %lu\n"
283 "RX CRC Error(>1000): %lu\n"
284 "RX ICV Error: %lu\n",
285 priv->stats.rxint,
286 priv->stats.rxerr,
287 priv->stats.rxcrcerrmin,
288 priv->stats.rxcrcerrmid,
289 priv->stats.rxcrcerrmax,
290 priv->stats.rxicverr
291 );
292
293 *eof = 1;
294 return len;
295}
296
c8d86be3
GKH		 297static int proc_get_stats_tx(char *page, char **start,
298 off_t offset, int count,
299 int *eof, void *data)
300{
301 struct net_device *dev = data;
302 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
303
304 int len = 0;
305 unsigned long totalOK;
306
307 totalOK=priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
308 len += snprintf(page + len, count - len,
309 /* "TX normal priority ok int: %lu\n"
310 "TX normal priority error int: %lu\n"
311 "TX high priority ok int: %lu\n"
312 "TX high priority failed error int: %lu\n"
313 "TX low priority ok int: %lu\n"
314 "TX low priority failed error int: %lu\n"
315 "TX bytes: %lu\n"
316 "TX packets: %lu\n"
317 "TX queue resume: %lu\n"
318 "TX queue stopped?: %d\n"
319 "TX fifo overflow: %lu\n"
320 //"SW TX stop: %lu\n"
321 //"SW TX wake: %lu\n"
322 "TX beacon: %lu\n"
323 "TX beacon aborted: %lu\n",
324 priv->stats.txnpokint,
325 priv->stats.txnperr,
326 priv->stats.txhpokint,
327 priv->stats.txhperr,
328 priv->stats.txlpokint,
329 priv->stats.txlperr,
330 priv->ieee80211->stats.tx_bytes,
331 priv->ieee80211->stats.tx_packets,
332 priv->stats.txresumed,
333 netif_queue_stopped(dev),
334 priv->stats.txoverflow,
335 //priv->ieee80211->ieee_stats.swtxstop,
336 //priv->ieee80211->ieee_stats.swtxawake,
337 priv->stats.txbeacon,
338 priv->stats.txbeaconerr */
339 "TX OK: %lu\n"
340 "TX Error: %lu\n"
341 "TX Retry: %lu\n"
342 "TX beacon OK: %lu\n"
343 "TX beacon error: %lu\n",
344 totalOK,
345 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
346 priv->stats.txretry,
347 priv->stats.txbeacon,
348 priv->stats.txbeaconerr
349 );
350
351 *eof = 1;
352 return len;
353}
354
c8d86be3
GKH		 355void rtl8180_proc_module_init(void)
356{
357 DMESG("Initializing proc filesystem");
c8d86be3 358 rtl8180_proc=create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net);
c8d86be3
GKH		 359}
360
361
362void rtl8180_proc_module_remove(void)
363{
c8d86be3 364 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
c8d86be3
GKH		 365}
366
367
368void rtl8180_proc_remove_one(struct net_device *dev)
369{
370 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
371 if (priv->dir_dev) {
372 remove_proc_entry("stats-hw", priv->dir_dev);
373 remove_proc_entry("stats-tx", priv->dir_dev);
374 remove_proc_entry("stats-rx", priv->dir_dev);
375// remove_proc_entry("stats-ieee", priv->dir_dev);
376// remove_proc_entry("stats-ap", priv->dir_dev);
377 remove_proc_entry("registers", priv->dir_dev);
378 remove_proc_entry(dev->name, rtl8180_proc);
379 priv->dir_dev = NULL;
380 }
381}
382
383
384void rtl8180_proc_init_one(struct net_device *dev)
385{
386 struct proc_dir_entry *e;
387 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
be286fd2 388 priv->dir_dev = rtl8180_proc;
c8d86be3 389 if (!priv->dir_dev) {
be286fd2 390 DMESGE("Unable to initialize /proc/net/r8180/%s\n",
c8d86be3
GKH		 391 dev->name);
392 return;
393 }
394
395 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
396 priv->dir_dev, proc_get_stats_hw, dev);
397
398 if (!e) {
399 DMESGE("Unable to initialize "
be286fd2 400 "/proc/net/r8180/%s/stats-hw\n",
c8d86be3
GKH		 401 dev->name);
402 }
403
404 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
405 priv->dir_dev, proc_get_stats_rx, dev);
406
407 if (!e) {
408 DMESGE("Unable to initialize "
be286fd2 409 "/proc/net/r8180/%s/stats-rx\n",
c8d86be3
GKH		 410 dev->name);
411 }
412
413
414 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
415 priv->dir_dev, proc_get_stats_tx, dev);
416
417 if (!e) {
418 DMESGE("Unable to initialize "
be286fd2 419 "/proc/net/r8180/%s/stats-tx\n",
c8d86be3
GKH		 420 dev->name);
421 }
c8d86be3
GKH		 422
423 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
424 priv->dir_dev, proc_get_registers, dev);
425
426 if (!e) {
427 DMESGE("Unable to initialize "
be286fd2 428 "/proc/net/r8180/%s/registers\n",
c8d86be3
GKH		 429 dev->name);
430 }
431}
432/****************************************************************************
433 -----------------------------MISC STUFF-------------------------
434*****************************************************************************/
435/*
436 FIXME: check if we can use some standard already-existent
437 data type+functions in kernel
438*/
439
440short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
441 struct buffer **bufferhead)
442{
c8d86be3
GKH		 443 struct buffer *tmp;
444
445 if(! *buffer){
446
447 *buffer = kmalloc(sizeof(struct buffer),GFP_KERNEL);
448
449 if (*buffer == NULL) {
450 DMESGE("Failed to kmalloc head of TX/RX struct");
451 return -1;
452 }
453 (*buffer)->next=*buffer;
454 (*buffer)->buf=buf;
455 (*buffer)->dma=dma;
456 if(bufferhead !=NULL)
457 (*bufferhead) = (*buffer);
458 return 0;
459 }
460 tmp=*buffer;
461
462 while(tmp->next!=(*buffer)) tmp=tmp->next;
463 if ((tmp->next= kmalloc(sizeof(struct buffer),GFP_KERNEL)) == NULL){
464 DMESGE("Failed to kmalloc TX/RX struct");
465 return -1;
466 }
467 tmp->next->buf=buf;
468 tmp->next->dma=dma;
469 tmp->next->next=*buffer;
470
471 return 0;
472}
473
474
475void buffer_free(struct net_device *dev,struct buffer **buffer,int len,short
476consistent)
477{
478
479 struct buffer *tmp,*next;
480 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
481 struct pci_dev *pdev=priv->pdev;
482 //int i;
483
484 if(! *buffer) return;
485
486 /*for(tmp=*buffer; tmp->next != *buffer; tmp=tmp->next)
487
488 */
489 tmp=*buffer;
490 do{
491 next=tmp->next;
492 if(consistent){
493 pci_free_consistent(pdev,len,
494 tmp->buf,tmp->dma);
495 }else{
496 pci_unmap_single(pdev, tmp->dma,
497 len,PCI_DMA_FROMDEVICE);
498 kfree(tmp->buf);
499 }
500 kfree(tmp);
501 tmp = next;
502 }
503 while(next != *buffer);
504
505 *buffer=NULL;
506}
507
508
509void print_buffer(u32 *buffer, int len)
510{
511 int i;
512 u8 *buf =(u8*)buffer;
513
514 printk("ASCII BUFFER DUMP (len: %x):\n",len);
515
516 for(i=0;i<len;i++)
517 printk("%c",buf[i]);
518
519 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
520
521 for(i=0;i<len;i++)
522 printk("%02x",buf[i]);
523
524 printk("\n");
525}
526
527
528int get_curr_tx_free_desc(struct net_device *dev, int priority)
529{
530 struct r8180_priv *priv = ieee80211_priv(dev);
531 u32* tail;
532 u32* head;
533 int ret;
534
535 switch (priority){
536 case MANAGE_PRIORITY:
537 head = priv->txmapringhead;
538 tail = priv->txmapringtail;
539 break;
540 case BK_PRIORITY:
541 head = priv->txbkpringhead;
542 tail = priv->txbkpringtail;
543 break;
544 case BE_PRIORITY:
545 head = priv->txbepringhead;
546 tail = priv->txbepringtail;
547 break;
548 case VI_PRIORITY:
549 head = priv->txvipringhead;
550 tail = priv->txvipringtail;
551 break;
552 case VO_PRIORITY:
553 head = priv->txvopringhead;
554 tail = priv->txvopringtail;
555 break;
556 case HI_PRIORITY:
557 head = priv->txhpringhead;
558 tail = priv->txhpringtail;
559 break;
560 default:
561 return -1;
562 }
563
564 //DMESG("%x %x", head, tail);
565
566 /* FIXME FIXME FIXME FIXME */
567
c8d86be3
GKH		 568 if( head <= tail )
569 ret = priv->txringcount - (tail - head)/8;
570 else
571 ret = (head - tail)/8;
572
573 if(ret > priv->txringcount ) DMESG("BUG");
574 return ret;
c8d86be3
GKH		 575}
576
577
578short check_nic_enought_desc(struct net_device *dev, int priority)
579{
580 struct r8180_priv *priv = ieee80211_priv(dev);
581 struct ieee80211_device *ieee = netdev_priv(dev);
582
583 int requiredbyte, required;
584 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
585
586 if(ieee->current_network.QoS_Enable) {
587 requiredbyte += 2;
588 };
589
590 required = requiredbyte / (priv->txbuffsize-4);
591 if (requiredbyte % priv->txbuffsize) required++;
592 /* for now we keep two free descriptor as a safety boundary
593 * between the tail and the head
594 */
595
596 return (required+2 < get_curr_tx_free_desc(dev,priority));
597}
598
c8d86be3
GKH		 599void fix_tx_fifo(struct net_device *dev)
600{
601 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
602 u32 *tmp;
603 int i;
ff954853 604
c8d86be3
GKH		 605 for (tmp=priv->txmapring, i=0;
606 i < priv->txringcount;
607 tmp+=8, i++){
608 *tmp = *tmp &~ (1<<31);
609 }
610
611 for (tmp=priv->txbkpring, i=0;
612 i < priv->txringcount;
613 tmp+=8, i++) {
614 *tmp = *tmp &~ (1<<31);
615 }
616
617 for (tmp=priv->txbepring, i=0;
618 i < priv->txringcount;
619 tmp+=8, i++){
620 *tmp = *tmp &~ (1<<31);
621 }
622 for (tmp=priv->txvipring, i=0;
623 i < priv->txringcount;
624 tmp+=8, i++) {
625 *tmp = *tmp &~ (1<<31);
626 }
627
628 for (tmp=priv->txvopring, i=0;
629 i < priv->txringcount;
630 tmp+=8, i++){
631 *tmp = *tmp &~ (1<<31);
632 }
633
634 for (tmp=priv->txhpring, i=0;
635 i < priv->txringcount;
636 tmp+=8,i++){
637 *tmp = *tmp &~ (1<<31);
638 }
639
640 for (tmp=priv->txbeaconring, i=0;
641 i < priv->txbeaconcount;
642 tmp+=8, i++){
643 *tmp = *tmp &~ (1<<31);
644 }
ff954853 645
c8d86be3
GKH		 646 priv->txmapringtail = priv->txmapring;
647 priv->txmapringhead = priv->txmapring;
648 priv->txmapbufstail = priv->txmapbufs;
649
650 priv->txbkpringtail = priv->txbkpring;
651 priv->txbkpringhead = priv->txbkpring;
652 priv->txbkpbufstail = priv->txbkpbufs;
653
654 priv->txbepringtail = priv->txbepring;
655 priv->txbepringhead = priv->txbepring;
656 priv->txbepbufstail = priv->txbepbufs;
657
658 priv->txvipringtail = priv->txvipring;
659 priv->txvipringhead = priv->txvipring;
660 priv->txvipbufstail = priv->txvipbufs;
661
662 priv->txvopringtail = priv->txvopring;
663 priv->txvopringhead = priv->txvopring;
664 priv->txvopbufstail = priv->txvopbufs;
665
666 priv->txhpringtail = priv->txhpring;
667 priv->txhpringhead = priv->txhpring;
668 priv->txhpbufstail = priv->txhpbufs;
669
670 priv->txbeaconringtail = priv->txbeaconring;
671 priv->txbeaconbufstail = priv->txbeaconbufs;
672 set_nic_txring(dev);
673
674 ieee80211_reset_queue(priv->ieee80211);
675 priv->ack_tx_to_ieee = 0;
676}
677
678
679void fix_rx_fifo(struct net_device *dev)
680{
681 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
682 u32 *tmp;
683 struct buffer *rxbuf;
684 u8 rx_desc_size;
685
c8d86be3 686 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 687
c8d86be3
GKH		 688 for (tmp=priv->rxring, rxbuf=priv->rxbufferhead;
689 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
690 tmp+=rx_desc_size,rxbuf=rxbuf->next){
691 *(tmp+2) = rxbuf->dma;
692 *tmp=*tmp &~ 0xfff;
693 *tmp=*tmp | priv->rxbuffersize;
694 *tmp |= (1<<31);
695 }
696
c8d86be3
GKH		 697 priv->rxringtail=priv->rxring;
698 priv->rxbuffer=priv->rxbufferhead;
699 priv->rx_skb_complete=1;
700 set_nic_rxring(dev);
701}
702
703
704/****************************************************************************
705 ------------------------------HW STUFF---------------------------
706*****************************************************************************/
707
708unsigned char QUALITY_MAP[] = {
709 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61,
710 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c,
711 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f,
712 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29,
713 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
714 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20,
715 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e,
716 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19,
717 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f,
718 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00
719};
720
721unsigned char STRENGTH_MAP[] = {
722 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
723 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
724 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
725 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
726 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
727 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
728 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
729 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
730 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
731 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
732};
733
734void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual){
735 //void Mlme_UpdateRssiSQ(struct net_device *dev, u8 *rssi, u8 *qual){
736 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
737 u32 temp;
738 u32 temp2;
739 u32 temp3;
740 u32 lsb;
741 u32 q;
742 u32 orig_qual;
743 u8 _rssi;
744
745 q = *qual;
746 orig_qual = *qual;
747 _rssi = 0; // avoid gcc complains..
748
749 if (q <= 0x4e) {
750 temp = QUALITY_MAP[q];
751 } else {
752 if( q & 0x80 ) {
753 temp = 0x32;
754 } else {
755 temp = 1;
756 }
757 }
758
759 *qual = temp;
760 temp2 = *rssi;
761
762 switch(priv->rf_chip){
763 case RFCHIPID_RFMD:
764 lsb = temp2 & 1;
765 temp2 &= 0x7e;
766 if ( !lsb || !(temp2 <= 0x3c) ) {
767 temp2 = 0x64;
768 } else {
769 temp2 = 100 * temp2 / 0x3c;
770 }
771 *rssi = temp2 & 0xff;
772 _rssi = temp2 & 0xff;
773 break;
774 case RFCHIPID_INTERSIL:
775 lsb = temp2;
776 temp2 &= 0xfffffffe;
777 temp2 *= 251;
778 temp3 = temp2;
779 temp2 <<= 6;
780 temp3 += temp2;
781 temp3 <<= 1;
782 temp2 = 0x4950df;
783 temp2 -= temp3;
784 lsb &= 1;
785 if ( temp2 <= 0x3e0000 ) {
786 if ( temp2 < 0xffef0000 )
787 temp2 = 0xffef0000;
788 } else {
789 temp2 = 0x3e0000;
790 }
791 if ( !lsb ) {
792 temp2 -= 0xf0000;
793 } else {
794 temp2 += 0xf0000;
795 }
796
797 temp3 = 0x4d0000;
798 temp3 -= temp2;
799 temp3 *= 100;
800 temp3 = temp3 / 0x6d;
801 temp3 >>= 0x10;
802 _rssi = temp3 & 0xff;
803 *rssi = temp3 & 0xff;
804 break;
805 case RFCHIPID_GCT:
806 lsb = temp2 & 1;
807 temp2 &= 0x7e;
808 if ( ! lsb || !(temp2 <= 0x3c) ){
809 temp2 = 0x64;
810 } else {
811 temp2 = (100 * temp2) / 0x3c;
812 }
813 *rssi = temp2 & 0xff;
814 _rssi = temp2 & 0xff;
815 break;
816 case RFCHIPID_PHILIPS:
817 if( orig_qual <= 0x4e ){
818 _rssi = STRENGTH_MAP[orig_qual];
819 *rssi = _rssi;
820 } else {
821 orig_qual -= 0x80;
822 if ( !orig_qual ){
823 _rssi = 1;
824 *rssi = 1;
825 } else {
826 _rssi = 0x32;
827 *rssi = 0x32;
828 }
829 }
830 break;
831
832 /* case 4 */
833 case RFCHIPID_MAXIM:
834 lsb = temp2 & 1;
835 temp2 &= 0x7e;
836 temp2 >>= 1;
837 temp2 += 0x42;
838 if( lsb != 0 ){
839 temp2 += 0xa;
840 }
841 *rssi = temp2 & 0xff;
842 _rssi = temp2 & 0xff;
843 break;
844 }
845
846 if ( _rssi < 0x64 ){
847 if ( _rssi == 0 ) {
848 *rssi = 1;
849 }
850 } else {
851 *rssi = 0x64;
852 }
853
854 return;
855}
856
857
858void rtl8180_irq_enable(struct net_device *dev)
859{
860 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
861 priv->irq_enabled = 1;
862/*
863 write_nic_word(dev,INTA_MASK,INTA_RXOK | INTA_RXDESCERR | INTA_RXOVERFLOW |\
864 INTA_TXOVERFLOW | INTA_HIPRIORITYDESCERR | INTA_HIPRIORITYDESCOK |\
865 INTA_NORMPRIORITYDESCERR | INTA_NORMPRIORITYDESCOK |\
866 INTA_LOWPRIORITYDESCERR | INTA_LOWPRIORITYDESCOK | INTA_TIMEOUT);
867*/
868 write_nic_word(dev,INTA_MASK, priv->irq_mask);
869}
870
871
872void rtl8180_irq_disable(struct net_device *dev)
873{
874 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
875
c8d86be3 876 write_nic_dword(dev,IMR,0);
c8d86be3
GKH		 877 force_pci_posting(dev);
878 priv->irq_enabled = 0;
879}
880
881
882void rtl8180_set_mode(struct net_device *dev,int mode)
883{
884 u8 ecmd;
885 ecmd=read_nic_byte(dev, EPROM_CMD);
886 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
887 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
888 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
889 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
890 write_nic_byte(dev, EPROM_CMD, ecmd);
891}
892
893void rtl8180_adapter_start(struct net_device *dev);
894void rtl8180_beacon_tx_enable(struct net_device *dev);
895
896void rtl8180_update_msr(struct net_device *dev)
897{
898 struct r8180_priv *priv = ieee80211_priv(dev);
899 u8 msr;
900 u32 rxconf;
901
902 msr = read_nic_byte(dev, MSR);
903 msr &= ~ MSR_LINK_MASK;
904
905 rxconf=read_nic_dword(dev,RX_CONF);
906
907 if(priv->ieee80211->state == IEEE80211_LINKED)
908 {
909 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
910 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
911 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
912 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
913 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
914 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
915 else
916 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
917 rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
918
919 }else {
920 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
921 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
922 }
923
924 write_nic_byte(dev, MSR, msr);
925 write_nic_dword(dev, RX_CONF, rxconf);
926
927}
928
929
930
931void rtl8180_set_chan(struct net_device *dev,short ch)
932{
933 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
934
935 if((ch > 14) || (ch < 1))
936 {
d599edca 937 printk("In %s: Invalid chnanel %d\n", __func__, ch);
c8d86be3
GKH		 938 return;
939 }
940
941 priv->chan=ch;
d599edca 942 //printk("in %s:channel is %d\n",__func__,ch);
c8d86be3
GKH		 943 priv->rf_set_chan(dev,priv->chan);
944
945}
946
947
948void rtl8180_rx_enable(struct net_device *dev)
949{
950 u8 cmd;
951 u32 rxconf;
952 /* for now we accept data, management & ctl frame*/
953 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
954
955 rxconf=read_nic_dword(dev,RX_CONF);
956 rxconf = rxconf &~ MAC_FILTER_MASK;
957 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
958 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
959 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
960 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
961// rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
962 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
963
964 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
965 dev->flags & IFF_PROMISC){
966 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
967 }else{
968 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
969 if(priv->card_8185 == 0)
970 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
971 }
972
973 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
974 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
975 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
976 }*/
977
978 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
979 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
980 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
981 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
982 }
983
984 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
985 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
986
987 //if(!priv->card_8185){
988 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
989 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
990 //}
991
992 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
993 rxconf = rxconf &~ MAX_RX_DMA_MASK;
994 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
995
996 //if(!priv->card_8185)
997 rxconf = rxconf | RCR_ONLYERLPKT;
998
999 rxconf = rxconf &~ RCR_CS_MASK;
1000 if(!priv->card_8185)
1001 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
1002// rxconf &=~ 0xfff00000;
1003// rxconf |= 0x90100000;//9014f76f;
1004 write_nic_dword(dev, RX_CONF, rxconf);
1005
1006 fix_rx_fifo(dev);
1007
c8d86be3
GKH		 1008 cmd=read_nic_byte(dev,CMD);
1009 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
1010
1011 /* In rtl8139 driver seems that DMA threshold has to be written
1012 * after enabling RX, so we rewrite RX_CONFIG register
1013 */
1014 //mdelay(100);
1015// write_nic_dword(dev, RX_CONF, rxconf);
1016
1017}
1018
1019
1020void set_nic_txring(struct net_device *dev)
1021{
1022 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1023// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1024
1025 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
1026// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1027 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
1028// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1029 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
1030// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1031 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
1032// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1033 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
1034// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1035 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
1036// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
1037
1038 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
1039}
1040
1041
1042void rtl8180_conttx_enable(struct net_device *dev)
1043{
1044 u32 txconf;
1045 txconf = read_nic_dword(dev,TX_CONF);
1046 txconf = txconf &~ TX_LOOPBACK_MASK;
1047 txconf = txconf | (TX_LOOPBACK_CONTINUE <<TX_LOOPBACK_SHIFT);
1048 write_nic_dword(dev,TX_CONF,txconf);
1049}
1050
1051
1052void rtl8180_conttx_disable(struct net_device *dev)
1053{
1054 u32 txconf;
1055 txconf = read_nic_dword(dev,TX_CONF);
1056 txconf = txconf &~ TX_LOOPBACK_MASK;
1057 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
1058 write_nic_dword(dev,TX_CONF,txconf);
1059}
1060
1061
1062void rtl8180_tx_enable(struct net_device *dev)
1063{
1064 u8 cmd;
1065 u8 tx_agc_ctl;
1066 u8 byte;
1067 u32 txconf;
1068 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1069 txconf= read_nic_dword(dev,TX_CONF);
1070
1071
1072 if(priv->card_8185){
1073
1074
1075 byte = read_nic_byte(dev,CW_CONF);
1076 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
1077 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
1078 write_nic_byte(dev, CW_CONF, byte);
1079
1080 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
1081 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
1082 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
1083 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
1084 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
1085 /*
1086 write_nic_word(dev, 0x5e, 0x01);
1087 force_pci_posting(dev);
1088 mdelay(1);
1089 write_nic_word(dev, 0xfe, 0x10);
1090 force_pci_posting(dev);
1091 mdelay(1);
1092 write_nic_word(dev, 0x5e, 0x00);
1093 force_pci_posting(dev);
1094 mdelay(1);
1095 */
1096 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
1097 }
1098
1099 if(priv->card_8185){
1100
1101 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
1102
1103 }else{
1104
1105 if(hwseqnum)
1106 txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
1107 else
1108 txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
1109 }
1110
1111 txconf = txconf &~ TX_LOOPBACK_MASK;
1112 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
1113 txconf = txconf &~ TCR_DPRETRY_MASK;
1114 txconf = txconf &~ TCR_RTSRETRY_MASK;
1115 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
1116 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
1117 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
1118
1119 if(priv->card_8185){
1120 if(priv->hw_plcp_len)
1121 txconf = txconf &~ TCR_PLCP_LEN;
1122 else
1123 txconf = txconf | TCR_PLCP_LEN;
1124 }else{
1125 txconf = txconf &~ TCR_SAT;
1126 }
1127 txconf = txconf &~ TCR_MXDMA_MASK;
1128 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
1129 txconf = txconf | TCR_CWMIN;
1130 txconf = txconf | TCR_DISCW;
1131
1132// if(priv->ieee80211->hw_wep)
1133// txconf=txconf &~ (1<<TX_NOICV_SHIFT);
1134// else
1135 txconf=txconf | (1<<TX_NOICV_SHIFT);
1136
1137 write_nic_dword(dev,TX_CONF,txconf);
1138
1139
1140 fix_tx_fifo(dev);
1141
c8d86be3
GKH		 1142 cmd=read_nic_byte(dev,CMD);
1143 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1144
1145// mdelay(100);
1146 write_nic_dword(dev,TX_CONF,txconf);
1147// #endif
1148/*
1149 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
1150 write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
1151 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1152 */
1153}
1154
1155
1156void rtl8180_beacon_tx_enable(struct net_device *dev)
1157{
1158 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1159
1160 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1161 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
1162 write_nic_byte(dev,TPPollStop, priv->dma_poll_mask);
c8d86be3
GKH		 1163 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1164}
1165
1166
1167void rtl8180_beacon_tx_disable(struct net_device *dev)
1168{
1169 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1170
1171 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1172 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
1173 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1174 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1175
1176}
1177
1178
1179void rtl8180_rtx_disable(struct net_device *dev)
1180{
1181 u8 cmd;
1182 struct r8180_priv *priv = ieee80211_priv(dev);
1183
1184 cmd=read_nic_byte(dev,CMD);
1185 write_nic_byte(dev, CMD, cmd &~ \
1186 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
1187 force_pci_posting(dev);
1188 mdelay(10);
1189 /*while (read_nic_byte(dev,CMD) & (1<<CMD_RX_ENABLE_SHIFT))
1190 udelay(10);
1191 */
1192
1193 if(!priv->rx_skb_complete)
1194 dev_kfree_skb_any(priv->rx_skb);
1195}
1196
c8d86be3
GKH		 1197short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
1198 int addr)
1199{
1200 int i;
1201 u32 *desc;
1202 u32 *tmp;
1203 dma_addr_t dma_desc, dma_tmp;
1204 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1205 struct pci_dev *pdev = priv->pdev;
1206 void *buf;
1207
1208 if((bufsize & 0xfff) != bufsize) {
1209 DMESGE ("TX buffer allocation too large");
1210 return 0;
1211 }
1212 desc = (u32*)pci_alloc_consistent(pdev,
1213 sizeof(u32)*8*count+256, &dma_desc);
1214 if(desc==NULL) return -1;
1215 if(dma_desc & 0xff){
1216
1217 /*
1218 * descriptor's buffer must be 256 byte aligned
1219 * we shouldn't be here, since we set DMA mask !
1220 */
be286fd2 1221 WARN(1, "DMA buffer is not aligned\n");
c8d86be3
GKH		 1222 }
1223 tmp=desc;
1224 for (i=0;i<count;i++)
1225 {
1226 buf = (void*)pci_alloc_consistent(pdev,bufsize,&dma_tmp);
1227 if (buf == NULL) return -ENOMEM;
1228
1229 switch(addr) {
c8d86be3
GKH		 1230 case TX_MANAGEPRIORITY_RING_ADDR:
1231 if(-1 == buffer_add(&(priv->txmapbufs),buf,dma_tmp,NULL)){
1232 DMESGE("Unable to allocate mem for buffer NP");
1233 return -ENOMEM;
1234 }
1235 break;
1236
1237 case TX_BKPRIORITY_RING_ADDR:
1238 if(-1 == buffer_add(&(priv->txbkpbufs),buf,dma_tmp,NULL)){
1239 DMESGE("Unable to allocate mem for buffer LP");
1240 return -ENOMEM;
1241 }
1242 break;
1243 case TX_BEPRIORITY_RING_ADDR:
1244 if(-1 == buffer_add(&(priv->txbepbufs),buf,dma_tmp,NULL)){
1245 DMESGE("Unable to allocate mem for buffer NP");
1246 return -ENOMEM;
1247 }
1248 break;
1249
1250 case TX_VIPRIORITY_RING_ADDR:
1251 if(-1 == buffer_add(&(priv->txvipbufs),buf,dma_tmp,NULL)){
1252 DMESGE("Unable to allocate mem for buffer LP");
1253 return -ENOMEM;
1254 }
1255 break;
1256 case TX_VOPRIORITY_RING_ADDR:
1257 if(-1 == buffer_add(&(priv->txvopbufs),buf,dma_tmp,NULL)){
1258 DMESGE("Unable to allocate mem for buffer NP");
1259 return -ENOMEM;
1260 }
1261 break;
c8d86be3
GKH		 1262 case TX_HIGHPRIORITY_RING_ADDR:
1263 if(-1 == buffer_add(&(priv->txhpbufs),buf,dma_tmp,NULL)){
1264 DMESGE("Unable to allocate mem for buffer HP");
1265 return -ENOMEM;
1266 }
1267 break;
1268 case TX_BEACON_RING_ADDR:
1269 if(-1 == buffer_add(&(priv->txbeaconbufs),buf,dma_tmp,NULL)){
1270 DMESGE("Unable to allocate mem for buffer BP");
1271 return -ENOMEM;
1272 }
1273 break;
1274 }
1275 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1276 *(tmp+2) = (u32)dma_tmp;
1277 *(tmp+3) = bufsize;
1278
1279 if(i+1<count)
1280 *(tmp+4) = (u32)dma_desc+((i+1)*8*4);
1281 else
1282 *(tmp+4) = (u32)dma_desc;
1283
1284 tmp=tmp+8;
1285 }
1286
1287 switch(addr) {
1288 case TX_MANAGEPRIORITY_RING_ADDR:
1289 priv->txmapringdma=dma_desc;
1290 priv->txmapring=desc;
1291 break;
1292
1293 case TX_BKPRIORITY_RING_ADDR:
1294 priv->txbkpringdma=dma_desc;
1295 priv->txbkpring=desc;
1296 break;
1297
1298 case TX_BEPRIORITY_RING_ADDR:
1299 priv->txbepringdma=dma_desc;
1300 priv->txbepring=desc;
1301 break;
1302
1303 case TX_VIPRIORITY_RING_ADDR:
1304 priv->txvipringdma=dma_desc;
1305 priv->txvipring=desc;
1306 break;
1307
1308 case TX_VOPRIORITY_RING_ADDR:
1309 priv->txvopringdma=dma_desc;
1310 priv->txvopring=desc;
1311 break;
1312
1313 case TX_HIGHPRIORITY_RING_ADDR:
1314 priv->txhpringdma=dma_desc;
1315 priv->txhpring=desc;
1316 break;
1317
1318 case TX_BEACON_RING_ADDR:
1319 priv->txbeaconringdma=dma_desc;
1320 priv->txbeaconring=desc;
1321 break;
1322
1323 }
1324
c8d86be3
GKH		 1325 return 0;
1326}
1327
1328
1329void free_tx_desc_rings(struct net_device *dev)
1330{
1331
1332 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1333 struct pci_dev *pdev=priv->pdev;
1334 int count = priv->txringcount;
1335
1336 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1337 priv->txmapring, priv->txmapringdma);
1338 buffer_free(dev,&(priv->txmapbufs),priv->txbuffsize,1);
1339
1340 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1341 priv->txbkpring, priv->txbkpringdma);
1342 buffer_free(dev,&(priv->txbkpbufs),priv->txbuffsize,1);
1343
1344 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1345 priv->txbepring, priv->txbepringdma);
1346 buffer_free(dev,&(priv->txbepbufs),priv->txbuffsize,1);
1347
1348 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1349 priv->txvipring, priv->txvipringdma);
1350 buffer_free(dev,&(priv->txvipbufs),priv->txbuffsize,1);
1351
1352 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1353 priv->txvopring, priv->txvopringdma);
1354 buffer_free(dev,&(priv->txvopbufs),priv->txbuffsize,1);
1355
1356 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1357 priv->txhpring, priv->txhpringdma);
1358 buffer_free(dev,&(priv->txhpbufs),priv->txbuffsize,1);
1359
1360 count = priv->txbeaconcount;
1361 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1362 priv->txbeaconring, priv->txbeaconringdma);
1363 buffer_free(dev,&(priv->txbeaconbufs),priv->txbuffsize,1);
1364}
1365
c8d86be3
GKH		 1366void free_rx_desc_ring(struct net_device *dev)
1367{
1368 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1369 struct pci_dev *pdev = priv->pdev;
1370
1371 int count = priv->rxringcount;
1372
c8d86be3
GKH		 1373 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1374 priv->rxring, priv->rxringdma);
c8d86be3
GKH		 1375
1376 buffer_free(dev,&(priv->rxbuffer),priv->rxbuffersize,0);
1377}
1378
1379
1380short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
1381{
1382 int i;
1383 u32 *desc;
1384 u32 *tmp;
1385 dma_addr_t dma_desc,dma_tmp;
1386 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1387 struct pci_dev *pdev=priv->pdev;
1388 void *buf;
1389 u8 rx_desc_size;
1390
c8d86be3 1391 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3
GKH		 1392
1393 if((bufsize & 0xfff) != bufsize){
1394 DMESGE ("RX buffer allocation too large");
1395 return -1;
1396 }
1397
1398 desc = (u32*)pci_alloc_consistent(pdev,sizeof(u32)*rx_desc_size*count+256,
1399 &dma_desc);
1400
1401 if(dma_desc & 0xff){
1402
1403 /*
1404 * descriptor's buffer must be 256 byte aligned
1405 * should never happen since we specify the DMA mask
1406 */
be286fd2 1407 WARN(1, "DMA buffer is not aligned\n");
c8d86be3
GKH		 1408 }
1409
1410 priv->rxring=desc;
1411 priv->rxringdma=dma_desc;
1412 tmp=desc;
1413
1414 for (i=0;i<count;i++){
1415
1416 if ((buf= kmalloc(bufsize * sizeof(u8),GFP_ATOMIC)) == NULL){
1417 DMESGE("Failed to kmalloc RX buffer");
1418 return -1;
1419 }
1420
1421 dma_tmp = pci_map_single(pdev,buf,bufsize * sizeof(u8),
1422 PCI_DMA_FROMDEVICE);
1423
c8d86be3
GKH		 1424 //buf = (void*)pci_alloc_consistent(pdev,bufsize,&dma_tmp);
1425 if(-1 == buffer_add(&(priv->rxbuffer), buf,dma_tmp,
1426 &(priv->rxbufferhead))){
1427 DMESGE("Unable to allocate mem RX buf");
1428 return -1;
1429 }
1430 *tmp = 0; //zero pads the header of the descriptor
1431 *tmp = *tmp |( bufsize&0xfff);
1432 *(tmp+2) = (u32)dma_tmp;
1433 *tmp = *tmp |(1<<31); // descriptor void, owned by the NIC
1434
c8d86be3
GKH		 1435 tmp=tmp+rx_desc_size;
1436 }
1437
1438 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor
1439
c8d86be3
GKH		 1440 return 0;
1441}
1442
1443
1444void set_nic_rxring(struct net_device *dev)
1445{
1446 u8 pgreg;
1447 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1448
1449 //rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
1450
1451 pgreg=read_nic_byte(dev, PGSELECT);
1452 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
1453
1454 //rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
1455
1456 write_nic_dword(dev, RXRING_ADDR,priv->rxringdma);
1457}
1458
1459
1460void rtl8180_reset(struct net_device *dev)
1461{
1462 //u32 txconf = 0x80e00707; //FIXME: Make me understandable
1463 u8 cr;
1464
1465 //write_nic_dword(dev,TX_CONF,txconf);
1466
1467 rtl8180_irq_disable(dev);
1468
1469 cr=read_nic_byte(dev,CMD);
1470 cr = cr & 2;
1471 cr = cr | (1<<CMD_RST_SHIFT);
1472 write_nic_byte(dev,CMD,cr);
1473
1474 force_pci_posting(dev);
1475
1476 mdelay(200);
1477
1478 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1479 DMESGW("Card reset timeout!");
1480 else
1481 DMESG("Card successfully reset");
1482
1483//#ifndef CONFIG_RTL8185B
1484 rtl8180_set_mode(dev,EPROM_CMD_LOAD);
1485 force_pci_posting(dev);
1486 mdelay(200);
1487//#endif
1488}
1489
1490inline u16 ieeerate2rtlrate(int rate)
1491{
1492 switch(rate){
1493 case 10:
1494 return 0;
1495 case 20:
1496 return 1;
1497 case 55:
1498 return 2;
1499 case 110:
1500 return 3;
1501 case 60:
1502 return 4;
1503 case 90:
1504 return 5;
1505 case 120:
1506 return 6;
1507 case 180:
1508 return 7;
1509 case 240:
1510 return 8;
1511 case 360:
1512 return 9;
1513 case 480:
1514 return 10;
1515 case 540:
1516 return 11;
1517 default:
1518 return 3;
1519
1520 }
1521}
1522
1523static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540,720};
1524inline u16 rtl8180_rate2rate(short rate)
1525{
1526 if (rate >12) return 10;
1527 return rtl_rate[rate];
1528}
1529inline u8 rtl8180_IsWirelessBMode(u16 rate)
1530{
1531 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
1532 return 1;
1533 else return 0;
1534}
1535u16 N_DBPSOfRate(u16 DataRate);
1536u16 ComputeTxTime(
1537 u16 FrameLength,
1538 u16 DataRate,
1539 u8 bManagementFrame,
1540 u8 bShortPreamble
1541)
1542{
1543 u16 FrameTime;
1544 u16 N_DBPS;
1545 u16 Ceiling;
1546
1547 if( rtl8180_IsWirelessBMode(DataRate) )
1548 {
1549 if( bManagementFrame || !bShortPreamble || DataRate == 10 )
1550 { // long preamble
1551 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
1552 }
1553 else
1554 { // Short preamble
1555 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
1556 }
1557 if( ( FrameLength*8 % (DataRate/10) ) != 0 ) //Get the Ceilling
1558 FrameTime ++;
1559 } else { //802.11g DSSS-OFDM PLCP length field calculation.
1560 N_DBPS = N_DBPSOfRate(DataRate);
1561 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
1562 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
1563 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
1564 }
1565 return FrameTime;
1566}
1567u16 N_DBPSOfRate(u16 DataRate)
1568{
1569 u16 N_DBPS = 24;
1570
1571 switch(DataRate)
1572 {
1573 case 60:
1574 N_DBPS = 24;
1575 break;
1576
1577 case 90:
1578 N_DBPS = 36;
1579 break;
1580
1581 case 120:
1582 N_DBPS = 48;
1583 break;
1584
1585 case 180:
1586 N_DBPS = 72;
1587 break;
1588
1589 case 240:
1590 N_DBPS = 96;
1591 break;
1592
1593 case 360:
1594 N_DBPS = 144;
1595 break;
1596
1597 case 480:
1598 N_DBPS = 192;
1599 break;
1600
1601 case 540:
1602 N_DBPS = 216;
1603 break;
1604
1605 default:
1606 break;
1607 }
1608
1609 return N_DBPS;
1610}
1611
1612//{by amy 080312
1613//
1614// Description:
1615// For Netgear case, they want good-looking singal strength.
1616// 2004.12.05, by rcnjko.
1617//
1618long
1619NetgearSignalStrengthTranslate(
1620 long LastSS,
1621 long CurrSS
1622 )
1623{
1624 long RetSS;
1625
1626 // Step 1. Scale mapping.
1627 if(CurrSS >= 71 && CurrSS <= 100)
1628 {
1629 RetSS = 90 + ((CurrSS - 70) / 3);
1630 }
1631 else if(CurrSS >= 41 && CurrSS <= 70)
1632 {
1633 RetSS = 78 + ((CurrSS - 40) / 3);
1634 }
1635 else if(CurrSS >= 31 && CurrSS <= 40)
1636 {
1637 RetSS = 66 + (CurrSS - 30);
1638 }
1639 else if(CurrSS >= 21 && CurrSS <= 30)
1640 {
1641 RetSS = 54 + (CurrSS - 20);
1642 }
1643 else if(CurrSS >= 5 && CurrSS <= 20)
1644 {
1645 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
1646 }
1647 else if(CurrSS == 4)
1648 {
1649 RetSS = 36;
1650 }
1651 else if(CurrSS == 3)
1652 {
1653 RetSS = 27;
1654 }
1655 else if(CurrSS == 2)
1656 {
1657 RetSS = 18;
1658 }
1659 else if(CurrSS == 1)
1660 {
1661 RetSS = 9;
1662 }
1663 else
1664 {
1665 RetSS = CurrSS;
1666 }
1667 //RT_TRACE(COMP_DBG, DBG_LOUD, ("##### After Mapping: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS));
1668
1669 // Step 2. Smoothing.
1670 if(LastSS > 0)
1671 {
1672 RetSS = ((LastSS * 5) + (RetSS)+ 5) / 6;
1673 }
1674 //RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$$$ After Smoothing: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS));
1675
1676 return RetSS;
1677}
1678//
1679// Description:
1680// Translate 0-100 signal strength index into dBm.
1681//
1682long
1683TranslateToDbm8185(
1684 u8 SignalStrengthIndex // 0-100 index.
1685 )
1686{
1687 long SignalPower; // in dBm.
1688
1689 // Translate to dBm (x=0.5y-95).
1690 SignalPower = (long)((SignalStrengthIndex + 1) >> 1);
1691 SignalPower -= 95;
1692
1693 return SignalPower;
1694}
1695//
1696// Description:
1697// Perform signal smoothing for dynamic mechanism.
1698// This is different with PerformSignalSmoothing8185 in smoothing fomula.
1699// No dramatic adjustion is apply because dynamic mechanism need some degree
1700// of correctness. Ported from 8187B.
1701// 2007-02-26, by Bruce.
1702//
1703void
1704PerformUndecoratedSignalSmoothing8185(
1705 struct r8180_priv *priv,
1706 bool bCckRate
1707 )
1708{
1709
1710
1711 // Determin the current packet is CCK rate.
1712 priv->bCurCCKPkt = bCckRate;
1713
1714 if(priv->UndecoratedSmoothedSS >= 0)
1715 {
1716 priv->UndecoratedSmoothedSS = ( (priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10) ) / 6;
1717 }
1718 else
1719 {
1720 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10;
1721 }
1722
1723 priv->UndercorateSmoothedRxPower = ( (priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower* 11)) / 60;
1724
1725// printk("Sommthing SignalSterngth (%d) => UndecoratedSmoothedSS (%d)\n", priv->SignalStrength, priv->UndecoratedSmoothedSS);
1726// printk("Sommthing RxPower (%d) => UndecoratedRxPower (%d)\n", priv->RxPower, priv->UndercorateSmoothedRxPower);
1727
1728 //if(priv->CurCCKRSSI >= 0 && bCckRate)
1729 if(bCckRate)
1730 {
1731 priv->CurCCKRSSI = priv->RSSI;
1732 }
1733 else
1734 {
1735 priv->CurCCKRSSI = 0;
1736 }
1737
1738 // Boundary checking.
1739 // TODO: The overflow condition does happen, if we want to fix,
1740 // we shall recalculate thresholds first.
1741 if(priv->UndecoratedSmoothedSS > 100)
1742 {
1743// printk("UndecoratedSmoothedSS(%d) overflow, SignalStrength(%d)\n", priv->UndecoratedSmoothedSS, priv->SignalStrength);
1744 }
1745 if(priv->UndecoratedSmoothedSS < 0)
1746 {
1747// printk("UndecoratedSmoothedSS(%d) underflow, SignalStrength(%d)\n", priv->UndecoratedSmoothedSS, priv->SignalStrength);
1748 }
1749
1750}
1751
1752//by amy 080312}
1753
1754/* This is rough RX isr handling routine*/
1755void rtl8180_rx(struct net_device *dev)
1756{
1757 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1758 struct sk_buff *tmp_skb;
1759
1760 //struct sk_buff *skb;
1761 short first,last;
1762 u32 len;
1763 int lastlen;
1764 unsigned char quality, signal;
1765 u8 rate;
1766 //u32 *prism_hdr;
1767 u32 *tmp,*tmp2;
1768 u8 rx_desc_size;
1769 u8 padding;
1770 //u32 count=0;
1771 char rxpower = 0;
1772 u32 RXAGC = 0;
1773 long RxAGC_dBm = 0;
1774 u8 LNA=0, BB=0;
1775 u8 LNA_gain[4]={02, 17, 29, 39};
1776 u8 Antenna = 0;
1777 struct ieee80211_hdr *hdr;//by amy
1778 u16 fc,type;
1779 u8 bHwError = 0,bCRC = 0,bICV = 0;
1780 //bHwError = 0;
1781 //bCRC = 0;
1782 //bICV = 0;
1783 bool bCckRate = false;
1784 u8 RSSI = 0;
1785 long SignalStrengthIndex = 0;//+by amy 080312
1786// u8 SignalStrength = 0;
1787 struct ieee80211_rx_stats stats = {
1788 .signal = 0,
1789 .noise = -98,
1790 .rate = 0,
1791 // .mac_time = jiffies,
1792 .freq = IEEE80211_24GHZ_BAND,
1793 };
1794
c8d86be3
GKH		 1795 stats.nic_type = NIC_8185B;
1796 rx_desc_size = 8;
1797
c8d86be3
GKH		 1798 //printk("receive frame!%d\n",count++);
1799 //if (!priv->rxbuffer) DMESG ("EE: NIC RX ack, but RX queue corrupted!");
1800 //else {
1801
1802 if ((*(priv->rxringtail)) & (1<<31)) {
1803
1804 /* we have got an RX int, but the descriptor
1805 * we are pointing is empty*/
1806
1807 priv->stats.rxnodata++;
1808 priv->ieee80211->stats.rx_errors++;
1809
1810 /* if (! *(priv->rxring) & (1<<31)) {
1811
1812 priv->stats.rxreset++;
1813 priv->rxringtail=priv->rxring;
1814 priv->rxbuffer=priv->rxbufferhead;
1815
1816 }else{*/
1817
c8d86be3
GKH		 1818 tmp2 = NULL;
1819 tmp = priv->rxringtail;
1820 do{
1821 if(tmp == priv->rxring)
1822 //tmp = priv->rxring + (priv->rxringcount )*rx_desc_size; xiong-2006-11-15
1823 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size;
1824 else
1825 tmp -= rx_desc_size;
1826
1827 if(! (*tmp & (1<<31)))
1828 tmp2 = tmp;
1829 }while(tmp != priv->rxring);
1830
1831 if(tmp2) priv->rxringtail = tmp2;
c8d86be3
GKH		 1832 //}
1833 }
1834
1835 /* while there are filled descriptors */
1836 while(!(*(priv->rxringtail) & (1<<31))){
1837 if(*(priv->rxringtail) & (1<<26))
1838 DMESGW("RX buffer overflow");
1839 if(*(priv->rxringtail) & (1<<12))
1840 priv->stats.rxicverr++;
1841
1842 if(*(priv->rxringtail) & (1<<27)){
1843 priv->stats.rxdmafail++;
1844 //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail);
1845 goto drop;
1846 }
1847
1848 pci_dma_sync_single_for_cpu(priv->pdev,
1849 priv->rxbuffer->dma,
1850 priv->rxbuffersize * \
1851 sizeof(u8),
1852 PCI_DMA_FROMDEVICE);
1853
1854 first = *(priv->rxringtail) & (1<<29) ? 1:0;
1855 if(first) priv->rx_prevlen=0;
1856
1857 last = *(priv->rxringtail) & (1<<28) ? 1:0;
1858 if(last){
1859 lastlen=((*priv->rxringtail) &0xfff);
1860
1861 /* if the last descriptor (that should
1862 * tell us the total packet len) tell
1863 * us something less than the descriptors
1864 * len we had until now, then there is some
1865 * problem..
1866 * workaround to prevent kernel panic
1867 */
1868 if(lastlen < priv->rx_prevlen)
1869 len=0;
1870 else
1871 len=lastlen-priv->rx_prevlen;
1872
1873 if(*(priv->rxringtail) & (1<<13)) {
1874//lastlen=((*priv->rxringtail) &0xfff);
1875 if ((*(priv->rxringtail) & 0xfff) <500)
1876 priv->stats.rxcrcerrmin++;
1877 else if ((*(priv->rxringtail) & 0x0fff) >1000)
1878 priv->stats.rxcrcerrmax++;
1879 else
1880 priv->stats.rxcrcerrmid++;
1881
1882 }
1883
1884 }else{
1885 len = priv->rxbuffersize;
1886 }
1887
c8d86be3
GKH		 1888 if(first && last) {
1889 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1890 }else if(first) {
1891 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1892 if(padding) {
1893 len -= 2;
1894 }
1895 }else {
1896 padding = 0;
1897 }
c8d86be3 1898 padding = 0;
c8d86be3
GKH		 1899 priv->rx_prevlen+=len;
1900
1901 if(priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100){
1902 /* HW is probably passing several buggy frames
1903 * without FD or LD flag set.
1904 * Throw this garbage away to prevent skb
1905 * memory exausting
1906 */
1907 if(!priv->rx_skb_complete)
1908 dev_kfree_skb_any(priv->rx_skb);
1909 priv->rx_skb_complete = 1;
1910 }
1911
c8d86be3
GKH		 1912 signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16);
1913 signal=(signal&0xfe)>>1; // Modify by hikaru 6.6
1914
1915 quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff));
1916
1917 stats.mac_time[0] = *(priv->rxringtail+1);
1918 stats.mac_time[1] = *(priv->rxringtail+2);
1919 rxpower =((char)(((*(priv->rxringtail+4))& (0x00ff0000))>>16))/2 - 42;
1920 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>> 8)) & (0x7f);
1921
c8d86be3
GKH		 1922 rate=((*(priv->rxringtail)) &
1923 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20;
1924
1925 stats.rate = rtl8180_rate2rate(rate);
1926 //DMESG("%d",rate);
1927 Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ;
1928// printk("in rtl8180_rx():Antenna is %d\n",Antenna);
1929//by amy for antenna
1930 if(!rtl8180_IsWirelessBMode(stats.rate))
1931 { // OFDM rate.
1932
1933 RxAGC_dBm = rxpower+1; //bias
1934 }
1935 else
1936 { // CCK rate.
1937 RxAGC_dBm = signal;//bit 0 discard
1938
1939 LNA = (u8) (RxAGC_dBm & 0x60 ) >> 5 ; //bit 6~ bit 5
1940 BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0
1941
1942 RxAGC_dBm = -( LNA_gain[LNA] + (BB *2) ); //Pin_11b=-(LNA_gain+BB_gain) (dBm)
1943
1944 RxAGC_dBm +=4; //bias
1945 }
1946
1947 if(RxAGC_dBm & 0x80) //absolute value
1948 RXAGC= ~(RxAGC_dBm)+1;
1949 bCckRate = rtl8180_IsWirelessBMode(stats.rate);
1950 // Translate RXAGC into 1-100.
1951 if(!rtl8180_IsWirelessBMode(stats.rate))
1952 { // OFDM rate.
1953 if(RXAGC>90)
1954 RXAGC=90;
1955 else if(RXAGC<25)
1956 RXAGC=25;
1957 RXAGC=(90-RXAGC)*100/65;
1958 }
1959 else
1960 { // CCK rate.
1961 if(RXAGC>95)
1962 RXAGC=95;
1963 else if(RXAGC<30)
1964 RXAGC=30;
1965 RXAGC=(95-RXAGC)*100/65;
1966 }
1967 priv->SignalStrength = (u8)RXAGC;
1968 priv->RecvSignalPower = RxAGC_dBm ; // It can use directly by SD3 CMLin
1969 priv->RxPower = rxpower;
1970 priv->RSSI = RSSI;
1971//{by amy 080312
1972 // SQ translation formular is provided by SD3 DZ. 2006.06.27, by rcnjko.
1973 if(quality >= 127)
1974 quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now;
1975 else if(quality < 27)
1976 quality = 100;
1977 else
1978 quality = 127 - quality;
1979 priv->SignalQuality = quality;
1980 if(!priv->card_8185)
1981 printk("check your card type\n");
1982
1983 stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength;
1984 stats.signalstrength = RXAGC;
1985 if(stats.signalstrength > 100)
1986 stats.signalstrength = 100;
1987 stats.signalstrength = (stats.signalstrength * 70)/100 + 30;
1988 // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength);
1989 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality;
1990 stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual;
1991//by amy 080312}
1992 bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 )
1993 | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 );
1994 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13;
1995 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12;
1996 hdr = (struct ieee80211_hdr *)priv->rxbuffer->buf;
1997 fc = le16_to_cpu(hdr->frame_ctl);
1998 type = WLAN_FC_GET_TYPE(fc);
1999
2000 if((IEEE80211_FTYPE_CTL != type) &&
2001 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
2002 && (!bHwError) && (!bCRC)&& (!bICV))
2003 {
2004//by amy 080312
2005 // Perform signal smoothing for dynamic mechanism on demand.
2006 // This is different with PerformSignalSmoothing8185 in smoothing fomula.
2007 // No dramatic adjustion is apply because dynamic mechanism need some degree
2008 // of correctness. 2007.01.23, by shien chang.
2009 PerformUndecoratedSignalSmoothing8185(priv,bCckRate);
2010 //
2011 // For good-looking singal strength.
2012 //
2013 SignalStrengthIndex = NetgearSignalStrengthTranslate(
2014 priv->LastSignalStrengthInPercent,
2015 priv->SignalStrength);
2016
2017 priv->LastSignalStrengthInPercent = SignalStrengthIndex;
2018 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex);
2019 //
2020 // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified,
2021 // so we record the correct power here.
2022 //
2023 priv->Stats_SignalQuality =(long) (priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6;
2024 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower -1) / 6;
2025
2026 // Figure out which antenna that received the lasted packet.
2027 priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main.
2028//by amy 080312
2029 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength);
2030 }
2031
2032//by amy for antenna
2033
2034
2035
2036
2037
2038
2039#ifndef DUMMY_RX
2040 if(first){
2041 if(!priv->rx_skb_complete){
2042 /* seems that HW sometimes fails to reiceve and
2043 doesn't provide the last descriptor */
c8d86be3
GKH		 2044 dev_kfree_skb_any(priv->rx_skb);
2045 priv->stats.rxnolast++;
c8d86be3
GKH		 2046 }
2047 /* support for prism header has been originally added by Christian */
2048 if(priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2049
c8d86be3
GKH		 2050 }else{
2051 priv->rx_skb = dev_alloc_skb(len+2);
2052 if( !priv->rx_skb) goto drop;
c8d86be3
GKH		 2053 }
2054
2055 priv->rx_skb_complete=0;
2056 priv->rx_skb->dev=dev;
2057 }else{
2058 /* if we are here we should have already RXed
2059 * the first frame.
2060 * If we get here and the skb is not allocated then
2061 * we have just throw out garbage (skb not allocated)
2062 * and we are still rxing garbage....
2063 */
2064 if(!priv->rx_skb_complete){
2065
2066 tmp_skb= dev_alloc_skb(priv->rx_skb->len +len+2);
2067
2068 if(!tmp_skb) goto drop;
2069
2070 tmp_skb->dev=dev;
c8d86be3 2071
c8d86be3
GKH		 2072 memcpy(skb_put(tmp_skb,priv->rx_skb->len),
2073 priv->rx_skb->data,
2074 priv->rx_skb->len);
c8d86be3
GKH		 2075
2076 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH		 2077
2078 priv->rx_skb=tmp_skb;
2079 }
2080 }
ff954853 2081
c8d86be3 2082 if(!priv->rx_skb_complete) {
c8d86be3
GKH		 2083 if(padding) {
2084 memcpy(skb_put(priv->rx_skb,len),
2085 (((unsigned char *)priv->rxbuffer->buf) + 2),len);
2086 } else {
c8d86be3
GKH		 2087 memcpy(skb_put(priv->rx_skb,len),
2088 priv->rxbuffer->buf,len);
c8d86be3 2089 }
c8d86be3 2090 }
c8d86be3
GKH		 2091
2092 if(last && !priv->rx_skb_complete){
c8d86be3
GKH		 2093 if(priv->rx_skb->len > 4)
2094 skb_trim(priv->rx_skb,priv->rx_skb->len-4);
c8d86be3
GKH		 2095#ifndef RX_DONT_PASS_UL
2096 if(!ieee80211_rx(priv->ieee80211,
2097 priv->rx_skb, &stats)){
c8d86be3
GKH		 2098#endif // RX_DONT_PASS_UL
2099
2100 dev_kfree_skb_any(priv->rx_skb);
2101#ifndef RX_DONT_PASS_UL
2102 }
c8d86be3
GKH		 2103#endif
2104 priv->rx_skb_complete=1;
2105 }
2106
2107#endif //DUMMY_RX
2108
2109 pci_dma_sync_single_for_device(priv->pdev,
2110 priv->rxbuffer->dma,
2111 priv->rxbuffersize * \
2112 sizeof(u8),
2113 PCI_DMA_FROMDEVICE);
2114
2115
2116drop: // this is used when we have not enought mem
2117
2118 /* restore the descriptor */
2119 *(priv->rxringtail+2)=priv->rxbuffer->dma;
2120 *(priv->rxringtail)=*(priv->rxringtail) &~ 0xfff;
2121 *(priv->rxringtail)=
2122 *(priv->rxringtail) | priv->rxbuffersize;
2123
2124 *(priv->rxringtail)=
2125 *(priv->rxringtail) | (1<<31);
2126 //^empty descriptor
2127
2128 //wmb();
2129
c8d86be3
GKH		 2130 //unsigned long flags;
2131 //spin_lock_irqsave(&priv->irq_lock,flags);
2132
2133 priv->rxringtail+=rx_desc_size;
2134 if(priv->rxringtail >=
2135 (priv->rxring)+(priv->rxringcount )*rx_desc_size)
2136 priv->rxringtail=priv->rxring;
2137
2138 //spin_unlock_irqrestore(&priv->irq_lock,flags);
2139
2140
2141 priv->rxbuffer=(priv->rxbuffer->next);
2142
2143 }
2144
2145
2146
2147// if(get_curr_tx_free_desc(dev,priority))
2148// ieee80211_sta_ps_sleep(priv->ieee80211, &tmp, &tmp2);
2149
2150
2151
2152}
2153
2154
2155void rtl8180_dma_kick(struct net_device *dev, int priority)
2156{
2157 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2158
2159 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2160/*
2161
2162 switch(priority){
2163
2164 case LOW_PRIORITY:
2165
2166 write_nic_byte(dev,TX_DMA_POLLING,
2167 (1<< TX_DMA_POLLING_LOWPRIORITY_SHIFT) |
2168 priv->dma_poll_mask);
2169 break;
2170
2171 case NORM_PRIORITY:
2172
2173 write_nic_byte(dev,TX_DMA_POLLING,
2174 (1<< TX_DMA_POLLING_NORMPRIORITY_SHIFT) |
2175 priv->dma_poll_mask);
2176 break;
2177
2178 case HI_PRIORITY:
2179
2180 write_nic_byte(dev,TX_DMA_POLLING,
2181 (1<< TX_DMA_POLLING_HIPRIORITY_SHIFT) |
2182 priv->dma_poll_mask);
2183 break;
2184
2185 }
2186*/
2187 write_nic_byte(dev, TX_DMA_POLLING,
2188 (1 << (priority + 1)) | priv->dma_poll_mask);
2189 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2190
2191 force_pci_posting(dev);
2192}
2193
c8d86be3
GKH		 2194void rtl8180_data_hard_stop(struct net_device *dev)
2195{
2196 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2197
2198 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 2199 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ;
2200 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 2201 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2202}
2203
2204
2205void rtl8180_data_hard_resume(struct net_device *dev)
2206{
2207 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2208
2209 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 2210 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ);
2211 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 2212 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2213}
2214
2215
2216/* this function TX data frames when the ieee80211 stack requires this.
2217 * It checks also if we need to stop the ieee tx queue, eventually do it
2218 */
2219void rtl8180_hard_data_xmit(struct sk_buff *skb,struct net_device *dev, int
2220rate)
2221{
2222 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2223 int mode;
2224 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data;
2225 short morefrag = (h->frame_ctl) & IEEE80211_FCTL_MOREFRAGS;
2226 unsigned long flags;
2227 int priority;
2228 //static int count = 0;
2229
2230 mode = priv->ieee80211->iw_mode;
2231
2232 rate = ieeerate2rtlrate(rate);
2233 /*
2234 * This function doesn't require lock because we make
2235 * sure it's called with the tx_lock already acquired.
2236 * this come from the kernel's hard_xmit callback (trought
2237 * the ieee stack, or from the try_wake_queue (again trought
2238 * the ieee stack.
2239 */
c8d86be3 2240 priority = AC2Q(skb->priority);
c8d86be3
GKH		 2241 spin_lock_irqsave(&priv->tx_lock,flags);
2242
2243 if(priv->ieee80211->bHwRadioOff)
2244 {
2245 spin_unlock_irqrestore(&priv->tx_lock,flags);
2246
2247 return;
2248 }
2249
2250 //printk(KERN_WARNING "priority = %d@%d\n", priority, count++);
2251 if (!check_nic_enought_desc(dev, priority)){
2252 //DMESG("Error: no descriptor left by previous TX (avail %d) ",
2253 // get_curr_tx_free_desc(dev, priority));
2254 DMESGW("Error: no descriptor left by previous TX (avail %d) ",
2255 get_curr_tx_free_desc(dev, priority));
2256 //printk(KERN_WARNING "==============================================================> \n");
2257 ieee80211_stop_queue(priv->ieee80211);
2258 }
2259 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag,0,rate);
2260 if (!check_nic_enought_desc(dev, priority))
2261 ieee80211_stop_queue(priv->ieee80211);
2262
2263 //dev_kfree_skb_any(skb);
2264 spin_unlock_irqrestore(&priv->tx_lock,flags);
2265
2266}
2267
2268/* This is a rough attempt to TX a frame
2269 * This is called by the ieee 80211 stack to TX management frames.
2270 * If the ring is full packet are dropped (for data frame the queue
2271 * is stopped before this can happen). For this reason it is better
2272 * if the descriptors are larger than the largest management frame
2273 * we intend to TX: i'm unsure what the HW does if it will not found
2274 * the last fragment of a frame because it has been dropped...
2275 * Since queues for Management and Data frames are different we
2276 * might use a different lock than tx_lock (for example mgmt_tx_lock)
2277 */
2278/* these function may loops if invoked with 0 descriptors or 0 len buffer*/
2279int rtl8180_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
2280{
2281 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2282
2283 unsigned long flags;
2284
2285 int priority;
2286
c8d86be3 2287 priority = MANAGE_PRIORITY;
c8d86be3
GKH		 2288
2289 spin_lock_irqsave(&priv->tx_lock,flags);
2290
2291 if(priv->ieee80211->bHwRadioOff)
2292 {
2293 spin_unlock_irqrestore(&priv->tx_lock,flags);
2294
2295 dev_kfree_skb_any(skb);
ec634fe3 2296 return NETDEV_TX_OK;
c8d86be3
GKH		 2297 }
2298
2299 rtl8180_tx(dev, skb->data, skb->len, priority,
2300 0, 0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
2301
2302 priv->ieee80211->stats.tx_bytes+=skb->len;
2303 priv->ieee80211->stats.tx_packets++;
2304 spin_unlock_irqrestore(&priv->tx_lock,flags);
2305
2306 dev_kfree_skb_any(skb);
ec634fe3 2307 return NETDEV_TX_OK;
c8d86be3
GKH		 2308}
2309
2310// longpre 144+48 shortpre 72+24
2311u16 rtl8180_len2duration(u32 len, short rate,short* ext)
2312{
2313 u16 duration;
2314 u16 drift;
2315 *ext=0;
2316
2317 switch(rate){
2318 case 0://1mbps
2319 *ext=0;
2320 duration = ((len+4)<<4) /0x2;
2321 drift = ((len+4)<<4) % 0x2;
2322 if(drift ==0 ) break;
2323 duration++;
2324 break;
2325
2326 case 1://2mbps
2327 *ext=0;
2328 duration = ((len+4)<<4) /0x4;
2329 drift = ((len+4)<<4) % 0x4;
2330 if(drift ==0 ) break;
2331 duration++;
2332 break;
2333
2334 case 2: //5.5mbps
2335 *ext=0;
2336 duration = ((len+4)<<4) /0xb;
2337 drift = ((len+4)<<4) % 0xb;
2338 if(drift ==0 )
2339 break;
2340 duration++;
2341 break;
2342
2343 default:
2344 case 3://11mbps
2345 *ext=0;
2346 duration = ((len+4)<<4) /0x16;
2347 drift = ((len+4)<<4) % 0x16;
2348 if(drift ==0 )
2349 break;
2350 duration++;
2351 if(drift > 6)
2352 break;
2353 *ext=1;
2354 break;
2355 }
2356
2357 return duration;
2358}
2359
2360
2361void rtl8180_prepare_beacon(struct net_device *dev)
2362{
2363
2364 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2365
2366 struct sk_buff *skb;
2367
2368 u16 word = read_nic_word(dev, BcnItv);
2369 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
2370 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval);//0x64;
2371 write_nic_word(dev, BcnItv, word);
2372
2373
2374 skb = ieee80211_get_beacon(priv->ieee80211);
2375 if(skb){
2376 rtl8180_tx(dev,skb->data,skb->len,BEACON_PRIORITY,
2377 0,0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
2378 dev_kfree_skb_any(skb);
2379 }
c8d86be3
GKH		 2380}
2381
2382/* This function do the real dirty work: it enqueues a TX command
2383 * descriptor in the ring buffer, copyes the frame in a TX buffer
2384 * and kicks the NIC to ensure it does the DMA transfer.
2385 */
2386short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority,
2387 short morefrag, short descfrag, int rate)
2388{
2389 struct r8180_priv *priv = ieee80211_priv(dev);
2390 u32 *tail,*temp_tail;
2391 u32 *begin;
2392 u32 *buf;
2393 int i;
2394 int remain;
2395 int buflen;
2396 int count;
2397 //u16 AckCtsTime;
2398 //u16 FrameTime;
2399 u16 duration;
2400 short ext;
2401 struct buffer* buflist;
2402 //unsigned long flags;
c8d86be3
GKH		 2403 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf;
2404 u8 dest[ETH_ALEN];
2405 u8 bUseShortPreamble = 0;
2406 u8 bCTSEnable = 0;
2407 u8 bRTSEnable = 0;
2408 //u16 RTSRate = 22;
2409 //u8 RetryLimit = 0;
2410 u16 Duration = 0;
2411 u16 RtsDur = 0;
2412 u16 ThisFrameTime = 0;
2413 u16 TxDescDuration = 0;
2414 u8 ownbit_flag = false; //added by david woo for sync Tx, 2007.12.14
c8d86be3
GKH		 2415
2416 switch(priority) {
2417 case MANAGE_PRIORITY:
2418 tail=priv->txmapringtail;
2419 begin=priv->txmapring;
2420 buflist = priv->txmapbufstail;
2421 count = priv->txringcount;
2422 break;
2423
2424 case BK_PRIORITY:
2425 tail=priv->txbkpringtail;
2426 begin=priv->txbkpring;
2427 buflist = priv->txbkpbufstail;
2428 count = priv->txringcount;
2429 break;
2430
2431 case BE_PRIORITY:
2432 tail=priv->txbepringtail;
2433 begin=priv->txbepring;
2434 buflist = priv->txbepbufstail;
2435 count = priv->txringcount;
2436 break;
2437
2438 case VI_PRIORITY:
2439 tail=priv->txvipringtail;
2440 begin=priv->txvipring;
2441 buflist = priv->txvipbufstail;
2442 count = priv->txringcount;
2443 break;
2444
2445 case VO_PRIORITY:
2446 tail=priv->txvopringtail;
2447 begin=priv->txvopring;
2448 buflist = priv->txvopbufstail;
2449 count = priv->txringcount;
2450 break;
2451
2452 case HI_PRIORITY:
2453 tail=priv->txhpringtail;
2454 begin=priv->txhpring;
2455 buflist = priv->txhpbufstail;
2456 count = priv->txringcount;
2457 break;
2458
2459 case BEACON_PRIORITY:
2460 tail=priv->txbeaconringtail;
2461 begin=priv->txbeaconring;
2462 buflist = priv->txbeaconbufstail;
2463 count = priv->txbeaconcount;
2464 break;
2465
2466 default:
2467 return -1;
2468 break;
2469 }
2470
2471 //printk("in rtl8180_tx(): rate is %d\n",priv->ieee80211->rate);
2472#if 1
2473 memcpy(&dest, frag_hdr->addr1, ETH_ALEN);
2474 if (is_multicast_ether_addr(dest) ||
2475 is_broadcast_ether_addr(dest))
2476 {
2477 Duration = 0;
2478 RtsDur = 0;
2479 bRTSEnable = 0;
2480 bCTSEnable = 0;
2481
2482 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2483 TxDescDuration = ThisFrameTime;
2484 } else {// Unicast packet
2485 //u8 AckRate;
2486 u16 AckTime;
2487
2488 //YJ,add,080828,for Keep alive
2489 priv->NumTxUnicast++;
2490
2491 // Figure out ACK rate according to BSS basic rate and Tx rate, 2006.03.08 by rcnjko.
2492 //AckRate = ComputeAckRate( pMgntInfo->mBrates, (u1Byte)(pTcb->DataRate) );
2493 // Figure out ACK time according to the AckRate and assume long preamble is used on receiver, 2006.03.08, by rcnjko.
2494 //AckTime = ComputeTxTime( sAckCtsLng/8, AckRate, FALSE, FALSE);
2495 //For simplicity, just use the 1M basic rate
2496 //AckTime = ComputeTxTime(14, 540,0, 0); // AckCTSLng = 14 use 1M bps send
2497 AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
2498 //AckTime = ComputeTxTime(14, 2,false, false); // AckCTSLng = 14 use 1M bps send
2499
2500 if ( ((len + sCrcLng) > priv->rts) && priv->rts )
2501 { // RTS/CTS.
2502 u16 RtsTime, CtsTime;
2503 //u16 CtsRate;
2504 bRTSEnable = 1;
2505 bCTSEnable = 0;
2506
2507 // Rate and time required for RTS.
2508 RtsTime = ComputeTxTime( sAckCtsLng/8,priv->ieee80211->basic_rate, 0, 0);
2509 // Rate and time required for CTS.
2510 CtsTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
2511
2512 // Figure out time required to transmit this frame.
2513 ThisFrameTime = ComputeTxTime(len + sCrcLng,
2514 rtl8180_rate2rate(rate),
2515 0,
2516 bUseShortPreamble);
2517
2518 // RTS-CTS-ThisFrame-ACK.
2519 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime;
2520
2521 TxDescDuration = RtsTime + RtsDur;
2522 }
2523 else {// Normal case.
2524 bCTSEnable = 0;
2525 bRTSEnable = 0;
2526 RtsDur = 0;
2527
2528 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2529 TxDescDuration = ThisFrameTime + aSifsTime + AckTime;
2530 }
2531
2532 if(!(frag_hdr->frame_ctl & IEEE80211_FCTL_MOREFRAGS)) { //no more fragment
2533 // ThisFrame-ACK.
2534 Duration = aSifsTime + AckTime;
2535 } else { // One or more fragments remained.
2536 u16 NextFragTime;
2537 NextFragTime = ComputeTxTime( len + sCrcLng, //pretend following packet length equal current packet
2538 rtl8180_rate2rate(rate),
2539 0,
2540 bUseShortPreamble );
2541
2542 //ThisFrag-ACk-NextFrag-ACK.
2543 Duration = NextFragTime + 3*aSifsTime + 2*AckTime;
2544 }
2545
2546 } // End of Unicast packet
2547
2548 frag_hdr->duration_id = Duration;
2549#endif
2550
2551 buflen=priv->txbuffsize;
2552 remain=len;
2553 temp_tail = tail;
2554//printk("================================>buflen = %d, remain = %d!\n", buflen,remain);
2555 while(remain!=0){
c8d86be3
GKH		 2556 mb();
2557 if(!buflist){
2558 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority);
2559 //spin_unlock_irqrestore(&priv->tx_lock,flags);
2560 return -1;
2561 }
2562 buf=buflist->buf;
2563
2564 if( (*tail & (1<<31)) && (priority != BEACON_PRIORITY)){
2565
2566 DMESGW("No more TX desc, returning %x of %x",
2567 remain,len);
2568 priv->stats.txrdu++;
c8d86be3
GKH		 2569 // spin_unlock_irqrestore(&priv->tx_lock,flags);
2570
2571 return remain;
2572
2573 }
2574
2575 *tail= 0; // zeroes header
2576 *(tail+1) = 0;
2577 *(tail+3) = 0;
2578 *(tail+5) = 0;
2579 *(tail+6) = 0;
2580 *(tail+7) = 0;
2581
2582 if(priv->card_8185){
2583 //FIXME: this should be triggered by HW encryption parameters.
2584 *tail |= (1<<15); //no encrypt
2585// *tail |= (1<<30); //raise int when completed
2586 }
2587 // *tail = *tail | (1<<16);
2588 if(remain==len && !descfrag) {
2589 ownbit_flag = false; //added by david woo,2007.12.14
c8d86be3
GKH		 2590 *tail = *tail| (1<<29) ; //fist segment of the packet
2591 *tail = *tail |(len);
2592 } else {
2593 ownbit_flag = true;
2594 }
2595
2596 for(i=0;i<buflen&& remain >0;i++,remain--){
2597 ((u8*)buf)[i]=txbuf[i]; //copy data into descriptor pointed DMAble buffer
2598 if(remain == 4 && i+4 >= buflen) break;
2599 /* ensure the last desc has at least 4 bytes payload */
2600
2601 }
2602 txbuf = txbuf + i;
2603 *(tail+3)=*(tail+3) &~ 0xfff;
2604 *(tail+3)=*(tail+3) | i; // buffer lenght
2605 // Use short preamble or not
2606 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE)
2607 if (priv->plcp_preamble_mode==1 && rate!=0) // short mode now, not long!
2608 // *tail |= (1<<16); // enable short preamble mode.
2609
c8d86be3
GKH		 2610 if(bCTSEnable) {
2611 *tail |= (1<<18);
2612 }
2613
2614 if(bRTSEnable) //rts enable
2615 {
2616 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE
2617 *tail |= (1<<23);//rts enable
2618 *(tail+1) |=(RtsDur&0xffff);//RTS Duration
2619 }
2620 *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION
2621// *(tail+3) |= (0xe6<<16);
2622 *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ;
c8d86be3
GKH		 2623
2624 *tail = *tail | ((rate&0xf) << 24);
2625 //DMESG("rate %d",rate);
2626
2627 if(priv->card_8185){
c8d86be3
GKH		 2628 // *(tail+5) = 0;
2629 }
2630
2631 /* hw_plcp_len is not used for rtl8180 chip */
2632 /* FIXME */
2633 if(priv->card_8185 == 0 || !priv->hw_plcp_len){
2634
2635 duration = rtl8180_len2duration(len,
2636 rate,&ext);
2637
c8d86be3
GKH		 2638 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16);
2639 if(ext) *(tail+1) = *(tail+1) |(1<<31); //plcp length extension
2640 }
2641
2642 if(morefrag) *tail = (*tail) | (1<<17); // more fragment
2643 if(!remain) *tail = (*tail) | (1<<28); // last segment of frame
2644
c8d86be3
GKH		 2645 *(tail+5) = *(tail+5)|(2<<27);
2646 *(tail+7) = *(tail+7)|(1<<4);
2647
2648 wmb();
2649 if(ownbit_flag)
2650 {
2651 *tail = *tail | (1<<31); // descriptor ready to be txed
2652 }
2653
c8d86be3
GKH		 2654 if((tail - begin)/8 == count-1)
2655 tail=begin;
2656
2657 else
2658 tail=tail+8;
2659
2660 buflist=buflist->next;
2661
2662 mb();
2663
2664 switch(priority) {
2665 case MANAGE_PRIORITY:
2666 priv->txmapringtail=tail;
2667 priv->txmapbufstail=buflist;
2668 break;
2669
2670 case BK_PRIORITY:
2671 priv->txbkpringtail=tail;
2672 priv->txbkpbufstail=buflist;
2673 break;
2674
2675 case BE_PRIORITY:
2676 priv->txbepringtail=tail;
2677 priv->txbepbufstail=buflist;
2678 break;
2679
2680 case VI_PRIORITY:
2681 priv->txvipringtail=tail;
2682 priv->txvipbufstail=buflist;
2683 break;
2684
2685 case VO_PRIORITY:
2686 priv->txvopringtail=tail;
2687 priv->txvopbufstail=buflist;
2688 break;
2689
2690 case HI_PRIORITY:
2691 priv->txhpringtail=tail;
2692 priv->txhpbufstail = buflist;
2693 break;
2694
2695 case BEACON_PRIORITY:
2696 /* the HW seems to be happy with the 1st
2697 * descriptor filled and the 2nd empty...
2698 * So always update descriptor 1 and never
2699 * touch 2nd
2700 */
2701 // priv->txbeaconringtail=tail;
2702 // priv->txbeaconbufstail=buflist;
2703
2704 break;
2705
2706 }
2707
2708 //rtl8180_dma_kick(dev,priority);
2709 }
2710 *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed
2711 rtl8180_dma_kick(dev,priority);
2712 //spin_unlock_irqrestore(&priv->tx_lock,flags);
2713
2714 return 0;
2715
2716}
2717
2718
2719void rtl8180_irq_rx_tasklet(struct r8180_priv * priv);
2720
2721
2722void rtl8180_link_change(struct net_device *dev)
2723{
2724 struct r8180_priv *priv = ieee80211_priv(dev);
2725 u16 beacon_interval;
2726
2727 struct ieee80211_network *net = &priv->ieee80211->current_network;
2728// rtl8180_adapter_start(dev);
2729 rtl8180_update_msr(dev);
2730
2731
2732 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2733
2734 write_nic_dword(dev,BSSID,((u32*)net->bssid)[0]);
2735 write_nic_word(dev,BSSID+4,((u16*)net->bssid)[2]);
2736
2737
2738 beacon_interval = read_nic_dword(dev,BEACON_INTERVAL);
2739 beacon_interval &= ~ BEACON_INTERVAL_MASK;
2740 beacon_interval |= net->beacon_interval;
2741 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval);
2742
2743 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
2744
2745
2746 /*
2747 u16 atim = read_nic_dword(dev,ATIM);
2748 u16 = u16 &~ ATIM_MASK;
2749 u16 = u16 | beacon->atim;
2750 */
c8d86be3
GKH		 2751
2752 if(priv->card_8185)
2753 rtl8180_set_chan(dev, priv->chan);
2754
2755
2756}
2757
2758void rtl8180_rq_tx_ack(struct net_device *dev){
2759
2760 struct r8180_priv *priv = ieee80211_priv(dev);
d599edca 2761// printk("====================>%s\n",__func__);
c8d86be3
GKH		 2762 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)|CONFIG4_PWRMGT);
2763 priv->ack_tx_to_ieee = 1;
2764}
2765
2766short rtl8180_is_tx_queue_empty(struct net_device *dev){
2767
2768 struct r8180_priv *priv = ieee80211_priv(dev);
2769 u32* d;
2770
2771 for (d = priv->txmapring;
2772 d < priv->txmapring + priv->txringcount;d+=8)
2773 if(*d & (1<<31)) return 0;
2774
2775 for (d = priv->txbkpring;
2776 d < priv->txbkpring + priv->txringcount;d+=8)
2777 if(*d & (1<<31)) return 0;
2778
2779 for (d = priv->txbepring;
2780 d < priv->txbepring + priv->txringcount;d+=8)
2781 if(*d & (1<<31)) return 0;
2782
2783 for (d = priv->txvipring;
2784 d < priv->txvipring + priv->txringcount;d+=8)
2785 if(*d & (1<<31)) return 0;
2786
2787 for (d = priv->txvopring;
2788 d < priv->txvopring + priv->txringcount;d+=8)
2789 if(*d & (1<<31)) return 0;
2790
2791 for (d = priv->txhpring;
2792 d < priv->txhpring + priv->txringcount;d+=8)
2793 if(*d & (1<<31)) return 0;
2794 return 1;
2795}
2796/* FIXME FIXME 5msecs is random */
2797#define HW_WAKE_DELAY 5
2798
2799void rtl8180_hw_wakeup(struct net_device *dev)
2800{
2801 unsigned long flags;
2802
2803 struct r8180_priv *priv = ieee80211_priv(dev);
2804
2805 spin_lock_irqsave(&priv->ps_lock,flags);
2806 //DMESG("Waken up!");
2807 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)&~CONFIG4_PWRMGT);
2808
2809 if(priv->rf_wakeup)
2810 priv->rf_wakeup(dev);
2811// mdelay(HW_WAKE_DELAY);
2812 spin_unlock_irqrestore(&priv->ps_lock,flags);
2813}
2814
2815void rtl8180_hw_sleep_down(struct net_device *dev)
2816{
2817 unsigned long flags;
2818
2819 struct r8180_priv *priv = ieee80211_priv(dev);
2820
2821 spin_lock_irqsave(&priv->ps_lock,flags);
2822 //DMESG("Sleep!");
2823
2824 if(priv->rf_sleep)
2825 priv->rf_sleep(dev);
2826 spin_unlock_irqrestore(&priv->ps_lock,flags);
2827}
2828
2829
2830void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl)
2831{
2832
2833 struct r8180_priv *priv = ieee80211_priv(dev);
2834
2835 u32 rb = jiffies;
2836 unsigned long flags;
2837
2838 spin_lock_irqsave(&priv->ps_lock,flags);
2839
2840 /* Writing HW register with 0 equals to disable
2841 * the timer, that is not really what we want
2842 */
2843 tl -= MSECS(4+16+7);
2844
2845 //if(tl == 0) tl = 1;
2846
2847 /* FIXME HACK FIXME HACK */
2848// force_pci_posting(dev);
2849 //mdelay(1);
2850
2851// rb = read_nic_dword(dev, TSFTR);
2852
2853 /* If the interval in witch we are requested to sleep is too
2854 * short then give up and remain awake
2855 */
2856 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
2857 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
2858 spin_unlock_irqrestore(&priv->ps_lock,flags);
2859 printk("too short to sleep\n");
2860 return;
2861 }
2862
2863// write_nic_dword(dev, TimerInt, tl);
2864// rb = read_nic_dword(dev, TSFTR);
2865 {
2866 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
2867 // if (tl<rb)
2868
2869 //lzm,add,080828
2870 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp);
2871
2872 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
2873 }
2874 /* if we suspect the TimerInt is gone beyond tl
2875 * while setting it, then give up
2876 */
2877#if 1
2878 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
2879 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
2880 spin_unlock_irqrestore(&priv->ps_lock,flags);
2881 return;
2882 }
2883#endif
2884// if(priv->rf_sleep)
2885// priv->rf_sleep(dev);
2886
2887 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq);
2888 spin_unlock_irqrestore(&priv->ps_lock,flags);
2889}
2890
2891
2892//void rtl8180_wmm_param_update(struct net_device *dev,u8 *ac_param)
c8d86be3
GKH		 2893void rtl8180_wmm_param_update(struct work_struct * work)
2894{
2895 struct ieee80211_device * ieee = container_of(work, struct ieee80211_device,wmm_param_update_wq);
2896 //struct r8180_priv *priv = (struct r8180_priv*)(ieee->priv);
2897 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 2898 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param);
2899 u8 mode = ieee->current_network.mode;
2900 AC_CODING eACI;
2901 AC_PARAM AcParam;
2902 PAC_PARAM pAcParam;
2903 u8 i;
2904
c8d86be3
GKH		 2905 if(!ieee->current_network.QoS_Enable){
2906 //legacy ac_xx_param update
2907 AcParam.longData = 0;
2908 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2909 AcParam.f.AciAifsn.f.ACM = 0;
2910 AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin.
2911 AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax.
2912 AcParam.f.TXOPLimit = 0;
2913 for(eACI = 0; eACI < AC_MAX; eACI++){
2914 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2915 {
2916 u8 u1bAIFS;
2917 u32 u4bAcParam;
2918 pAcParam = (PAC_PARAM)(&AcParam);
2919 // Retrive paramters to udpate.
2920 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN *(((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2921 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)|
2922 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)|
2923 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)|
2924 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2925 switch(eACI){
2926 case AC1_BK:
2927 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2928 break;
2929
2930 case AC0_BE:
2931 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2932 break;
2933
2934 case AC2_VI:
2935 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2936 break;
2937
2938 case AC3_VO:
2939 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2940 break;
2941
2942 default:
2943 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI);
2944 break;
2945 }
2946 }
2947 }
2948 return;
2949 }
2950
2951 for(i = 0; i < AC_MAX; i++){
2952 //AcParam.longData = 0;
2953 pAcParam = (AC_PARAM * )ac_param;
2954 {
2955 AC_CODING eACI;
2956 u8 u1bAIFS;
2957 u32 u4bAcParam;
2958
2959 // Retrive paramters to udpate.
2960 eACI = pAcParam->f.AciAifsn.f.ACI;
2961 //Mode G/A: slotTimeTimer = 9; Mode B: 20
2962 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2963 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2964 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2965 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2966 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2967
2968 switch(eACI){
2969 case AC1_BK:
2970 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2971 break;
2972
2973 case AC0_BE:
2974 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2975 break;
2976
2977 case AC2_VI:
2978 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2979 break;
2980
2981 case AC3_VO:
2982 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2983 break;
2984
2985 default:
2986 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2987 break;
2988 }
2989 }
2990 ac_param += (sizeof(AC_PARAM));
2991 }
c8d86be3
GKH		 2992}
2993
c8d86be3 2994void rtl8180_tx_irq_wq(struct work_struct *work);
c8d86be3
GKH		 2995void rtl8180_restart_wq(struct work_struct *work);
2996//void rtl8180_rq_tx_ack(struct work_struct *work);
c8d86be3 2997void rtl8180_watch_dog_wq(struct work_struct *work);
c8d86be3 2998void rtl8180_hw_wakeup_wq(struct work_struct *work);
c8d86be3 2999void rtl8180_hw_sleep_wq(struct work_struct *work);
c8d86be3 3000void rtl8180_sw_antenna_wq(struct work_struct *work);
0370453f
BZ		 3001void rtl8180_watch_dog(struct net_device *dev);
3002
c8d86be3
GKH		 3003void watch_dog_adaptive(unsigned long data)
3004{
3005 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data);
3006// DMESG("---->watch_dog_adaptive()\n");
3007 if(!priv->up)
3008 {
3009 DMESG("<----watch_dog_adaptive():driver is not up!\n");
3010 return;
3011 }
3012
3013 // queue_work(priv->ieee80211->wq,&priv->ieee80211->watch_dog_wq);
3014//{by amy 080312
3015#if 1
3016 // Tx High Power Mechanism.
3017#ifdef HIGH_POWER
3018 if(CheckHighPower((struct net_device *)data))
3019 {
3020 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq);
3021 }
3022#endif
3023
c8d86be3
GKH		 3024 // Tx Power Tracking on 87SE.
3025#ifdef TX_TRACK
3026 //if( priv->bTxPowerTrack ) //lzm mod 080826
3027 if( CheckTxPwrTracking((struct net_device *)data));
3028 TxPwrTracking87SE((struct net_device *)data);
c8d86be3
GKH		 3029#endif
3030
3031 // Perform DIG immediately.
3032#ifdef SW_DIG
3033 if(CheckDig((struct net_device *)data) == true)
3034 {
3035 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq);
3036 }
3037#endif
3038#endif
3039//by amy 080312}
3040 rtl8180_watch_dog((struct net_device *)data);
3041
3042
3043 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem);
3044
3045 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
3046 add_timer(&priv->watch_dog_timer);
3047// DMESG("<----watch_dog_adaptive()\n");
3048}
3049
c8d86be3
GKH		 3050
3051static CHANNEL_LIST ChannelPlan[] = {
3052 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC
3053 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
3054 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
3055 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI.
3056 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI.
3057 {{14,36,40,44,48,52,56,60,64},9}, //MKK
3058 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1
3059 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel.
3060 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC
3061 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
3062 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826
3063};
3064
3065static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee)
3066{
3067 int i;
3068
3069 //lzm add 080826
3070 ieee->MinPassiveChnlNum=MAX_CHANNEL_NUMBER+1;
3071 ieee->IbssStartChnl=0;
3072
3073 switch (channel_plan)
3074 {
3075 case COUNTRY_CODE_FCC:
3076 case COUNTRY_CODE_IC:
3077 case COUNTRY_CODE_ETSI:
3078 case COUNTRY_CODE_SPAIN:
3079 case COUNTRY_CODE_FRANCE:
3080 case COUNTRY_CODE_MKK:
3081 case COUNTRY_CODE_MKK1:
3082 case COUNTRY_CODE_ISRAEL:
3083 case COUNTRY_CODE_TELEC:
3084 {
3085 Dot11d_Init(ieee);
3086 ieee->bGlobalDomain = false;
3087 if (ChannelPlan[channel_plan].Len != 0){
3088 // Clear old channel map
3089 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
3090 // Set new channel map
3091 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
3092 {
3093 if(ChannelPlan[channel_plan].Channel[i] <= 14)
3094 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
3095 }
3096 }
3097 break;
3098 }
3099 case COUNTRY_CODE_GLOBAL_DOMAIN:
3100 {
3101 GET_DOT11D_INFO(ieee)->bEnabled = 0;
3102 Dot11d_Reset(ieee);
3103 ieee->bGlobalDomain = true;
3104 break;
3105 }
3106 case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826
3107 {
3108 ieee->MinPassiveChnlNum=12;
3109 ieee->IbssStartChnl= 10;
3110 break;
3111 }
3112 default:
3113 {
3114 Dot11d_Init(ieee);
3115 ieee->bGlobalDomain = false;
3116 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
3117 for (i=1;i<=14;i++)
3118 {
3119 GET_DOT11D_INFO(ieee)->channel_map[i] = 1;
3120 }
3121 break;
3122 }
3123 }
3124}
c8d86be3
GKH		 3125
3126//Add for RF power on power off by lizhaoming 080512
c8d86be3 3127void GPIOChangeRFWorkItemCallBack(struct work_struct *work);
c8d86be3
GKH		 3128
3129//YJ,add,080828
3130static void rtl8180_statistics_init(struct Stats *pstats)
3131{
3132 memset(pstats, 0, sizeof(struct Stats));
3133}
3134static void rtl8180_link_detect_init(plink_detect_t plink_detect)
3135{
3136 memset(plink_detect, 0, sizeof(link_detect_t));
3137 plink_detect->SlotNum = DEFAULT_SLOT_NUM;
3138}
3139//YJ,add,080828,end
3140
3141short rtl8180_init(struct net_device *dev)
3142{
3143 struct r8180_priv *priv = ieee80211_priv(dev);
3144 u16 word;
3145 u16 version;
3146 u8 hw_version;
3147 //u8 config3;
3148 u32 usValue;
3149 u16 tmpu16;
3150 int i, j;
3151
c8d86be3
GKH		 3152 priv->channel_plan = eprom_read(dev, EEPROM_COUNTRY_CODE>>1) & 0xFF;
3153 if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){
3154 printk("rtl8180_init:Error channel plan! Set to default.\n");
3155 priv->channel_plan = 0;
3156 }
3157 //priv->channel_plan = 9; //Global Domain
3158
3159 DMESG("Channel plan is %d\n",priv->channel_plan);
3160 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211);
c8d86be3
GKH		 3161
3162 //memcpy(priv->stats,0,sizeof(struct Stats));
3163
3164 //FIXME: these constants are placed in a bad pleace.
3165 priv->txbuffsize = 2048;//1024;
3166 priv->txringcount = 32;//32;
3167 priv->rxbuffersize = 2048;//1024;
3168 priv->rxringcount = 64;//32;
3169 priv->txbeaconcount = 2;
3170 priv->rx_skb_complete = 1;
3171 //priv->txnp_pending.ispending=0;
3172 /* ^^ the SKB does not containt a partial RXed
3173 * packet (is empty)
3174 */
3175
c8d86be3 3176 priv->RegThreeWireMode = HW_THREE_WIRE_SI;
c8d86be3
GKH		 3177
3178//Add for RF power on power off by lizhaoming 080512
3179 priv->RFChangeInProgress = false;
3180 priv->SetRFPowerStateInProgress = false;
3181 priv->RFProgType = 0;
3182 priv->bInHctTest = false;
3183
3184 priv->irq_enabled=0;
3185
3186//YJ,modified,080828
c8d86be3
GKH		 3187 rtl8180_statistics_init(&priv->stats);
3188 rtl8180_link_detect_init(&priv->link_detect);
c8d86be3
GKH		 3189//YJ,modified,080828,end
3190
3191
3192 priv->ack_tx_to_ieee = 0;
3193 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
3194 priv->ieee80211->iw_mode = IW_MODE_INFRA;
3195 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
3196 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
3197 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
3198 priv->ieee80211->active_scan = 1;
3199 priv->ieee80211->rate = 110; //11 mbps
3200 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION;
3201 priv->ieee80211->host_encrypt = 1;
3202 priv->ieee80211->host_decrypt = 1;
3203 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup;
3204 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack;
3205 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep;
3206 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty;
3207
3208 priv->hw_wep = hwwep;
3209 priv->prism_hdr=0;
3210 priv->dev=dev;
3211 priv->retry_rts = DEFAULT_RETRY_RTS;
3212 priv->retry_data = DEFAULT_RETRY_DATA;
3213 priv->RFChangeInProgress = false;
3214 priv->SetRFPowerStateInProgress = false;
3215 priv->RFProgType = 0;
3216 priv->bInHctTest = false;
3217 priv->bInactivePs = true;//false;
3218 priv->ieee80211->bInactivePs = priv->bInactivePs;
3219 priv->bSwRfProcessing = false;
3220 priv->eRFPowerState = eRfOff;
3221 priv->RfOffReason = 0;
3222 priv->LedStrategy = SW_LED_MODE0;
3223 //priv->NumRxOkInPeriod = 0; //YJ,del,080828
3224 //priv->NumTxOkInPeriod = 0; //YJ,del,080828
3225 priv->TxPollingTimes = 0;//lzm add 080826
3226 priv->bLeisurePs = true;
3227 priv->dot11PowerSaveMode = eActive;
3228//by amy for antenna
3229 priv->AdMinCheckPeriod = 5;
3230 priv->AdMaxCheckPeriod = 10;
3231// Lower signal strength threshold to fit the HW participation in antenna diversity. +by amy 080312
3232 priv->AdMaxRxSsThreshold = 30;//60->30
3233 priv->AdRxSsThreshold = 20;//50->20
3234 priv->AdCheckPeriod = priv->AdMinCheckPeriod;
3235 priv->AdTickCount = 0;
3236 priv->AdRxSignalStrength = -1;
3237 priv->RegSwAntennaDiversityMechanism = 0;
3238 priv->RegDefaultAntenna = 0;
3239 priv->SignalStrength = 0;
3240 priv->AdRxOkCnt = 0;
3241 priv->CurrAntennaIndex = 0;
3242 priv->AdRxSsBeforeSwitched = 0;
3243 init_timer(&priv->SwAntennaDiversityTimer);
3244 priv->SwAntennaDiversityTimer.data = (unsigned long)dev;
3245 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback;
3246//by amy for antenna
3247//{by amy 080312
3248 priv->bDigMechanism = 1;
3249 priv->InitialGain = 6;
3250 priv->bXtalCalibration = false;
3251 priv->XtalCal_Xin = 0;
3252 priv->XtalCal_Xout = 0;
3253 priv->bTxPowerTrack = false;
3254 priv->ThermalMeter = 0;
3255 priv->FalseAlarmRegValue = 0;
3256 priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG.
3257 priv->DIG_NumberFallbackVote = 0;
3258 priv->DIG_NumberUpgradeVote = 0;
3259 priv->LastSignalStrengthInPercent = 0;
3260 priv->Stats_SignalStrength = 0;
3261 priv->LastRxPktAntenna = 0;
3262 priv->SignalQuality = 0; // in 0-100 index.
3263 priv->Stats_SignalQuality = 0;
3264 priv->RecvSignalPower = 0; // in dBm.
3265 priv->Stats_RecvSignalPower = 0;
3266 priv->AdMainAntennaRxOkCnt = 0;
3267 priv->AdAuxAntennaRxOkCnt = 0;
3268 priv->bHWAdSwitched = false;
3269 priv->bRegHighPowerMechanism = true;
3270 priv->RegHiPwrUpperTh = 77;
3271 priv->RegHiPwrLowerTh = 75;
3272 priv->RegRSSIHiPwrUpperTh = 70;
3273 priv->RegRSSIHiPwrLowerTh = 20;
3274 priv->bCurCCKPkt = false;
3275 priv->UndecoratedSmoothedSS = -1;
3276 priv->bToUpdateTxPwr = false;
3277 priv->CurCCKRSSI = 0;
3278 priv->RxPower = 0;
3279 priv->RSSI = 0;
3280 //YJ,add,080828
3281 priv->NumTxOkTotal = 0;
3282 priv->NumTxUnicast = 0;
3283 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL;
3284 priv->PowerProfile = POWER_PROFILE_AC;
3285 //YJ,add,080828,end
3286//by amy for rate adaptive
3287 priv->CurrRetryCnt=0;
3288 priv->LastRetryCnt=0;
3289 priv->LastTxokCnt=0;
3290 priv->LastRxokCnt=0;
3291 priv->LastRetryRate=0;
3292 priv->bTryuping=0;
3293 priv->CurrTxRate=0;
3294 priv->CurrRetryRate=0;
3295 priv->TryupingCount=0;
3296 priv->TryupingCountNoData=0;
3297 priv->TryDownCountLowData=0;
3298 priv->LastTxOKBytes=0;
3299 priv->LastFailTxRate=0;
3300 priv->LastFailTxRateSS=0;
3301 priv->FailTxRateCount=0;
3302 priv->LastTxThroughput=0;
3303 priv->NumTxOkBytesTotal=0;
3304 priv->ForcedDataRate = 0;
3305 priv->RegBModeGainStage = 1;
3306
3307//by amy for rate adaptive
3308//by amy 080312}
3309 priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
3310 spin_lock_init(&priv->irq_lock);
3311 spin_lock_init(&priv->irq_th_lock);
3312 spin_lock_init(&priv->tx_lock);
3313 spin_lock_init(&priv->ps_lock);
3314 spin_lock_init(&priv->rf_ps_lock);
3315 sema_init(&priv->wx_sem,1);
3316 sema_init(&priv->rf_state,1);
c8d86be3
GKH		 3317 INIT_WORK(&priv->reset_wq,(void*) rtl8180_restart_wq);
3318 INIT_WORK(&priv->tx_irq_wq,(void*) rtl8180_tx_irq_wq);
3319 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8180_hw_wakeup_wq);
3320 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8180_hw_sleep_wq);
3321 //INIT_DELAYED_WORK(&priv->ieee80211->watch_dog_wq,(void*) rtl8180_watch_dog_wq);
3322 //INIT_DELAYED_WORK(&priv->ieee80211->sw_antenna_wq,(void*) rtl8180_sw_antenna_wq);
3323 INIT_WORK(&priv->ieee80211->wmm_param_update_wq,(void*) rtl8180_wmm_param_update);
3324 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,(void*)rtl8180_rate_adapter);//+by amy 080312
3325 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,(void*)rtl8180_hw_dig_wq);//+by amy 080312
3326 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,(void*)rtl8180_tx_pw_wq);//+by amy 080312
3327
3328 //add for RF power on power off by lizhaoming 080512
3329 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,(void*) GPIOChangeRFWorkItemCallBack);
c8d86be3
GKH		 3330 //INIT_WORK(&priv->reset_wq,(void*) rtl8180_restart_wq,dev);
3331
3332 tasklet_init(&priv->irq_rx_tasklet,
3333 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet,
3334 (unsigned long)priv);
3335//by amy
3336 init_timer(&priv->watch_dog_timer);
3337 priv->watch_dog_timer.data = (unsigned long)dev;
3338 priv->watch_dog_timer.function = watch_dog_adaptive;
3339//by amy
3340
3341//{by amy 080312
3342//by amy for rate adaptive
3343 init_timer(&priv->rateadapter_timer);
3344 priv->rateadapter_timer.data = (unsigned long)dev;
3345 priv->rateadapter_timer.function = timer_rate_adaptive;
3346 priv->RateAdaptivePeriod= RATE_ADAPTIVE_TIMER_PERIOD;
3347 priv->bEnhanceTxPwr=false;
3348//by amy for rate adaptive
3349//by amy 080312}
3350 //priv->ieee80211->func =
3351 // kmalloc(sizeof(struct ieee80211_helper_functions),GFP_KERNEL);
3352 //memset(priv->ieee80211->func, 0,
3353 // sizeof(struct ieee80211_helper_functions));
3354
3355 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit;
3356 priv->ieee80211->set_chan = rtl8180_set_chan;
3357 priv->ieee80211->link_change = rtl8180_link_change;
3358 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit;
3359 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop;
3360 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume;
3361
3362 priv->ieee80211->init_wmmparam_flag = 0;
3363
3364 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon;
3365 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable;
3366 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
3367
c8d86be3
GKH		 3368 priv->MWIEnable = 0;
3369
3370 priv->ShortRetryLimit = 7;
3371 priv->LongRetryLimit = 7;
3372 priv->EarlyRxThreshold = 7;
3373
3374 priv->CSMethod = (0x01 << 29);
3375
3376 priv->TransmitConfig =
3377 1<<TCR_DurProcMode_OFFSET | //for RTL8185B, duration setting by HW
3378 (7<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
3379 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit
3380 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
3381 (0 ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
3382
3383 priv->ReceiveConfig =
c8d86be3
GKH		 3384// RCR_ENMARP |
3385 RCR_AMF | RCR_ADF | //accept management/data
3386 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
3387 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
3388 //RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
3389 (7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
3390 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
3391 (priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0);
3392
3393 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER |
3394 IMR_THPDER | IMR_THPDOK |
3395 IMR_TVODER | IMR_TVODOK |
3396 IMR_TVIDER | IMR_TVIDOK |
3397 IMR_TBEDER | IMR_TBEDOK |
3398 IMR_TBKDER | IMR_TBKDOK |
3399 IMR_RDU | // To handle the defragmentation not enough Rx descriptors case. Annie, 2006-03-27.
3400 IMR_RER | IMR_ROK |
3401 IMR_RQoSOK; // <NOTE> ROK and RQoSOK are mutually exclusive, so, we must handle RQoSOK interrupt to receive QoS frames, 2005.12.09, by rcnjko.
3402
3403 priv->InitialGain = 6;
c8d86be3
GKH		 3404
3405 hw_version =( read_nic_dword(dev, TCR) & TCR_HWVERID_MASK)>>TCR_HWVERID_SHIFT;
3406
3407 switch (hw_version){
c8d86be3 3408 case HW_VERID_R8185B_B:
c8d86be3
GKH		 3409 priv->card_8185 = VERSION_8187S_C;
3410 DMESG("MAC controller is a RTL8187SE b/g");
3411 priv->phy_ver = 2;
3412 break;
c8d86be3
GKH		 3413 case HW_VERID_R8185_ABC:
3414 DMESG("MAC controller is a RTL8185 b/g");
3415 priv->card_8185 = 1;
3416 /* you should not find a card with 8225 PHY ver < C*/
3417 priv->phy_ver = 2;
3418 break;
3419
3420 case HW_VERID_R8185_D:
3421 DMESG("MAC controller is a RTL8185 b/g (V. D)");
3422 priv->card_8185 = 2;
3423 /* you should not find a card with 8225 PHY ver < C*/
3424 priv->phy_ver = 2;
3425 break;
3426
3427 case HW_VERID_R8180_ABCD:
3428 DMESG("MAC controller is a RTL8180");
3429 priv->card_8185 = 0;
3430 break;
3431
3432 case HW_VERID_R8180_F:
3433 DMESG("MAC controller is a RTL8180 (v. F)");
3434 priv->card_8185 = 0;
3435 break;
3436
3437 default:
3438 DMESGW("MAC chip not recognized: version %x. Assuming RTL8180",hw_version);
3439 priv->card_8185 = 0;
3440 break;
3441 }
3442
3443 if(priv->card_8185){
3444 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION;
3445 priv->ieee80211->short_slot = 1;
3446 }
3447 /* you should not found any 8185 Ver B Card */
3448 priv->card_8185_Bversion = 0;
3449
c8d86be3
GKH		 3450 // just for sync 85
3451 priv->card_type = PCI;
3452 DMESG("This is a PCI NIC");
c8d86be3
GKH		 3453 priv->enable_gpio0 = 0;
3454
3455//by amy for antenna
c8d86be3
GKH		 3456 usValue = eprom_read(dev, EEPROM_SW_REVD_OFFSET);
3457 DMESG("usValue is 0x%x\n",usValue);
c8d86be3
GKH		 3458 //3Read AntennaDiversity
3459 // SW Antenna Diversity.
3460 if( (usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE )
3461 {
3462 priv->EEPROMSwAntennaDiversity = false;
3463 //printk("EEPROM Disable SW Antenna Diversity\n");
3464 }
3465 else
3466 {
3467 priv->EEPROMSwAntennaDiversity = true;
3468 //printk("EEPROM Enable SW Antenna Diversity\n");
3469 }
3470 // Default Antenna to use.
3471 if( (usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1 )
3472 {
3473 priv->EEPROMDefaultAntenna1 = false;
3474 //printk("EEPROM Default Antenna 0\n");
3475 }
3476 else
3477 {
3478 priv->EEPROMDefaultAntenna1 = true;
3479 //printk("EEPROM Default Antenna 1\n");
3480 }
3481
3482 //
3483 // Antenna diversity mechanism. Added by Roger, 2007.11.05.
3484 //
3485 if( priv->RegSwAntennaDiversityMechanism == 0 ) // Auto
3486 {// 0: default from EEPROM.
3487 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity;
3488 }
3489 else
3490 {// 1:disable antenna diversity, 2: enable antenna diversity.
3491 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1)? false : true);
3492 }
3493 //printk("bSwAntennaDiverity = %d\n", priv->bSwAntennaDiverity);
3494
3495
3496 //
3497 // Default antenna settings. Added by Roger, 2007.11.05.
3498 //
3499 if( priv->RegDefaultAntenna == 0)
3500 {// 0: default from EEPROM.
3501 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1;
3502 }
3503 else
3504 {// 1: main, 2: aux.
3505 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna== 2) ? true : false);
3506 }
3507 //printk("bDefaultAntenna1 = %d\n", priv->bDefaultAntenna1);
c8d86be3
GKH		 3508//by amy for antenna
3509 /* rtl8185 can calc plcp len in HW.*/
3510 priv->hw_plcp_len = 1;
3511
3512 priv->plcp_preamble_mode = 2;
3513 /*the eeprom type is stored in RCR register bit #6 */
3514 if (RCR_9356SEL & read_nic_dword(dev, RCR)){
3515 priv->epromtype=EPROM_93c56;
3516 //DMESG("Reported EEPROM chip is a 93c56 (2Kbit)");
3517 }else{
3518 priv->epromtype=EPROM_93c46;
3519 //DMESG("Reported EEPROM chip is a 93c46 (1Kbit)");
3520 }
3521
c8d86be3
GKH		 3522 dev->dev_addr[0]=eprom_read(dev,MAC_ADR) & 0xff;
3523 dev->dev_addr[1]=(eprom_read(dev,MAC_ADR) & 0xff00)>>8;
3524 dev->dev_addr[2]=eprom_read(dev,MAC_ADR+1) & 0xff;
3525 dev->dev_addr[3]=(eprom_read(dev,MAC_ADR+1) & 0xff00)>>8;
3526 dev->dev_addr[4]=eprom_read(dev,MAC_ADR+2) & 0xff;
3527 dev->dev_addr[5]=(eprom_read(dev,MAC_ADR+2) & 0xff00)>>8;
3528 //DMESG("Card MAC address is "MAC_FMT, MAC_ARG(dev->dev_addr));
3529
3530
3531 for(i=1,j=0; i<14; i+=2,j++){
3532
3533 word = eprom_read(dev,EPROM_TXPW_CH1_2 + j);
3534 priv->chtxpwr[i]=word & 0xff;
3535 priv->chtxpwr[i+1]=(word & 0xff00)>>8;
c8d86be3
GKH		 3536 }
3537 if(priv->card_8185){
3538 for(i=1,j=0; i<14; i+=2,j++){
3539
3540 word = eprom_read(dev,EPROM_TXPW_OFDM_CH1_2 + j);
3541 priv->chtxpwr_ofdm[i]=word & 0xff;
3542 priv->chtxpwr_ofdm[i+1]=(word & 0xff00)>>8;
c8d86be3
GKH		 3543 }
3544 }
3545//{by amy 080312
3546 //3Read crystal calibtration and thermal meter indication on 87SE.
3547
3548 // By SD3 SY's request. Added by Roger, 2007.12.11.
3549
3550 tmpu16 = eprom_read(dev, EEPROM_RSV>>1);
3551
3552 //printk("ReadAdapterInfo8185(): EEPROM_RSV(%04x)\n", tmpu16);
3553
3554 // Crystal calibration for Xin and Xout resp.
3555 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; // 0~7.5pF
3556 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK)>>4; // 0~7.5pF
3557 if((tmpu16 & EEPROM_XTAL_CAL_ENABLE)>>12)
3558 priv->bXtalCalibration = true;
3559
3560 // Thermal meter reference indication.
3561 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK)>>8);
3562 if((tmpu16 & EEPROM_THERMAL_METER_ENABLE)>>13)
3563 priv->bTxPowerTrack = true;
3564
3565//by amy 080312}
c8d86be3
GKH		 3566 word = eprom_read(dev,EPROM_TXPW_BASE);
3567 priv->cck_txpwr_base = word & 0xf;
3568 priv->ofdm_txpwr_base = (word>>4) & 0xf;
c8d86be3
GKH		 3569
3570 version = eprom_read(dev,EPROM_VERSION);
3571 DMESG("EEPROM version %x",version);
3572 if( (!priv->card_8185) && version < 0x0101){
3573 DMESG ("EEPROM version too old, assuming defaults");
3574 DMESG ("If you see this message *plase* send your \
3575DMESG output to andreamrl@tiscali.it THANKS");
3576 priv->digphy=1;
3577 priv->antb=0;
3578 priv->diversity=1;
3579 priv->cs_treshold=0xc;
3580 priv->rcr_csense=1;
3581 priv->rf_chip=RFCHIPID_PHILIPS;
3582 }else{
3583 if(!priv->card_8185){
3584 u8 rfparam = eprom_read(dev,RF_PARAM);
3585 DMESG("RfParam: %x",rfparam);
3586
3587 priv->digphy = rfparam & (1<<RF_PARAM_DIGPHY_SHIFT) ? 0:1;
3588 priv->antb = rfparam & (1<<RF_PARAM_ANTBDEFAULT_SHIFT) ? 1:0;
3589
3590 priv->rcr_csense = (rfparam & RF_PARAM_CARRIERSENSE_MASK) >>
3591 RF_PARAM_CARRIERSENSE_SHIFT;
3592
3593 priv->diversity =
3594 (read_nic_byte(dev,CONFIG2)&(1<<CONFIG2_ANTENNA_SHIFT)) ? 1:0;
3595 }else{
3596 priv->rcr_csense = 3;
3597 }
3598
3599 priv->cs_treshold = (eprom_read(dev,ENERGY_TRESHOLD)&0xff00) >>8;
3600
3601 priv->rf_chip = 0xff & eprom_read(dev,RFCHIPID);
3602 }
3603
c8d86be3
GKH		 3604 priv->rf_chip = RF_ZEBRA4;
3605 priv->rf_sleep = rtl8225z4_rf_sleep;
3606 priv->rf_wakeup = rtl8225z4_rf_wakeup;
c8d86be3
GKH		 3607 //DMESG("Card reports RF frontend Realtek 8225z2");
3608 //DMESGW("This driver has EXPERIMENTAL support for this chipset.");
3609 //DMESGW("use it with care and at your own risk and");
3610 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!");
3611
3612 priv->rf_close = rtl8225z2_rf_close;
3613 priv->rf_init = rtl8225z2_rf_init;
3614 priv->rf_set_chan = rtl8225z2_rf_set_chan;
3615 priv->rf_set_sens = NULL;
c8d86be3
GKH		 3616
3617 if(!priv->card_8185){
3618 if(priv->antb)
3619 DMESG ("Antenna B is default antenna");
3620 else
3621 DMESG ("Antenna A is default antenna");
3622
3623 if(priv->diversity)
3624 DMESG ("Antenna diversity is enabled");
3625 else
3626 DMESG("Antenna diversity is disabled");
3627
3628 DMESG("Carrier sense %d",priv->rcr_csense);
3629 }
3630
3631 if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount))
3632 return -ENOMEM;
3633
3634 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3635 TX_MANAGEPRIORITY_RING_ADDR))
3636 return -ENOMEM;
3637
3638 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3639 TX_BKPRIORITY_RING_ADDR))
3640 return -ENOMEM;
3641
3642 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3643 TX_BEPRIORITY_RING_ADDR))
3644 return -ENOMEM;
3645
3646 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3647 TX_VIPRIORITY_RING_ADDR))
3648 return -ENOMEM;
3649
3650 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3651 TX_VOPRIORITY_RING_ADDR))
3652 return -ENOMEM;
3653
3654 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3655 TX_HIGHPRIORITY_RING_ADDR))
3656 return -ENOMEM;
3657
3658 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount,
3659 TX_BEACON_RING_ADDR))
3660 return -ENOMEM;
3661
3662
3663 //priv->beacon_buf=NULL;
3664
3665 if(!priv->card_8185){
3666
3667 if(read_nic_byte(dev, CONFIG0) & (1<<CONFIG0_WEP40_SHIFT))
3668 DMESG ("40-bit WEP is supported in hardware");
3669 else
3670 DMESG ("40-bit WEP is NOT supported in hardware");
3671
3672 if(read_nic_byte(dev,CONFIG0) & (1<<CONFIG0_WEP104_SHIFT))
3673 DMESG ("104-bit WEP is supported in hardware");
3674 else
3675 DMESG ("104-bit WEP is NOT supported in hardware");
3676 }
3677#if !defined(SA_SHIRQ)
3678 if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){
3679#else
3680 if(request_irq(dev->irq, (void *)rtl8180_interrupt, SA_SHIRQ, dev->name, dev)){
3681#endif
3682 DMESGE("Error allocating IRQ %d",dev->irq);
3683 return -1;
3684 }else{
3685 priv->irq=dev->irq;
3686 DMESG("IRQ %d",dev->irq);
3687 }
3688
c8d86be3
GKH		 3689 return 0;
3690
3691}
3692
3693
3694void rtl8180_no_hw_wep(struct net_device *dev)
3695{
3696 struct r8180_priv *priv = ieee80211_priv(dev);
3697
3698 if(!priv->card_8185)
3699 {
3700 u8 security;
3701
3702 security = read_nic_byte(dev, SECURITY);
3703 security &=~(1<<SECURITY_WEP_TX_ENABLE_SHIFT);
3704 security &=~(1<<SECURITY_WEP_RX_ENABLE_SHIFT);
3705
3706 write_nic_byte(dev, SECURITY, security);
3707
3708 }else{
3709
3710 //FIXME!!!
3711 }
3712 /*
3713 write_nic_dword(dev,TX_CONF,read_nic_dword(dev,TX_CONF) |
3714 (1<<TX_NOICV_SHIFT) );
3715 */
3716// priv->ieee80211->hw_wep=0;
3717}
3718
3719
3720void rtl8180_set_hw_wep(struct net_device *dev)
3721{
3722 struct r8180_priv *priv = ieee80211_priv(dev);
3723 u8 pgreg;
3724 u8 security;
3725 u32 key0_word4;
3726
3727 pgreg=read_nic_byte(dev, PGSELECT);
3728 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
3729
3730 key0_word4 = read_nic_dword(dev, KEY0+4+4+4);
3731 key0_word4 &= ~ 0xff;
3732 key0_word4 |= priv->key0[3]& 0xff;
3733 write_nic_dword(dev,KEY0,(priv->key0[0]));
3734 write_nic_dword(dev,KEY0+4,(priv->key0[1]));
3735 write_nic_dword(dev,KEY0+4+4,(priv->key0[2]));
3736 write_nic_dword(dev,KEY0+4+4+4,(key0_word4));
3737
3738 /*
3739 TX_CONF,read_nic_dword(dev,TX_CONF) &~(1<<TX_NOICV_SHIFT));
3740 */
3741
3742 security = read_nic_byte(dev,SECURITY);
3743 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT);
3744 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT);
3745 security &= ~ SECURITY_ENCRYP_MASK;
3746 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT);
3747
3748 write_nic_byte(dev, SECURITY, security);
3749
3750 DMESG("key %x %x %x %x",read_nic_dword(dev,KEY0+4+4+4),
3751 read_nic_dword(dev,KEY0+4+4),read_nic_dword(dev,KEY0+4),
3752 read_nic_dword(dev,KEY0));
3753
3754 //priv->ieee80211->hw_wep=1;
3755}
3756
3757
3758void rtl8185_rf_pins_enable(struct net_device *dev)
3759{
3760// u16 tmp;
3761// tmp = read_nic_word(dev, RFPinsEnable);
3762 write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp);
3763// write_nic_word(dev, RFPinsEnable,7 | tmp);
3764}
3765
3766
3767void rtl8185_set_anaparam2(struct net_device *dev, u32 a)
3768{
3769 u8 conf3;
3770
3771 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3772
3773 conf3 = read_nic_byte(dev, CONFIG3);
3774 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3775 write_nic_dword(dev, ANAPARAM2, a);
3776
3777 conf3 = read_nic_byte(dev, CONFIG3);
3778 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3779 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3780
3781}
3782
3783
3784void rtl8180_set_anaparam(struct net_device *dev, u32 a)
3785{
3786 u8 conf3;
3787
3788 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3789
3790 conf3 = read_nic_byte(dev, CONFIG3);
3791 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3792 write_nic_dword(dev, ANAPARAM, a);
3793
3794 conf3 = read_nic_byte(dev, CONFIG3);
3795 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3796 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3797}
3798
3799
3800void rtl8185_tx_antenna(struct net_device *dev, u8 ant)
3801{
3802 write_nic_byte(dev, TX_ANTENNA, ant);
3803 force_pci_posting(dev);
3804 mdelay(1);
3805}
3806
3807
3808void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data)
3809{
3810 //u8 phyr;
3811 u32 phyw;
3812 //int i;
3813
3814 adr |= 0x80;
3815
3816 phyw= ((data<<8) | adr);
c8d86be3 3817
c8d86be3
GKH		 3818 // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register.
3819 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24));
3820 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16));
3821 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8));
3822 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff) ));
5521a513 3823
c8d86be3
GKH		 3824 /* this is ok to fail when we write AGC table. check for AGC table might be
3825 * done by masking with 0x7f instead of 0xff
3826 */
3827 //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr);
3828}
3829
3830
3831inline void write_phy_ofdm (struct net_device *dev, u8 adr, u32 data)
3832{
3833 data = data & 0xff;
3834 rtl8185_write_phy(dev, adr, data);
3835}
3836
3837
3838void write_phy_cck (struct net_device *dev, u8 adr, u32 data)
3839{
3840 data = data & 0xff;
3841 rtl8185_write_phy(dev, adr, data | 0x10000);
3842}
3843
3844
3845/* 70*3 = 210 ms
3846 * I hope this is enougth
3847 */
3848#define MAX_PHY 70
3849void write_phy(struct net_device *dev, u8 adr, u8 data)
3850{
3851 u32 phy;
3852 int i;
3853
3854 phy = 0xff0000;
3855 phy |= adr;
3856 phy |= 0x80; /* this should enable writing */
3857 phy |= (data<<8);
3858
3859 //PHY_ADR, PHY_R and PHY_W are contig and treated as one dword
3860 write_nic_dword(dev,PHY_ADR, phy);
3861
3862 phy= 0xffff00;
3863 phy |= adr;
3864
3865 write_nic_dword(dev,PHY_ADR, phy);
3866 for(i=0;i<MAX_PHY;i++){
3867 phy=read_nic_dword(dev,PHY_ADR);
3868 phy= phy & 0xff0000;
3869 phy= phy >> 16;
3870 if(phy == data){ //SUCCESS!
3871 force_pci_posting(dev);
3872 mdelay(3); //random value
c8d86be3
GKH		 3873 return;
3874 }else{
3875 force_pci_posting(dev);
3876 mdelay(3); //random value
3877 }
3878 }
3879 DMESGW ("Phy writing %x %x failed!", adr,data);
3880}
3881
3882void rtl8185_set_rate(struct net_device *dev)
3883{
3884 int i;
3885 u16 word;
3886 int basic_rate,min_rr_rate,max_rr_rate;
3887
3888// struct r8180_priv *priv = ieee80211_priv(dev);
3889
3890 //if (ieee80211_is_54g(priv->ieee80211->current_network) &&
3891// priv->ieee80211->state == IEEE80211_LINKED){
3892 basic_rate = ieeerate2rtlrate(240);
3893 min_rr_rate = ieeerate2rtlrate(60);
3894 max_rr_rate = ieeerate2rtlrate(240);
3895
3896//
3897// }else{
3898// basic_rate = ieeerate2rtlrate(20);
3899// min_rr_rate = ieeerate2rtlrate(10);
3900// max_rr_rate = ieeerate2rtlrate(110);
3901// }
3902
3903 write_nic_byte(dev, RESP_RATE,
3904 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3905
3906 word = read_nic_word(dev, BRSR);
3907 word &= ~BRSR_MBR_8185;
3908
3909
3910 for(i=0;i<=basic_rate;i++)
3911 word |= (1<<i);
3912
3913 write_nic_word(dev, BRSR, word);
3914 //DMESG("RR:%x BRSR: %x", read_nic_byte(dev,RESP_RATE),read_nic_word(dev,BRSR));
3915}
3916
3917
3918
3919void rtl8180_adapter_start(struct net_device *dev)
3920{
3921 struct r8180_priv *priv = ieee80211_priv(dev);
3922 u32 anaparam;
3923 u16 word;
3924 u8 config3;
3925// int i;
3926
3927 rtl8180_rtx_disable(dev);
3928 rtl8180_reset(dev);
3929
3930 /* seems that 0xffff or 0xafff will cause
3931 * HW interrupt line crash
3932 */
3933
3934 //priv->irq_mask = 0xafff;
3935// priv->irq_mask = 0x4fcf;
3936
3937 /* enable beacon timeout, beacon TX ok and err
3938 * LP tx ok and err, HP TX ok and err, NP TX ok and err,
3939 * RX ok and ERR, and GP timer */
3940 priv->irq_mask = 0x6fcf;
3941
3942 priv->dma_poll_mask = 0;
3943
3944 rtl8180_beacon_tx_disable(dev);
3945
3946 if(priv->card_type == CARDBUS ){
3947 config3=read_nic_byte(dev, CONFIG3);
3948 write_nic_byte(dev,CONFIG3,config3 | CONFIG3_FuncRegEn);
3949 write_nic_word(dev,FEMR, FEMR_INTR | FEMR_WKUP | FEMR_GWAKE |
3950 read_nic_word(dev, FEMR));
3951 }
3952 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3953 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
3954 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
3955 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3956
3957 rtl8180_update_msr(dev);
3958
3959 if(!priv->card_8185){
3960 anaparam = eprom_read(dev,EPROM_ANAPARAM_ADDRLWORD);
3961 anaparam |= eprom_read(dev,EPROM_ANAPARAM_ADDRHWORD)<<16;
3962
3963 rtl8180_set_anaparam(dev,anaparam);
3964 }
3965 /* These might be unnecessary since we do in rx_enable / tx_enable */
3966 fix_rx_fifo(dev);
3967 fix_tx_fifo(dev);
3968 /*set_nic_rxring(dev);
3969 set_nic_txring(dev);*/
3970
3971 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3972
3973 /*
3974 The following is very strange. seems to be that 1 means test mode,
3975 but we need to acknolwledges the nic when a packet is ready
3976 altought we set it to 0
3977 */
3978
3979 write_nic_byte(dev,
3980 CONFIG2, read_nic_byte(dev,CONFIG2) &~\
3981 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT));
3982 //^the nic isn't in test mode
3983 if(priv->card_8185)
3984 write_nic_byte(dev,
3985 CONFIG2, read_nic_byte(dev,CONFIG2)|(1<<4));
3986
3987 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3988
3989 write_nic_dword(dev,INT_TIMEOUT,0);
c8d86be3
GKH		 3990
3991 if(!priv->card_8185)
3992 {
3993 /*
3994 experimental - this might be needed to calibrate AGC,
3995 anyway it shouldn't hurt
3996 */
3997 write_nic_byte(dev, CONFIG5,
3998 read_nic_byte(dev, CONFIG5) | (1<<AGCRESET_SHIFT));
3999 read_nic_byte(dev, CONFIG5);
4000 udelay(15);
4001 write_nic_byte(dev, CONFIG5,
4002 read_nic_byte(dev, CONFIG5) &~ (1<<AGCRESET_SHIFT));
4003 }else{
4004
4005 write_nic_byte(dev, WPA_CONFIG, 0);
4006 //write_nic_byte(dev, TESTR, 0xd);
4007 }
4008
4009 rtl8180_no_hw_wep(dev);
4010
4011 if(priv->card_8185){
4012 rtl8185_set_rate(dev);
4013 write_nic_byte(dev, RATE_FALLBACK, 0x81);
4014 // write_nic_byte(dev, 0xdf, 0x15);
4015 }else{
4016 word = read_nic_word(dev, BRSR);
4017 word &= ~BRSR_MBR;
4018 word &= ~BRSR_BPLCP;
4019 word |= ieeerate2rtlrate(priv->ieee80211->basic_rate);
4020//by amy
4021 word |= 0x0f;
4022//by amy
4023 write_nic_word(dev, BRSR, word);
4024 }
4025
4026
4027 if(priv->card_8185){
4028 write_nic_byte(dev, GP_ENABLE,read_nic_byte(dev, GP_ENABLE) & ~(1<<6));
4029
4030 //FIXME cfg 3 ClkRun enable - isn't it ReadOnly ?
4031 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
4032 write_nic_byte(dev,CONFIG3, read_nic_byte(dev, CONFIG3)
4033|(1<<CONFIG3_CLKRUN_SHIFT));
4034 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
4035
4036 }
4037
4038 priv->rf_init(dev);
4039
4040 if(priv->rf_set_sens != NULL)
4041 priv->rf_set_sens(dev,priv->sens);
4042 rtl8180_irq_enable(dev);
4043
4044 netif_start_queue(dev);
4045 /*DMESG ("lfree %d",get_curr_tx_free_desc(dev,LOW_PRIORITY));
4046
4047 DMESG ("nfree %d",get_curr_tx_free_desc(dev,NORM_PRIORITY));
4048
4049 DMESG ("hfree %d",get_curr_tx_free_desc(dev,HI_PRIORITY));
4050 if(check_nic_enought_desc(dev,NORM_PRIORITY)) DMESG("NORM OK");
4051 if(check_nic_enought_desc(dev,HI_PRIORITY)) DMESG("HI OK");
4052 if(check_nic_enought_desc(dev,LOW_PRIORITY)) DMESG("LOW OK");*/
4053}
4054
4055
4056
4057/* this configures registers for beacon tx and enables it via
4058 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might
4059 * be used to stop beacon transmission
4060 */
4061void rtl8180_start_tx_beacon(struct net_device *dev)
4062{
4063// struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
4064 u16 word;
4065// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
4066
4067 DMESG("Enabling beacon TX");
4068 //write_nic_byte(dev, 0x42,0xe6);// TCR
4069// set_nic_txring(dev);
4070// fix_tx_fifo(dev);
4071 rtl8180_prepare_beacon(dev);
4072 rtl8180_irq_disable(dev);
4073 rtl8180_beacon_tx_enable(dev);
c8d86be3 4074
c8d86be3
GKH		 4075 word = read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd;
4076 write_nic_word(dev, AtimWnd,word);// word |=
4077//priv->ieee80211->current_network.atim_window);
4078
4079 word = read_nic_word(dev, BintrItv);
4080 word &= ~BintrItv_BintrItv;
4081 word |= 1000;/*priv->ieee80211->current_network.beacon_interval *
4082 ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
4083 // FIXME: check if correct ^^ worked with 0x3e8;
4084 */
4085 write_nic_word(dev, BintrItv, word);
4086
4087
4088 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
4089
4090// rtl8180_beacon_tx_enable(dev);
c8d86be3 4091 rtl8185b_irq_enable(dev);
c8d86be3
GKH		 4092 /* VV !!!!!!!!!! VV*/
4093 /*
4094 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
4095 write_nic_byte(dev,0x9d,0x00);
4096 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
4097*/
4098// DMESG("ring %x %x", priv->txlpringdma,read_nic_dword(dev,TLPDA));
4099
4100}
4101
4102
4103
4104/***************************************************************************
4105 -------------------------------NET STUFF---------------------------
4106***************************************************************************/
4107static struct net_device_stats *rtl8180_stats(struct net_device *dev)
4108{
4109 struct r8180_priv *priv = ieee80211_priv(dev);
4110
4111 return &priv->ieee80211->stats;
4112}
4113//
4114// Change current and default preamble mode.
4115// 2005.01.06, by rcnjko.
4116//
4117bool
4118MgntActSet_802_11_PowerSaveMode(
4119 struct r8180_priv *priv,
4120 RT_PS_MODE rtPsMode
4121)
4122{
4123
4124 // Currently, we do not change power save mode on IBSS mode.
4125 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
4126 {
4127 return false;
4128 }
4129
4130 //
4131 // <RJ_NOTE> If we make HW to fill up the PwrMgt bit for us,
4132 // some AP will not response to our mgnt frames with PwrMgt bit set,
4133 // e.g. cannot associate the AP.
4134 // So I commented out it. 2005.02.16, by rcnjko.
4135 //
4136// // Change device's power save mode.
4137// Adapter->HalFunc.SetPSModeHandler( Adapter, rtPsMode );
4138
4139 // Update power save mode configured.
4140// priv->dot11PowerSaveMode = rtPsMode;
4141 priv->ieee80211->ps = rtPsMode;
4142 // Determine ListenInterval.
5521a513 4143
c8d86be3
GKH		 4144 return true;
4145}
4146
4147//================================================================================
4148// Leisure Power Save in linked state.
4149//================================================================================
4150
4151//
4152// Description:
4153// Enter the leisure power save mode.
4154//
4155void
4156LeisurePSEnter(
4157 struct r8180_priv *priv
4158 )
4159{
4160 if (priv->bLeisurePs)
4161 {
4162 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED)
4163 {
4164 //printk("----Enter PS\n");
4165 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE
4166 }
4167 }
4168}
4169
4170
4171//
4172// Description:
4173// Leave the leisure power save mode.
4174//
4175void
4176LeisurePSLeave(
4177 struct r8180_priv *priv
4178 )
4179{
4180 if (priv->bLeisurePs)
4181 {
4182 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED)
4183 {
4184 //printk("----Leave PS\n");
4185 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
4186 }
4187 }
4188}
0370453f 4189
c8d86be3
GKH		 4190void rtl8180_hw_wakeup_wq (struct work_struct *work)
4191{
4192// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4193// struct ieee80211_device * ieee = (struct ieee80211_device*)
4194// container_of(work, struct ieee80211_device, watch_dog_wq);
bf6aede7 4195 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 4196 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
4197 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 4198
4199// printk("dev is %d\n",dev);
d599edca 4200// printk("&*&(^*(&(&=========>%s()\n", __func__);
c8d86be3
GKH		 4201 rtl8180_hw_wakeup(dev);
4202
4203}
4204
c8d86be3
GKH		 4205void rtl8180_hw_sleep_wq (struct work_struct *work)
4206{
4207// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4208// struct ieee80211_device * ieee = (struct ieee80211_device*)
4209// container_of(work, struct ieee80211_device, watch_dog_wq);
bf6aede7 4210 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 4211 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
4212 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 4213
4214 rtl8180_hw_sleep_down(dev);
4215}
4216
4217//YJ,add,080828,for KeepAlive
4218static void MgntLinkKeepAlive(struct r8180_priv *priv )
4219{
4220 if (priv->keepAliveLevel == 0)
4221 return;
4222
4223 if(priv->ieee80211->state == IEEE80211_LINKED)
4224 {
4225 //
4226 // Keep-Alive.
4227 //
4228 //printk("LastTx:%d Tx:%d LastRx:%d Rx:%ld Idle:%d\n",priv->link_detect.LastNumTxUnicast,priv->NumTxUnicast, priv->link_detect.LastNumRxUnicast, priv->ieee80211->NumRxUnicast, priv->link_detect.IdleCount);
4229
4230 if ( (priv->keepAliveLevel== 2) ||
4231 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast &&
4232 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast )
4233 )
4234 {
4235 priv->link_detect.IdleCount++;
4236
4237 //
4238 // Send a Keep-Alive packet packet to AP if we had been idle for a while.
4239 //
4240 if(priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1) )
4241 {
4242 priv->link_detect.IdleCount = 0;
4243 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false);
4244 }
4245 }
4246 else
4247 {
4248 priv->link_detect.IdleCount = 0;
4249 }
4250 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast;
4251 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast;
4252 }
4253}
4254//YJ,add,080828,for KeepAlive,end
4255
4256static u8 read_acadapter_file(char *filename);
4257void rtl8180_watch_dog(struct net_device *dev)
4258{
4259 struct r8180_priv *priv = ieee80211_priv(dev);
4260 bool bEnterPS = false;
4261 bool bBusyTraffic = false;
4262 u32 TotalRxNum = 0;
4263 u16 SlotIndex = 0;
4264 u16 i = 0;
4265#ifdef ENABLE_IPS
4266 if(priv->ieee80211->actscanning == false){
4267 if((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)){
4268 IPSEnter(dev);
4269 }
4270 }
4271#endif
4272 //YJ,add,080828,for link state check
4273 if((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)){
4274 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum;
4275 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod;
4276 for( i=0; i<priv->link_detect.SlotNum; i++ )
4277 TotalRxNum+= priv->link_detect.RxFrameNum[i];
4278 //printk("&&&&&=== TotalRxNum = %d\n", TotalRxNum);
4279 if(TotalRxNum == 0){
4280 priv->ieee80211->state = IEEE80211_ASSOCIATING;
4281 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
4282 }
4283 }
4284
4285 //YJ,add,080828,for KeepAlive
4286 MgntLinkKeepAlive(priv);
4287
4288 //YJ,add,080828,for LPS
4289#ifdef ENABLE_LPS
4290 if(priv->PowerProfile == POWER_PROFILE_BATTERY )
4291 {
4292 //Turn on LeisurePS on battery power
4293 //printk("!!!!!On battery power\n");
4294 priv->bLeisurePs = true;
4295 }
4296 else if(priv->PowerProfile == POWER_PROFILE_AC )
4297 {
4298 // Turn off LeisurePS on AC power
4299 //printk("----On AC power\n");
4300 LeisurePSLeave(priv);
4301 priv->bLeisurePs= false;
4302 }
4303#endif
4304
c8d86be3
GKH		 4305#ifdef ENABLE_LPS
4306 if(priv->ieee80211->state == IEEE80211_LINKED){
4307 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod;
4308 //printk("TxOk=%d RxOk=%d\n", priv->link_detect.NumTxOkInPeriod, priv->link_detect.NumRxOkInPeriod);
4309 if( priv->link_detect.NumRxOkInPeriod> 666 ||
4310 priv->link_detect.NumTxOkInPeriod> 666 ) {
4311 bBusyTraffic = true;
4312 }
4313 if(((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8)
4314 || (priv->link_detect.NumRxOkInPeriod > 2)) {
4315 bEnterPS= false;
4316 }
4317 else {
4318 bEnterPS= true;
4319 }
4320
4321 if(bEnterPS) {
4322 LeisurePSEnter(priv);
4323 }
4324 else {
4325 LeisurePSLeave(priv);
4326 }
4327 }
4328 else{
4329 LeisurePSLeave(priv);
4330 }
4331#endif
4332 priv->link_detect.bBusyTraffic = bBusyTraffic;
4333 priv->link_detect.NumRxOkInPeriod = 0;
4334 priv->link_detect.NumTxOkInPeriod = 0;
4335 priv->ieee80211->NumRxDataInPeriod = 0;
4336 priv->ieee80211->NumRxBcnInPeriod = 0;
c8d86be3
GKH		 4337}
4338int _rtl8180_up(struct net_device *dev)
4339{
4340 struct r8180_priv *priv = ieee80211_priv(dev);
4341 //int i;
4342
4343 priv->up=1;
4344
4345 DMESG("Bringing up iface");
c8d86be3
GKH		 4346 rtl8185b_adapter_start(dev);
4347 rtl8185b_rx_enable(dev);
4348 rtl8185b_tx_enable(dev);
c8d86be3
GKH		 4349#ifdef ENABLE_IPS
4350 if(priv->bInactivePs){
4351 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
4352 IPSLeave(dev);
4353 }
4354#endif
4355//by amy 080312
4356#ifdef RATE_ADAPT
4357 timer_rate_adaptive((unsigned long)dev);
4358#endif
4359//by amy 080312
4360 watch_dog_adaptive((unsigned long)dev);
4361#ifdef SW_ANTE
4362 if(priv->bSwAntennaDiverity)
4363 SwAntennaDiversityTimerCallback(dev);
4364#endif
4365// IPSEnter(dev);
4366 ieee80211_softmac_start_protocol(priv->ieee80211);
4367
4368//Add for RF power on power off by lizhaoming 080512
4369// priv->eRFPowerState = eRfOn;
4370// printk("\n--------Start queue_work:GPIOChangeRFWorkItem");
4371// queue_delayed_work(priv->ieee80211->wq,&priv->ieee80211->GPIOChangeRFWorkItem,1000);
4372
4373 return 0;
4374}
4375
4376
4377int rtl8180_open(struct net_device *dev)
4378{
4379 struct r8180_priv *priv = ieee80211_priv(dev);
4380 int ret;
4381
4382 down(&priv->wx_sem);
4383 ret = rtl8180_up(dev);
4384 up(&priv->wx_sem);
4385 return ret;
4386
4387}
4388
4389
4390int rtl8180_up(struct net_device *dev)
4391{
4392 struct r8180_priv *priv = ieee80211_priv(dev);
4393
4394 if (priv->up == 1) return -1;
4395
4396 return _rtl8180_up(dev);
4397}
4398
4399
4400int rtl8180_close(struct net_device *dev)
4401{
4402 struct r8180_priv *priv = ieee80211_priv(dev);
4403 int ret;
4404
4405 down(&priv->wx_sem);
4406 ret = rtl8180_down(dev);
4407 up(&priv->wx_sem);
4408
4409 return ret;
4410
4411}
4412
4413int rtl8180_down(struct net_device *dev)
4414{
4415 struct r8180_priv *priv = ieee80211_priv(dev);
4416
4417 if (priv->up == 0) return -1;
4418
4419 priv->up=0;
4420
4421 ieee80211_softmac_stop_protocol(priv->ieee80211);
4422 /* FIXME */
4423 if (!netif_queue_stopped(dev))
4424 netif_stop_queue(dev);
4425 rtl8180_rtx_disable(dev);
4426 rtl8180_irq_disable(dev);
4427 del_timer_sync(&priv->watch_dog_timer);
4428 //cancel_delayed_work(&priv->ieee80211->watch_dog_wq);
4429//{by amy 080312
4430 del_timer_sync(&priv->rateadapter_timer);
4431 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
4432//by amy 080312}
4433 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
4434 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
4435 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
4436 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
4437 del_timer_sync(&priv->SwAntennaDiversityTimer);
4438 SetZebraRFPowerState8185(dev,eRfOff);
4439 //ieee80211_softmac_stop_protocol(priv->ieee80211);
4440 memset(&(priv->ieee80211->current_network),0,sizeof(struct ieee80211_network));
4441 priv->ieee80211->state = IEEE80211_NOLINK;
4442 return 0;
4443}
4444
c8d86be3
GKH		 4445void rtl8180_restart_wq(struct work_struct *work)
4446{
4447 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
4448 struct net_device *dev = priv->dev;
0370453f 4449
c8d86be3
GKH		 4450 down(&priv->wx_sem);
4451
4452 rtl8180_commit(dev);
4453
4454 up(&priv->wx_sem);
4455}
4456
4457void rtl8180_restart(struct net_device *dev)
4458{
4459 struct r8180_priv *priv = ieee80211_priv(dev);
4460 //rtl8180_commit(dev);
4461 schedule_work(&priv->reset_wq);
4462 //DMESG("TXTIMEOUT");
4463}
4464
4465
4466void rtl8180_commit(struct net_device *dev)
4467{
4468 struct r8180_priv *priv = ieee80211_priv(dev);
4469
4470 if (priv->up == 0) return ;
4471//+by amy 080312
4472 del_timer_sync(&priv->watch_dog_timer);
4473 //cancel_delayed_work(&priv->ieee80211->watch_dog_wq);
4474//{by amy 080312
4475//by amy for rate adaptive
4476 del_timer_sync(&priv->rateadapter_timer);
4477 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
4478//by amy for rate adaptive
4479//by amy 080312}
4480 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
4481 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
4482 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
4483 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
4484 del_timer_sync(&priv->SwAntennaDiversityTimer);
4485 ieee80211_softmac_stop_protocol(priv->ieee80211);
4486 rtl8180_irq_disable(dev);
4487 rtl8180_rtx_disable(dev);
4488 _rtl8180_up(dev);
4489}
4490
4491
4492static void r8180_set_multicast(struct net_device *dev)
4493{
4494 struct r8180_priv *priv = ieee80211_priv(dev);
4495 short promisc;
4496
4497 //down(&priv->wx_sem);
4498
4499 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
4500
4501 if (promisc != priv->promisc)
4502 rtl8180_restart(dev);
4503
4504 priv->promisc = promisc;
4505
4506 //up(&priv->wx_sem);
4507}
4508
c8d86be3
GKH		 4509int r8180_set_mac_adr(struct net_device *dev, void *mac)
4510{
4511 struct r8180_priv *priv = ieee80211_priv(dev);
4512 struct sockaddr *addr = mac;
4513
4514 down(&priv->wx_sem);
4515
4516 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
4517
4518 if(priv->ieee80211->iw_mode == IW_MODE_MASTER)
4519 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN);
4520
4521 if (priv->up) {
4522 rtl8180_down(dev);
4523 rtl8180_up(dev);
4524 }
4525
4526 up(&priv->wx_sem);
4527
4528 return 0;
4529}
4530
4531/* based on ipw2200 driver */
4532int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4533{
4534 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
4535
4536 struct iwreq *wrq = (struct iwreq *) rq;
4537 int ret=-1;
4538 switch (cmd) {
4539 case RTL_IOCTL_WPA_SUPPLICANT:
4540 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
4541 return ret;
4542
4543 default:
4544 return -EOPNOTSUPP;
4545 }
4546
4547 return -EOPNOTSUPP;
4548}
4549
4550
4551
4552/****************************************************************************
4553 -----------------------------PCI STUFF---------------------------
4554*****************************************************************************/
4555
727ae303
AB		 4556static const struct net_device_ops rtl8180_netdev_ops = {
4557 .ndo_open = rtl8180_open,
4558 .ndo_stop = rtl8180_close,
4559 .ndo_get_stats = rtl8180_stats,
4560 .ndo_tx_timeout = rtl8180_restart,
4561 .ndo_do_ioctl = rtl8180_ioctl,
4562 .ndo_set_multicast_list = r8180_set_multicast,
4563 .ndo_set_mac_address = r8180_set_mac_adr,
4564 .ndo_validate_addr = eth_validate_addr,
4565 .ndo_change_mtu = eth_change_mtu,
4566 .ndo_start_xmit = ieee80211_xmit,
4567};
c8d86be3
GKH		 4568
4569static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
4570 const struct pci_device_id *id)
4571{
4572 unsigned long ioaddr = 0;
4573 struct net_device *dev = NULL;
4574 struct r8180_priv *priv= NULL;
4575 //u8 *ptr;
4576 u8 unit = 0;
4577
c8d86be3 4578 unsigned long pmem_start, pmem_len, pmem_flags;
c8d86be3
GKH		 4579
4580 DMESG("Configuring chip resources");
4581
4582 if( pci_enable_device (pdev) ){
4583 DMESG("Failed to enable PCI device");
4584 return -EIO;
4585 }
4586
4587 pci_set_master(pdev);
4588 //pci_set_wmi(pdev);
4589 pci_set_dma_mask(pdev, 0xffffff00ULL);
4590 pci_set_consistent_dma_mask(pdev,0xffffff00ULL);
4591 dev = alloc_ieee80211(sizeof(struct r8180_priv));
4592 if (!dev)
4593 return -ENOMEM;
4594 priv = ieee80211_priv(dev);
4595 priv->ieee80211 = netdev_priv(dev);
4596
c8d86be3
GKH		 4597 pci_set_drvdata(pdev, dev);
4598 SET_NETDEV_DEV(dev, &pdev->dev);
4599
4600 priv = ieee80211_priv(dev);
4601// memset(priv,0,sizeof(struct r8180_priv));
4602 priv->pdev=pdev;
4603
4604
c8d86be3
GKH		 4605
4606 pmem_start = pci_resource_start(pdev, 1);
4607 pmem_len = pci_resource_len(pdev, 1);
4608 pmem_flags = pci_resource_flags (pdev, 1);
4609
4610 if (!(pmem_flags & IORESOURCE_MEM)) {
4611 DMESG("region #1 not a MMIO resource, aborting");
4612 goto fail;
4613 }
4614
4615 //DMESG("Memory mapped space @ 0x%08lx ", pmem_start);
4616 if( ! request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) {
4617 DMESG("request_mem_region failed!");
4618 goto fail;
4619 }
4620
4621
4622 ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len);
4623 if( ioaddr == (unsigned long)NULL ){
4624 DMESG("ioremap failed!");
4625 // release_mem_region( pmem_start, pmem_len );
4626 goto fail1;
4627 }
4628
4629 dev->mem_start = ioaddr; // shared mem start
4630 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
4631
c8d86be3 4632
c8d86be3
GKH		 4633 //pci_read_config_byte(pdev, 0x05, ptr);
4634 //pci_write_config_byte(pdev, 0x05, (*ptr) & (~0x04));
4635 pci_read_config_byte(pdev, 0x05, &unit);
4636 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
c8d86be3
GKH		 4637
4638 dev->irq = pdev->irq;
4639 priv->irq = 0;
4640
727ae303 4641 dev->netdev_ops = &rtl8180_netdev_ops;
c8d86be3 4642 dev->wireless_handlers = &r8180_wx_handlers_def;
c8d86be3 4643
c8d86be3
GKH		 4644 dev->type=ARPHRD_ETHER;
4645 dev->watchdog_timeo = HZ*3; //added by david woo, 2007.12.13
4646
4647 if (dev_alloc_name(dev, ifname) < 0){
4648 DMESG("Oops: devname already taken! Trying wlan%%d...\n");
4649 ifname = "wlan%d";
4650 // ifname = "ath%d";
4651 dev_alloc_name(dev, ifname);
4652 }
4653
4654
4655 if(rtl8180_init(dev)!=0){
4656 DMESG("Initialization failed");
4657 goto fail1;
4658 }
4659
4660 netif_carrier_off(dev);
4661
4662 register_netdev(dev);
4663
4664 rtl8180_proc_init_one(dev);
4665
4666 DMESG("Driver probe completed\n");
4667 return 0;
4668
4669fail1:
4670
c8d86be3
GKH		 4671 if( dev->mem_start != (unsigned long)NULL ){
4672 iounmap( (void *)dev->mem_start );
4673 release_mem_region( pci_resource_start(pdev, 1),
4674 pci_resource_len(pdev, 1) );
4675 }
c8d86be3
GKH		 4676
4677
4678fail:
4679 if(dev){
4680
4681 if (priv->irq) {
4682 free_irq(dev->irq, dev);
4683 dev->irq=0;
4684 }
4685 free_ieee80211(dev);
4686 }
4687
4688 pci_disable_device(pdev);
4689
4690 DMESG("wlan driver load failed\n");
4691 pci_set_drvdata(pdev, NULL);
4692 return -ENODEV;
4693
4694}
4695
4696
4697static void __devexit rtl8180_pci_remove(struct pci_dev *pdev)
4698{
4699 struct r8180_priv *priv;
4700 struct net_device *dev = pci_get_drvdata(pdev);
4701 if(dev){
4702
4703 unregister_netdev(dev);
4704
4705 priv=ieee80211_priv(dev);
4706
4707 rtl8180_proc_remove_one(dev);
4708 rtl8180_down(dev);
4709 priv->rf_close(dev);
4710 rtl8180_reset(dev);
4711 //rtl8180_rtx_disable(dev);
4712 //rtl8180_irq_disable(dev);
4713 mdelay(10);
4714 //write_nic_word(dev,INTA,read_nic_word(dev,INTA));
4715 //force_pci_posting(dev);
4716 //mdelay(10);
4717
4718 if(priv->irq){
4719
4720 DMESG("Freeing irq %d",dev->irq);
4721 free_irq(dev->irq, dev);
4722 priv->irq=0;
4723
4724 }
4725
4726 free_rx_desc_ring(dev);
4727 free_tx_desc_rings(dev);
4728 // free_beacon_desc_ring(dev,priv->txbeaconcount);
4729
c8d86be3
GKH		 4730 if( dev->mem_start != (unsigned long)NULL ){
4731 iounmap( (void *)dev->mem_start );
4732 release_mem_region( pci_resource_start(pdev, 1),
4733 pci_resource_len(pdev, 1) );
4734 }
c8d86be3
GKH		 4735
4736 free_ieee80211(dev);
4737 }
4738 pci_disable_device(pdev);
4739
4740 DMESG("wlan driver removed\n");
4741}
4742
4743
4744/* fun with the built-in ieee80211 stack... */
4745extern int ieee80211_crypto_init(void);
4746extern void ieee80211_crypto_deinit(void);
4747extern int ieee80211_crypto_tkip_init(void);
4748extern void ieee80211_crypto_tkip_exit(void);
4749extern int ieee80211_crypto_ccmp_init(void);
4750extern void ieee80211_crypto_ccmp_exit(void);
4751extern int ieee80211_crypto_wep_init(void);
4752extern void ieee80211_crypto_wep_exit(void);
4753
4754static int __init rtl8180_pci_module_init(void)
4755{
4756 int ret;
4757
4758 ret = ieee80211_crypto_init();
4759 if (ret) {
4760 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret);
4761 return ret;
4762 }
4763 ret = ieee80211_crypto_tkip_init();
4764 if (ret) {
4765 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret);
4766 return ret;
4767 }
4768 ret = ieee80211_crypto_ccmp_init();
4769 if (ret) {
4770 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret);
4771 return ret;
4772 }
4773 ret = ieee80211_crypto_wep_init();
4774 if (ret) {
4775 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret);
4776 return ret;
4777 }
4778
4779 printk(KERN_INFO "\nLinux kernel driver for RTL8180 \
4780/ RTL8185 based WLAN cards\n");
4781 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n");
4782 DMESG("Initializing module");
4783 DMESG("Wireless extensions version %d", WIRELESS_EXT);
4784 rtl8180_proc_module_init();
4785
c8d86be3 4786 if(0!=pci_register_driver(&rtl8180_pci_driver))
c8d86be3
GKH		 4787 //if(0!=pci_module_init(&rtl8180_pci_driver))
4788 {
4789 DMESG("No device found");
4790 /*pci_unregister_driver (&rtl8180_pci_driver);*/
4791 return -ENODEV;
4792 }
4793 return 0;
4794}
4795
4796
4797static void __exit rtl8180_pci_module_exit(void)
4798{
4799 pci_unregister_driver (&rtl8180_pci_driver);
4800 rtl8180_proc_module_remove();
c8d86be3
GKH		 4801 ieee80211_crypto_tkip_exit();
4802 ieee80211_crypto_ccmp_exit();
4803 ieee80211_crypto_wep_exit();
096c55d1 4804 ieee80211_crypto_deinit();
c8d86be3
GKH		 4805 DMESG("Exiting");
4806}
4807
4808
4809void rtl8180_try_wake_queue(struct net_device *dev, int pri)
4810{
4811 unsigned long flags;
4812 short enough_desc;
4813 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
4814
4815 spin_lock_irqsave(&priv->tx_lock,flags);
4816 enough_desc = check_nic_enought_desc(dev,pri);
4817 spin_unlock_irqrestore(&priv->tx_lock,flags);
4818
4819 if(enough_desc)
4820 ieee80211_wake_queue(priv->ieee80211);
4821}
4822
4823/*****************************************************************************
4824 -----------------------------IRQ STUFF---------------------------
4825******************************************************************************/
4826
4827void rtl8180_tx_isr(struct net_device *dev, int pri,short error)
4828{
4829 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
4830
4831 u32 *tail; //tail virtual addr
4832 u32 *head; //head virtual addr
4833 u32 *begin;//start of ring virtual addr
4834 u32 *nicv; //nic pointer virtual addr
4835// u32 *txdv; //packet just TXed
4836 u32 nic; //nic pointer physical addr
4837 u32 nicbegin;// start of ring physical addr
4838// short txed;
4839 unsigned long flag;
4840 /* physical addr are ok on 32 bits since we set DMA mask*/
4841
4842 int offs;
4843 int j,i;
4844 int hd;
4845 if (error) priv->stats.txretry++; //tony 20060601
4846 spin_lock_irqsave(&priv->tx_lock,flag);
4847 switch(pri) {
4848 case MANAGE_PRIORITY:
4849 tail = priv->txmapringtail;
4850 begin = priv->txmapring;
4851 head = priv->txmapringhead;
4852 nic = read_nic_dword(dev,TX_MANAGEPRIORITY_RING_ADDR);
4853 nicbegin = priv->txmapringdma;
4854 break;
4855
4856 case BK_PRIORITY:
4857 tail = priv->txbkpringtail;
4858 begin = priv->txbkpring;
4859 head = priv->txbkpringhead;
4860 nic = read_nic_dword(dev,TX_BKPRIORITY_RING_ADDR);
4861 nicbegin = priv->txbkpringdma;
4862 break;
4863
4864 case BE_PRIORITY:
4865 tail = priv->txbepringtail;
4866 begin = priv->txbepring;
4867 head = priv->txbepringhead;
4868 nic = read_nic_dword(dev,TX_BEPRIORITY_RING_ADDR);
4869 nicbegin = priv->txbepringdma;
4870 break;
4871
4872 case VI_PRIORITY:
4873 tail = priv->txvipringtail;
4874 begin = priv->txvipring;
4875 head = priv->txvipringhead;
4876 nic = read_nic_dword(dev,TX_VIPRIORITY_RING_ADDR);
4877 nicbegin = priv->txvipringdma;
4878 break;
4879
4880 case VO_PRIORITY:
4881 tail = priv->txvopringtail;
4882 begin = priv->txvopring;
4883 head = priv->txvopringhead;
4884 nic = read_nic_dword(dev,TX_VOPRIORITY_RING_ADDR);
4885 nicbegin = priv->txvopringdma;
4886 break;
4887
4888 case HI_PRIORITY:
4889 tail = priv->txhpringtail;
4890 begin = priv->txhpring;
4891 head = priv->txhpringhead;
4892 nic = read_nic_dword(dev,TX_HIGHPRIORITY_RING_ADDR);
4893 nicbegin = priv->txhpringdma;
4894 break;
4895
4896 default:
4897 spin_unlock_irqrestore(&priv->tx_lock,flag);
4898 return ;
4899 }
4900/* DMESG("%x %s %x %x",((int)nic & 0xfff)/8/4,
4901 *(priv->txnpring + ((int)nic&0xfff)/4/8) & (1<<31) ? "filled" : "empty",
4902 (priv->txnpringtail - priv->txnpring)/8,(priv->txnpringhead -
4903priv->txnpring)/8);
4904*/
4905 //nicv = (u32*) ((nic - nicbegin) + (int)begin);
4906 nicv = (u32*) ((nic - nicbegin) + (u8*)begin);
4907 if((head <= tail && (nicv > tail || nicv < head)) ||
4908 (head > tail && (nicv > tail && nicv < head))){
c8d86be3 4909 DMESGW("nic has lost pointer");
c8d86be3
GKH		 4910 spin_unlock_irqrestore(&priv->tx_lock,flag);
4911 rtl8180_restart(dev);
4912 return;
4913 }
4914
4915 /* we check all the descriptors between the head and the nic,
4916 * but not the currenly pointed by the nic (the next to be txed)
4917 * and the previous of the pointed (might be in process ??)
4918 */
4919 //if (head == nic) return;
4920 //DMESG("%x %x",head,nic);
4921 offs = (nic - nicbegin);
4922 //DMESG("%x %x %x",nic ,(u32)nicbegin, (int)nic -nicbegin);
4923
4924 offs = offs / 8 /4;
4925
4926 hd = (head - begin) /8;
4927
4928 if(offs >= hd)
4929 j = offs - hd;
4930 else
4931 j = offs + (priv->txringcount -1 -hd);
4932 // j= priv->txringcount -1- (hd - offs);
4933
4934 j-=2;
4935 if(j<0) j=0;
4936
4937
4938 for(i=0;i<j;i++)
4939 {
4940// printk("+++++++++++++check status desc\n");
4941 if((*head) & (1<<31))
4942 break;
4943 if(((*head)&(0x10000000)) != 0){
4944// printk("++++++++++++++last desc,retry count is %d\n",((*head) & (0x000000ff)));
4945 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff));
4946#if 1
4947 if(!error)
4948 {
4949 priv->NumTxOkTotal++;
4950// printk("NumTxOkTotal is %d\n",priv->NumTxOkTotal++);
4951 }
4952#endif
d599edca 4953 // printk("in function %s:curr_retry_count is %d\n",__func__,((*head) & (0x000000ff)));
c8d86be3
GKH		 4954 }
4955 if(!error){
4956 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff);
4957 }
d599edca 4958// printk("in function %s:curr_txokbyte_count is %d\n",__func__,(*(head+3)) & (0x00000fff));
c8d86be3
GKH		 4959 *head = *head &~ (1<<31);
4960
4961 if((head - begin)/8 == priv->txringcount-1)
4962 head=begin;
4963
4964 else
4965 head+=8;
4966 }
c8d86be3 4967
c8d86be3
GKH		 4968 //DMESG("%x",txdv[0]);
4969 /* the head has been moved to the last certainly TXed
4970 * (or at least processed by the nic) packet.
4971 * The driver take forcefully owning of all these packets
4972 * If the packet previous of the nic pointer has been
4973 * processed this doesn't matter: it will be checked
4974 * here at the next round. Anyway if no more packet are
4975 * TXed no memory leak occour at all.
4976 */
4977
4978 switch(pri) {
4979 case MANAGE_PRIORITY:
4980 priv->txmapringhead = head;
4981 //printk("1==========================================> priority check!\n");
4982 if(priv->ack_tx_to_ieee){
4983 // try to implement power-save mode 2008.1.22
4984 // printk("2==========================================> priority check!\n");
4985#if 1
4986 if(rtl8180_is_tx_queue_empty(dev)){
4987 // printk("tx queue empty, after send null sleep packet, try to sleep !\n");
4988 priv->ack_tx_to_ieee = 0;
4989 ieee80211_ps_tx_ack(priv->ieee80211,!error);
4990 }
4991#endif
4992 }
4993 break;
4994
4995 case BK_PRIORITY:
4996 priv->txbkpringhead = head;
4997 break;
4998
4999 case BE_PRIORITY:
5000 priv->txbepringhead = head;
5001 break;
5002
5003 case VI_PRIORITY:
5004 priv->txvipringhead = head;
5005 break;
5006
5007 case VO_PRIORITY:
5008 priv->txvopringhead = head;
5009 break;
5010
5011 case HI_PRIORITY:
5012 priv->txhpringhead = head;
5013 break;
5014 }
5015
5016 /*DMESG("%x %x %x", (priv->txnpringhead - priv->txnpring) /8 ,
5017 (priv->txnpringtail - priv->txnpring) /8,
5018 offs );
5019 */
5020
5021 spin_unlock_irqrestore(&priv->tx_lock,flag);
5022
5023}
5024
c8d86be3
GKH		 5025void rtl8180_tx_irq_wq(struct work_struct *work)
5026{
5027 //struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
bf6aede7 5028 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 5029 struct ieee80211_device * ieee = (struct ieee80211_device*)
5030 container_of(dwork, struct ieee80211_device, watch_dog_wq);
5031 struct net_device *dev = ieee->dev;
0370453f 5032
c8d86be3
GKH		 5033 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
5034}
5035irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs)
5036{
5037 struct net_device *dev = (struct net_device *) netdev;
5038 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
5039 unsigned long flags;
5040 u32 inta;
5041
5042 /* We should return IRQ_NONE, but for now let me keep this */
5043 if(priv->irq_enabled == 0) return IRQ_HANDLED;
5044
5045 spin_lock_irqsave(&priv->irq_th_lock,flags);
5046
c8d86be3
GKH		 5047 //ISR: 4bytes
5048 inta = read_nic_dword(dev, ISR);// & priv->IntrMask;
5049 write_nic_dword(dev,ISR,inta); // reset int situation
c8d86be3
GKH		 5050
5051 priv->stats.shints++;
5052
5053 //DMESG("Enter interrupt, ISR value = 0x%08x", inta);
5054
5055 if(!inta){
5056 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
5057 return IRQ_HANDLED;
5058 /*
5059 most probably we can safely return IRQ_NONE,
5060 but for now is better to avoid problems
5061 */
5062 }
5063
5064 if(inta == 0xffff){
5065 /* HW disappared */
5066 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
5067 return IRQ_HANDLED;
5068 }
5069
5070 priv->stats.ints++;
c8d86be3
GKH		 5071 //priv->irqpending = inta;
5072
5073
5074 if(!netif_running(dev)) {
5075 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
5076 return IRQ_HANDLED;
5077 }
5078
5079 if(inta & ISR_TimeOut){
5080 write_nic_dword(dev, TimerInt, 0);
5081 //DMESG("=================>waking up");
5082// rtl8180_hw_wakeup(dev);
5083 }
5084
5085 if(inta & ISR_TBDOK){
5086 priv->stats.txbeacon++;
5087 }
5088
5089 if(inta & ISR_TBDER){
5090 priv->stats.txbeaconerr++;
5091 }
5092
5093 if(inta & IMR_TMGDOK ) {
5094// priv->NumTxOkTotal++;
5095 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
5096// schedule_work(&priv->tx_irq_wq);
5097
5098 }
5099
5100 if(inta & ISR_THPDER){
c8d86be3
GKH		 5101 priv->stats.txhperr++;
5102 rtl8180_tx_isr(dev,HI_PRIORITY,1);
5103 priv->ieee80211->stats.tx_errors++;
5104 }
5105
5106 if(inta & ISR_THPDOK){ //High priority tx ok
c8d86be3
GKH		 5107// priv->NumTxOkTotal++;
5108 //priv->NumTxOkInPeriod++; //YJ,del,080828
5109 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
5110 priv->stats.txhpokint++;
5111 rtl8180_tx_isr(dev,HI_PRIORITY,0);
5112 }
5113
5114 if(inta & ISR_RER) {
5115 priv->stats.rxerr++;
c8d86be3 5116 }
c8d86be3
GKH		 5117 if(inta & ISR_TBKDER){ //corresponding to BK_PRIORITY
5118 priv->stats.txbkperr++;
5119 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH		 5120 //tasklet_schedule(&priv->irq_tx_tasklet);
5121 rtl8180_tx_isr(dev,BK_PRIORITY,1);
5122 rtl8180_try_wake_queue(dev, BE_PRIORITY);
5123 }
5124
5125 if(inta & ISR_TBEDER){ //corresponding to BE_PRIORITY
5126 priv->stats.txbeperr++;
5127 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH		 5128 rtl8180_tx_isr(dev,BE_PRIORITY,1);
5129 //tasklet_schedule(&priv->irq_tx_tasklet);
5130 rtl8180_try_wake_queue(dev, BE_PRIORITY);
5131 }
c8d86be3
GKH		 5132 if(inta & ISR_TNPDER){ //corresponding to VO_PRIORITY
5133 priv->stats.txnperr++;
5134 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH		 5135 //tasklet_schedule(&priv->irq_tx_tasklet);
5136 rtl8180_tx_isr(dev,NORM_PRIORITY,1);
c8d86be3 5137 rtl8180_try_wake_queue(dev, NORM_PRIORITY);
c8d86be3
GKH		 5138 }
5139
5140 if(inta & ISR_TLPDER){ //corresponding to VI_PRIORITY
5141 priv->stats.txlperr++;
5142 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH		 5143 rtl8180_tx_isr(dev,LOW_PRIORITY,1);
5144 //tasklet_schedule(&priv->irq_tx_tasklet);
5145 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
5146 }
5147
5148 if(inta & ISR_ROK){
c8d86be3
GKH		 5149 //priv->NumRxOkInPeriod++; //YJ,del,080828
5150 priv->stats.rxint++;
5151 tasklet_schedule(&priv->irq_rx_tasklet);
5152 }
5153
5154 if(inta & ISR_RQoSOK ){
c8d86be3
GKH		 5155 //priv->NumRxOkInPeriod++; //YJ,del,080828
5156 priv->stats.rxint++;
5157 tasklet_schedule(&priv->irq_rx_tasklet);
5158 }
5159 if(inta & ISR_BcnInt) {
5160 //DMESG("Preparing Beacons");
5161 rtl8180_prepare_beacon(dev);
5162 }
5163
5164 if(inta & ISR_RDU){
c8d86be3
GKH		 5165 DMESGW("No RX descriptor available");
5166 priv->stats.rxrdu++;
c8d86be3
GKH		 5167 tasklet_schedule(&priv->irq_rx_tasklet);
5168 /*queue_work(priv->workqueue ,&priv->restart_work);*/
5169
5170 }
5171 if(inta & ISR_RXFOVW){
c8d86be3
GKH		 5172 priv->stats.rxoverflow++;
5173 tasklet_schedule(&priv->irq_rx_tasklet);
5174 //queue_work(priv->workqueue ,&priv->restart_work);
5175 }
5176
5177 if(inta & ISR_TXFOVW) priv->stats.txoverflow++;
5178
5179 if(inta & ISR_TNPDOK){ //Normal priority tx ok
c8d86be3
GKH		 5180// priv->NumTxOkTotal++;
5181 //priv->NumTxOkInPeriod++; //YJ,del,080828
5182 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
5183 // priv->ieee80211->stats.tx_packets++;
5184 priv->stats.txnpokint++;
5185 rtl8180_tx_isr(dev,NORM_PRIORITY,0);
5186 }
5187
5188 if(inta & ISR_TLPDOK){ //Low priority tx ok
c8d86be3
GKH		 5189// priv->NumTxOkTotal++;
5190 //priv->NumTxOkInPeriod++; //YJ,del,080828
5191 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
5192 // priv->ieee80211->stats.tx_packets++;
5193 priv->stats.txlpokint++;
5194 rtl8180_tx_isr(dev,LOW_PRIORITY,0);
5195 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
5196 }
5197
c8d86be3
GKH		 5198 if(inta & ISR_TBKDOK){ //corresponding to BK_PRIORITY
5199 priv->stats.txbkpokint++;
c8d86be3
GKH		 5200// priv->NumTxOkTotal++;
5201 //priv->NumTxOkInPeriod++; //YJ,del,080828
5202 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
5203 rtl8180_tx_isr(dev,BK_PRIORITY,0);
5204 rtl8180_try_wake_queue(dev, BE_PRIORITY);
5205 }
5206
5207 if(inta & ISR_TBEDOK){ //corresponding to BE_PRIORITY
5208 priv->stats.txbeperr++;
c8d86be3
GKH		 5209// priv->NumTxOkTotal++;
5210 //priv->NumTxOkInPeriod++; //YJ,del,080828
5211 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
5212 rtl8180_tx_isr(dev,BE_PRIORITY,0);
5213 rtl8180_try_wake_queue(dev, BE_PRIORITY);
5214 }
c8d86be3
GKH		 5215 force_pci_posting(dev);
5216 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
5217
5218 return IRQ_HANDLED;
5219}
5220
5221
5222void rtl8180_irq_rx_tasklet(struct r8180_priv* priv)
5223{
5224// unsigned long flags;
5225
5226/* spin_lock_irqsave(&priv->irq_lock, flags);
5227 priv->irq_mask &=~IMR_ROK;
5228 priv->irq_mask &=~IMR_RDU;
5229
5230 rtl8180_irq_enable(priv->dev);
5231 spin_unlock_irqrestore(&priv->irq_lock, flags);
5232*/
5233 rtl8180_rx(priv->dev);
5234
5235/* spin_lock_irqsave(&priv->irq_lock, flags);
5236 priv->irq_mask |= IMR_ROK;
5237 priv->irq_mask |= IMR_RDU;
5238 rtl8180_irq_enable(priv->dev);
5239 spin_unlock_irqrestore(&priv->irq_lock, flags);
5240*/
5241}
5242
5243/****************************************************************************
5244lizhaoming--------------------------- RF power on/power off -----------------
5245*****************************************************************************/
5246
c8d86be3
GKH		 5247void GPIOChangeRFWorkItemCallBack(struct work_struct *work)
5248{
bf6aede7 5249 //struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 5250 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work);
5251 struct net_device *dev = ieee->dev;
5252 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 5253
5254 //u16 tmp2byte;
5255 u8 btPSR;
5256 u8 btConfig0;
5257 RT_RF_POWER_STATE eRfPowerStateToSet;
5258 bool bActuallySet=false;
5259
5260 char *argv[3];
5261 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh";
5262 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL};
5263 static int readf_count = 0;
5264 //printk("============>%s in \n", __func__);
5265
5266#ifdef ENABLE_LPS
5267 if(readf_count % 10 == 0)
5268 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state");
5269
5270 readf_count = (readf_count+1)%0xffff;
c8d86be3
GKH		 5271#endif
5272 {
5273 // We should turn off LED before polling FF51[4].
5274
5275 //Turn off LED.
5276 btPSR = read_nic_byte(dev, PSR);
5277 write_nic_byte(dev, PSR, (btPSR & ~BIT3));
5278
5279 //It need to delay 4us suggested by Jong, 2008-01-16
5280 udelay(4);
5281
5282 //HW radio On/Off according to the value of FF51[4](config0)
5283 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0);
5284
5285 //Turn on LED.
5286 write_nic_byte(dev, PSR, btPSR| BIT3);
5287
5288 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;
5289
5290 if((priv->ieee80211->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
5291 {
5292 priv->ieee80211->bHwRadioOff = false;
5293 bActuallySet = true;
5294 }
5295 else if((priv->ieee80211->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
5296 {
5297 priv->ieee80211->bHwRadioOff = true;
5298 bActuallySet = true;
5299 }
5300
5301 if(bActuallySet)
5302 {
5303 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
5304
5305 /* To update the UI status for Power status changed */
5306 if(priv->ieee80211->bHwRadioOff == true)
5307 argv[1] = "RFOFF";
5308 else{
5309 //if(!priv->RfOffReason)
5310 argv[1] = "RFON";
5311 //else
5312 // argv[1] = "RFOFF";
5313 }
5314 argv[0] = RadioPowerPath;
5315 argv[2] = NULL;
5316
5317 call_usermodehelper(RadioPowerPath,argv,envp,1);
5318 }
5319
5320 }
5321
5322}
5323
5324static u8 read_acadapter_file(char *filename)
5325{
c8d86be3
GKH		 5326 return 0;
5327}
5328
5329/***************************************************************************
5330 ------------------- module init / exit stubs ----------------
5331****************************************************************************/
5332module_init(rtl8180_pci_module_init);
5333module_exit(rtl8180_pci_module_exit);
5334
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