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Commit | Line | Data |
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c8d86be3 GKH |
1 | /* |
2 | This is part of rtl818x pci OpenSource driver - v 0.1 | |
3 | Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> | |
4 | Released under the terms of GPL (General Public License) | |
5 | ||
6 | Parts of this driver are based on the GPL part of the official | |
7 | Realtek driver. | |
8 | ||
9 | Parts of this driver are based on the rtl8180 driver skeleton | |
10 | from Patric Schenke & Andres Salomon. | |
11 | ||
12 | Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. | |
13 | ||
14 | Parts of BB/RF code are derived from David Young rtl8180 netbsd driver. | |
15 | ||
16 | RSSI calc function from 'The Deuce' | |
17 | ||
18 | Some ideas borrowed from the 8139too.c driver included in linux kernel. | |
19 | ||
20 | We (I?) want to thanks the Authors of those projecs and also the | |
21 | Ndiswrapper's project Authors. | |
22 | ||
23 | A big big thanks goes also to Realtek corp. for their help in my attempt to | |
24 | add RTL8185 and RTL8225 support, and to David Young also. | |
b6d11c07 BZ |
25 | |
26 | Power management interface routines. | |
27 | Written by Mariusz Matuszek. | |
c8d86be3 GKH |
28 | */ |
29 | ||
c8d86be3 | 30 | #undef RX_DONT_PASS_UL |
c8d86be3 | 31 | #undef DUMMY_RX |
c8d86be3 | 32 | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
c8d86be3 | 34 | #include <linux/syscalls.h> |
742821ce | 35 | #include <linux/eeprom_93cx6.h> |
fd882783 | 36 | |
c8d86be3 GKH |
37 | #include "r8180_hw.h" |
38 | #include "r8180.h" | |
c8d86be3 | 39 | #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */ |
c8d86be3 GKH |
40 | #include "r8180_93cx6.h" /* Card EEPROM */ |
41 | #include "r8180_wx.h" | |
42 | #include "r8180_dm.h" | |
43 | ||
fd9b8d6e | 44 | #include "ieee80211/dot11d.h" |
c8d86be3 | 45 | |
c8d86be3 GKH |
46 | static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = { |
47 | { | |
48 | .vendor = PCI_VENDOR_ID_REALTEK, | |
c8d86be3 GKH |
49 | .device = 0x8199, |
50 | .subvendor = PCI_ANY_ID, | |
51 | .subdevice = PCI_ANY_ID, | |
52 | .driver_data = 0, | |
53 | }, | |
c8d86be3 GKH |
54 | { |
55 | .vendor = 0, | |
56 | .device = 0, | |
57 | .subvendor = 0, | |
58 | .subdevice = 0, | |
59 | .driver_data = 0, | |
60 | } | |
61 | }; | |
62 | ||
63 | ||
64 | static char* ifname = "wlan%d"; | |
65 | static int hwseqnum = 0; | |
c8d86be3 GKH |
66 | static int hwwep = 0; |
67 | static int channels = 0x3fff; | |
68 | ||
69 | #define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) | |
70 | #define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) | |
71 | MODULE_LICENSE("GPL"); | |
72 | MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl); | |
73 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
74 | MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards"); | |
75 | ||
76 | ||
c8d86be3 GKH |
77 | module_param(ifname, charp, S_IRUGO|S_IWUSR ); |
78 | module_param(hwseqnum,int, S_IRUGO|S_IWUSR); | |
79 | module_param(hwwep,int, S_IRUGO|S_IWUSR); | |
80 | module_param(channels,int, S_IRUGO|S_IWUSR); | |
c8d86be3 GKH |
81 | |
82 | MODULE_PARM_DESC(devname," Net interface name, wlan%d=default"); | |
c8d86be3 GKH |
83 | MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default"); |
84 | MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards"); | |
85 | MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI"); | |
86 | ||
87 | ||
88 | static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, | |
89 | const struct pci_device_id *id); | |
90 | ||
91 | static void __devexit rtl8180_pci_remove(struct pci_dev *pdev); | |
92 | ||
93 | static void rtl8180_shutdown (struct pci_dev *pdev) | |
94 | { | |
95 | struct net_device *dev = pci_get_drvdata(pdev); | |
727ae303 AB |
96 | if (dev->netdev_ops->ndo_stop) |
97 | dev->netdev_ops->ndo_stop(dev); | |
c8d86be3 GKH |
98 | pci_disable_device(pdev); |
99 | } | |
100 | ||
b6d11c07 BZ |
101 | static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) |
102 | { | |
103 | struct net_device *dev = pci_get_drvdata(pdev); | |
104 | ||
105 | if (!netif_running(dev)) | |
106 | goto out_pci_suspend; | |
107 | ||
108 | if (dev->netdev_ops->ndo_stop) | |
109 | dev->netdev_ops->ndo_stop(dev); | |
110 | ||
111 | netif_device_detach(dev); | |
112 | ||
113 | out_pci_suspend: | |
114 | pci_save_state(pdev); | |
115 | pci_disable_device(pdev); | |
116 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static int rtl8180_resume(struct pci_dev *pdev) | |
121 | { | |
122 | struct net_device *dev = pci_get_drvdata(pdev); | |
123 | int err; | |
124 | u32 val; | |
125 | ||
126 | pci_set_power_state(pdev, PCI_D0); | |
127 | ||
128 | err = pci_enable_device(pdev); | |
129 | if (err) { | |
130 | printk(KERN_ERR "%s: pci_enable_device failed on resume\n", | |
131 | dev->name); | |
132 | ||
133 | return err; | |
134 | } | |
135 | ||
136 | pci_restore_state(pdev); | |
137 | ||
138 | /* | |
139 | * Suspend/Resume resets the PCI configuration space, so we have to | |
140 | * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries | |
141 | * from interfering with C3 CPU state. pci_restore_state won't help | |
142 | * here since it only restores the first 64 bytes pci config header. | |
143 | */ | |
144 | pci_read_config_dword(pdev, 0x40, &val); | |
145 | if ((val & 0x0000ff00) != 0) | |
146 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
147 | ||
148 | if (!netif_running(dev)) | |
149 | goto out; | |
150 | ||
151 | if (dev->netdev_ops->ndo_open) | |
152 | dev->netdev_ops->ndo_open(dev); | |
153 | ||
154 | netif_device_attach(dev); | |
155 | out: | |
156 | return 0; | |
157 | } | |
158 | ||
c8d86be3 | 159 | static struct pci_driver rtl8180_pci_driver = { |
fd882783 BZ |
160 | .name = RTL8180_MODULE_NAME, |
161 | .id_table = rtl8180_pci_id_tbl, | |
162 | .probe = rtl8180_pci_probe, | |
163 | .remove = __devexit_p(rtl8180_pci_remove), | |
164 | .suspend = rtl8180_suspend, | |
165 | .resume = rtl8180_resume, | |
c8d86be3 GKH |
166 | .shutdown = rtl8180_shutdown, |
167 | }; | |
168 | ||
c8d86be3 GKH |
169 | u8 read_nic_byte(struct net_device *dev, int x) |
170 | { | |
171 | return 0xff&readb((u8*)dev->mem_start +x); | |
172 | } | |
173 | ||
174 | u32 read_nic_dword(struct net_device *dev, int x) | |
175 | { | |
176 | return readl((u8*)dev->mem_start +x); | |
177 | } | |
178 | ||
179 | u16 read_nic_word(struct net_device *dev, int x) | |
180 | { | |
181 | return readw((u8*)dev->mem_start +x); | |
182 | } | |
183 | ||
184 | void write_nic_byte(struct net_device *dev, int x,u8 y) | |
185 | { | |
186 | writeb(y,(u8*)dev->mem_start +x); | |
187 | udelay(20); | |
188 | } | |
189 | ||
190 | void write_nic_dword(struct net_device *dev, int x,u32 y) | |
191 | { | |
192 | writel(y,(u8*)dev->mem_start +x); | |
193 | udelay(20); | |
194 | } | |
195 | ||
196 | void write_nic_word(struct net_device *dev, int x,u16 y) | |
197 | { | |
198 | writew(y,(u8*)dev->mem_start +x); | |
199 | udelay(20); | |
200 | } | |
201 | ||
c8d86be3 GKH |
202 | inline void force_pci_posting(struct net_device *dev) |
203 | { | |
204 | read_nic_byte(dev,EPROM_CMD); | |
c8d86be3 | 205 | mb(); |
c8d86be3 GKH |
206 | } |
207 | ||
c8d86be3 GKH |
208 | irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs); |
209 | void set_nic_rxring(struct net_device *dev); | |
210 | void set_nic_txring(struct net_device *dev); | |
211 | static struct net_device_stats *rtl8180_stats(struct net_device *dev); | |
212 | void rtl8180_commit(struct net_device *dev); | |
213 | void rtl8180_start_tx_beacon(struct net_device *dev); | |
214 | ||
c8d86be3 GKH |
215 | static struct proc_dir_entry *rtl8180_proc = NULL; |
216 | ||
217 | static int proc_get_registers(char *page, char **start, | |
218 | off_t offset, int count, | |
219 | int *eof, void *data) | |
220 | { | |
221 | struct net_device *dev = data; | |
c8d86be3 GKH |
222 | int len = 0; |
223 | int i,n; | |
fd882783 | 224 | int max = 0xff; |
c8d86be3 GKH |
225 | |
226 | /* This dump the current register page */ | |
fd882783 BZ |
227 | for (n = 0; n <= max;) { |
228 | len += snprintf(page + len, count - len, "\nD: %2x > ", n); | |
c8d86be3 | 229 | |
fd882783 BZ |
230 | for (i = 0; i < 16 && n <= max; i++, n++) |
231 | len += snprintf(page + len, count - len, "%2x ", | |
232 | read_nic_byte(dev, n)); | |
c8d86be3 GKH |
233 | } |
234 | len += snprintf(page + len, count - len,"\n"); | |
235 | ||
c8d86be3 GKH |
236 | *eof = 1; |
237 | return len; | |
c8d86be3 GKH |
238 | } |
239 | ||
240 | int get_curr_tx_free_desc(struct net_device *dev, int priority); | |
241 | ||
242 | static int proc_get_stats_hw(char *page, char **start, | |
243 | off_t offset, int count, | |
244 | int *eof, void *data) | |
245 | { | |
c8d86be3 | 246 | int len = 0; |
c8d86be3 | 247 | |
c8d86be3 GKH |
248 | *eof = 1; |
249 | return len; | |
250 | } | |
251 | ||
c8d86be3 GKH |
252 | static int proc_get_stats_rx(char *page, char **start, |
253 | off_t offset, int count, | |
254 | int *eof, void *data) | |
255 | { | |
256 | struct net_device *dev = data; | |
257 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
258 | ||
259 | int len = 0; | |
260 | ||
261 | len += snprintf(page + len, count - len, | |
c8d86be3 GKH |
262 | "RX OK: %lu\n" |
263 | "RX Retry: %lu\n" | |
264 | "RX CRC Error(0-500): %lu\n" | |
265 | "RX CRC Error(500-1000): %lu\n" | |
266 | "RX CRC Error(>1000): %lu\n" | |
267 | "RX ICV Error: %lu\n", | |
268 | priv->stats.rxint, | |
269 | priv->stats.rxerr, | |
270 | priv->stats.rxcrcerrmin, | |
271 | priv->stats.rxcrcerrmid, | |
272 | priv->stats.rxcrcerrmax, | |
273 | priv->stats.rxicverr | |
274 | ); | |
275 | ||
276 | *eof = 1; | |
277 | return len; | |
278 | } | |
279 | ||
c8d86be3 GKH |
280 | static int proc_get_stats_tx(char *page, char **start, |
281 | off_t offset, int count, | |
282 | int *eof, void *data) | |
283 | { | |
284 | struct net_device *dev = data; | |
285 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
286 | ||
287 | int len = 0; | |
288 | unsigned long totalOK; | |
289 | ||
290 | totalOK=priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint; | |
291 | len += snprintf(page + len, count - len, | |
c8d86be3 GKH |
292 | "TX OK: %lu\n" |
293 | "TX Error: %lu\n" | |
294 | "TX Retry: %lu\n" | |
295 | "TX beacon OK: %lu\n" | |
296 | "TX beacon error: %lu\n", | |
297 | totalOK, | |
298 | priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr, | |
299 | priv->stats.txretry, | |
300 | priv->stats.txbeacon, | |
301 | priv->stats.txbeaconerr | |
302 | ); | |
303 | ||
304 | *eof = 1; | |
305 | return len; | |
306 | } | |
307 | ||
c8d86be3 GKH |
308 | void rtl8180_proc_module_init(void) |
309 | { | |
310 | DMESG("Initializing proc filesystem"); | |
c8d86be3 | 311 | rtl8180_proc=create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net); |
c8d86be3 GKH |
312 | } |
313 | ||
c8d86be3 GKH |
314 | void rtl8180_proc_module_remove(void) |
315 | { | |
c8d86be3 | 316 | remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net); |
c8d86be3 GKH |
317 | } |
318 | ||
c8d86be3 GKH |
319 | void rtl8180_proc_remove_one(struct net_device *dev) |
320 | { | |
321 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
322 | if (priv->dir_dev) { | |
323 | remove_proc_entry("stats-hw", priv->dir_dev); | |
324 | remove_proc_entry("stats-tx", priv->dir_dev); | |
325 | remove_proc_entry("stats-rx", priv->dir_dev); | |
c8d86be3 GKH |
326 | remove_proc_entry("registers", priv->dir_dev); |
327 | remove_proc_entry(dev->name, rtl8180_proc); | |
328 | priv->dir_dev = NULL; | |
329 | } | |
330 | } | |
331 | ||
c8d86be3 GKH |
332 | void rtl8180_proc_init_one(struct net_device *dev) |
333 | { | |
334 | struct proc_dir_entry *e; | |
335 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
fd882783 | 336 | |
be286fd2 | 337 | priv->dir_dev = rtl8180_proc; |
c8d86be3 | 338 | if (!priv->dir_dev) { |
be286fd2 | 339 | DMESGE("Unable to initialize /proc/net/r8180/%s\n", |
c8d86be3 GKH |
340 | dev->name); |
341 | return; | |
342 | } | |
343 | ||
344 | e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO, | |
345 | priv->dir_dev, proc_get_stats_hw, dev); | |
c8d86be3 GKH |
346 | if (!e) { |
347 | DMESGE("Unable to initialize " | |
be286fd2 | 348 | "/proc/net/r8180/%s/stats-hw\n", |
c8d86be3 GKH |
349 | dev->name); |
350 | } | |
351 | ||
352 | e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO, | |
353 | priv->dir_dev, proc_get_stats_rx, dev); | |
c8d86be3 GKH |
354 | if (!e) { |
355 | DMESGE("Unable to initialize " | |
be286fd2 | 356 | "/proc/net/r8180/%s/stats-rx\n", |
c8d86be3 GKH |
357 | dev->name); |
358 | } | |
359 | ||
360 | ||
361 | e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO, | |
362 | priv->dir_dev, proc_get_stats_tx, dev); | |
c8d86be3 GKH |
363 | if (!e) { |
364 | DMESGE("Unable to initialize " | |
be286fd2 | 365 | "/proc/net/r8180/%s/stats-tx\n", |
c8d86be3 GKH |
366 | dev->name); |
367 | } | |
c8d86be3 GKH |
368 | |
369 | e = create_proc_read_entry("registers", S_IFREG | S_IRUGO, | |
370 | priv->dir_dev, proc_get_registers, dev); | |
c8d86be3 GKH |
371 | if (!e) { |
372 | DMESGE("Unable to initialize " | |
be286fd2 | 373 | "/proc/net/r8180/%s/registers\n", |
c8d86be3 GKH |
374 | dev->name); |
375 | } | |
376 | } | |
fd882783 | 377 | |
c8d86be3 GKH |
378 | /* |
379 | FIXME: check if we can use some standard already-existent | |
380 | data type+functions in kernel | |
381 | */ | |
382 | ||
383 | short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma, | |
384 | struct buffer **bufferhead) | |
385 | { | |
c8d86be3 GKH |
386 | struct buffer *tmp; |
387 | ||
388 | if(! *buffer){ | |
389 | ||
390 | *buffer = kmalloc(sizeof(struct buffer),GFP_KERNEL); | |
391 | ||
392 | if (*buffer == NULL) { | |
393 | DMESGE("Failed to kmalloc head of TX/RX struct"); | |
394 | return -1; | |
395 | } | |
396 | (*buffer)->next=*buffer; | |
397 | (*buffer)->buf=buf; | |
398 | (*buffer)->dma=dma; | |
399 | if(bufferhead !=NULL) | |
400 | (*bufferhead) = (*buffer); | |
401 | return 0; | |
402 | } | |
403 | tmp=*buffer; | |
404 | ||
405 | while(tmp->next!=(*buffer)) tmp=tmp->next; | |
53756de3 JP |
406 | tmp->next = kmalloc(sizeof(struct buffer),GFP_KERNEL); |
407 | if (tmp->next == NULL) { | |
c8d86be3 GKH |
408 | DMESGE("Failed to kmalloc TX/RX struct"); |
409 | return -1; | |
410 | } | |
411 | tmp->next->buf=buf; | |
412 | tmp->next->dma=dma; | |
413 | tmp->next->next=*buffer; | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
c8d86be3 GKH |
418 | void buffer_free(struct net_device *dev,struct buffer **buffer,int len,short |
419 | consistent) | |
420 | { | |
421 | ||
422 | struct buffer *tmp,*next; | |
423 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
424 | struct pci_dev *pdev=priv->pdev; | |
c8d86be3 | 425 | |
fd882783 BZ |
426 | if (!*buffer) |
427 | return; | |
c8d86be3 | 428 | |
fd882783 | 429 | tmp = *buffer; |
c8d86be3 | 430 | |
c8d86be3 GKH |
431 | do{ |
432 | next=tmp->next; | |
433 | if(consistent){ | |
434 | pci_free_consistent(pdev,len, | |
435 | tmp->buf,tmp->dma); | |
436 | }else{ | |
437 | pci_unmap_single(pdev, tmp->dma, | |
438 | len,PCI_DMA_FROMDEVICE); | |
439 | kfree(tmp->buf); | |
440 | } | |
441 | kfree(tmp); | |
442 | tmp = next; | |
443 | } | |
444 | while(next != *buffer); | |
445 | ||
446 | *buffer=NULL; | |
447 | } | |
448 | ||
c8d86be3 GKH |
449 | void print_buffer(u32 *buffer, int len) |
450 | { | |
451 | int i; | |
452 | u8 *buf =(u8*)buffer; | |
453 | ||
454 | printk("ASCII BUFFER DUMP (len: %x):\n",len); | |
455 | ||
456 | for(i=0;i<len;i++) | |
457 | printk("%c",buf[i]); | |
458 | ||
459 | printk("\nBINARY BUFFER DUMP (len: %x):\n",len); | |
460 | ||
461 | for(i=0;i<len;i++) | |
462 | printk("%02x",buf[i]); | |
463 | ||
464 | printk("\n"); | |
465 | } | |
466 | ||
c8d86be3 GKH |
467 | int get_curr_tx_free_desc(struct net_device *dev, int priority) |
468 | { | |
469 | struct r8180_priv *priv = ieee80211_priv(dev); | |
470 | u32* tail; | |
471 | u32* head; | |
472 | int ret; | |
473 | ||
474 | switch (priority){ | |
475 | case MANAGE_PRIORITY: | |
476 | head = priv->txmapringhead; | |
477 | tail = priv->txmapringtail; | |
478 | break; | |
479 | case BK_PRIORITY: | |
480 | head = priv->txbkpringhead; | |
481 | tail = priv->txbkpringtail; | |
482 | break; | |
483 | case BE_PRIORITY: | |
484 | head = priv->txbepringhead; | |
485 | tail = priv->txbepringtail; | |
486 | break; | |
487 | case VI_PRIORITY: | |
488 | head = priv->txvipringhead; | |
489 | tail = priv->txvipringtail; | |
490 | break; | |
491 | case VO_PRIORITY: | |
492 | head = priv->txvopringhead; | |
493 | tail = priv->txvopringtail; | |
494 | break; | |
495 | case HI_PRIORITY: | |
496 | head = priv->txhpringhead; | |
497 | tail = priv->txhpringtail; | |
498 | break; | |
499 | default: | |
500 | return -1; | |
501 | } | |
502 | ||
fd882783 | 503 | if (head <= tail) |
c8d86be3 GKH |
504 | ret = priv->txringcount - (tail - head)/8; |
505 | else | |
506 | ret = (head - tail)/8; | |
507 | ||
fd882783 BZ |
508 | if (ret > priv->txringcount) |
509 | DMESG("BUG"); | |
510 | ||
c8d86be3 | 511 | return ret; |
c8d86be3 GKH |
512 | } |
513 | ||
c8d86be3 GKH |
514 | short check_nic_enought_desc(struct net_device *dev, int priority) |
515 | { | |
516 | struct r8180_priv *priv = ieee80211_priv(dev); | |
517 | struct ieee80211_device *ieee = netdev_priv(dev); | |
c8d86be3 | 518 | int requiredbyte, required; |
fd882783 | 519 | |
c8d86be3 GKH |
520 | requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data); |
521 | ||
fd882783 | 522 | if (ieee->current_network.QoS_Enable) |
c8d86be3 | 523 | requiredbyte += 2; |
c8d86be3 GKH |
524 | |
525 | required = requiredbyte / (priv->txbuffsize-4); | |
fd882783 BZ |
526 | |
527 | if (requiredbyte % priv->txbuffsize) | |
528 | required++; | |
529 | ||
c8d86be3 GKH |
530 | /* for now we keep two free descriptor as a safety boundary |
531 | * between the tail and the head | |
532 | */ | |
533 | ||
534 | return (required+2 < get_curr_tx_free_desc(dev,priority)); | |
535 | } | |
536 | ||
c8d86be3 GKH |
537 | void fix_tx_fifo(struct net_device *dev) |
538 | { | |
539 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
540 | u32 *tmp; | |
541 | int i; | |
ff954853 | 542 | |
c8d86be3 GKH |
543 | for (tmp=priv->txmapring, i=0; |
544 | i < priv->txringcount; | |
545 | tmp+=8, i++){ | |
546 | *tmp = *tmp &~ (1<<31); | |
547 | } | |
548 | ||
549 | for (tmp=priv->txbkpring, i=0; | |
550 | i < priv->txringcount; | |
551 | tmp+=8, i++) { | |
552 | *tmp = *tmp &~ (1<<31); | |
553 | } | |
554 | ||
555 | for (tmp=priv->txbepring, i=0; | |
556 | i < priv->txringcount; | |
557 | tmp+=8, i++){ | |
558 | *tmp = *tmp &~ (1<<31); | |
559 | } | |
560 | for (tmp=priv->txvipring, i=0; | |
561 | i < priv->txringcount; | |
562 | tmp+=8, i++) { | |
563 | *tmp = *tmp &~ (1<<31); | |
564 | } | |
565 | ||
566 | for (tmp=priv->txvopring, i=0; | |
567 | i < priv->txringcount; | |
568 | tmp+=8, i++){ | |
569 | *tmp = *tmp &~ (1<<31); | |
570 | } | |
571 | ||
572 | for (tmp=priv->txhpring, i=0; | |
573 | i < priv->txringcount; | |
574 | tmp+=8,i++){ | |
575 | *tmp = *tmp &~ (1<<31); | |
576 | } | |
577 | ||
578 | for (tmp=priv->txbeaconring, i=0; | |
579 | i < priv->txbeaconcount; | |
580 | tmp+=8, i++){ | |
581 | *tmp = *tmp &~ (1<<31); | |
582 | } | |
ff954853 | 583 | |
c8d86be3 GKH |
584 | priv->txmapringtail = priv->txmapring; |
585 | priv->txmapringhead = priv->txmapring; | |
586 | priv->txmapbufstail = priv->txmapbufs; | |
587 | ||
588 | priv->txbkpringtail = priv->txbkpring; | |
589 | priv->txbkpringhead = priv->txbkpring; | |
590 | priv->txbkpbufstail = priv->txbkpbufs; | |
591 | ||
592 | priv->txbepringtail = priv->txbepring; | |
593 | priv->txbepringhead = priv->txbepring; | |
594 | priv->txbepbufstail = priv->txbepbufs; | |
595 | ||
596 | priv->txvipringtail = priv->txvipring; | |
597 | priv->txvipringhead = priv->txvipring; | |
598 | priv->txvipbufstail = priv->txvipbufs; | |
599 | ||
600 | priv->txvopringtail = priv->txvopring; | |
601 | priv->txvopringhead = priv->txvopring; | |
602 | priv->txvopbufstail = priv->txvopbufs; | |
603 | ||
604 | priv->txhpringtail = priv->txhpring; | |
605 | priv->txhpringhead = priv->txhpring; | |
606 | priv->txhpbufstail = priv->txhpbufs; | |
607 | ||
608 | priv->txbeaconringtail = priv->txbeaconring; | |
609 | priv->txbeaconbufstail = priv->txbeaconbufs; | |
610 | set_nic_txring(dev); | |
611 | ||
612 | ieee80211_reset_queue(priv->ieee80211); | |
613 | priv->ack_tx_to_ieee = 0; | |
614 | } | |
615 | ||
c8d86be3 GKH |
616 | void fix_rx_fifo(struct net_device *dev) |
617 | { | |
618 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
619 | u32 *tmp; | |
620 | struct buffer *rxbuf; | |
621 | u8 rx_desc_size; | |
622 | ||
c8d86be3 | 623 | rx_desc_size = 8; // 4*8 = 32 bytes |
c8d86be3 | 624 | |
c8d86be3 GKH |
625 | for (tmp=priv->rxring, rxbuf=priv->rxbufferhead; |
626 | (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size); | |
627 | tmp+=rx_desc_size,rxbuf=rxbuf->next){ | |
628 | *(tmp+2) = rxbuf->dma; | |
629 | *tmp=*tmp &~ 0xfff; | |
630 | *tmp=*tmp | priv->rxbuffersize; | |
631 | *tmp |= (1<<31); | |
632 | } | |
633 | ||
c8d86be3 GKH |
634 | priv->rxringtail=priv->rxring; |
635 | priv->rxbuffer=priv->rxbufferhead; | |
636 | priv->rx_skb_complete=1; | |
637 | set_nic_rxring(dev); | |
638 | } | |
639 | ||
c8d86be3 | 640 | unsigned char QUALITY_MAP[] = { |
fd882783 BZ |
641 | 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61, |
642 | 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c, | |
643 | 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f, | |
644 | 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29, | |
645 | 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, | |
646 | 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20, | |
647 | 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e, | |
648 | 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19, | |
649 | 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f, | |
650 | 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00 | |
c8d86be3 GKH |
651 | }; |
652 | ||
653 | unsigned char STRENGTH_MAP[] = { | |
fd882783 BZ |
654 | 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e, |
655 | 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50, | |
656 | 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f, | |
657 | 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b, | |
658 | 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17, | |
659 | 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13, | |
660 | 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f, | |
661 | 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b, | |
662 | 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07, | |
663 | 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00 | |
c8d86be3 GKH |
664 | }; |
665 | ||
fd882783 BZ |
666 | void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual) |
667 | { | |
c8d86be3 GKH |
668 | u32 temp; |
669 | u32 temp2; | |
c8d86be3 GKH |
670 | u32 q; |
671 | u32 orig_qual; | |
672 | u8 _rssi; | |
673 | ||
674 | q = *qual; | |
675 | orig_qual = *qual; | |
676 | _rssi = 0; // avoid gcc complains.. | |
677 | ||
678 | if (q <= 0x4e) { | |
679 | temp = QUALITY_MAP[q]; | |
680 | } else { | |
681 | if( q & 0x80 ) { | |
682 | temp = 0x32; | |
683 | } else { | |
684 | temp = 1; | |
685 | } | |
686 | } | |
687 | ||
688 | *qual = temp; | |
689 | temp2 = *rssi; | |
690 | ||
c8d86be3 GKH |
691 | if ( _rssi < 0x64 ){ |
692 | if ( _rssi == 0 ) { | |
693 | *rssi = 1; | |
694 | } | |
695 | } else { | |
696 | *rssi = 0x64; | |
697 | } | |
698 | ||
699 | return; | |
700 | } | |
701 | ||
c8d86be3 GKH |
702 | void rtl8180_irq_enable(struct net_device *dev) |
703 | { | |
704 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
fd882783 | 705 | |
c8d86be3 | 706 | priv->irq_enabled = 1; |
c8d86be3 GKH |
707 | write_nic_word(dev,INTA_MASK, priv->irq_mask); |
708 | } | |
709 | ||
c8d86be3 GKH |
710 | void rtl8180_irq_disable(struct net_device *dev) |
711 | { | |
712 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
713 | ||
c8d86be3 | 714 | write_nic_dword(dev,IMR,0); |
c8d86be3 GKH |
715 | force_pci_posting(dev); |
716 | priv->irq_enabled = 0; | |
717 | } | |
718 | ||
c8d86be3 GKH |
719 | void rtl8180_set_mode(struct net_device *dev,int mode) |
720 | { | |
721 | u8 ecmd; | |
fd882783 | 722 | |
c8d86be3 GKH |
723 | ecmd=read_nic_byte(dev, EPROM_CMD); |
724 | ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK; | |
725 | ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT); | |
726 | ecmd=ecmd &~ (1<<EPROM_CS_SHIFT); | |
727 | ecmd=ecmd &~ (1<<EPROM_CK_SHIFT); | |
728 | write_nic_byte(dev, EPROM_CMD, ecmd); | |
729 | } | |
730 | ||
731 | void rtl8180_adapter_start(struct net_device *dev); | |
732 | void rtl8180_beacon_tx_enable(struct net_device *dev); | |
733 | ||
734 | void rtl8180_update_msr(struct net_device *dev) | |
735 | { | |
736 | struct r8180_priv *priv = ieee80211_priv(dev); | |
737 | u8 msr; | |
738 | u32 rxconf; | |
739 | ||
740 | msr = read_nic_byte(dev, MSR); | |
741 | msr &= ~ MSR_LINK_MASK; | |
742 | ||
743 | rxconf=read_nic_dword(dev,RX_CONF); | |
744 | ||
745 | if(priv->ieee80211->state == IEEE80211_LINKED) | |
746 | { | |
747 | if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) | |
748 | msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT); | |
749 | else if (priv->ieee80211->iw_mode == IW_MODE_MASTER) | |
750 | msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT); | |
751 | else if (priv->ieee80211->iw_mode == IW_MODE_INFRA) | |
752 | msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT); | |
753 | else | |
754 | msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); | |
755 | rxconf |= (1<<RX_CHECK_BSSID_SHIFT); | |
756 | ||
757 | }else { | |
758 | msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); | |
759 | rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT); | |
760 | } | |
761 | ||
762 | write_nic_byte(dev, MSR, msr); | |
763 | write_nic_dword(dev, RX_CONF, rxconf); | |
c8d86be3 GKH |
764 | } |
765 | ||
c8d86be3 GKH |
766 | void rtl8180_set_chan(struct net_device *dev,short ch) |
767 | { | |
768 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
769 | ||
fd882783 | 770 | if ((ch > 14) || (ch < 1)) { |
d599edca | 771 | printk("In %s: Invalid chnanel %d\n", __func__, ch); |
c8d86be3 GKH |
772 | return; |
773 | } | |
774 | ||
775 | priv->chan=ch; | |
c8d86be3 | 776 | priv->rf_set_chan(dev,priv->chan); |
c8d86be3 GKH |
777 | } |
778 | ||
c8d86be3 GKH |
779 | void rtl8180_rx_enable(struct net_device *dev) |
780 | { | |
781 | u8 cmd; | |
782 | u32 rxconf; | |
783 | /* for now we accept data, management & ctl frame*/ | |
784 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
785 | ||
786 | rxconf=read_nic_dword(dev,RX_CONF); | |
787 | rxconf = rxconf &~ MAC_FILTER_MASK; | |
788 | rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT); | |
789 | rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT); | |
790 | rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT); | |
791 | rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT); | |
fd882783 BZ |
792 | if (dev->flags & IFF_PROMISC) |
793 | DMESG("NIC in promisc mode"); | |
c8d86be3 GKH |
794 | |
795 | if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \ | |
796 | dev->flags & IFF_PROMISC){ | |
797 | rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT); | |
798 | }else{ | |
799 | rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT); | |
c8d86be3 GKH |
800 | } |
801 | ||
c8d86be3 GKH |
802 | if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){ |
803 | rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT); | |
804 | rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT); | |
805 | rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT); | |
806 | } | |
807 | ||
808 | if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR) | |
809 | rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT); | |
810 | ||
fd882783 BZ |
811 | rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK; |
812 | rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT); | |
c8d86be3 GKH |
813 | |
814 | rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT); | |
815 | rxconf = rxconf &~ MAX_RX_DMA_MASK; | |
816 | rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT); | |
817 | ||
fd882783 | 818 | rxconf = rxconf | RCR_ONLYERLPKT; |
c8d86be3 GKH |
819 | |
820 | rxconf = rxconf &~ RCR_CS_MASK; | |
fd882783 | 821 | |
c8d86be3 GKH |
822 | write_nic_dword(dev, RX_CONF, rxconf); |
823 | ||
824 | fix_rx_fifo(dev); | |
825 | ||
c8d86be3 GKH |
826 | cmd=read_nic_byte(dev,CMD); |
827 | write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT)); | |
c8d86be3 GKH |
828 | } |
829 | ||
c8d86be3 GKH |
830 | void set_nic_txring(struct net_device *dev) |
831 | { | |
832 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 GKH |
833 | |
834 | write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma); | |
c8d86be3 | 835 | write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma); |
c8d86be3 | 836 | write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma); |
c8d86be3 | 837 | write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma); |
c8d86be3 | 838 | write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma); |
c8d86be3 | 839 | write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma); |
c8d86be3 GKH |
840 | write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma); |
841 | } | |
842 | ||
c8d86be3 GKH |
843 | void rtl8180_conttx_enable(struct net_device *dev) |
844 | { | |
845 | u32 txconf; | |
fd882783 | 846 | |
c8d86be3 GKH |
847 | txconf = read_nic_dword(dev,TX_CONF); |
848 | txconf = txconf &~ TX_LOOPBACK_MASK; | |
849 | txconf = txconf | (TX_LOOPBACK_CONTINUE <<TX_LOOPBACK_SHIFT); | |
850 | write_nic_dword(dev,TX_CONF,txconf); | |
851 | } | |
852 | ||
c8d86be3 GKH |
853 | void rtl8180_conttx_disable(struct net_device *dev) |
854 | { | |
855 | u32 txconf; | |
fd882783 | 856 | |
c8d86be3 GKH |
857 | txconf = read_nic_dword(dev,TX_CONF); |
858 | txconf = txconf &~ TX_LOOPBACK_MASK; | |
859 | txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT); | |
860 | write_nic_dword(dev,TX_CONF,txconf); | |
861 | } | |
862 | ||
c8d86be3 GKH |
863 | void rtl8180_tx_enable(struct net_device *dev) |
864 | { | |
865 | u8 cmd; | |
866 | u8 tx_agc_ctl; | |
867 | u8 byte; | |
868 | u32 txconf; | |
869 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 | 870 | |
fd882783 | 871 | txconf = read_nic_dword(dev, TX_CONF); |
c8d86be3 | 872 | |
d44eb889 LF |
873 | byte = read_nic_byte(dev, CW_CONF); |
874 | byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT); | |
875 | byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT); | |
876 | write_nic_byte(dev, CW_CONF, byte); | |
c8d86be3 | 877 | |
d44eb889 LF |
878 | tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL); |
879 | tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT); | |
880 | tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT); | |
881 | tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT); | |
882 | write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl); | |
883 | write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */ | |
884 | ||
885 | txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT); | |
c8d86be3 GKH |
886 | |
887 | txconf = txconf &~ TX_LOOPBACK_MASK; | |
888 | txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT); | |
889 | txconf = txconf &~ TCR_DPRETRY_MASK; | |
890 | txconf = txconf &~ TCR_RTSRETRY_MASK; | |
891 | txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT); | |
892 | txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT); | |
893 | txconf = txconf &~ (1<<TX_NOCRC_SHIFT); | |
894 | ||
d44eb889 LF |
895 | if (priv->hw_plcp_len) |
896 | txconf = txconf & ~TCR_PLCP_LEN; | |
897 | else | |
898 | txconf = txconf | TCR_PLCP_LEN; | |
fd882783 | 899 | |
c8d86be3 GKH |
900 | txconf = txconf &~ TCR_MXDMA_MASK; |
901 | txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT); | |
902 | txconf = txconf | TCR_CWMIN; | |
903 | txconf = txconf | TCR_DISCW; | |
904 | ||
fd882783 | 905 | txconf = txconf | (1 << TX_NOICV_SHIFT); |
c8d86be3 GKH |
906 | |
907 | write_nic_dword(dev,TX_CONF,txconf); | |
908 | ||
c8d86be3 GKH |
909 | fix_tx_fifo(dev); |
910 | ||
c8d86be3 GKH |
911 | cmd=read_nic_byte(dev,CMD); |
912 | write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT)); | |
913 | ||
c8d86be3 | 914 | write_nic_dword(dev,TX_CONF,txconf); |
c8d86be3 GKH |
915 | } |
916 | ||
c8d86be3 GKH |
917 | void rtl8180_beacon_tx_enable(struct net_device *dev) |
918 | { | |
919 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
920 | ||
921 | rtl8180_set_mode(dev,EPROM_CMD_CONFIG); | |
c8d86be3 GKH |
922 | priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ); |
923 | write_nic_byte(dev,TPPollStop, priv->dma_poll_mask); | |
c8d86be3 GKH |
924 | rtl8180_set_mode(dev,EPROM_CMD_NORMAL); |
925 | } | |
926 | ||
c8d86be3 GKH |
927 | void rtl8180_beacon_tx_disable(struct net_device *dev) |
928 | { | |
929 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
930 | ||
931 | rtl8180_set_mode(dev,EPROM_CMD_CONFIG); | |
c8d86be3 GKH |
932 | priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ; |
933 | write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask); | |
c8d86be3 GKH |
934 | rtl8180_set_mode(dev,EPROM_CMD_NORMAL); |
935 | ||
936 | } | |
937 | ||
c8d86be3 GKH |
938 | void rtl8180_rtx_disable(struct net_device *dev) |
939 | { | |
940 | u8 cmd; | |
941 | struct r8180_priv *priv = ieee80211_priv(dev); | |
942 | ||
943 | cmd=read_nic_byte(dev,CMD); | |
944 | write_nic_byte(dev, CMD, cmd &~ \ | |
945 | ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT))); | |
946 | force_pci_posting(dev); | |
947 | mdelay(10); | |
c8d86be3 GKH |
948 | |
949 | if(!priv->rx_skb_complete) | |
950 | dev_kfree_skb_any(priv->rx_skb); | |
951 | } | |
952 | ||
c8d86be3 GKH |
953 | short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count, |
954 | int addr) | |
955 | { | |
956 | int i; | |
957 | u32 *desc; | |
958 | u32 *tmp; | |
959 | dma_addr_t dma_desc, dma_tmp; | |
960 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
961 | struct pci_dev *pdev = priv->pdev; | |
962 | void *buf; | |
963 | ||
964 | if((bufsize & 0xfff) != bufsize) { | |
965 | DMESGE ("TX buffer allocation too large"); | |
966 | return 0; | |
967 | } | |
968 | desc = (u32*)pci_alloc_consistent(pdev, | |
969 | sizeof(u32)*8*count+256, &dma_desc); | |
fd882783 BZ |
970 | if (desc == NULL) |
971 | return -1; | |
c8d86be3 | 972 | |
fd882783 | 973 | if (dma_desc & 0xff) |
c8d86be3 GKH |
974 | /* |
975 | * descriptor's buffer must be 256 byte aligned | |
976 | * we shouldn't be here, since we set DMA mask ! | |
977 | */ | |
be286fd2 | 978 | WARN(1, "DMA buffer is not aligned\n"); |
fd882783 BZ |
979 | |
980 | tmp = desc; | |
981 | ||
982 | for (i = 0; i < count; i++) { | |
983 | buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp); | |
984 | if (buf == NULL) | |
985 | return -ENOMEM; | |
c8d86be3 GKH |
986 | |
987 | switch(addr) { | |
c8d86be3 GKH |
988 | case TX_MANAGEPRIORITY_RING_ADDR: |
989 | if(-1 == buffer_add(&(priv->txmapbufs),buf,dma_tmp,NULL)){ | |
990 | DMESGE("Unable to allocate mem for buffer NP"); | |
991 | return -ENOMEM; | |
992 | } | |
993 | break; | |
c8d86be3 GKH |
994 | case TX_BKPRIORITY_RING_ADDR: |
995 | if(-1 == buffer_add(&(priv->txbkpbufs),buf,dma_tmp,NULL)){ | |
996 | DMESGE("Unable to allocate mem for buffer LP"); | |
997 | return -ENOMEM; | |
998 | } | |
999 | break; | |
1000 | case TX_BEPRIORITY_RING_ADDR: | |
1001 | if(-1 == buffer_add(&(priv->txbepbufs),buf,dma_tmp,NULL)){ | |
1002 | DMESGE("Unable to allocate mem for buffer NP"); | |
1003 | return -ENOMEM; | |
1004 | } | |
1005 | break; | |
c8d86be3 GKH |
1006 | case TX_VIPRIORITY_RING_ADDR: |
1007 | if(-1 == buffer_add(&(priv->txvipbufs),buf,dma_tmp,NULL)){ | |
1008 | DMESGE("Unable to allocate mem for buffer LP"); | |
1009 | return -ENOMEM; | |
1010 | } | |
1011 | break; | |
1012 | case TX_VOPRIORITY_RING_ADDR: | |
1013 | if(-1 == buffer_add(&(priv->txvopbufs),buf,dma_tmp,NULL)){ | |
1014 | DMESGE("Unable to allocate mem for buffer NP"); | |
1015 | return -ENOMEM; | |
1016 | } | |
1017 | break; | |
c8d86be3 GKH |
1018 | case TX_HIGHPRIORITY_RING_ADDR: |
1019 | if(-1 == buffer_add(&(priv->txhpbufs),buf,dma_tmp,NULL)){ | |
1020 | DMESGE("Unable to allocate mem for buffer HP"); | |
1021 | return -ENOMEM; | |
1022 | } | |
1023 | break; | |
1024 | case TX_BEACON_RING_ADDR: | |
1025 | if(-1 == buffer_add(&(priv->txbeaconbufs),buf,dma_tmp,NULL)){ | |
1026 | DMESGE("Unable to allocate mem for buffer BP"); | |
1027 | return -ENOMEM; | |
1028 | } | |
1029 | break; | |
1030 | } | |
1031 | *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv | |
1032 | *(tmp+2) = (u32)dma_tmp; | |
1033 | *(tmp+3) = bufsize; | |
1034 | ||
1035 | if(i+1<count) | |
1036 | *(tmp+4) = (u32)dma_desc+((i+1)*8*4); | |
1037 | else | |
1038 | *(tmp+4) = (u32)dma_desc; | |
1039 | ||
1040 | tmp=tmp+8; | |
1041 | } | |
1042 | ||
1043 | switch(addr) { | |
1044 | case TX_MANAGEPRIORITY_RING_ADDR: | |
1045 | priv->txmapringdma=dma_desc; | |
1046 | priv->txmapring=desc; | |
1047 | break; | |
c8d86be3 GKH |
1048 | case TX_BKPRIORITY_RING_ADDR: |
1049 | priv->txbkpringdma=dma_desc; | |
1050 | priv->txbkpring=desc; | |
1051 | break; | |
c8d86be3 GKH |
1052 | case TX_BEPRIORITY_RING_ADDR: |
1053 | priv->txbepringdma=dma_desc; | |
1054 | priv->txbepring=desc; | |
1055 | break; | |
c8d86be3 GKH |
1056 | case TX_VIPRIORITY_RING_ADDR: |
1057 | priv->txvipringdma=dma_desc; | |
1058 | priv->txvipring=desc; | |
1059 | break; | |
c8d86be3 GKH |
1060 | case TX_VOPRIORITY_RING_ADDR: |
1061 | priv->txvopringdma=dma_desc; | |
1062 | priv->txvopring=desc; | |
1063 | break; | |
c8d86be3 GKH |
1064 | case TX_HIGHPRIORITY_RING_ADDR: |
1065 | priv->txhpringdma=dma_desc; | |
1066 | priv->txhpring=desc; | |
1067 | break; | |
c8d86be3 GKH |
1068 | case TX_BEACON_RING_ADDR: |
1069 | priv->txbeaconringdma=dma_desc; | |
1070 | priv->txbeaconring=desc; | |
1071 | break; | |
1072 | ||
1073 | } | |
1074 | ||
c8d86be3 GKH |
1075 | return 0; |
1076 | } | |
1077 | ||
c8d86be3 GKH |
1078 | void free_tx_desc_rings(struct net_device *dev) |
1079 | { | |
c8d86be3 GKH |
1080 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
1081 | struct pci_dev *pdev=priv->pdev; | |
1082 | int count = priv->txringcount; | |
1083 | ||
1084 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1085 | priv->txmapring, priv->txmapringdma); | |
1086 | buffer_free(dev,&(priv->txmapbufs),priv->txbuffsize,1); | |
1087 | ||
1088 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1089 | priv->txbkpring, priv->txbkpringdma); | |
1090 | buffer_free(dev,&(priv->txbkpbufs),priv->txbuffsize,1); | |
1091 | ||
1092 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1093 | priv->txbepring, priv->txbepringdma); | |
1094 | buffer_free(dev,&(priv->txbepbufs),priv->txbuffsize,1); | |
1095 | ||
1096 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1097 | priv->txvipring, priv->txvipringdma); | |
1098 | buffer_free(dev,&(priv->txvipbufs),priv->txbuffsize,1); | |
1099 | ||
1100 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1101 | priv->txvopring, priv->txvopringdma); | |
1102 | buffer_free(dev,&(priv->txvopbufs),priv->txbuffsize,1); | |
1103 | ||
1104 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1105 | priv->txhpring, priv->txhpringdma); | |
1106 | buffer_free(dev,&(priv->txhpbufs),priv->txbuffsize,1); | |
1107 | ||
1108 | count = priv->txbeaconcount; | |
1109 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1110 | priv->txbeaconring, priv->txbeaconringdma); | |
1111 | buffer_free(dev,&(priv->txbeaconbufs),priv->txbuffsize,1); | |
1112 | } | |
1113 | ||
c8d86be3 GKH |
1114 | void free_rx_desc_ring(struct net_device *dev) |
1115 | { | |
1116 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1117 | struct pci_dev *pdev = priv->pdev; | |
c8d86be3 GKH |
1118 | int count = priv->rxringcount; |
1119 | ||
c8d86be3 GKH |
1120 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, |
1121 | priv->rxring, priv->rxringdma); | |
c8d86be3 GKH |
1122 | |
1123 | buffer_free(dev,&(priv->rxbuffer),priv->rxbuffersize,0); | |
1124 | } | |
1125 | ||
c8d86be3 GKH |
1126 | short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count) |
1127 | { | |
1128 | int i; | |
1129 | u32 *desc; | |
1130 | u32 *tmp; | |
1131 | dma_addr_t dma_desc,dma_tmp; | |
1132 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1133 | struct pci_dev *pdev=priv->pdev; | |
1134 | void *buf; | |
1135 | u8 rx_desc_size; | |
1136 | ||
c8d86be3 | 1137 | rx_desc_size = 8; // 4*8 = 32 bytes |
c8d86be3 GKH |
1138 | |
1139 | if((bufsize & 0xfff) != bufsize){ | |
1140 | DMESGE ("RX buffer allocation too large"); | |
1141 | return -1; | |
1142 | } | |
1143 | ||
1144 | desc = (u32*)pci_alloc_consistent(pdev,sizeof(u32)*rx_desc_size*count+256, | |
1145 | &dma_desc); | |
1146 | ||
fd882783 | 1147 | if (dma_desc & 0xff) |
c8d86be3 GKH |
1148 | /* |
1149 | * descriptor's buffer must be 256 byte aligned | |
1150 | * should never happen since we specify the DMA mask | |
1151 | */ | |
be286fd2 | 1152 | WARN(1, "DMA buffer is not aligned\n"); |
c8d86be3 GKH |
1153 | |
1154 | priv->rxring=desc; | |
1155 | priv->rxringdma=dma_desc; | |
1156 | tmp=desc; | |
1157 | ||
fd882783 | 1158 | for (i = 0; i < count; i++) { |
53756de3 JP |
1159 | buf = kmalloc(bufsize * sizeof(u8),GFP_ATOMIC); |
1160 | if (buf == NULL) { | |
c8d86be3 GKH |
1161 | DMESGE("Failed to kmalloc RX buffer"); |
1162 | return -1; | |
1163 | } | |
1164 | ||
1165 | dma_tmp = pci_map_single(pdev,buf,bufsize * sizeof(u8), | |
1166 | PCI_DMA_FROMDEVICE); | |
1167 | ||
c8d86be3 GKH |
1168 | if(-1 == buffer_add(&(priv->rxbuffer), buf,dma_tmp, |
1169 | &(priv->rxbufferhead))){ | |
1170 | DMESGE("Unable to allocate mem RX buf"); | |
1171 | return -1; | |
1172 | } | |
1173 | *tmp = 0; //zero pads the header of the descriptor | |
1174 | *tmp = *tmp |( bufsize&0xfff); | |
1175 | *(tmp+2) = (u32)dma_tmp; | |
1176 | *tmp = *tmp |(1<<31); // descriptor void, owned by the NIC | |
1177 | ||
c8d86be3 GKH |
1178 | tmp=tmp+rx_desc_size; |
1179 | } | |
1180 | ||
1181 | *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor | |
1182 | ||
c8d86be3 GKH |
1183 | return 0; |
1184 | } | |
1185 | ||
1186 | ||
1187 | void set_nic_rxring(struct net_device *dev) | |
1188 | { | |
1189 | u8 pgreg; | |
1190 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1191 | ||
c8d86be3 GKH |
1192 | pgreg=read_nic_byte(dev, PGSELECT); |
1193 | write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT)); | |
1194 | ||
c8d86be3 GKH |
1195 | write_nic_dword(dev, RXRING_ADDR,priv->rxringdma); |
1196 | } | |
1197 | ||
c8d86be3 GKH |
1198 | void rtl8180_reset(struct net_device *dev) |
1199 | { | |
c8d86be3 GKH |
1200 | u8 cr; |
1201 | ||
c8d86be3 GKH |
1202 | rtl8180_irq_disable(dev); |
1203 | ||
1204 | cr=read_nic_byte(dev,CMD); | |
1205 | cr = cr & 2; | |
1206 | cr = cr | (1<<CMD_RST_SHIFT); | |
1207 | write_nic_byte(dev,CMD,cr); | |
1208 | ||
1209 | force_pci_posting(dev); | |
1210 | ||
1211 | mdelay(200); | |
1212 | ||
1213 | if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT)) | |
1214 | DMESGW("Card reset timeout!"); | |
1215 | else | |
1216 | DMESG("Card successfully reset"); | |
1217 | ||
c8d86be3 GKH |
1218 | rtl8180_set_mode(dev,EPROM_CMD_LOAD); |
1219 | force_pci_posting(dev); | |
1220 | mdelay(200); | |
c8d86be3 GKH |
1221 | } |
1222 | ||
1223 | inline u16 ieeerate2rtlrate(int rate) | |
1224 | { | |
1225 | switch(rate){ | |
1226 | case 10: | |
fd882783 | 1227 | return 0; |
c8d86be3 | 1228 | case 20: |
fd882783 | 1229 | return 1; |
c8d86be3 | 1230 | case 55: |
fd882783 | 1231 | return 2; |
c8d86be3 | 1232 | case 110: |
fd882783 | 1233 | return 3; |
c8d86be3 | 1234 | case 60: |
fd882783 | 1235 | return 4; |
c8d86be3 | 1236 | case 90: |
fd882783 | 1237 | return 5; |
c8d86be3 | 1238 | case 120: |
fd882783 | 1239 | return 6; |
c8d86be3 | 1240 | case 180: |
fd882783 | 1241 | return 7; |
c8d86be3 | 1242 | case 240: |
fd882783 | 1243 | return 8; |
c8d86be3 | 1244 | case 360: |
fd882783 | 1245 | return 9; |
c8d86be3 | 1246 | case 480: |
fd882783 | 1247 | return 10; |
c8d86be3 | 1248 | case 540: |
fd882783 | 1249 | return 11; |
c8d86be3 | 1250 | default: |
fd882783 | 1251 | return 3; |
c8d86be3 GKH |
1252 | } |
1253 | } | |
1254 | ||
1255 | static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540,720}; | |
fd882783 | 1256 | |
c8d86be3 GKH |
1257 | inline u16 rtl8180_rate2rate(short rate) |
1258 | { | |
fd882783 BZ |
1259 | if (rate > 12) |
1260 | return 10; | |
c8d86be3 GKH |
1261 | return rtl_rate[rate]; |
1262 | } | |
fd882783 | 1263 | |
c8d86be3 GKH |
1264 | inline u8 rtl8180_IsWirelessBMode(u16 rate) |
1265 | { | |
1266 | if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) ) | |
1267 | return 1; | |
fd882783 BZ |
1268 | else |
1269 | return 0; | |
c8d86be3 | 1270 | } |
fd882783 | 1271 | |
c8d86be3 | 1272 | u16 N_DBPSOfRate(u16 DataRate); |
fd882783 BZ |
1273 | |
1274 | u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame, | |
1275 | u8 bShortPreamble) | |
c8d86be3 GKH |
1276 | { |
1277 | u16 FrameTime; | |
1278 | u16 N_DBPS; | |
1279 | u16 Ceiling; | |
1280 | ||
fd882783 BZ |
1281 | if (rtl8180_IsWirelessBMode(DataRate)) { |
1282 | if (bManagementFrame || !bShortPreamble || DataRate == 10) | |
1283 | /* long preamble */ | |
c8d86be3 | 1284 | FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10))); |
c8d86be3 | 1285 | else |
fd882783 | 1286 | /* short preamble */ |
c8d86be3 | 1287 | FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10))); |
fd882783 BZ |
1288 | |
1289 | if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */ | |
1290 | FrameTime++; | |
1291 | } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */ | |
c8d86be3 GKH |
1292 | N_DBPS = N_DBPSOfRate(DataRate); |
1293 | Ceiling = (16 + 8*FrameLength + 6) / N_DBPS | |
1294 | + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0); | |
1295 | FrameTime = (u16)(16 + 4 + 4*Ceiling + 6); | |
1296 | } | |
1297 | return FrameTime; | |
1298 | } | |
fd882783 | 1299 | |
c8d86be3 GKH |
1300 | u16 N_DBPSOfRate(u16 DataRate) |
1301 | { | |
1302 | u16 N_DBPS = 24; | |
1303 | ||
fd882783 BZ |
1304 | switch (DataRate) { |
1305 | case 60: | |
1306 | N_DBPS = 24; | |
1307 | break; | |
1308 | case 90: | |
1309 | N_DBPS = 36; | |
1310 | break; | |
1311 | case 120: | |
1312 | N_DBPS = 48; | |
1313 | break; | |
1314 | case 180: | |
1315 | N_DBPS = 72; | |
1316 | break; | |
1317 | case 240: | |
1318 | N_DBPS = 96; | |
1319 | break; | |
1320 | case 360: | |
1321 | N_DBPS = 144; | |
1322 | break; | |
1323 | case 480: | |
1324 | N_DBPS = 192; | |
1325 | break; | |
1326 | case 540: | |
1327 | N_DBPS = 216; | |
1328 | break; | |
1329 | default: | |
1330 | break; | |
1331 | } | |
c8d86be3 | 1332 | |
fd882783 | 1333 | return N_DBPS; |
c8d86be3 GKH |
1334 | } |
1335 | ||
c8d86be3 GKH |
1336 | // |
1337 | // Description: | |
1338 | // For Netgear case, they want good-looking singal strength. | |
c8d86be3 | 1339 | // |
fd882783 | 1340 | long NetgearSignalStrengthTranslate(long LastSS, long CurrSS) |
c8d86be3 GKH |
1341 | { |
1342 | long RetSS; | |
1343 | ||
1344 | // Step 1. Scale mapping. | |
fd882783 | 1345 | if (CurrSS >= 71 && CurrSS <= 100) |
c8d86be3 | 1346 | RetSS = 90 + ((CurrSS - 70) / 3); |
fd882783 | 1347 | else if (CurrSS >= 41 && CurrSS <= 70) |
c8d86be3 | 1348 | RetSS = 78 + ((CurrSS - 40) / 3); |
fd882783 | 1349 | else if (CurrSS >= 31 && CurrSS <= 40) |
c8d86be3 | 1350 | RetSS = 66 + (CurrSS - 30); |
fd882783 | 1351 | else if (CurrSS >= 21 && CurrSS <= 30) |
c8d86be3 | 1352 | RetSS = 54 + (CurrSS - 20); |
fd882783 | 1353 | else if (CurrSS >= 5 && CurrSS <= 20) |
c8d86be3 | 1354 | RetSS = 42 + (((CurrSS - 5) * 2) / 3); |
fd882783 | 1355 | else if (CurrSS == 4) |
c8d86be3 | 1356 | RetSS = 36; |
fd882783 | 1357 | else if (CurrSS == 3) |
c8d86be3 | 1358 | RetSS = 27; |
fd882783 | 1359 | else if (CurrSS == 2) |
c8d86be3 | 1360 | RetSS = 18; |
fd882783 | 1361 | else if (CurrSS == 1) |
c8d86be3 | 1362 | RetSS = 9; |
c8d86be3 | 1363 | else |
c8d86be3 | 1364 | RetSS = CurrSS; |
c8d86be3 GKH |
1365 | |
1366 | // Step 2. Smoothing. | |
1367 | if(LastSS > 0) | |
c8d86be3 | 1368 | RetSS = ((LastSS * 5) + (RetSS)+ 5) / 6; |
c8d86be3 GKH |
1369 | |
1370 | return RetSS; | |
1371 | } | |
fd882783 | 1372 | |
c8d86be3 GKH |
1373 | // |
1374 | // Description: | |
1375 | // Translate 0-100 signal strength index into dBm. | |
1376 | // | |
fd882783 | 1377 | long TranslateToDbm8185(u8 SignalStrengthIndex) |
c8d86be3 | 1378 | { |
fd882783 | 1379 | long SignalPower; |
c8d86be3 GKH |
1380 | |
1381 | // Translate to dBm (x=0.5y-95). | |
1382 | SignalPower = (long)((SignalStrengthIndex + 1) >> 1); | |
1383 | SignalPower -= 95; | |
1384 | ||
1385 | return SignalPower; | |
1386 | } | |
fd882783 | 1387 | |
c8d86be3 GKH |
1388 | // |
1389 | // Description: | |
1390 | // Perform signal smoothing for dynamic mechanism. | |
1391 | // This is different with PerformSignalSmoothing8185 in smoothing fomula. | |
1392 | // No dramatic adjustion is apply because dynamic mechanism need some degree | |
1393 | // of correctness. Ported from 8187B. | |
c8d86be3 | 1394 | // |
fd882783 BZ |
1395 | void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv, |
1396 | bool bCckRate) | |
c8d86be3 | 1397 | { |
c8d86be3 GKH |
1398 | // Determin the current packet is CCK rate. |
1399 | priv->bCurCCKPkt = bCckRate; | |
1400 | ||
fd882783 | 1401 | if (priv->UndecoratedSmoothedSS >= 0) |
c8d86be3 | 1402 | priv->UndecoratedSmoothedSS = ( (priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10) ) / 6; |
c8d86be3 | 1403 | else |
c8d86be3 | 1404 | priv->UndecoratedSmoothedSS = priv->SignalStrength * 10; |
c8d86be3 GKH |
1405 | |
1406 | priv->UndercorateSmoothedRxPower = ( (priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower* 11)) / 60; | |
1407 | ||
fd882783 | 1408 | if (bCckRate) |
c8d86be3 | 1409 | priv->CurCCKRSSI = priv->RSSI; |
c8d86be3 | 1410 | else |
c8d86be3 | 1411 | priv->CurCCKRSSI = 0; |
c8d86be3 GKH |
1412 | } |
1413 | ||
c8d86be3 GKH |
1414 | |
1415 | /* This is rough RX isr handling routine*/ | |
1416 | void rtl8180_rx(struct net_device *dev) | |
1417 | { | |
1418 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1419 | struct sk_buff *tmp_skb; | |
c8d86be3 GKH |
1420 | short first,last; |
1421 | u32 len; | |
1422 | int lastlen; | |
1423 | unsigned char quality, signal; | |
1424 | u8 rate; | |
c8d86be3 GKH |
1425 | u32 *tmp,*tmp2; |
1426 | u8 rx_desc_size; | |
1427 | u8 padding; | |
c8d86be3 GKH |
1428 | char rxpower = 0; |
1429 | u32 RXAGC = 0; | |
1430 | long RxAGC_dBm = 0; | |
1431 | u8 LNA=0, BB=0; | |
1432 | u8 LNA_gain[4]={02, 17, 29, 39}; | |
1433 | u8 Antenna = 0; | |
0604384d | 1434 | struct ieee80211_hdr_4addr *hdr; |
c8d86be3 GKH |
1435 | u16 fc,type; |
1436 | u8 bHwError = 0,bCRC = 0,bICV = 0; | |
c8d86be3 GKH |
1437 | bool bCckRate = false; |
1438 | u8 RSSI = 0; | |
fd882783 | 1439 | long SignalStrengthIndex = 0; |
c8d86be3 GKH |
1440 | struct ieee80211_rx_stats stats = { |
1441 | .signal = 0, | |
1442 | .noise = -98, | |
1443 | .rate = 0, | |
c8d86be3 GKH |
1444 | .freq = IEEE80211_24GHZ_BAND, |
1445 | }; | |
1446 | ||
c8d86be3 GKH |
1447 | stats.nic_type = NIC_8185B; |
1448 | rx_desc_size = 8; | |
1449 | ||
c8d86be3 | 1450 | if ((*(priv->rxringtail)) & (1<<31)) { |
c8d86be3 GKH |
1451 | /* we have got an RX int, but the descriptor |
1452 | * we are pointing is empty*/ | |
1453 | ||
1454 | priv->stats.rxnodata++; | |
1455 | priv->ieee80211->stats.rx_errors++; | |
1456 | ||
c8d86be3 GKH |
1457 | tmp2 = NULL; |
1458 | tmp = priv->rxringtail; | |
1459 | do{ | |
1460 | if(tmp == priv->rxring) | |
c8d86be3 GKH |
1461 | tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size; |
1462 | else | |
1463 | tmp -= rx_desc_size; | |
1464 | ||
1465 | if(! (*tmp & (1<<31))) | |
1466 | tmp2 = tmp; | |
1467 | }while(tmp != priv->rxring); | |
1468 | ||
1469 | if(tmp2) priv->rxringtail = tmp2; | |
c8d86be3 GKH |
1470 | } |
1471 | ||
1472 | /* while there are filled descriptors */ | |
1473 | while(!(*(priv->rxringtail) & (1<<31))){ | |
1474 | if(*(priv->rxringtail) & (1<<26)) | |
1475 | DMESGW("RX buffer overflow"); | |
1476 | if(*(priv->rxringtail) & (1<<12)) | |
1477 | priv->stats.rxicverr++; | |
1478 | ||
1479 | if(*(priv->rxringtail) & (1<<27)){ | |
1480 | priv->stats.rxdmafail++; | |
1481 | //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail); | |
1482 | goto drop; | |
1483 | } | |
1484 | ||
1485 | pci_dma_sync_single_for_cpu(priv->pdev, | |
1486 | priv->rxbuffer->dma, | |
1487 | priv->rxbuffersize * \ | |
1488 | sizeof(u8), | |
1489 | PCI_DMA_FROMDEVICE); | |
1490 | ||
1491 | first = *(priv->rxringtail) & (1<<29) ? 1:0; | |
1492 | if(first) priv->rx_prevlen=0; | |
1493 | ||
1494 | last = *(priv->rxringtail) & (1<<28) ? 1:0; | |
1495 | if(last){ | |
1496 | lastlen=((*priv->rxringtail) &0xfff); | |
1497 | ||
1498 | /* if the last descriptor (that should | |
1499 | * tell us the total packet len) tell | |
1500 | * us something less than the descriptors | |
1501 | * len we had until now, then there is some | |
1502 | * problem.. | |
1503 | * workaround to prevent kernel panic | |
1504 | */ | |
1505 | if(lastlen < priv->rx_prevlen) | |
1506 | len=0; | |
1507 | else | |
1508 | len=lastlen-priv->rx_prevlen; | |
1509 | ||
1510 | if(*(priv->rxringtail) & (1<<13)) { | |
c8d86be3 GKH |
1511 | if ((*(priv->rxringtail) & 0xfff) <500) |
1512 | priv->stats.rxcrcerrmin++; | |
1513 | else if ((*(priv->rxringtail) & 0x0fff) >1000) | |
1514 | priv->stats.rxcrcerrmax++; | |
1515 | else | |
1516 | priv->stats.rxcrcerrmid++; | |
1517 | ||
1518 | } | |
1519 | ||
1520 | }else{ | |
1521 | len = priv->rxbuffersize; | |
1522 | } | |
1523 | ||
c8d86be3 GKH |
1524 | if(first && last) { |
1525 | padding = ((*(priv->rxringtail+3))&(0x04000000))>>26; | |
1526 | }else if(first) { | |
1527 | padding = ((*(priv->rxringtail+3))&(0x04000000))>>26; | |
1528 | if(padding) { | |
1529 | len -= 2; | |
1530 | } | |
1531 | }else { | |
1532 | padding = 0; | |
1533 | } | |
c8d86be3 | 1534 | padding = 0; |
c8d86be3 GKH |
1535 | priv->rx_prevlen+=len; |
1536 | ||
1537 | if(priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100){ | |
1538 | /* HW is probably passing several buggy frames | |
1539 | * without FD or LD flag set. | |
1540 | * Throw this garbage away to prevent skb | |
1541 | * memory exausting | |
1542 | */ | |
1543 | if(!priv->rx_skb_complete) | |
1544 | dev_kfree_skb_any(priv->rx_skb); | |
1545 | priv->rx_skb_complete = 1; | |
1546 | } | |
1547 | ||
c8d86be3 | 1548 | signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16); |
1994130e | 1549 | signal = (signal & 0xfe) >> 1; |
c8d86be3 GKH |
1550 | |
1551 | quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff)); | |
1552 | ||
1553 | stats.mac_time[0] = *(priv->rxringtail+1); | |
1554 | stats.mac_time[1] = *(priv->rxringtail+2); | |
1555 | rxpower =((char)(((*(priv->rxringtail+4))& (0x00ff0000))>>16))/2 - 42; | |
1556 | RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>> 8)) & (0x7f); | |
1557 | ||
c8d86be3 GKH |
1558 | rate=((*(priv->rxringtail)) & |
1559 | ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20; | |
1560 | ||
1561 | stats.rate = rtl8180_rate2rate(rate); | |
c8d86be3 | 1562 | Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ; |
c8d86be3 GKH |
1563 | if(!rtl8180_IsWirelessBMode(stats.rate)) |
1564 | { // OFDM rate. | |
1565 | ||
1566 | RxAGC_dBm = rxpower+1; //bias | |
1567 | } | |
1568 | else | |
1569 | { // CCK rate. | |
1570 | RxAGC_dBm = signal;//bit 0 discard | |
1571 | ||
1572 | LNA = (u8) (RxAGC_dBm & 0x60 ) >> 5 ; //bit 6~ bit 5 | |
1573 | BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0 | |
1574 | ||
1575 | RxAGC_dBm = -( LNA_gain[LNA] + (BB *2) ); //Pin_11b=-(LNA_gain+BB_gain) (dBm) | |
1576 | ||
1577 | RxAGC_dBm +=4; //bias | |
1578 | } | |
1579 | ||
1580 | if(RxAGC_dBm & 0x80) //absolute value | |
1581 | RXAGC= ~(RxAGC_dBm)+1; | |
1582 | bCckRate = rtl8180_IsWirelessBMode(stats.rate); | |
1583 | // Translate RXAGC into 1-100. | |
1584 | if(!rtl8180_IsWirelessBMode(stats.rate)) | |
1585 | { // OFDM rate. | |
1586 | if(RXAGC>90) | |
1587 | RXAGC=90; | |
1588 | else if(RXAGC<25) | |
1589 | RXAGC=25; | |
1590 | RXAGC=(90-RXAGC)*100/65; | |
1591 | } | |
1592 | else | |
1593 | { // CCK rate. | |
1594 | if(RXAGC>95) | |
1595 | RXAGC=95; | |
1596 | else if(RXAGC<30) | |
1597 | RXAGC=30; | |
1598 | RXAGC=(95-RXAGC)*100/65; | |
1599 | } | |
1600 | priv->SignalStrength = (u8)RXAGC; | |
1994130e | 1601 | priv->RecvSignalPower = RxAGC_dBm; |
c8d86be3 GKH |
1602 | priv->RxPower = rxpower; |
1603 | priv->RSSI = RSSI; | |
1994130e | 1604 | /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */ |
c8d86be3 GKH |
1605 | if(quality >= 127) |
1606 | quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now; | |
1607 | else if(quality < 27) | |
1608 | quality = 100; | |
1609 | else | |
1610 | quality = 127 - quality; | |
1611 | priv->SignalQuality = quality; | |
c8d86be3 GKH |
1612 | |
1613 | stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength; | |
1614 | stats.signalstrength = RXAGC; | |
1615 | if(stats.signalstrength > 100) | |
1616 | stats.signalstrength = 100; | |
1617 | stats.signalstrength = (stats.signalstrength * 70)/100 + 30; | |
1618 | // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength); | |
1619 | stats.rssi = priv->wstats.qual.qual = priv->SignalQuality; | |
1620 | stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual; | |
c8d86be3 GKH |
1621 | bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 ) |
1622 | | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 ); | |
1623 | bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13; | |
1624 | bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12; | |
0604384d | 1625 | hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf; |
c8d86be3 GKH |
1626 | fc = le16_to_cpu(hdr->frame_ctl); |
1627 | type = WLAN_FC_GET_TYPE(fc); | |
1628 | ||
1629 | if((IEEE80211_FTYPE_CTL != type) && | |
1630 | (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)) | |
1631 | && (!bHwError) && (!bCRC)&& (!bICV)) | |
1632 | { | |
1994130e LF |
1633 | /* Perform signal smoothing for dynamic |
1634 | * mechanism on demand. This is different | |
1635 | * with PerformSignalSmoothing8185 in smoothing | |
1636 | * fomula. No dramatic adjustion is apply | |
1637 | * because dynamic mechanism need some degree | |
1638 | * of correctness. */ | |
c8d86be3 GKH |
1639 | PerformUndecoratedSignalSmoothing8185(priv,bCckRate); |
1640 | // | |
1641 | // For good-looking singal strength. | |
1642 | // | |
1643 | SignalStrengthIndex = NetgearSignalStrengthTranslate( | |
1644 | priv->LastSignalStrengthInPercent, | |
1645 | priv->SignalStrength); | |
1646 | ||
1647 | priv->LastSignalStrengthInPercent = SignalStrengthIndex; | |
1648 | priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex); | |
1649 | // | |
1650 | // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified, | |
1651 | // so we record the correct power here. | |
1652 | // | |
1653 | priv->Stats_SignalQuality =(long) (priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6; | |
1654 | priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower -1) / 6; | |
1655 | ||
1656 | // Figure out which antenna that received the lasted packet. | |
1657 | priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main. | |
c8d86be3 GKH |
1658 | SwAntennaDiversityRxOk8185(dev, priv->SignalStrength); |
1659 | } | |
1660 | ||
c8d86be3 GKH |
1661 | if(first){ |
1662 | if(!priv->rx_skb_complete){ | |
1663 | /* seems that HW sometimes fails to reiceve and | |
1664 | doesn't provide the last descriptor */ | |
c8d86be3 GKH |
1665 | dev_kfree_skb_any(priv->rx_skb); |
1666 | priv->stats.rxnolast++; | |
c8d86be3 GKH |
1667 | } |
1668 | /* support for prism header has been originally added by Christian */ | |
1669 | if(priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR){ | |
1670 | ||
c8d86be3 GKH |
1671 | }else{ |
1672 | priv->rx_skb = dev_alloc_skb(len+2); | |
1673 | if( !priv->rx_skb) goto drop; | |
c8d86be3 GKH |
1674 | } |
1675 | ||
1676 | priv->rx_skb_complete=0; | |
1677 | priv->rx_skb->dev=dev; | |
1678 | }else{ | |
1679 | /* if we are here we should have already RXed | |
1680 | * the first frame. | |
1681 | * If we get here and the skb is not allocated then | |
1682 | * we have just throw out garbage (skb not allocated) | |
1683 | * and we are still rxing garbage.... | |
1684 | */ | |
1685 | if(!priv->rx_skb_complete){ | |
1686 | ||
1687 | tmp_skb= dev_alloc_skb(priv->rx_skb->len +len+2); | |
1688 | ||
1689 | if(!tmp_skb) goto drop; | |
1690 | ||
1691 | tmp_skb->dev=dev; | |
c8d86be3 | 1692 | |
c8d86be3 GKH |
1693 | memcpy(skb_put(tmp_skb,priv->rx_skb->len), |
1694 | priv->rx_skb->data, | |
1695 | priv->rx_skb->len); | |
c8d86be3 GKH |
1696 | |
1697 | dev_kfree_skb_any(priv->rx_skb); | |
c8d86be3 GKH |
1698 | |
1699 | priv->rx_skb=tmp_skb; | |
1700 | } | |
1701 | } | |
ff954853 | 1702 | |
c8d86be3 | 1703 | if(!priv->rx_skb_complete) { |
c8d86be3 GKH |
1704 | if(padding) { |
1705 | memcpy(skb_put(priv->rx_skb,len), | |
1706 | (((unsigned char *)priv->rxbuffer->buf) + 2),len); | |
1707 | } else { | |
c8d86be3 GKH |
1708 | memcpy(skb_put(priv->rx_skb,len), |
1709 | priv->rxbuffer->buf,len); | |
c8d86be3 | 1710 | } |
c8d86be3 | 1711 | } |
c8d86be3 GKH |
1712 | |
1713 | if(last && !priv->rx_skb_complete){ | |
c8d86be3 GKH |
1714 | if(priv->rx_skb->len > 4) |
1715 | skb_trim(priv->rx_skb,priv->rx_skb->len-4); | |
df574b8e | 1716 | if(!ieee80211_rtl_rx(priv->ieee80211, |
1994130e | 1717 | priv->rx_skb, &stats)) |
c8d86be3 | 1718 | dev_kfree_skb_any(priv->rx_skb); |
c8d86be3 GKH |
1719 | priv->rx_skb_complete=1; |
1720 | } | |
1721 | ||
c8d86be3 GKH |
1722 | pci_dma_sync_single_for_device(priv->pdev, |
1723 | priv->rxbuffer->dma, | |
1724 | priv->rxbuffersize * \ | |
1725 | sizeof(u8), | |
1726 | PCI_DMA_FROMDEVICE); | |
1727 | ||
bbc9a991 | 1728 | drop: // this is used when we have not enough mem |
c8d86be3 GKH |
1729 | /* restore the descriptor */ |
1730 | *(priv->rxringtail+2)=priv->rxbuffer->dma; | |
1731 | *(priv->rxringtail)=*(priv->rxringtail) &~ 0xfff; | |
1732 | *(priv->rxringtail)= | |
1733 | *(priv->rxringtail) | priv->rxbuffersize; | |
1734 | ||
1735 | *(priv->rxringtail)= | |
1736 | *(priv->rxringtail) | (1<<31); | |
c8d86be3 GKH |
1737 | |
1738 | priv->rxringtail+=rx_desc_size; | |
1739 | if(priv->rxringtail >= | |
1740 | (priv->rxring)+(priv->rxringcount )*rx_desc_size) | |
1741 | priv->rxringtail=priv->rxring; | |
1742 | ||
c8d86be3 | 1743 | priv->rxbuffer=(priv->rxbuffer->next); |
c8d86be3 | 1744 | } |
c8d86be3 GKH |
1745 | } |
1746 | ||
1747 | ||
1748 | void rtl8180_dma_kick(struct net_device *dev, int priority) | |
1749 | { | |
1750 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1751 | ||
1752 | rtl8180_set_mode(dev,EPROM_CMD_CONFIG); | |
c8d86be3 GKH |
1753 | write_nic_byte(dev, TX_DMA_POLLING, |
1754 | (1 << (priority + 1)) | priv->dma_poll_mask); | |
1755 | rtl8180_set_mode(dev,EPROM_CMD_NORMAL); | |
1756 | ||
1757 | force_pci_posting(dev); | |
1758 | } | |
1759 | ||
c8d86be3 GKH |
1760 | void rtl8180_data_hard_stop(struct net_device *dev) |
1761 | { | |
1762 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1763 | ||
1764 | rtl8180_set_mode(dev,EPROM_CMD_CONFIG); | |
c8d86be3 GKH |
1765 | priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ; |
1766 | write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask); | |
c8d86be3 GKH |
1767 | rtl8180_set_mode(dev,EPROM_CMD_NORMAL); |
1768 | } | |
1769 | ||
c8d86be3 GKH |
1770 | void rtl8180_data_hard_resume(struct net_device *dev) |
1771 | { | |
1772 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1773 | ||
1774 | rtl8180_set_mode(dev,EPROM_CMD_CONFIG); | |
c8d86be3 GKH |
1775 | priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ); |
1776 | write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask); | |
c8d86be3 GKH |
1777 | rtl8180_set_mode(dev,EPROM_CMD_NORMAL); |
1778 | } | |
1779 | ||
c8d86be3 GKH |
1780 | /* this function TX data frames when the ieee80211 stack requires this. |
1781 | * It checks also if we need to stop the ieee tx queue, eventually do it | |
1782 | */ | |
1783 | void rtl8180_hard_data_xmit(struct sk_buff *skb,struct net_device *dev, int | |
1784 | rate) | |
1785 | { | |
1786 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1787 | int mode; | |
1788 | struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data; | |
b6b1ac69 | 1789 | short morefrag = (h->frame_control) & IEEE80211_FCTL_MOREFRAGS; |
c8d86be3 GKH |
1790 | unsigned long flags; |
1791 | int priority; | |
c8d86be3 GKH |
1792 | |
1793 | mode = priv->ieee80211->iw_mode; | |
1794 | ||
1795 | rate = ieeerate2rtlrate(rate); | |
1796 | /* | |
1797 | * This function doesn't require lock because we make | |
1798 | * sure it's called with the tx_lock already acquired. | |
bbc9a991 AGR |
1799 | * this come from the kernel's hard_xmit callback (through |
1800 | * the ieee stack, or from the try_wake_queue (again through | |
c8d86be3 GKH |
1801 | * the ieee stack. |
1802 | */ | |
c8d86be3 | 1803 | priority = AC2Q(skb->priority); |
c8d86be3 GKH |
1804 | spin_lock_irqsave(&priv->tx_lock,flags); |
1805 | ||
1806 | if(priv->ieee80211->bHwRadioOff) | |
1807 | { | |
1808 | spin_unlock_irqrestore(&priv->tx_lock,flags); | |
1809 | ||
1810 | return; | |
1811 | } | |
1812 | ||
c8d86be3 | 1813 | if (!check_nic_enought_desc(dev, priority)){ |
c8d86be3 GKH |
1814 | DMESGW("Error: no descriptor left by previous TX (avail %d) ", |
1815 | get_curr_tx_free_desc(dev, priority)); | |
df574b8e | 1816 | ieee80211_rtl_stop_queue(priv->ieee80211); |
c8d86be3 GKH |
1817 | } |
1818 | rtl8180_tx(dev, skb->data, skb->len, priority, morefrag,0,rate); | |
1819 | if (!check_nic_enought_desc(dev, priority)) | |
df574b8e | 1820 | ieee80211_rtl_stop_queue(priv->ieee80211); |
c8d86be3 | 1821 | |
c8d86be3 | 1822 | spin_unlock_irqrestore(&priv->tx_lock,flags); |
c8d86be3 GKH |
1823 | } |
1824 | ||
1825 | /* This is a rough attempt to TX a frame | |
1826 | * This is called by the ieee 80211 stack to TX management frames. | |
1827 | * If the ring is full packet are dropped (for data frame the queue | |
1828 | * is stopped before this can happen). For this reason it is better | |
1829 | * if the descriptors are larger than the largest management frame | |
1830 | * we intend to TX: i'm unsure what the HW does if it will not found | |
1831 | * the last fragment of a frame because it has been dropped... | |
1832 | * Since queues for Management and Data frames are different we | |
1833 | * might use a different lock than tx_lock (for example mgmt_tx_lock) | |
1834 | */ | |
1835 | /* these function may loops if invoked with 0 descriptors or 0 len buffer*/ | |
1836 | int rtl8180_hard_start_xmit(struct sk_buff *skb,struct net_device *dev) | |
1837 | { | |
1838 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 | 1839 | unsigned long flags; |
c8d86be3 GKH |
1840 | int priority; |
1841 | ||
c8d86be3 | 1842 | priority = MANAGE_PRIORITY; |
c8d86be3 GKH |
1843 | |
1844 | spin_lock_irqsave(&priv->tx_lock,flags); | |
1845 | ||
fd882783 | 1846 | if (priv->ieee80211->bHwRadioOff) { |
c8d86be3 | 1847 | spin_unlock_irqrestore(&priv->tx_lock,flags); |
c8d86be3 | 1848 | dev_kfree_skb_any(skb); |
ec634fe3 | 1849 | return NETDEV_TX_OK; |
c8d86be3 GKH |
1850 | } |
1851 | ||
1852 | rtl8180_tx(dev, skb->data, skb->len, priority, | |
1853 | 0, 0,ieeerate2rtlrate(priv->ieee80211->basic_rate)); | |
1854 | ||
1855 | priv->ieee80211->stats.tx_bytes+=skb->len; | |
1856 | priv->ieee80211->stats.tx_packets++; | |
1857 | spin_unlock_irqrestore(&priv->tx_lock,flags); | |
1858 | ||
1859 | dev_kfree_skb_any(skb); | |
ec634fe3 | 1860 | return NETDEV_TX_OK; |
c8d86be3 GKH |
1861 | } |
1862 | ||
1863 | // longpre 144+48 shortpre 72+24 | |
1864 | u16 rtl8180_len2duration(u32 len, short rate,short* ext) | |
1865 | { | |
1866 | u16 duration; | |
1867 | u16 drift; | |
1868 | *ext=0; | |
1869 | ||
1870 | switch(rate){ | |
1871 | case 0://1mbps | |
1872 | *ext=0; | |
1873 | duration = ((len+4)<<4) /0x2; | |
1874 | drift = ((len+4)<<4) % 0x2; | |
1875 | if(drift ==0 ) break; | |
1876 | duration++; | |
1877 | break; | |
c8d86be3 GKH |
1878 | case 1://2mbps |
1879 | *ext=0; | |
1880 | duration = ((len+4)<<4) /0x4; | |
1881 | drift = ((len+4)<<4) % 0x4; | |
1882 | if(drift ==0 ) break; | |
1883 | duration++; | |
1884 | break; | |
c8d86be3 GKH |
1885 | case 2: //5.5mbps |
1886 | *ext=0; | |
1887 | duration = ((len+4)<<4) /0xb; | |
1888 | drift = ((len+4)<<4) % 0xb; | |
1889 | if(drift ==0 ) | |
1890 | break; | |
1891 | duration++; | |
1892 | break; | |
c8d86be3 GKH |
1893 | default: |
1894 | case 3://11mbps | |
1895 | *ext=0; | |
1896 | duration = ((len+4)<<4) /0x16; | |
1897 | drift = ((len+4)<<4) % 0x16; | |
1898 | if(drift ==0 ) | |
1899 | break; | |
1900 | duration++; | |
1901 | if(drift > 6) | |
1902 | break; | |
1903 | *ext=1; | |
1904 | break; | |
1905 | } | |
1906 | ||
1907 | return duration; | |
1908 | } | |
1909 | ||
c8d86be3 GKH |
1910 | void rtl8180_prepare_beacon(struct net_device *dev) |
1911 | { | |
c8d86be3 | 1912 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
c8d86be3 GKH |
1913 | struct sk_buff *skb; |
1914 | ||
1915 | u16 word = read_nic_word(dev, BcnItv); | |
1916 | word &= ~BcnItv_BcnItv; // clear Bcn_Itv | |
1917 | word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval);//0x64; | |
1918 | write_nic_word(dev, BcnItv, word); | |
1919 | ||
c8d86be3 GKH |
1920 | skb = ieee80211_get_beacon(priv->ieee80211); |
1921 | if(skb){ | |
1922 | rtl8180_tx(dev,skb->data,skb->len,BEACON_PRIORITY, | |
1923 | 0,0,ieeerate2rtlrate(priv->ieee80211->basic_rate)); | |
1924 | dev_kfree_skb_any(skb); | |
1925 | } | |
c8d86be3 GKH |
1926 | } |
1927 | ||
1928 | /* This function do the real dirty work: it enqueues a TX command | |
1929 | * descriptor in the ring buffer, copyes the frame in a TX buffer | |
1930 | * and kicks the NIC to ensure it does the DMA transfer. | |
1931 | */ | |
1932 | short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority, | |
1933 | short morefrag, short descfrag, int rate) | |
1934 | { | |
1935 | struct r8180_priv *priv = ieee80211_priv(dev); | |
1936 | u32 *tail,*temp_tail; | |
1937 | u32 *begin; | |
1938 | u32 *buf; | |
1939 | int i; | |
1940 | int remain; | |
1941 | int buflen; | |
1942 | int count; | |
c8d86be3 GKH |
1943 | u16 duration; |
1944 | short ext; | |
1945 | struct buffer* buflist; | |
c8d86be3 GKH |
1946 | struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf; |
1947 | u8 dest[ETH_ALEN]; | |
1948 | u8 bUseShortPreamble = 0; | |
1949 | u8 bCTSEnable = 0; | |
1950 | u8 bRTSEnable = 0; | |
c8d86be3 GKH |
1951 | u16 Duration = 0; |
1952 | u16 RtsDur = 0; | |
1953 | u16 ThisFrameTime = 0; | |
1954 | u16 TxDescDuration = 0; | |
1994130e | 1955 | u8 ownbit_flag = false; |
c8d86be3 GKH |
1956 | |
1957 | switch(priority) { | |
1958 | case MANAGE_PRIORITY: | |
1959 | tail=priv->txmapringtail; | |
1960 | begin=priv->txmapring; | |
1961 | buflist = priv->txmapbufstail; | |
1962 | count = priv->txringcount; | |
1963 | break; | |
c8d86be3 GKH |
1964 | case BK_PRIORITY: |
1965 | tail=priv->txbkpringtail; | |
1966 | begin=priv->txbkpring; | |
1967 | buflist = priv->txbkpbufstail; | |
1968 | count = priv->txringcount; | |
1969 | break; | |
c8d86be3 GKH |
1970 | case BE_PRIORITY: |
1971 | tail=priv->txbepringtail; | |
1972 | begin=priv->txbepring; | |
1973 | buflist = priv->txbepbufstail; | |
1974 | count = priv->txringcount; | |
1975 | break; | |
c8d86be3 GKH |
1976 | case VI_PRIORITY: |
1977 | tail=priv->txvipringtail; | |
1978 | begin=priv->txvipring; | |
1979 | buflist = priv->txvipbufstail; | |
1980 | count = priv->txringcount; | |
1981 | break; | |
c8d86be3 GKH |
1982 | case VO_PRIORITY: |
1983 | tail=priv->txvopringtail; | |
1984 | begin=priv->txvopring; | |
1985 | buflist = priv->txvopbufstail; | |
1986 | count = priv->txringcount; | |
1987 | break; | |
c8d86be3 GKH |
1988 | case HI_PRIORITY: |
1989 | tail=priv->txhpringtail; | |
1990 | begin=priv->txhpring; | |
1991 | buflist = priv->txhpbufstail; | |
1992 | count = priv->txringcount; | |
1993 | break; | |
c8d86be3 GKH |
1994 | case BEACON_PRIORITY: |
1995 | tail=priv->txbeaconringtail; | |
1996 | begin=priv->txbeaconring; | |
1997 | buflist = priv->txbeaconbufstail; | |
1998 | count = priv->txbeaconcount; | |
1999 | break; | |
c8d86be3 GKH |
2000 | default: |
2001 | return -1; | |
2002 | break; | |
2003 | } | |
2004 | ||
c8d86be3 GKH |
2005 | memcpy(&dest, frag_hdr->addr1, ETH_ALEN); |
2006 | if (is_multicast_ether_addr(dest) || | |
2007 | is_broadcast_ether_addr(dest)) | |
2008 | { | |
2009 | Duration = 0; | |
2010 | RtsDur = 0; | |
2011 | bRTSEnable = 0; | |
2012 | bCTSEnable = 0; | |
2013 | ||
2014 | ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble); | |
2015 | TxDescDuration = ThisFrameTime; | |
2016 | } else {// Unicast packet | |
c8d86be3 GKH |
2017 | u16 AckTime; |
2018 | ||
2019 | //YJ,add,080828,for Keep alive | |
2020 | priv->NumTxUnicast++; | |
2021 | ||
1994130e LF |
2022 | /* Figure out ACK rate according to BSS basic rate |
2023 | * and Tx rate. */ | |
c8d86be3 | 2024 | AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send |
c8d86be3 GKH |
2025 | |
2026 | if ( ((len + sCrcLng) > priv->rts) && priv->rts ) | |
2027 | { // RTS/CTS. | |
2028 | u16 RtsTime, CtsTime; | |
2029 | //u16 CtsRate; | |
2030 | bRTSEnable = 1; | |
2031 | bCTSEnable = 0; | |
2032 | ||
2033 | // Rate and time required for RTS. | |
2034 | RtsTime = ComputeTxTime( sAckCtsLng/8,priv->ieee80211->basic_rate, 0, 0); | |
2035 | // Rate and time required for CTS. | |
2036 | CtsTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send | |
2037 | ||
2038 | // Figure out time required to transmit this frame. | |
2039 | ThisFrameTime = ComputeTxTime(len + sCrcLng, | |
2040 | rtl8180_rate2rate(rate), | |
2041 | 0, | |
2042 | bUseShortPreamble); | |
2043 | ||
2044 | // RTS-CTS-ThisFrame-ACK. | |
2045 | RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime; | |
2046 | ||
2047 | TxDescDuration = RtsTime + RtsDur; | |
2048 | } | |
2049 | else {// Normal case. | |
2050 | bCTSEnable = 0; | |
2051 | bRTSEnable = 0; | |
2052 | RtsDur = 0; | |
2053 | ||
2054 | ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble); | |
2055 | TxDescDuration = ThisFrameTime + aSifsTime + AckTime; | |
2056 | } | |
2057 | ||
b6b1ac69 | 2058 | if (!(frag_hdr->frame_control & IEEE80211_FCTL_MOREFRAGS)) { |
c8d86be3 GKH |
2059 | // ThisFrame-ACK. |
2060 | Duration = aSifsTime + AckTime; | |
2061 | } else { // One or more fragments remained. | |
2062 | u16 NextFragTime; | |
2063 | NextFragTime = ComputeTxTime( len + sCrcLng, //pretend following packet length equal current packet | |
2064 | rtl8180_rate2rate(rate), | |
2065 | 0, | |
2066 | bUseShortPreamble ); | |
2067 | ||
2068 | //ThisFrag-ACk-NextFrag-ACK. | |
2069 | Duration = NextFragTime + 3*aSifsTime + 2*AckTime; | |
2070 | } | |
2071 | ||
2072 | } // End of Unicast packet | |
2073 | ||
2074 | frag_hdr->duration_id = Duration; | |
c8d86be3 GKH |
2075 | |
2076 | buflen=priv->txbuffsize; | |
2077 | remain=len; | |
2078 | temp_tail = tail; | |
fd882783 | 2079 | |
c8d86be3 | 2080 | while(remain!=0){ |
c8d86be3 GKH |
2081 | mb(); |
2082 | if(!buflist){ | |
2083 | DMESGE("TX buffer error, cannot TX frames. pri %d.", priority); | |
c8d86be3 GKH |
2084 | return -1; |
2085 | } | |
2086 | buf=buflist->buf; | |
2087 | ||
fd882783 BZ |
2088 | if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) { |
2089 | DMESGW("No more TX desc, returning %x of %x", | |
2090 | remain, len); | |
2091 | priv->stats.txrdu++; | |
c8d86be3 | 2092 | return remain; |
c8d86be3 GKH |
2093 | } |
2094 | ||
2095 | *tail= 0; // zeroes header | |
2096 | *(tail+1) = 0; | |
2097 | *(tail+3) = 0; | |
2098 | *(tail+5) = 0; | |
2099 | *(tail+6) = 0; | |
2100 | *(tail+7) = 0; | |
2101 | ||
d44eb889 LF |
2102 | /*FIXME: this should be triggered by HW encryption parameters.*/ |
2103 | *tail |= (1<<15); /* no encrypt */ | |
fd882783 | 2104 | |
c8d86be3 | 2105 | if(remain==len && !descfrag) { |
1994130e | 2106 | ownbit_flag = false; |
c8d86be3 GKH |
2107 | *tail = *tail| (1<<29) ; //fist segment of the packet |
2108 | *tail = *tail |(len); | |
2109 | } else { | |
2110 | ownbit_flag = true; | |
2111 | } | |
2112 | ||
2113 | for(i=0;i<buflen&& remain >0;i++,remain--){ | |
2114 | ((u8*)buf)[i]=txbuf[i]; //copy data into descriptor pointed DMAble buffer | |
2115 | if(remain == 4 && i+4 >= buflen) break; | |
2116 | /* ensure the last desc has at least 4 bytes payload */ | |
2117 | ||
2118 | } | |
2119 | txbuf = txbuf + i; | |
2120 | *(tail+3)=*(tail+3) &~ 0xfff; | |
2121 | *(tail+3)=*(tail+3) | i; // buffer lenght | |
2122 | // Use short preamble or not | |
2123 | if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2124 | if (priv->plcp_preamble_mode==1 && rate!=0) // short mode now, not long! | |
b3184e1e | 2125 | ;// *tail |= (1<<16); // enable short preamble mode. |
c8d86be3 | 2126 | |
c8d86be3 GKH |
2127 | if(bCTSEnable) { |
2128 | *tail |= (1<<18); | |
2129 | } | |
2130 | ||
2131 | if(bRTSEnable) //rts enable | |
2132 | { | |
2133 | *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE | |
2134 | *tail |= (1<<23);//rts enable | |
2135 | *(tail+1) |=(RtsDur&0xffff);//RTS Duration | |
2136 | } | |
2137 | *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION | |
2138 | // *(tail+3) |= (0xe6<<16); | |
2139 | *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ; | |
c8d86be3 GKH |
2140 | |
2141 | *tail = *tail | ((rate&0xf) << 24); | |
c8d86be3 GKH |
2142 | |
2143 | /* hw_plcp_len is not used for rtl8180 chip */ | |
2144 | /* FIXME */ | |
d44eb889 | 2145 | if (!priv->hw_plcp_len) { |
fd882783 | 2146 | duration = rtl8180_len2duration(len, rate, &ext); |
c8d86be3 GKH |
2147 | *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16); |
2148 | if(ext) *(tail+1) = *(tail+1) |(1<<31); //plcp length extension | |
2149 | } | |
2150 | ||
2151 | if(morefrag) *tail = (*tail) | (1<<17); // more fragment | |
2152 | if(!remain) *tail = (*tail) | (1<<28); // last segment of frame | |
2153 | ||
c8d86be3 GKH |
2154 | *(tail+5) = *(tail+5)|(2<<27); |
2155 | *(tail+7) = *(tail+7)|(1<<4); | |
2156 | ||
2157 | wmb(); | |
2158 | if(ownbit_flag) | |
2159 | { | |
2160 | *tail = *tail | (1<<31); // descriptor ready to be txed | |
2161 | } | |
2162 | ||
c8d86be3 GKH |
2163 | if((tail - begin)/8 == count-1) |
2164 | tail=begin; | |
c8d86be3 GKH |
2165 | else |
2166 | tail=tail+8; | |
2167 | ||
2168 | buflist=buflist->next; | |
2169 | ||
2170 | mb(); | |
2171 | ||
2172 | switch(priority) { | |
2173 | case MANAGE_PRIORITY: | |
2174 | priv->txmapringtail=tail; | |
2175 | priv->txmapbufstail=buflist; | |
2176 | break; | |
c8d86be3 GKH |
2177 | case BK_PRIORITY: |
2178 | priv->txbkpringtail=tail; | |
2179 | priv->txbkpbufstail=buflist; | |
2180 | break; | |
c8d86be3 GKH |
2181 | case BE_PRIORITY: |
2182 | priv->txbepringtail=tail; | |
2183 | priv->txbepbufstail=buflist; | |
2184 | break; | |
c8d86be3 GKH |
2185 | case VI_PRIORITY: |
2186 | priv->txvipringtail=tail; | |
2187 | priv->txvipbufstail=buflist; | |
2188 | break; | |
c8d86be3 GKH |
2189 | case VO_PRIORITY: |
2190 | priv->txvopringtail=tail; | |
2191 | priv->txvopbufstail=buflist; | |
2192 | break; | |
c8d86be3 GKH |
2193 | case HI_PRIORITY: |
2194 | priv->txhpringtail=tail; | |
2195 | priv->txhpbufstail = buflist; | |
2196 | break; | |
c8d86be3 GKH |
2197 | case BEACON_PRIORITY: |
2198 | /* the HW seems to be happy with the 1st | |
2199 | * descriptor filled and the 2nd empty... | |
2200 | * So always update descriptor 1 and never | |
2201 | * touch 2nd | |
2202 | */ | |
c8d86be3 | 2203 | break; |
c8d86be3 | 2204 | } |
c8d86be3 GKH |
2205 | } |
2206 | *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed | |
2207 | rtl8180_dma_kick(dev,priority); | |
c8d86be3 GKH |
2208 | |
2209 | return 0; | |
c8d86be3 GKH |
2210 | } |
2211 | ||
c8d86be3 GKH |
2212 | void rtl8180_irq_rx_tasklet(struct r8180_priv * priv); |
2213 | ||
c8d86be3 GKH |
2214 | void rtl8180_link_change(struct net_device *dev) |
2215 | { | |
2216 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2217 | u16 beacon_interval; | |
c8d86be3 | 2218 | struct ieee80211_network *net = &priv->ieee80211->current_network; |
c8d86be3 | 2219 | |
fd882783 | 2220 | rtl8180_update_msr(dev); |
c8d86be3 GKH |
2221 | |
2222 | rtl8180_set_mode(dev,EPROM_CMD_CONFIG); | |
2223 | ||
2224 | write_nic_dword(dev,BSSID,((u32*)net->bssid)[0]); | |
2225 | write_nic_word(dev,BSSID+4,((u16*)net->bssid)[2]); | |
2226 | ||
c8d86be3 GKH |
2227 | beacon_interval = read_nic_dword(dev,BEACON_INTERVAL); |
2228 | beacon_interval &= ~ BEACON_INTERVAL_MASK; | |
2229 | beacon_interval |= net->beacon_interval; | |
2230 | write_nic_dword(dev, BEACON_INTERVAL, beacon_interval); | |
2231 | ||
2232 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
2233 | ||
d44eb889 | 2234 | rtl8180_set_chan(dev, priv->chan); |
c8d86be3 GKH |
2235 | } |
2236 | ||
2237 | void rtl8180_rq_tx_ack(struct net_device *dev){ | |
2238 | ||
2239 | struct r8180_priv *priv = ieee80211_priv(dev); | |
fd882783 | 2240 | |
c8d86be3 GKH |
2241 | write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)|CONFIG4_PWRMGT); |
2242 | priv->ack_tx_to_ieee = 1; | |
2243 | } | |
2244 | ||
2245 | short rtl8180_is_tx_queue_empty(struct net_device *dev){ | |
2246 | ||
2247 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2248 | u32* d; | |
2249 | ||
2250 | for (d = priv->txmapring; | |
2251 | d < priv->txmapring + priv->txringcount;d+=8) | |
2252 | if(*d & (1<<31)) return 0; | |
2253 | ||
2254 | for (d = priv->txbkpring; | |
2255 | d < priv->txbkpring + priv->txringcount;d+=8) | |
2256 | if(*d & (1<<31)) return 0; | |
2257 | ||
2258 | for (d = priv->txbepring; | |
2259 | d < priv->txbepring + priv->txringcount;d+=8) | |
2260 | if(*d & (1<<31)) return 0; | |
2261 | ||
2262 | for (d = priv->txvipring; | |
2263 | d < priv->txvipring + priv->txringcount;d+=8) | |
2264 | if(*d & (1<<31)) return 0; | |
2265 | ||
2266 | for (d = priv->txvopring; | |
2267 | d < priv->txvopring + priv->txringcount;d+=8) | |
2268 | if(*d & (1<<31)) return 0; | |
2269 | ||
2270 | for (d = priv->txhpring; | |
2271 | d < priv->txhpring + priv->txringcount;d+=8) | |
2272 | if(*d & (1<<31)) return 0; | |
2273 | return 1; | |
2274 | } | |
2275 | /* FIXME FIXME 5msecs is random */ | |
2276 | #define HW_WAKE_DELAY 5 | |
2277 | ||
2278 | void rtl8180_hw_wakeup(struct net_device *dev) | |
2279 | { | |
2280 | unsigned long flags; | |
c8d86be3 GKH |
2281 | struct r8180_priv *priv = ieee80211_priv(dev); |
2282 | ||
2283 | spin_lock_irqsave(&priv->ps_lock,flags); | |
c8d86be3 | 2284 | write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)&~CONFIG4_PWRMGT); |
fd882783 | 2285 | if (priv->rf_wakeup) |
c8d86be3 | 2286 | priv->rf_wakeup(dev); |
c8d86be3 GKH |
2287 | spin_unlock_irqrestore(&priv->ps_lock,flags); |
2288 | } | |
2289 | ||
2290 | void rtl8180_hw_sleep_down(struct net_device *dev) | |
2291 | { | |
2292 | unsigned long flags; | |
c8d86be3 GKH |
2293 | struct r8180_priv *priv = ieee80211_priv(dev); |
2294 | ||
2295 | spin_lock_irqsave(&priv->ps_lock,flags); | |
c8d86be3 GKH |
2296 | if(priv->rf_sleep) |
2297 | priv->rf_sleep(dev); | |
2298 | spin_unlock_irqrestore(&priv->ps_lock,flags); | |
2299 | } | |
2300 | ||
c8d86be3 GKH |
2301 | void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl) |
2302 | { | |
c8d86be3 | 2303 | struct r8180_priv *priv = ieee80211_priv(dev); |
c8d86be3 GKH |
2304 | u32 rb = jiffies; |
2305 | unsigned long flags; | |
2306 | ||
2307 | spin_lock_irqsave(&priv->ps_lock,flags); | |
2308 | ||
2309 | /* Writing HW register with 0 equals to disable | |
2310 | * the timer, that is not really what we want | |
2311 | */ | |
2312 | tl -= MSECS(4+16+7); | |
2313 | ||
c8d86be3 GKH |
2314 | /* If the interval in witch we are requested to sleep is too |
2315 | * short then give up and remain awake | |
2316 | */ | |
2317 | if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME)) | |
2318 | ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) { | |
2319 | spin_unlock_irqrestore(&priv->ps_lock,flags); | |
2320 | printk("too short to sleep\n"); | |
2321 | return; | |
2322 | } | |
2323 | ||
c8d86be3 GKH |
2324 | { |
2325 | u32 tmp = (tl>rb)?(tl-rb):(rb-tl); | |
c8d86be3 | 2326 | |
c8d86be3 GKH |
2327 | priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp); |
2328 | ||
2329 | queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb | |
2330 | } | |
2331 | /* if we suspect the TimerInt is gone beyond tl | |
2332 | * while setting it, then give up | |
2333 | */ | |
fd882783 | 2334 | |
c8d86be3 GKH |
2335 | if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))|| |
2336 | ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) { | |
2337 | spin_unlock_irqrestore(&priv->ps_lock,flags); | |
2338 | return; | |
2339 | } | |
c8d86be3 GKH |
2340 | |
2341 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq); | |
2342 | spin_unlock_irqrestore(&priv->ps_lock,flags); | |
2343 | } | |
2344 | ||
c8d86be3 GKH |
2345 | void rtl8180_wmm_param_update(struct work_struct * work) |
2346 | { | |
2347 | struct ieee80211_device * ieee = container_of(work, struct ieee80211_device,wmm_param_update_wq); | |
c8d86be3 | 2348 | struct net_device *dev = ieee->dev; |
c8d86be3 GKH |
2349 | u8 *ac_param = (u8 *)(ieee->current_network.wmm_param); |
2350 | u8 mode = ieee->current_network.mode; | |
2351 | AC_CODING eACI; | |
2352 | AC_PARAM AcParam; | |
2353 | PAC_PARAM pAcParam; | |
2354 | u8 i; | |
2355 | ||
c8d86be3 GKH |
2356 | if(!ieee->current_network.QoS_Enable){ |
2357 | //legacy ac_xx_param update | |
2358 | AcParam.longData = 0; | |
2359 | AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS. | |
2360 | AcParam.f.AciAifsn.f.ACM = 0; | |
2361 | AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin. | |
2362 | AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax. | |
2363 | AcParam.f.TXOPLimit = 0; | |
2364 | for(eACI = 0; eACI < AC_MAX; eACI++){ | |
2365 | AcParam.f.AciAifsn.f.ACI = (u8)eACI; | |
2366 | { | |
2367 | u8 u1bAIFS; | |
2368 | u32 u4bAcParam; | |
2369 | pAcParam = (PAC_PARAM)(&AcParam); | |
2370 | // Retrive paramters to udpate. | |
2371 | u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN *(((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime; | |
2372 | u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)| | |
2373 | (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)| | |
2374 | (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)| | |
2375 | (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); | |
2376 | switch(eACI){ | |
2377 | case AC1_BK: | |
2378 | write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); | |
2379 | break; | |
c8d86be3 GKH |
2380 | case AC0_BE: |
2381 | write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); | |
2382 | break; | |
c8d86be3 GKH |
2383 | case AC2_VI: |
2384 | write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); | |
2385 | break; | |
c8d86be3 GKH |
2386 | case AC3_VO: |
2387 | write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); | |
2388 | break; | |
c8d86be3 GKH |
2389 | default: |
2390 | printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI); | |
2391 | break; | |
2392 | } | |
2393 | } | |
2394 | } | |
2395 | return; | |
2396 | } | |
2397 | ||
2398 | for(i = 0; i < AC_MAX; i++){ | |
2399 | //AcParam.longData = 0; | |
2400 | pAcParam = (AC_PARAM * )ac_param; | |
2401 | { | |
2402 | AC_CODING eACI; | |
2403 | u8 u1bAIFS; | |
2404 | u32 u4bAcParam; | |
2405 | ||
2406 | // Retrive paramters to udpate. | |
2407 | eACI = pAcParam->f.AciAifsn.f.ACI; | |
2408 | //Mode G/A: slotTimeTimer = 9; Mode B: 20 | |
2409 | u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime; | |
2410 | u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) | | |
2411 | (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) | | |
2412 | (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) | | |
2413 | (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); | |
2414 | ||
2415 | switch(eACI){ | |
2416 | case AC1_BK: | |
2417 | write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); | |
2418 | break; | |
c8d86be3 GKH |
2419 | case AC0_BE: |
2420 | write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); | |
2421 | break; | |
c8d86be3 GKH |
2422 | case AC2_VI: |
2423 | write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); | |
2424 | break; | |
c8d86be3 GKH |
2425 | case AC3_VO: |
2426 | write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); | |
2427 | break; | |
c8d86be3 GKH |
2428 | default: |
2429 | printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI); | |
2430 | break; | |
2431 | } | |
2432 | } | |
2433 | ac_param += (sizeof(AC_PARAM)); | |
2434 | } | |
c8d86be3 GKH |
2435 | } |
2436 | ||
c8d86be3 | 2437 | void rtl8180_tx_irq_wq(struct work_struct *work); |
c8d86be3 GKH |
2438 | void rtl8180_restart_wq(struct work_struct *work); |
2439 | //void rtl8180_rq_tx_ack(struct work_struct *work); | |
c8d86be3 | 2440 | void rtl8180_watch_dog_wq(struct work_struct *work); |
c8d86be3 | 2441 | void rtl8180_hw_wakeup_wq(struct work_struct *work); |
c8d86be3 | 2442 | void rtl8180_hw_sleep_wq(struct work_struct *work); |
c8d86be3 | 2443 | void rtl8180_sw_antenna_wq(struct work_struct *work); |
0370453f BZ |
2444 | void rtl8180_watch_dog(struct net_device *dev); |
2445 | ||
c8d86be3 GKH |
2446 | void watch_dog_adaptive(unsigned long data) |
2447 | { | |
fd882783 BZ |
2448 | struct r8180_priv* priv = ieee80211_priv((struct net_device *)data); |
2449 | ||
2450 | if (!priv->up) { | |
c8d86be3 GKH |
2451 | DMESG("<----watch_dog_adaptive():driver is not up!\n"); |
2452 | return; | |
2453 | } | |
2454 | ||
c8d86be3 | 2455 | // Tx High Power Mechanism. |
c8d86be3 | 2456 | if(CheckHighPower((struct net_device *)data)) |
c8d86be3 | 2457 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq); |
c8d86be3 | 2458 | |
c8d86be3 | 2459 | // Tx Power Tracking on 87SE. |
cffd4e16 | 2460 | if (CheckTxPwrTracking((struct net_device *)data)) |
c8d86be3 | 2461 | TxPwrTracking87SE((struct net_device *)data); |
c8d86be3 GKH |
2462 | |
2463 | // Perform DIG immediately. | |
c8d86be3 | 2464 | if(CheckDig((struct net_device *)data) == true) |
c8d86be3 | 2465 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq); |
c8d86be3 GKH |
2466 | rtl8180_watch_dog((struct net_device *)data); |
2467 | ||
c8d86be3 GKH |
2468 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem); |
2469 | ||
2470 | priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME); | |
2471 | add_timer(&priv->watch_dog_timer); | |
c8d86be3 GKH |
2472 | } |
2473 | ||
c8d86be3 GKH |
2474 | static CHANNEL_LIST ChannelPlan[] = { |
2475 | {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC | |
2476 | {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC | |
2477 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI | |
2478 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI. | |
2479 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI. | |
2480 | {{14,36,40,44,48,52,56,60,64},9}, //MKK | |
2481 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1 | |
2482 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel. | |
2483 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC | |
2484 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626 | |
2485 | {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826 | |
2486 | }; | |
2487 | ||
2488 | static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee) | |
2489 | { | |
2490 | int i; | |
2491 | ||
2492 | //lzm add 080826 | |
2493 | ieee->MinPassiveChnlNum=MAX_CHANNEL_NUMBER+1; | |
2494 | ieee->IbssStartChnl=0; | |
2495 | ||
2496 | switch (channel_plan) | |
2497 | { | |
2498 | case COUNTRY_CODE_FCC: | |
2499 | case COUNTRY_CODE_IC: | |
2500 | case COUNTRY_CODE_ETSI: | |
2501 | case COUNTRY_CODE_SPAIN: | |
2502 | case COUNTRY_CODE_FRANCE: | |
2503 | case COUNTRY_CODE_MKK: | |
2504 | case COUNTRY_CODE_MKK1: | |
2505 | case COUNTRY_CODE_ISRAEL: | |
2506 | case COUNTRY_CODE_TELEC: | |
2507 | { | |
2508 | Dot11d_Init(ieee); | |
2509 | ieee->bGlobalDomain = false; | |
2510 | if (ChannelPlan[channel_plan].Len != 0){ | |
2511 | // Clear old channel map | |
2512 | memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); | |
2513 | // Set new channel map | |
2514 | for (i=0;i<ChannelPlan[channel_plan].Len;i++) | |
2515 | { | |
2516 | if(ChannelPlan[channel_plan].Channel[i] <= 14) | |
2517 | GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1; | |
2518 | } | |
2519 | } | |
2520 | break; | |
2521 | } | |
2522 | case COUNTRY_CODE_GLOBAL_DOMAIN: | |
2523 | { | |
2524 | GET_DOT11D_INFO(ieee)->bEnabled = 0; | |
2525 | Dot11d_Reset(ieee); | |
2526 | ieee->bGlobalDomain = true; | |
2527 | break; | |
2528 | } | |
2529 | case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826 | |
2530 | { | |
2531 | ieee->MinPassiveChnlNum=12; | |
2532 | ieee->IbssStartChnl= 10; | |
2533 | break; | |
2534 | } | |
2535 | default: | |
2536 | { | |
2537 | Dot11d_Init(ieee); | |
2538 | ieee->bGlobalDomain = false; | |
2539 | memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); | |
2540 | for (i=1;i<=14;i++) | |
2541 | { | |
2542 | GET_DOT11D_INFO(ieee)->channel_map[i] = 1; | |
2543 | } | |
2544 | break; | |
2545 | } | |
2546 | } | |
2547 | } | |
c8d86be3 | 2548 | |
c8d86be3 | 2549 | void GPIOChangeRFWorkItemCallBack(struct work_struct *work); |
c8d86be3 GKH |
2550 | |
2551 | //YJ,add,080828 | |
2552 | static void rtl8180_statistics_init(struct Stats *pstats) | |
2553 | { | |
2554 | memset(pstats, 0, sizeof(struct Stats)); | |
2555 | } | |
fd882783 | 2556 | |
c8d86be3 GKH |
2557 | static void rtl8180_link_detect_init(plink_detect_t plink_detect) |
2558 | { | |
2559 | memset(plink_detect, 0, sizeof(link_detect_t)); | |
2560 | plink_detect->SlotNum = DEFAULT_SLOT_NUM; | |
2561 | } | |
2562 | //YJ,add,080828,end | |
2563 | ||
742821ce LF |
2564 | static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom) |
2565 | { | |
2566 | struct net_device *dev = eeprom->data; | |
2567 | u8 reg = read_nic_byte(dev, EPROM_CMD); | |
2568 | ||
2569 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
2570 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
2571 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
2572 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
2573 | } | |
2574 | ||
2575 | static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
2576 | { | |
2577 | struct net_device *dev = eeprom->data; | |
2578 | u8 reg = 2 << 6; | |
2579 | ||
2580 | if (eeprom->reg_data_in) | |
2581 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
2582 | if (eeprom->reg_data_out) | |
2583 | reg |= RTL818X_EEPROM_CMD_READ; | |
2584 | if (eeprom->reg_data_clock) | |
2585 | reg |= RTL818X_EEPROM_CMD_CK; | |
2586 | if (eeprom->reg_chip_select) | |
2587 | reg |= RTL818X_EEPROM_CMD_CS; | |
2588 | ||
2589 | write_nic_byte(dev, EPROM_CMD, reg); | |
2590 | read_nic_byte(dev, EPROM_CMD); | |
2591 | udelay(10); | |
2592 | } | |
2593 | ||
c8d86be3 GKH |
2594 | short rtl8180_init(struct net_device *dev) |
2595 | { | |
2596 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2597 | u16 word; | |
2598 | u16 version; | |
c8d86be3 GKH |
2599 | u32 usValue; |
2600 | u16 tmpu16; | |
2601 | int i, j; | |
742821ce LF |
2602 | struct eeprom_93cx6 eeprom; |
2603 | u16 eeprom_val; | |
2604 | ||
2605 | eeprom.data = dev; | |
2606 | eeprom.register_read = rtl8187se_eeprom_register_read; | |
2607 | eeprom.register_write = rtl8187se_eeprom_register_write; | |
2608 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
c8d86be3 | 2609 | |
742821ce LF |
2610 | eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val); |
2611 | priv->channel_plan = eeprom_val & 0xFF; | |
c8d86be3 GKH |
2612 | if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){ |
2613 | printk("rtl8180_init:Error channel plan! Set to default.\n"); | |
2614 | priv->channel_plan = 0; | |
2615 | } | |
c8d86be3 GKH |
2616 | |
2617 | DMESG("Channel plan is %d\n",priv->channel_plan); | |
2618 | rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211); | |
c8d86be3 | 2619 | |
c8d86be3 GKH |
2620 | //FIXME: these constants are placed in a bad pleace. |
2621 | priv->txbuffsize = 2048;//1024; | |
2622 | priv->txringcount = 32;//32; | |
2623 | priv->rxbuffersize = 2048;//1024; | |
2624 | priv->rxringcount = 64;//32; | |
2625 | priv->txbeaconcount = 2; | |
2626 | priv->rx_skb_complete = 1; | |
c8d86be3 | 2627 | |
c8d86be3 GKH |
2628 | priv->RFChangeInProgress = false; |
2629 | priv->SetRFPowerStateInProgress = false; | |
2630 | priv->RFProgType = 0; | |
2631 | priv->bInHctTest = false; | |
2632 | ||
2633 | priv->irq_enabled=0; | |
2634 | ||
c8d86be3 GKH |
2635 | rtl8180_statistics_init(&priv->stats); |
2636 | rtl8180_link_detect_init(&priv->link_detect); | |
c8d86be3 GKH |
2637 | |
2638 | priv->ack_tx_to_ieee = 0; | |
2639 | priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; | |
2640 | priv->ieee80211->iw_mode = IW_MODE_INFRA; | |
2641 | priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN | | |
2642 | IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | | |
2643 | IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE; | |
2644 | priv->ieee80211->active_scan = 1; | |
2645 | priv->ieee80211->rate = 110; //11 mbps | |
2646 | priv->ieee80211->modulation = IEEE80211_CCK_MODULATION; | |
2647 | priv->ieee80211->host_encrypt = 1; | |
2648 | priv->ieee80211->host_decrypt = 1; | |
2649 | priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup; | |
2650 | priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack; | |
2651 | priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep; | |
2652 | priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty; | |
2653 | ||
2654 | priv->hw_wep = hwwep; | |
2655 | priv->prism_hdr=0; | |
2656 | priv->dev=dev; | |
2657 | priv->retry_rts = DEFAULT_RETRY_RTS; | |
2658 | priv->retry_data = DEFAULT_RETRY_DATA; | |
2659 | priv->RFChangeInProgress = false; | |
2660 | priv->SetRFPowerStateInProgress = false; | |
2661 | priv->RFProgType = 0; | |
2662 | priv->bInHctTest = false; | |
2663 | priv->bInactivePs = true;//false; | |
2664 | priv->ieee80211->bInactivePs = priv->bInactivePs; | |
2665 | priv->bSwRfProcessing = false; | |
2666 | priv->eRFPowerState = eRfOff; | |
2667 | priv->RfOffReason = 0; | |
2668 | priv->LedStrategy = SW_LED_MODE0; | |
c8d86be3 GKH |
2669 | priv->TxPollingTimes = 0;//lzm add 080826 |
2670 | priv->bLeisurePs = true; | |
2671 | priv->dot11PowerSaveMode = eActive; | |
c8d86be3 GKH |
2672 | priv->AdMinCheckPeriod = 5; |
2673 | priv->AdMaxCheckPeriod = 10; | |
c8d86be3 GKH |
2674 | priv->AdMaxRxSsThreshold = 30;//60->30 |
2675 | priv->AdRxSsThreshold = 20;//50->20 | |
2676 | priv->AdCheckPeriod = priv->AdMinCheckPeriod; | |
2677 | priv->AdTickCount = 0; | |
2678 | priv->AdRxSignalStrength = -1; | |
2679 | priv->RegSwAntennaDiversityMechanism = 0; | |
2680 | priv->RegDefaultAntenna = 0; | |
2681 | priv->SignalStrength = 0; | |
2682 | priv->AdRxOkCnt = 0; | |
2683 | priv->CurrAntennaIndex = 0; | |
2684 | priv->AdRxSsBeforeSwitched = 0; | |
2685 | init_timer(&priv->SwAntennaDiversityTimer); | |
2686 | priv->SwAntennaDiversityTimer.data = (unsigned long)dev; | |
2687 | priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback; | |
c8d86be3 GKH |
2688 | priv->bDigMechanism = 1; |
2689 | priv->InitialGain = 6; | |
2690 | priv->bXtalCalibration = false; | |
2691 | priv->XtalCal_Xin = 0; | |
2692 | priv->XtalCal_Xout = 0; | |
2693 | priv->bTxPowerTrack = false; | |
2694 | priv->ThermalMeter = 0; | |
2695 | priv->FalseAlarmRegValue = 0; | |
2696 | priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG. | |
2697 | priv->DIG_NumberFallbackVote = 0; | |
2698 | priv->DIG_NumberUpgradeVote = 0; | |
2699 | priv->LastSignalStrengthInPercent = 0; | |
2700 | priv->Stats_SignalStrength = 0; | |
2701 | priv->LastRxPktAntenna = 0; | |
2702 | priv->SignalQuality = 0; // in 0-100 index. | |
2703 | priv->Stats_SignalQuality = 0; | |
2704 | priv->RecvSignalPower = 0; // in dBm. | |
2705 | priv->Stats_RecvSignalPower = 0; | |
2706 | priv->AdMainAntennaRxOkCnt = 0; | |
2707 | priv->AdAuxAntennaRxOkCnt = 0; | |
2708 | priv->bHWAdSwitched = false; | |
2709 | priv->bRegHighPowerMechanism = true; | |
2710 | priv->RegHiPwrUpperTh = 77; | |
2711 | priv->RegHiPwrLowerTh = 75; | |
2712 | priv->RegRSSIHiPwrUpperTh = 70; | |
2713 | priv->RegRSSIHiPwrLowerTh = 20; | |
2714 | priv->bCurCCKPkt = false; | |
2715 | priv->UndecoratedSmoothedSS = -1; | |
2716 | priv->bToUpdateTxPwr = false; | |
2717 | priv->CurCCKRSSI = 0; | |
2718 | priv->RxPower = 0; | |
2719 | priv->RSSI = 0; | |
c8d86be3 GKH |
2720 | priv->NumTxOkTotal = 0; |
2721 | priv->NumTxUnicast = 0; | |
2722 | priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL; | |
2723 | priv->PowerProfile = POWER_PROFILE_AC; | |
1994130e LF |
2724 | priv->CurrRetryCnt = 0; |
2725 | priv->LastRetryCnt = 0; | |
2726 | priv->LastTxokCnt = 0; | |
2727 | priv->LastRxokCnt = 0; | |
2728 | priv->LastRetryRate = 0; | |
2729 | priv->bTryuping = 0; | |
2730 | priv->CurrTxRate = 0; | |
2731 | priv->CurrRetryRate = 0; | |
2732 | priv->TryupingCount = 0; | |
2733 | priv->TryupingCountNoData = 0; | |
2734 | priv->TryDownCountLowData = 0; | |
2735 | priv->LastTxOKBytes = 0; | |
2736 | priv->LastFailTxRate = 0; | |
2737 | priv->LastFailTxRateSS = 0; | |
2738 | priv->FailTxRateCount = 0; | |
2739 | priv->LastTxThroughput = 0; | |
2740 | priv->NumTxOkBytesTotal = 0; | |
c8d86be3 GKH |
2741 | priv->ForcedDataRate = 0; |
2742 | priv->RegBModeGainStage = 1; | |
2743 | ||
1994130e | 2744 | priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; |
c8d86be3 GKH |
2745 | spin_lock_init(&priv->irq_lock); |
2746 | spin_lock_init(&priv->irq_th_lock); | |
2747 | spin_lock_init(&priv->tx_lock); | |
2748 | spin_lock_init(&priv->ps_lock); | |
2749 | spin_lock_init(&priv->rf_ps_lock); | |
1994130e LF |
2750 | sema_init(&priv->wx_sem, 1); |
2751 | sema_init(&priv->rf_state, 1); | |
2752 | INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq); | |
2753 | INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq); | |
2754 | INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq, | |
2755 | (void *)rtl8180_hw_wakeup_wq); | |
2756 | INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq, | |
2757 | (void *)rtl8180_hw_sleep_wq); | |
2758 | INIT_WORK(&priv->ieee80211->wmm_param_update_wq, | |
2759 | (void *)rtl8180_wmm_param_update); | |
2760 | INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq, | |
2761 | (void *)rtl8180_rate_adapter); | |
2762 | INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq, | |
2763 | (void *)rtl8180_hw_dig_wq); | |
2764 | INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq, | |
2765 | (void *)rtl8180_tx_pw_wq); | |
2766 | INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem, | |
2767 | (void *) GPIOChangeRFWorkItemCallBack); | |
c8d86be3 GKH |
2768 | tasklet_init(&priv->irq_rx_tasklet, |
2769 | (void(*)(unsigned long)) rtl8180_irq_rx_tasklet, | |
2770 | (unsigned long)priv); | |
fd882783 | 2771 | |
1994130e | 2772 | init_timer(&priv->watch_dog_timer); |
c8d86be3 GKH |
2773 | priv->watch_dog_timer.data = (unsigned long)dev; |
2774 | priv->watch_dog_timer.function = watch_dog_adaptive; | |
c8d86be3 | 2775 | |
1994130e LF |
2776 | init_timer(&priv->rateadapter_timer); |
2777 | priv->rateadapter_timer.data = (unsigned long)dev; | |
2778 | priv->rateadapter_timer.function = timer_rate_adaptive; | |
2779 | priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD; | |
2780 | priv->bEnhanceTxPwr = false; | |
c8d86be3 GKH |
2781 | |
2782 | priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit; | |
2783 | priv->ieee80211->set_chan = rtl8180_set_chan; | |
2784 | priv->ieee80211->link_change = rtl8180_link_change; | |
2785 | priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit; | |
2786 | priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop; | |
2787 | priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume; | |
2788 | ||
2789 | priv->ieee80211->init_wmmparam_flag = 0; | |
2790 | ||
2791 | priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon; | |
2792 | priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable; | |
2793 | priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; | |
2794 | ||
c8d86be3 GKH |
2795 | priv->MWIEnable = 0; |
2796 | ||
2797 | priv->ShortRetryLimit = 7; | |
2798 | priv->LongRetryLimit = 7; | |
2799 | priv->EarlyRxThreshold = 7; | |
2800 | ||
2801 | priv->CSMethod = (0x01 << 29); | |
2802 | ||
1994130e LF |
2803 | priv->TransmitConfig = TCR_DurProcMode_OFFSET | |
2804 | (7<<TCR_MXDMA_OFFSET) | | |
2805 | (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | | |
2806 | (priv->LongRetryLimit<<TCR_LRL_OFFSET) | | |
2807 | (0 ? TCR_SAT : 0); | |
2808 | ||
2809 | priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF | | |
2810 | RCR_AB | RCR_AM | RCR_APM | | |
2811 | (7<<RCR_MXDMA_OFFSET) | | |
2812 | (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | | |
2813 | (priv->EarlyRxThreshold == 7 ? | |
2814 | RCR_ONLYERLPKT : 0); | |
c8d86be3 GKH |
2815 | |
2816 | priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER | | |
1994130e LF |
2817 | IMR_THPDER | IMR_THPDOK | |
2818 | IMR_TVODER | IMR_TVODOK | | |
2819 | IMR_TVIDER | IMR_TVIDOK | | |
2820 | IMR_TBEDER | IMR_TBEDOK | | |
2821 | IMR_TBKDER | IMR_TBKDOK | | |
2822 | IMR_RDU | | |
2823 | IMR_RER | IMR_ROK | | |
2824 | IMR_RQoSOK; | |
c8d86be3 GKH |
2825 | |
2826 | priv->InitialGain = 6; | |
c8d86be3 | 2827 | |
d44eb889 LF |
2828 | DMESG("MAC controller is a RTL8187SE b/g"); |
2829 | priv->phy_ver = 2; | |
c8d86be3 | 2830 | |
d44eb889 LF |
2831 | priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION; |
2832 | priv->ieee80211->short_slot = 1; | |
c8d86be3 | 2833 | |
c8d86be3 | 2834 | // just for sync 85 |
c8d86be3 GKH |
2835 | priv->enable_gpio0 = 0; |
2836 | ||
742821ce LF |
2837 | eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val); |
2838 | usValue = eeprom_val; | |
c8d86be3 | 2839 | DMESG("usValue is 0x%x\n",usValue); |
c8d86be3 | 2840 | //3Read AntennaDiversity |
fd882783 | 2841 | |
c8d86be3 | 2842 | // SW Antenna Diversity. |
fd882783 | 2843 | if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE) |
c8d86be3 | 2844 | priv->EEPROMSwAntennaDiversity = false; |
c8d86be3 | 2845 | else |
c8d86be3 | 2846 | priv->EEPROMSwAntennaDiversity = true; |
fd882783 | 2847 | |
c8d86be3 | 2848 | // Default Antenna to use. |
fd882783 | 2849 | if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1) |
c8d86be3 | 2850 | priv->EEPROMDefaultAntenna1 = false; |
c8d86be3 | 2851 | else |
c8d86be3 | 2852 | priv->EEPROMDefaultAntenna1 = true; |
c8d86be3 | 2853 | |
c8d86be3 | 2854 | if( priv->RegSwAntennaDiversityMechanism == 0 ) // Auto |
fd882783 | 2855 | /* 0: default from EEPROM. */ |
c8d86be3 | 2856 | priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity; |
c8d86be3 | 2857 | else |
fd882783 | 2858 | /* 1:disable antenna diversity, 2: enable antenna diversity. */ |
c8d86be3 | 2859 | priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1)? false : true); |
c8d86be3 | 2860 | |
fd882783 BZ |
2861 | if (priv->RegDefaultAntenna == 0) |
2862 | /* 0: default from EEPROM. */ | |
c8d86be3 | 2863 | priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1; |
c8d86be3 | 2864 | else |
fd882783 | 2865 | /* 1: main, 2: aux. */ |
c8d86be3 | 2866 | priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna== 2) ? true : false); |
fd882783 | 2867 | |
c8d86be3 GKH |
2868 | /* rtl8185 can calc plcp len in HW.*/ |
2869 | priv->hw_plcp_len = 1; | |
2870 | ||
2871 | priv->plcp_preamble_mode = 2; | |
2872 | /*the eeprom type is stored in RCR register bit #6 */ | |
fd882783 | 2873 | if (RCR_9356SEL & read_nic_dword(dev, RCR)) |
c8d86be3 | 2874 | priv->epromtype=EPROM_93c56; |
fd882783 | 2875 | else |
c8d86be3 | 2876 | priv->epromtype=EPROM_93c46; |
c8d86be3 | 2877 | |
742821ce LF |
2878 | eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *) |
2879 | dev->dev_addr, 3); | |
c8d86be3 GKH |
2880 | |
2881 | for(i=1,j=0; i<14; i+=2,j++){ | |
742821ce | 2882 | eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word); |
c8d86be3 GKH |
2883 | priv->chtxpwr[i]=word & 0xff; |
2884 | priv->chtxpwr[i+1]=(word & 0xff00)>>8; | |
c8d86be3 | 2885 | } |
d44eb889 | 2886 | for (i = 1, j = 0; i < 14; i += 2, j++) { |
742821ce | 2887 | eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word); |
d44eb889 | 2888 | priv->chtxpwr_ofdm[i] = word & 0xff; |
1994130e | 2889 | priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8; |
c8d86be3 | 2890 | } |
fd882783 | 2891 | |
1994130e | 2892 | /* 3Read crystal calibtration and thermal meter indication on 87SE. */ |
742821ce | 2893 | eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16); |
c8d86be3 | 2894 | |
1994130e LF |
2895 | /* Crystal calibration for Xin and Xout resp. */ |
2896 | priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; | |
2897 | priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4; | |
2898 | if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12) | |
2899 | priv->bXtalCalibration = true; | |
c8d86be3 | 2900 | |
1994130e LF |
2901 | /* Thermal meter reference indication. */ |
2902 | priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8); | |
2903 | if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13) | |
2904 | priv->bTxPowerTrack = true; | |
c8d86be3 | 2905 | |
742821ce | 2906 | eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word); |
c8d86be3 GKH |
2907 | priv->cck_txpwr_base = word & 0xf; |
2908 | priv->ofdm_txpwr_base = (word>>4) & 0xf; | |
c8d86be3 | 2909 | |
742821ce | 2910 | eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version); |
c8d86be3 | 2911 | DMESG("EEPROM version %x",version); |
d44eb889 | 2912 | priv->rcr_csense = 3; |
c8d86be3 | 2913 | |
742821ce LF |
2914 | eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val); |
2915 | priv->cs_treshold = (eeprom_val & 0xff00) >> 8; | |
c8d86be3 | 2916 | |
742821ce | 2917 | eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val); |
c8d86be3 GKH |
2918 | priv->rf_sleep = rtl8225z4_rf_sleep; |
2919 | priv->rf_wakeup = rtl8225z4_rf_wakeup; | |
c8d86be3 GKH |
2920 | DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!"); |
2921 | ||
2922 | priv->rf_close = rtl8225z2_rf_close; | |
2923 | priv->rf_init = rtl8225z2_rf_init; | |
2924 | priv->rf_set_chan = rtl8225z2_rf_set_chan; | |
2925 | priv->rf_set_sens = NULL; | |
c8d86be3 | 2926 | |
c8d86be3 GKH |
2927 | if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount)) |
2928 | return -ENOMEM; | |
2929 | ||
2930 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, | |
2931 | TX_MANAGEPRIORITY_RING_ADDR)) | |
2932 | return -ENOMEM; | |
2933 | ||
2934 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, | |
2935 | TX_BKPRIORITY_RING_ADDR)) | |
2936 | return -ENOMEM; | |
2937 | ||
2938 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, | |
2939 | TX_BEPRIORITY_RING_ADDR)) | |
2940 | return -ENOMEM; | |
2941 | ||
2942 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, | |
2943 | TX_VIPRIORITY_RING_ADDR)) | |
2944 | return -ENOMEM; | |
2945 | ||
2946 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, | |
2947 | TX_VOPRIORITY_RING_ADDR)) | |
2948 | return -ENOMEM; | |
2949 | ||
2950 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, | |
2951 | TX_HIGHPRIORITY_RING_ADDR)) | |
2952 | return -ENOMEM; | |
2953 | ||
2954 | if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount, | |
2955 | TX_BEACON_RING_ADDR)) | |
2956 | return -ENOMEM; | |
2957 | ||
c8d86be3 | 2958 | if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){ |
c8d86be3 GKH |
2959 | DMESGE("Error allocating IRQ %d",dev->irq); |
2960 | return -1; | |
2961 | }else{ | |
2962 | priv->irq=dev->irq; | |
2963 | DMESG("IRQ %d",dev->irq); | |
2964 | } | |
2965 | ||
c8d86be3 | 2966 | return 0; |
c8d86be3 GKH |
2967 | } |
2968 | ||
c8d86be3 GKH |
2969 | void rtl8180_no_hw_wep(struct net_device *dev) |
2970 | { | |
c8d86be3 GKH |
2971 | } |
2972 | ||
c8d86be3 GKH |
2973 | void rtl8180_set_hw_wep(struct net_device *dev) |
2974 | { | |
2975 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2976 | u8 pgreg; | |
2977 | u8 security; | |
2978 | u32 key0_word4; | |
2979 | ||
2980 | pgreg=read_nic_byte(dev, PGSELECT); | |
2981 | write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT)); | |
2982 | ||
2983 | key0_word4 = read_nic_dword(dev, KEY0+4+4+4); | |
2984 | key0_word4 &= ~ 0xff; | |
2985 | key0_word4 |= priv->key0[3]& 0xff; | |
2986 | write_nic_dword(dev,KEY0,(priv->key0[0])); | |
2987 | write_nic_dword(dev,KEY0+4,(priv->key0[1])); | |
2988 | write_nic_dword(dev,KEY0+4+4,(priv->key0[2])); | |
2989 | write_nic_dword(dev,KEY0+4+4+4,(key0_word4)); | |
2990 | ||
c8d86be3 GKH |
2991 | security = read_nic_byte(dev,SECURITY); |
2992 | security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT); | |
2993 | security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT); | |
2994 | security &= ~ SECURITY_ENCRYP_MASK; | |
2995 | security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT); | |
2996 | ||
2997 | write_nic_byte(dev, SECURITY, security); | |
2998 | ||
2999 | DMESG("key %x %x %x %x",read_nic_dword(dev,KEY0+4+4+4), | |
3000 | read_nic_dword(dev,KEY0+4+4),read_nic_dword(dev,KEY0+4), | |
3001 | read_nic_dword(dev,KEY0)); | |
c8d86be3 GKH |
3002 | } |
3003 | ||
3004 | ||
3005 | void rtl8185_rf_pins_enable(struct net_device *dev) | |
3006 | { | |
3007 | // u16 tmp; | |
3008 | // tmp = read_nic_word(dev, RFPinsEnable); | |
3009 | write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp); | |
c8d86be3 GKH |
3010 | } |
3011 | ||
c8d86be3 GKH |
3012 | void rtl8185_set_anaparam2(struct net_device *dev, u32 a) |
3013 | { | |
3014 | u8 conf3; | |
3015 | ||
3016 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3017 | ||
3018 | conf3 = read_nic_byte(dev, CONFIG3); | |
3019 | write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT)); | |
3020 | write_nic_dword(dev, ANAPARAM2, a); | |
3021 | ||
3022 | conf3 = read_nic_byte(dev, CONFIG3); | |
3023 | write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT)); | |
3024 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
3025 | } |
3026 | ||
c8d86be3 GKH |
3027 | void rtl8180_set_anaparam(struct net_device *dev, u32 a) |
3028 | { | |
3029 | u8 conf3; | |
3030 | ||
3031 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3032 | ||
3033 | conf3 = read_nic_byte(dev, CONFIG3); | |
3034 | write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT)); | |
3035 | write_nic_dword(dev, ANAPARAM, a); | |
3036 | ||
3037 | conf3 = read_nic_byte(dev, CONFIG3); | |
3038 | write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT)); | |
3039 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
3040 | } | |
3041 | ||
c8d86be3 GKH |
3042 | void rtl8185_tx_antenna(struct net_device *dev, u8 ant) |
3043 | { | |
3044 | write_nic_byte(dev, TX_ANTENNA, ant); | |
3045 | force_pci_posting(dev); | |
3046 | mdelay(1); | |
3047 | } | |
3048 | ||
c8d86be3 GKH |
3049 | void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data) |
3050 | { | |
c8d86be3 | 3051 | u32 phyw; |
c8d86be3 GKH |
3052 | |
3053 | adr |= 0x80; | |
3054 | ||
3055 | phyw= ((data<<8) | adr); | |
c8d86be3 | 3056 | |
c8d86be3 GKH |
3057 | // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register. |
3058 | write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24)); | |
3059 | write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16)); | |
3060 | write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8)); | |
3061 | write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff) )); | |
5521a513 | 3062 | |
c8d86be3 GKH |
3063 | /* this is ok to fail when we write AGC table. check for AGC table might be |
3064 | * done by masking with 0x7f instead of 0xff | |
3065 | */ | |
3066 | //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr); | |
3067 | } | |
3068 | ||
c8d86be3 GKH |
3069 | inline void write_phy_ofdm (struct net_device *dev, u8 adr, u32 data) |
3070 | { | |
3071 | data = data & 0xff; | |
3072 | rtl8185_write_phy(dev, adr, data); | |
3073 | } | |
3074 | ||
c8d86be3 GKH |
3075 | void write_phy_cck (struct net_device *dev, u8 adr, u32 data) |
3076 | { | |
3077 | data = data & 0xff; | |
3078 | rtl8185_write_phy(dev, adr, data | 0x10000); | |
3079 | } | |
3080 | ||
c8d86be3 GKH |
3081 | void rtl8185_set_rate(struct net_device *dev) |
3082 | { | |
3083 | int i; | |
3084 | u16 word; | |
3085 | int basic_rate,min_rr_rate,max_rr_rate; | |
3086 | ||
c8d86be3 GKH |
3087 | basic_rate = ieeerate2rtlrate(240); |
3088 | min_rr_rate = ieeerate2rtlrate(60); | |
3089 | max_rr_rate = ieeerate2rtlrate(240); | |
3090 | ||
c8d86be3 GKH |
3091 | write_nic_byte(dev, RESP_RATE, |
3092 | max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT); | |
3093 | ||
3094 | word = read_nic_word(dev, BRSR); | |
3095 | word &= ~BRSR_MBR_8185; | |
3096 | ||
c8d86be3 GKH |
3097 | for(i=0;i<=basic_rate;i++) |
3098 | word |= (1<<i); | |
3099 | ||
3100 | write_nic_word(dev, BRSR, word); | |
c8d86be3 GKH |
3101 | } |
3102 | ||
c8d86be3 GKH |
3103 | void rtl8180_adapter_start(struct net_device *dev) |
3104 | { | |
3105 | struct r8180_priv *priv = ieee80211_priv(dev); | |
c8d86be3 GKH |
3106 | |
3107 | rtl8180_rtx_disable(dev); | |
3108 | rtl8180_reset(dev); | |
3109 | ||
c8d86be3 GKH |
3110 | /* enable beacon timeout, beacon TX ok and err |
3111 | * LP tx ok and err, HP TX ok and err, NP TX ok and err, | |
3112 | * RX ok and ERR, and GP timer */ | |
3113 | priv->irq_mask = 0x6fcf; | |
3114 | ||
3115 | priv->dma_poll_mask = 0; | |
3116 | ||
3117 | rtl8180_beacon_tx_disable(dev); | |
3118 | ||
c8d86be3 GKH |
3119 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
3120 | write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]); | |
3121 | write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff ); | |
3122 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
3123 | ||
3124 | rtl8180_update_msr(dev); | |
3125 | ||
c8d86be3 GKH |
3126 | /* These might be unnecessary since we do in rx_enable / tx_enable */ |
3127 | fix_rx_fifo(dev); | |
3128 | fix_tx_fifo(dev); | |
c8d86be3 GKH |
3129 | |
3130 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3131 | ||
3132 | /* | |
3133 | The following is very strange. seems to be that 1 means test mode, | |
3134 | but we need to acknolwledges the nic when a packet is ready | |
bbc9a991 | 3135 | although we set it to 0 |
c8d86be3 GKH |
3136 | */ |
3137 | ||
3138 | write_nic_byte(dev, | |
3139 | CONFIG2, read_nic_byte(dev,CONFIG2) &~\ | |
3140 | (1<<CONFIG2_DMA_POLLING_MODE_SHIFT)); | |
3141 | //^the nic isn't in test mode | |
d44eb889 | 3142 | write_nic_byte(dev, |
c8d86be3 GKH |
3143 | CONFIG2, read_nic_byte(dev,CONFIG2)|(1<<4)); |
3144 | ||
3145 | rtl8180_set_mode(dev,EPROM_CMD_NORMAL); | |
3146 | ||
3147 | write_nic_dword(dev,INT_TIMEOUT,0); | |
c8d86be3 | 3148 | |
d44eb889 | 3149 | write_nic_byte(dev, WPA_CONFIG, 0); |
c8d86be3 GKH |
3150 | |
3151 | rtl8180_no_hw_wep(dev); | |
3152 | ||
d44eb889 LF |
3153 | rtl8185_set_rate(dev); |
3154 | write_nic_byte(dev, RATE_FALLBACK, 0x81); | |
c8d86be3 | 3155 | |
d44eb889 | 3156 | write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6)); |
c8d86be3 | 3157 | |
d44eb889 LF |
3158 | /*FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */ |
3159 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3160 | write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | |
3161 | | (1 << CONFIG3_CLKRUN_SHIFT)); | |
3162 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
3163 | |
3164 | priv->rf_init(dev); | |
3165 | ||
3166 | if(priv->rf_set_sens != NULL) | |
3167 | priv->rf_set_sens(dev,priv->sens); | |
3168 | rtl8180_irq_enable(dev); | |
3169 | ||
3170 | netif_start_queue(dev); | |
c8d86be3 GKH |
3171 | } |
3172 | ||
c8d86be3 GKH |
3173 | /* this configures registers for beacon tx and enables it via |
3174 | * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might | |
3175 | * be used to stop beacon transmission | |
3176 | */ | |
3177 | void rtl8180_start_tx_beacon(struct net_device *dev) | |
3178 | { | |
c8d86be3 | 3179 | u16 word; |
c8d86be3 GKH |
3180 | |
3181 | DMESG("Enabling beacon TX"); | |
c8d86be3 GKH |
3182 | rtl8180_prepare_beacon(dev); |
3183 | rtl8180_irq_disable(dev); | |
3184 | rtl8180_beacon_tx_enable(dev); | |
c8d86be3 | 3185 | |
c8d86be3 GKH |
3186 | word = read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd; |
3187 | write_nic_word(dev, AtimWnd,word);// word |= | |
c8d86be3 GKH |
3188 | |
3189 | word = read_nic_word(dev, BintrItv); | |
3190 | word &= ~BintrItv_BintrItv; | |
3191 | word |= 1000;/*priv->ieee80211->current_network.beacon_interval * | |
3192 | ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1); | |
3193 | // FIXME: check if correct ^^ worked with 0x3e8; | |
3194 | */ | |
3195 | write_nic_word(dev, BintrItv, word); | |
3196 | ||
c8d86be3 GKH |
3197 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
3198 | ||
c8d86be3 | 3199 | rtl8185b_irq_enable(dev); |
c8d86be3 GKH |
3200 | } |
3201 | ||
c8d86be3 GKH |
3202 | static struct net_device_stats *rtl8180_stats(struct net_device *dev) |
3203 | { | |
3204 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3205 | ||
3206 | return &priv->ieee80211->stats; | |
3207 | } | |
3208 | // | |
3209 | // Change current and default preamble mode. | |
c8d86be3 GKH |
3210 | // |
3211 | bool | |
3212 | MgntActSet_802_11_PowerSaveMode( | |
3213 | struct r8180_priv *priv, | |
3214 | RT_PS_MODE rtPsMode | |
3215 | ) | |
3216 | { | |
c8d86be3 GKH |
3217 | // Currently, we do not change power save mode on IBSS mode. |
3218 | if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) | |
c8d86be3 | 3219 | return false; |
c8d86be3 | 3220 | |
c8d86be3 | 3221 | priv->ieee80211->ps = rtPsMode; |
5521a513 | 3222 | |
c8d86be3 GKH |
3223 | return true; |
3224 | } | |
3225 | ||
fd882783 | 3226 | void LeisurePSEnter(struct r8180_priv *priv) |
c8d86be3 | 3227 | { |
fd882783 | 3228 | if (priv->bLeisurePs) { |
c8d86be3 | 3229 | if (priv->ieee80211->ps == IEEE80211_PS_DISABLED) |
c8d86be3 | 3230 | MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE |
c8d86be3 GKH |
3231 | } |
3232 | } | |
3233 | ||
fd882783 | 3234 | void LeisurePSLeave(struct r8180_priv *priv) |
c8d86be3 | 3235 | { |
fd882783 | 3236 | if (priv->bLeisurePs) { |
c8d86be3 | 3237 | if (priv->ieee80211->ps != IEEE80211_PS_DISABLED) |
c8d86be3 | 3238 | MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED); |
c8d86be3 GKH |
3239 | } |
3240 | } | |
0370453f | 3241 | |
c8d86be3 GKH |
3242 | void rtl8180_hw_wakeup_wq (struct work_struct *work) |
3243 | { | |
bf6aede7 | 3244 | struct delayed_work *dwork = to_delayed_work(work); |
c8d86be3 GKH |
3245 | struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq); |
3246 | struct net_device *dev = ieee->dev; | |
c8d86be3 | 3247 | |
c8d86be3 | 3248 | rtl8180_hw_wakeup(dev); |
c8d86be3 GKH |
3249 | } |
3250 | ||
c8d86be3 GKH |
3251 | void rtl8180_hw_sleep_wq (struct work_struct *work) |
3252 | { | |
bf6aede7 | 3253 | struct delayed_work *dwork = to_delayed_work(work); |
c8d86be3 GKH |
3254 | struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq); |
3255 | struct net_device *dev = ieee->dev; | |
c8d86be3 GKH |
3256 | |
3257 | rtl8180_hw_sleep_down(dev); | |
3258 | } | |
3259 | ||
c8d86be3 GKH |
3260 | static void MgntLinkKeepAlive(struct r8180_priv *priv ) |
3261 | { | |
3262 | if (priv->keepAliveLevel == 0) | |
3263 | return; | |
3264 | ||
3265 | if(priv->ieee80211->state == IEEE80211_LINKED) | |
3266 | { | |
3267 | // | |
3268 | // Keep-Alive. | |
3269 | // | |
c8d86be3 GKH |
3270 | |
3271 | if ( (priv->keepAliveLevel== 2) || | |
3272 | (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast && | |
3273 | priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast ) | |
3274 | ) | |
3275 | { | |
3276 | priv->link_detect.IdleCount++; | |
3277 | ||
3278 | // | |
3279 | // Send a Keep-Alive packet packet to AP if we had been idle for a while. | |
3280 | // | |
3281 | if(priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1) ) | |
3282 | { | |
3283 | priv->link_detect.IdleCount = 0; | |
3284 | ieee80211_sta_ps_send_null_frame(priv->ieee80211, false); | |
3285 | } | |
3286 | } | |
3287 | else | |
3288 | { | |
3289 | priv->link_detect.IdleCount = 0; | |
3290 | } | |
3291 | priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast; | |
3292 | priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast; | |
3293 | } | |
3294 | } | |
c8d86be3 GKH |
3295 | |
3296 | static u8 read_acadapter_file(char *filename); | |
fd882783 | 3297 | |
c8d86be3 GKH |
3298 | void rtl8180_watch_dog(struct net_device *dev) |
3299 | { | |
3300 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3301 | bool bEnterPS = false; | |
3302 | bool bBusyTraffic = false; | |
3303 | u32 TotalRxNum = 0; | |
3304 | u16 SlotIndex = 0; | |
3305 | u16 i = 0; | |
c8d86be3 GKH |
3306 | if(priv->ieee80211->actscanning == false){ |
3307 | if((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)){ | |
3308 | IPSEnter(dev); | |
3309 | } | |
3310 | } | |
c8d86be3 GKH |
3311 | //YJ,add,080828,for link state check |
3312 | if((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)){ | |
3313 | SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum; | |
3314 | priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod; | |
3315 | for( i=0; i<priv->link_detect.SlotNum; i++ ) | |
3316 | TotalRxNum+= priv->link_detect.RxFrameNum[i]; | |
fd882783 | 3317 | |
c8d86be3 GKH |
3318 | if(TotalRxNum == 0){ |
3319 | priv->ieee80211->state = IEEE80211_ASSOCIATING; | |
3320 | queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq); | |
3321 | } | |
3322 | } | |
3323 | ||
3324 | //YJ,add,080828,for KeepAlive | |
3325 | MgntLinkKeepAlive(priv); | |
3326 | ||
3327 | //YJ,add,080828,for LPS | |
fd882783 | 3328 | if (priv->PowerProfile == POWER_PROFILE_BATTERY) |
c8d86be3 | 3329 | priv->bLeisurePs = true; |
fd882783 | 3330 | else if (priv->PowerProfile == POWER_PROFILE_AC) { |
c8d86be3 GKH |
3331 | LeisurePSLeave(priv); |
3332 | priv->bLeisurePs= false; | |
3333 | } | |
c8d86be3 | 3334 | |
c8d86be3 GKH |
3335 | if(priv->ieee80211->state == IEEE80211_LINKED){ |
3336 | priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod; | |
c8d86be3 GKH |
3337 | if( priv->link_detect.NumRxOkInPeriod> 666 || |
3338 | priv->link_detect.NumTxOkInPeriod> 666 ) { | |
3339 | bBusyTraffic = true; | |
3340 | } | |
3341 | if(((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8) | |
3342 | || (priv->link_detect.NumRxOkInPeriod > 2)) { | |
3343 | bEnterPS= false; | |
fd882783 | 3344 | } else |
c8d86be3 | 3345 | bEnterPS= true; |
c8d86be3 | 3346 | |
fd882783 | 3347 | if (bEnterPS) |
c8d86be3 | 3348 | LeisurePSEnter(priv); |
fd882783 | 3349 | else |
c8d86be3 | 3350 | LeisurePSLeave(priv); |
fd882783 | 3351 | } else |
c8d86be3 | 3352 | LeisurePSLeave(priv); |
c8d86be3 GKH |
3353 | priv->link_detect.bBusyTraffic = bBusyTraffic; |
3354 | priv->link_detect.NumRxOkInPeriod = 0; | |
3355 | priv->link_detect.NumTxOkInPeriod = 0; | |
3356 | priv->ieee80211->NumRxDataInPeriod = 0; | |
3357 | priv->ieee80211->NumRxBcnInPeriod = 0; | |
c8d86be3 | 3358 | } |
fd882783 | 3359 | |
c8d86be3 GKH |
3360 | int _rtl8180_up(struct net_device *dev) |
3361 | { | |
3362 | struct r8180_priv *priv = ieee80211_priv(dev); | |
c8d86be3 GKH |
3363 | |
3364 | priv->up=1; | |
3365 | ||
3366 | DMESG("Bringing up iface"); | |
c8d86be3 GKH |
3367 | rtl8185b_adapter_start(dev); |
3368 | rtl8185b_rx_enable(dev); | |
3369 | rtl8185b_tx_enable(dev); | |
c8d86be3 GKH |
3370 | if(priv->bInactivePs){ |
3371 | if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) | |
3372 | IPSLeave(dev); | |
3373 | } | |
c8d86be3 | 3374 | timer_rate_adaptive((unsigned long)dev); |
c8d86be3 | 3375 | watch_dog_adaptive((unsigned long)dev); |
c8d86be3 GKH |
3376 | if(priv->bSwAntennaDiverity) |
3377 | SwAntennaDiversityTimerCallback(dev); | |
c8d86be3 | 3378 | ieee80211_softmac_start_protocol(priv->ieee80211); |
c8d86be3 GKH |
3379 | return 0; |
3380 | } | |
3381 | ||
c8d86be3 GKH |
3382 | int rtl8180_open(struct net_device *dev) |
3383 | { | |
3384 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3385 | int ret; | |
3386 | ||
3387 | down(&priv->wx_sem); | |
3388 | ret = rtl8180_up(dev); | |
3389 | up(&priv->wx_sem); | |
3390 | return ret; | |
c8d86be3 GKH |
3391 | } |
3392 | ||
c8d86be3 GKH |
3393 | int rtl8180_up(struct net_device *dev) |
3394 | { | |
3395 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3396 | ||
3397 | if (priv->up == 1) return -1; | |
3398 | ||
3399 | return _rtl8180_up(dev); | |
3400 | } | |
3401 | ||
c8d86be3 GKH |
3402 | int rtl8180_close(struct net_device *dev) |
3403 | { | |
3404 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3405 | int ret; | |
3406 | ||
3407 | down(&priv->wx_sem); | |
3408 | ret = rtl8180_down(dev); | |
3409 | up(&priv->wx_sem); | |
3410 | ||
3411 | return ret; | |
c8d86be3 GKH |
3412 | } |
3413 | ||
3414 | int rtl8180_down(struct net_device *dev) | |
3415 | { | |
3416 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3417 | ||
fd882783 BZ |
3418 | if (priv->up == 0) |
3419 | return -1; | |
c8d86be3 GKH |
3420 | |
3421 | priv->up=0; | |
3422 | ||
3423 | ieee80211_softmac_stop_protocol(priv->ieee80211); | |
3424 | /* FIXME */ | |
3425 | if (!netif_queue_stopped(dev)) | |
3426 | netif_stop_queue(dev); | |
3427 | rtl8180_rtx_disable(dev); | |
3428 | rtl8180_irq_disable(dev); | |
3429 | del_timer_sync(&priv->watch_dog_timer); | |
fd882783 BZ |
3430 | del_timer_sync(&priv->rateadapter_timer); |
3431 | cancel_delayed_work(&priv->ieee80211->rate_adapter_wq); | |
c8d86be3 GKH |
3432 | cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); |
3433 | cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); | |
3434 | cancel_delayed_work(&priv->ieee80211->hw_dig_wq); | |
3435 | cancel_delayed_work(&priv->ieee80211->tx_pw_wq); | |
3436 | del_timer_sync(&priv->SwAntennaDiversityTimer); | |
3437 | SetZebraRFPowerState8185(dev,eRfOff); | |
c8d86be3 GKH |
3438 | memset(&(priv->ieee80211->current_network),0,sizeof(struct ieee80211_network)); |
3439 | priv->ieee80211->state = IEEE80211_NOLINK; | |
3440 | return 0; | |
3441 | } | |
3442 | ||
c8d86be3 GKH |
3443 | void rtl8180_restart_wq(struct work_struct *work) |
3444 | { | |
3445 | struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq); | |
3446 | struct net_device *dev = priv->dev; | |
0370453f | 3447 | |
c8d86be3 GKH |
3448 | down(&priv->wx_sem); |
3449 | ||
3450 | rtl8180_commit(dev); | |
3451 | ||
3452 | up(&priv->wx_sem); | |
3453 | } | |
3454 | ||
3455 | void rtl8180_restart(struct net_device *dev) | |
3456 | { | |
3457 | struct r8180_priv *priv = ieee80211_priv(dev); | |
fd882783 | 3458 | |
c8d86be3 | 3459 | schedule_work(&priv->reset_wq); |
c8d86be3 GKH |
3460 | } |
3461 | ||
c8d86be3 GKH |
3462 | void rtl8180_commit(struct net_device *dev) |
3463 | { | |
3464 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3465 | ||
fd882783 BZ |
3466 | if (priv->up == 0) |
3467 | return ; | |
3468 | ||
c8d86be3 | 3469 | del_timer_sync(&priv->watch_dog_timer); |
fd882783 BZ |
3470 | del_timer_sync(&priv->rateadapter_timer); |
3471 | cancel_delayed_work(&priv->ieee80211->rate_adapter_wq); | |
c8d86be3 GKH |
3472 | cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); |
3473 | cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); | |
3474 | cancel_delayed_work(&priv->ieee80211->hw_dig_wq); | |
3475 | cancel_delayed_work(&priv->ieee80211->tx_pw_wq); | |
3476 | del_timer_sync(&priv->SwAntennaDiversityTimer); | |
3477 | ieee80211_softmac_stop_protocol(priv->ieee80211); | |
3478 | rtl8180_irq_disable(dev); | |
3479 | rtl8180_rtx_disable(dev); | |
3480 | _rtl8180_up(dev); | |
3481 | } | |
3482 | ||
c8d86be3 GKH |
3483 | static void r8180_set_multicast(struct net_device *dev) |
3484 | { | |
3485 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3486 | short promisc; | |
3487 | ||
c8d86be3 GKH |
3488 | promisc = (dev->flags & IFF_PROMISC) ? 1:0; |
3489 | ||
3490 | if (promisc != priv->promisc) | |
3491 | rtl8180_restart(dev); | |
3492 | ||
3493 | priv->promisc = promisc; | |
c8d86be3 GKH |
3494 | } |
3495 | ||
c8d86be3 GKH |
3496 | int r8180_set_mac_adr(struct net_device *dev, void *mac) |
3497 | { | |
3498 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3499 | struct sockaddr *addr = mac; | |
3500 | ||
3501 | down(&priv->wx_sem); | |
3502 | ||
3503 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
3504 | ||
3505 | if(priv->ieee80211->iw_mode == IW_MODE_MASTER) | |
3506 | memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN); | |
3507 | ||
3508 | if (priv->up) { | |
3509 | rtl8180_down(dev); | |
3510 | rtl8180_up(dev); | |
3511 | } | |
3512 | ||
3513 | up(&priv->wx_sem); | |
3514 | ||
3515 | return 0; | |
3516 | } | |
3517 | ||
3518 | /* based on ipw2200 driver */ | |
3519 | int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
3520 | { | |
3521 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 GKH |
3522 | struct iwreq *wrq = (struct iwreq *) rq; |
3523 | int ret=-1; | |
fd882783 | 3524 | |
c8d86be3 | 3525 | switch (cmd) { |
fd882783 | 3526 | case RTL_IOCTL_WPA_SUPPLICANT: |
c8d86be3 GKH |
3527 | ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data); |
3528 | return ret; | |
fd882783 | 3529 | default: |
c8d86be3 GKH |
3530 | return -EOPNOTSUPP; |
3531 | } | |
3532 | ||
3533 | return -EOPNOTSUPP; | |
3534 | } | |
3535 | ||
727ae303 AB |
3536 | static const struct net_device_ops rtl8180_netdev_ops = { |
3537 | .ndo_open = rtl8180_open, | |
3538 | .ndo_stop = rtl8180_close, | |
3539 | .ndo_get_stats = rtl8180_stats, | |
3540 | .ndo_tx_timeout = rtl8180_restart, | |
3541 | .ndo_do_ioctl = rtl8180_ioctl, | |
3542 | .ndo_set_multicast_list = r8180_set_multicast, | |
3543 | .ndo_set_mac_address = r8180_set_mac_adr, | |
3544 | .ndo_validate_addr = eth_validate_addr, | |
3545 | .ndo_change_mtu = eth_change_mtu, | |
df574b8e | 3546 | .ndo_start_xmit = ieee80211_rtl_xmit, |
727ae303 | 3547 | }; |
c8d86be3 GKH |
3548 | |
3549 | static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, | |
3550 | const struct pci_device_id *id) | |
3551 | { | |
3552 | unsigned long ioaddr = 0; | |
3553 | struct net_device *dev = NULL; | |
3554 | struct r8180_priv *priv= NULL; | |
c8d86be3 GKH |
3555 | u8 unit = 0; |
3556 | ||
c8d86be3 | 3557 | unsigned long pmem_start, pmem_len, pmem_flags; |
c8d86be3 GKH |
3558 | |
3559 | DMESG("Configuring chip resources"); | |
3560 | ||
3561 | if( pci_enable_device (pdev) ){ | |
3562 | DMESG("Failed to enable PCI device"); | |
3563 | return -EIO; | |
3564 | } | |
3565 | ||
3566 | pci_set_master(pdev); | |
c8d86be3 GKH |
3567 | pci_set_dma_mask(pdev, 0xffffff00ULL); |
3568 | pci_set_consistent_dma_mask(pdev,0xffffff00ULL); | |
3569 | dev = alloc_ieee80211(sizeof(struct r8180_priv)); | |
3570 | if (!dev) | |
3571 | return -ENOMEM; | |
3572 | priv = ieee80211_priv(dev); | |
3573 | priv->ieee80211 = netdev_priv(dev); | |
3574 | ||
c8d86be3 GKH |
3575 | pci_set_drvdata(pdev, dev); |
3576 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3577 | ||
3578 | priv = ieee80211_priv(dev); | |
fd882783 | 3579 | priv->pdev = pdev; |
c8d86be3 GKH |
3580 | |
3581 | pmem_start = pci_resource_start(pdev, 1); | |
3582 | pmem_len = pci_resource_len(pdev, 1); | |
3583 | pmem_flags = pci_resource_flags (pdev, 1); | |
3584 | ||
3585 | if (!(pmem_flags & IORESOURCE_MEM)) { | |
3586 | DMESG("region #1 not a MMIO resource, aborting"); | |
3587 | goto fail; | |
3588 | } | |
3589 | ||
c8d86be3 GKH |
3590 | if( ! request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) { |
3591 | DMESG("request_mem_region failed!"); | |
3592 | goto fail; | |
3593 | } | |
3594 | ||
c8d86be3 GKH |
3595 | ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len); |
3596 | if( ioaddr == (unsigned long)NULL ){ | |
3597 | DMESG("ioremap failed!"); | |
c8d86be3 GKH |
3598 | goto fail1; |
3599 | } | |
3600 | ||
3601 | dev->mem_start = ioaddr; // shared mem start | |
3602 | dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end | |
3603 | ||
c8d86be3 GKH |
3604 | pci_read_config_byte(pdev, 0x05, &unit); |
3605 | pci_write_config_byte(pdev, 0x05, unit & (~0x04)); | |
c8d86be3 GKH |
3606 | |
3607 | dev->irq = pdev->irq; | |
3608 | priv->irq = 0; | |
3609 | ||
727ae303 | 3610 | dev->netdev_ops = &rtl8180_netdev_ops; |
c8d86be3 | 3611 | dev->wireless_handlers = &r8180_wx_handlers_def; |
c8d86be3 | 3612 | |
c8d86be3 | 3613 | dev->type=ARPHRD_ETHER; |
1994130e | 3614 | dev->watchdog_timeo = HZ*3; |
c8d86be3 GKH |
3615 | |
3616 | if (dev_alloc_name(dev, ifname) < 0){ | |
3617 | DMESG("Oops: devname already taken! Trying wlan%%d...\n"); | |
3618 | ifname = "wlan%d"; | |
c8d86be3 GKH |
3619 | dev_alloc_name(dev, ifname); |
3620 | } | |
3621 | ||
c8d86be3 GKH |
3622 | if(rtl8180_init(dev)!=0){ |
3623 | DMESG("Initialization failed"); | |
3624 | goto fail1; | |
3625 | } | |
3626 | ||
3627 | netif_carrier_off(dev); | |
3628 | ||
3629 | register_netdev(dev); | |
3630 | ||
3631 | rtl8180_proc_init_one(dev); | |
3632 | ||
3633 | DMESG("Driver probe completed\n"); | |
3634 | return 0; | |
c8d86be3 | 3635 | fail1: |
c8d86be3 GKH |
3636 | if( dev->mem_start != (unsigned long)NULL ){ |
3637 | iounmap( (void *)dev->mem_start ); | |
3638 | release_mem_region( pci_resource_start(pdev, 1), | |
3639 | pci_resource_len(pdev, 1) ); | |
3640 | } | |
c8d86be3 GKH |
3641 | fail: |
3642 | if(dev){ | |
c8d86be3 GKH |
3643 | if (priv->irq) { |
3644 | free_irq(dev->irq, dev); | |
3645 | dev->irq=0; | |
3646 | } | |
3647 | free_ieee80211(dev); | |
3648 | } | |
3649 | ||
3650 | pci_disable_device(pdev); | |
3651 | ||
3652 | DMESG("wlan driver load failed\n"); | |
3653 | pci_set_drvdata(pdev, NULL); | |
3654 | return -ENODEV; | |
c8d86be3 GKH |
3655 | } |
3656 | ||
c8d86be3 GKH |
3657 | static void __devexit rtl8180_pci_remove(struct pci_dev *pdev) |
3658 | { | |
3659 | struct r8180_priv *priv; | |
3660 | struct net_device *dev = pci_get_drvdata(pdev); | |
c8d86be3 | 3661 | |
fd882783 | 3662 | if (dev) { |
c8d86be3 GKH |
3663 | unregister_netdev(dev); |
3664 | ||
fd882783 | 3665 | priv = ieee80211_priv(dev); |
c8d86be3 GKH |
3666 | |
3667 | rtl8180_proc_remove_one(dev); | |
3668 | rtl8180_down(dev); | |
3669 | priv->rf_close(dev); | |
3670 | rtl8180_reset(dev); | |
c8d86be3 | 3671 | mdelay(10); |
c8d86be3 GKH |
3672 | |
3673 | if(priv->irq){ | |
c8d86be3 GKH |
3674 | DMESG("Freeing irq %d",dev->irq); |
3675 | free_irq(dev->irq, dev); | |
3676 | priv->irq=0; | |
c8d86be3 GKH |
3677 | } |
3678 | ||
3679 | free_rx_desc_ring(dev); | |
3680 | free_tx_desc_rings(dev); | |
c8d86be3 | 3681 | |
c8d86be3 GKH |
3682 | if( dev->mem_start != (unsigned long)NULL ){ |
3683 | iounmap( (void *)dev->mem_start ); | |
3684 | release_mem_region( pci_resource_start(pdev, 1), | |
3685 | pci_resource_len(pdev, 1) ); | |
3686 | } | |
c8d86be3 GKH |
3687 | |
3688 | free_ieee80211(dev); | |
3689 | } | |
3690 | pci_disable_device(pdev); | |
3691 | ||
3692 | DMESG("wlan driver removed\n"); | |
3693 | } | |
3694 | ||
c8d86be3 GKH |
3695 | /* fun with the built-in ieee80211 stack... */ |
3696 | extern int ieee80211_crypto_init(void); | |
3697 | extern void ieee80211_crypto_deinit(void); | |
3698 | extern int ieee80211_crypto_tkip_init(void); | |
3699 | extern void ieee80211_crypto_tkip_exit(void); | |
3700 | extern int ieee80211_crypto_ccmp_init(void); | |
3701 | extern void ieee80211_crypto_ccmp_exit(void); | |
3702 | extern int ieee80211_crypto_wep_init(void); | |
3703 | extern void ieee80211_crypto_wep_exit(void); | |
3704 | ||
3705 | static int __init rtl8180_pci_module_init(void) | |
3706 | { | |
3707 | int ret; | |
3708 | ||
3709 | ret = ieee80211_crypto_init(); | |
3710 | if (ret) { | |
3711 | printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret); | |
3712 | return ret; | |
3713 | } | |
3714 | ret = ieee80211_crypto_tkip_init(); | |
3715 | if (ret) { | |
3716 | printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret); | |
3717 | return ret; | |
3718 | } | |
3719 | ret = ieee80211_crypto_ccmp_init(); | |
3720 | if (ret) { | |
3721 | printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret); | |
3722 | return ret; | |
3723 | } | |
3724 | ret = ieee80211_crypto_wep_init(); | |
3725 | if (ret) { | |
3726 | printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret); | |
3727 | return ret; | |
3728 | } | |
3729 | ||
bc568942 | 3730 | printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n"); |
c8d86be3 GKH |
3731 | printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n"); |
3732 | DMESG("Initializing module"); | |
3733 | DMESG("Wireless extensions version %d", WIRELESS_EXT); | |
3734 | rtl8180_proc_module_init(); | |
3735 | ||
fd882783 | 3736 | if (pci_register_driver(&rtl8180_pci_driver)) { |
c8d86be3 | 3737 | DMESG("No device found"); |
c8d86be3 GKH |
3738 | return -ENODEV; |
3739 | } | |
3740 | return 0; | |
3741 | } | |
3742 | ||
c8d86be3 GKH |
3743 | static void __exit rtl8180_pci_module_exit(void) |
3744 | { | |
3745 | pci_unregister_driver (&rtl8180_pci_driver); | |
3746 | rtl8180_proc_module_remove(); | |
c8d86be3 GKH |
3747 | ieee80211_crypto_tkip_exit(); |
3748 | ieee80211_crypto_ccmp_exit(); | |
3749 | ieee80211_crypto_wep_exit(); | |
096c55d1 | 3750 | ieee80211_crypto_deinit(); |
c8d86be3 GKH |
3751 | DMESG("Exiting"); |
3752 | } | |
3753 | ||
c8d86be3 GKH |
3754 | void rtl8180_try_wake_queue(struct net_device *dev, int pri) |
3755 | { | |
3756 | unsigned long flags; | |
3757 | short enough_desc; | |
3758 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
3759 | ||
3760 | spin_lock_irqsave(&priv->tx_lock,flags); | |
3761 | enough_desc = check_nic_enought_desc(dev,pri); | |
3762 | spin_unlock_irqrestore(&priv->tx_lock,flags); | |
3763 | ||
3764 | if(enough_desc) | |
df574b8e | 3765 | ieee80211_rtl_wake_queue(priv->ieee80211); |
c8d86be3 GKH |
3766 | } |
3767 | ||
c8d86be3 GKH |
3768 | void rtl8180_tx_isr(struct net_device *dev, int pri,short error) |
3769 | { | |
3770 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 GKH |
3771 | u32 *tail; //tail virtual addr |
3772 | u32 *head; //head virtual addr | |
3773 | u32 *begin;//start of ring virtual addr | |
3774 | u32 *nicv; //nic pointer virtual addr | |
c8d86be3 GKH |
3775 | u32 nic; //nic pointer physical addr |
3776 | u32 nicbegin;// start of ring physical addr | |
c8d86be3 GKH |
3777 | unsigned long flag; |
3778 | /* physical addr are ok on 32 bits since we set DMA mask*/ | |
c8d86be3 GKH |
3779 | int offs; |
3780 | int j,i; | |
3781 | int hd; | |
3782 | if (error) priv->stats.txretry++; //tony 20060601 | |
3783 | spin_lock_irqsave(&priv->tx_lock,flag); | |
3784 | switch(pri) { | |
3785 | case MANAGE_PRIORITY: | |
3786 | tail = priv->txmapringtail; | |
3787 | begin = priv->txmapring; | |
3788 | head = priv->txmapringhead; | |
3789 | nic = read_nic_dword(dev,TX_MANAGEPRIORITY_RING_ADDR); | |
3790 | nicbegin = priv->txmapringdma; | |
3791 | break; | |
c8d86be3 GKH |
3792 | case BK_PRIORITY: |
3793 | tail = priv->txbkpringtail; | |
3794 | begin = priv->txbkpring; | |
3795 | head = priv->txbkpringhead; | |
3796 | nic = read_nic_dword(dev,TX_BKPRIORITY_RING_ADDR); | |
3797 | nicbegin = priv->txbkpringdma; | |
3798 | break; | |
c8d86be3 GKH |
3799 | case BE_PRIORITY: |
3800 | tail = priv->txbepringtail; | |
3801 | begin = priv->txbepring; | |
3802 | head = priv->txbepringhead; | |
3803 | nic = read_nic_dword(dev,TX_BEPRIORITY_RING_ADDR); | |
3804 | nicbegin = priv->txbepringdma; | |
3805 | break; | |
c8d86be3 GKH |
3806 | case VI_PRIORITY: |
3807 | tail = priv->txvipringtail; | |
3808 | begin = priv->txvipring; | |
3809 | head = priv->txvipringhead; | |
3810 | nic = read_nic_dword(dev,TX_VIPRIORITY_RING_ADDR); | |
3811 | nicbegin = priv->txvipringdma; | |
3812 | break; | |
c8d86be3 GKH |
3813 | case VO_PRIORITY: |
3814 | tail = priv->txvopringtail; | |
3815 | begin = priv->txvopring; | |
3816 | head = priv->txvopringhead; | |
3817 | nic = read_nic_dword(dev,TX_VOPRIORITY_RING_ADDR); | |
3818 | nicbegin = priv->txvopringdma; | |
3819 | break; | |
c8d86be3 GKH |
3820 | case HI_PRIORITY: |
3821 | tail = priv->txhpringtail; | |
3822 | begin = priv->txhpring; | |
3823 | head = priv->txhpringhead; | |
3824 | nic = read_nic_dword(dev,TX_HIGHPRIORITY_RING_ADDR); | |
3825 | nicbegin = priv->txhpringdma; | |
3826 | break; | |
3827 | ||
3828 | default: | |
3829 | spin_unlock_irqrestore(&priv->tx_lock,flag); | |
3830 | return ; | |
3831 | } | |
fd882783 | 3832 | |
c8d86be3 GKH |
3833 | nicv = (u32*) ((nic - nicbegin) + (u8*)begin); |
3834 | if((head <= tail && (nicv > tail || nicv < head)) || | |
3835 | (head > tail && (nicv > tail && nicv < head))){ | |
c8d86be3 | 3836 | DMESGW("nic has lost pointer"); |
c8d86be3 GKH |
3837 | spin_unlock_irqrestore(&priv->tx_lock,flag); |
3838 | rtl8180_restart(dev); | |
3839 | return; | |
3840 | } | |
3841 | ||
3842 | /* we check all the descriptors between the head and the nic, | |
bbc9a991 | 3843 | * but not the currently pointed by the nic (the next to be txed) |
c8d86be3 GKH |
3844 | * and the previous of the pointed (might be in process ??) |
3845 | */ | |
c8d86be3 | 3846 | offs = (nic - nicbegin); |
c8d86be3 | 3847 | offs = offs / 8 /4; |
c8d86be3 GKH |
3848 | hd = (head - begin) /8; |
3849 | ||
3850 | if(offs >= hd) | |
3851 | j = offs - hd; | |
3852 | else | |
3853 | j = offs + (priv->txringcount -1 -hd); | |
c8d86be3 GKH |
3854 | |
3855 | j-=2; | |
3856 | if(j<0) j=0; | |
3857 | ||
c8d86be3 GKH |
3858 | for(i=0;i<j;i++) |
3859 | { | |
c8d86be3 GKH |
3860 | if((*head) & (1<<31)) |
3861 | break; | |
3862 | if(((*head)&(0x10000000)) != 0){ | |
c8d86be3 | 3863 | priv->CurrRetryCnt += (u16)((*head) & (0x000000ff)); |
fd882783 | 3864 | if (!error) |
c8d86be3 | 3865 | priv->NumTxOkTotal++; |
c8d86be3 | 3866 | } |
fd882783 BZ |
3867 | |
3868 | if (!error) | |
c8d86be3 | 3869 | priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff); |
fd882783 | 3870 | |
c8d86be3 GKH |
3871 | *head = *head &~ (1<<31); |
3872 | ||
3873 | if((head - begin)/8 == priv->txringcount-1) | |
3874 | head=begin; | |
c8d86be3 GKH |
3875 | else |
3876 | head+=8; | |
3877 | } | |
c8d86be3 | 3878 | |
c8d86be3 GKH |
3879 | /* the head has been moved to the last certainly TXed |
3880 | * (or at least processed by the nic) packet. | |
3881 | * The driver take forcefully owning of all these packets | |
3882 | * If the packet previous of the nic pointer has been | |
3883 | * processed this doesn't matter: it will be checked | |
3884 | * here at the next round. Anyway if no more packet are | |
3885 | * TXed no memory leak occour at all. | |
3886 | */ | |
3887 | ||
3888 | switch(pri) { | |
3889 | case MANAGE_PRIORITY: | |
3890 | priv->txmapringhead = head; | |
fd882783 | 3891 | |
c8d86be3 | 3892 | if(priv->ack_tx_to_ieee){ |
c8d86be3 | 3893 | if(rtl8180_is_tx_queue_empty(dev)){ |
c8d86be3 GKH |
3894 | priv->ack_tx_to_ieee = 0; |
3895 | ieee80211_ps_tx_ack(priv->ieee80211,!error); | |
3896 | } | |
c8d86be3 GKH |
3897 | } |
3898 | break; | |
c8d86be3 GKH |
3899 | case BK_PRIORITY: |
3900 | priv->txbkpringhead = head; | |
3901 | break; | |
c8d86be3 GKH |
3902 | case BE_PRIORITY: |
3903 | priv->txbepringhead = head; | |
3904 | break; | |
c8d86be3 GKH |
3905 | case VI_PRIORITY: |
3906 | priv->txvipringhead = head; | |
3907 | break; | |
c8d86be3 GKH |
3908 | case VO_PRIORITY: |
3909 | priv->txvopringhead = head; | |
3910 | break; | |
c8d86be3 GKH |
3911 | case HI_PRIORITY: |
3912 | priv->txhpringhead = head; | |
3913 | break; | |
3914 | } | |
3915 | ||
c8d86be3 | 3916 | spin_unlock_irqrestore(&priv->tx_lock,flag); |
c8d86be3 GKH |
3917 | } |
3918 | ||
c8d86be3 GKH |
3919 | void rtl8180_tx_irq_wq(struct work_struct *work) |
3920 | { | |
bf6aede7 | 3921 | struct delayed_work *dwork = to_delayed_work(work); |
c8d86be3 GKH |
3922 | struct ieee80211_device * ieee = (struct ieee80211_device*) |
3923 | container_of(dwork, struct ieee80211_device, watch_dog_wq); | |
3924 | struct net_device *dev = ieee->dev; | |
0370453f | 3925 | |
c8d86be3 GKH |
3926 | rtl8180_tx_isr(dev,MANAGE_PRIORITY,0); |
3927 | } | |
3928 | irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs) | |
3929 | { | |
3930 | struct net_device *dev = (struct net_device *) netdev; | |
3931 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
3932 | unsigned long flags; | |
3933 | u32 inta; | |
3934 | ||
3935 | /* We should return IRQ_NONE, but for now let me keep this */ | |
3936 | if(priv->irq_enabled == 0) return IRQ_HANDLED; | |
3937 | ||
3938 | spin_lock_irqsave(&priv->irq_th_lock,flags); | |
3939 | ||
c8d86be3 GKH |
3940 | //ISR: 4bytes |
3941 | inta = read_nic_dword(dev, ISR);// & priv->IntrMask; | |
3942 | write_nic_dword(dev,ISR,inta); // reset int situation | |
c8d86be3 GKH |
3943 | |
3944 | priv->stats.shints++; | |
3945 | ||
c8d86be3 GKH |
3946 | if(!inta){ |
3947 | spin_unlock_irqrestore(&priv->irq_th_lock,flags); | |
3948 | return IRQ_HANDLED; | |
3949 | /* | |
3950 | most probably we can safely return IRQ_NONE, | |
3951 | but for now is better to avoid problems | |
3952 | */ | |
3953 | } | |
3954 | ||
fd882783 BZ |
3955 | if (inta == 0xffff) { |
3956 | /* HW disappared */ | |
3957 | spin_unlock_irqrestore(&priv->irq_th_lock, flags); | |
3958 | return IRQ_HANDLED; | |
c8d86be3 GKH |
3959 | } |
3960 | ||
3961 | priv->stats.ints++; | |
c8d86be3 GKH |
3962 | |
3963 | if(!netif_running(dev)) { | |
3964 | spin_unlock_irqrestore(&priv->irq_th_lock,flags); | |
3965 | return IRQ_HANDLED; | |
3966 | } | |
3967 | ||
fd882783 | 3968 | if (inta & ISR_TimeOut) |
c8d86be3 | 3969 | write_nic_dword(dev, TimerInt, 0); |
c8d86be3 | 3970 | |
fd882783 | 3971 | if (inta & ISR_TBDOK) |
c8d86be3 | 3972 | priv->stats.txbeacon++; |
c8d86be3 | 3973 | |
fd882783 | 3974 | if (inta & ISR_TBDER) |
c8d86be3 | 3975 | priv->stats.txbeaconerr++; |
c8d86be3 | 3976 | |
fd882783 | 3977 | if (inta & IMR_TMGDOK) |
c8d86be3 | 3978 | rtl8180_tx_isr(dev,MANAGE_PRIORITY,0); |
c8d86be3 GKH |
3979 | |
3980 | if(inta & ISR_THPDER){ | |
c8d86be3 GKH |
3981 | priv->stats.txhperr++; |
3982 | rtl8180_tx_isr(dev,HI_PRIORITY,1); | |
3983 | priv->ieee80211->stats.tx_errors++; | |
3984 | } | |
3985 | ||
3986 | if(inta & ISR_THPDOK){ //High priority tx ok | |
c8d86be3 GKH |
3987 | priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828 |
3988 | priv->stats.txhpokint++; | |
3989 | rtl8180_tx_isr(dev,HI_PRIORITY,0); | |
3990 | } | |
3991 | ||
3992 | if(inta & ISR_RER) { | |
3993 | priv->stats.rxerr++; | |
c8d86be3 | 3994 | } |
c8d86be3 GKH |
3995 | if(inta & ISR_TBKDER){ //corresponding to BK_PRIORITY |
3996 | priv->stats.txbkperr++; | |
3997 | priv->ieee80211->stats.tx_errors++; | |
c8d86be3 GKH |
3998 | rtl8180_tx_isr(dev,BK_PRIORITY,1); |
3999 | rtl8180_try_wake_queue(dev, BE_PRIORITY); | |
4000 | } | |
4001 | ||
4002 | if(inta & ISR_TBEDER){ //corresponding to BE_PRIORITY | |
4003 | priv->stats.txbeperr++; | |
4004 | priv->ieee80211->stats.tx_errors++; | |
c8d86be3 | 4005 | rtl8180_tx_isr(dev,BE_PRIORITY,1); |
c8d86be3 GKH |
4006 | rtl8180_try_wake_queue(dev, BE_PRIORITY); |
4007 | } | |
c8d86be3 GKH |
4008 | if(inta & ISR_TNPDER){ //corresponding to VO_PRIORITY |
4009 | priv->stats.txnperr++; | |
4010 | priv->ieee80211->stats.tx_errors++; | |
c8d86be3 | 4011 | rtl8180_tx_isr(dev,NORM_PRIORITY,1); |
c8d86be3 | 4012 | rtl8180_try_wake_queue(dev, NORM_PRIORITY); |
c8d86be3 GKH |
4013 | } |
4014 | ||
4015 | if(inta & ISR_TLPDER){ //corresponding to VI_PRIORITY | |
4016 | priv->stats.txlperr++; | |
4017 | priv->ieee80211->stats.tx_errors++; | |
c8d86be3 | 4018 | rtl8180_tx_isr(dev,LOW_PRIORITY,1); |
c8d86be3 GKH |
4019 | rtl8180_try_wake_queue(dev, LOW_PRIORITY); |
4020 | } | |
4021 | ||
4022 | if(inta & ISR_ROK){ | |
c8d86be3 GKH |
4023 | priv->stats.rxint++; |
4024 | tasklet_schedule(&priv->irq_rx_tasklet); | |
4025 | } | |
4026 | ||
4027 | if(inta & ISR_RQoSOK ){ | |
c8d86be3 GKH |
4028 | priv->stats.rxint++; |
4029 | tasklet_schedule(&priv->irq_rx_tasklet); | |
4030 | } | |
4031 | if(inta & ISR_BcnInt) { | |
c8d86be3 GKH |
4032 | rtl8180_prepare_beacon(dev); |
4033 | } | |
4034 | ||
4035 | if(inta & ISR_RDU){ | |
c8d86be3 GKH |
4036 | DMESGW("No RX descriptor available"); |
4037 | priv->stats.rxrdu++; | |
c8d86be3 | 4038 | tasklet_schedule(&priv->irq_rx_tasklet); |
c8d86be3 | 4039 | } |
fd882783 | 4040 | |
c8d86be3 | 4041 | if(inta & ISR_RXFOVW){ |
c8d86be3 GKH |
4042 | priv->stats.rxoverflow++; |
4043 | tasklet_schedule(&priv->irq_rx_tasklet); | |
c8d86be3 GKH |
4044 | } |
4045 | ||
fd882783 BZ |
4046 | if (inta & ISR_TXFOVW) |
4047 | priv->stats.txoverflow++; | |
c8d86be3 GKH |
4048 | |
4049 | if(inta & ISR_TNPDOK){ //Normal priority tx ok | |
c8d86be3 | 4050 | priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828 |
c8d86be3 GKH |
4051 | priv->stats.txnpokint++; |
4052 | rtl8180_tx_isr(dev,NORM_PRIORITY,0); | |
4053 | } | |
4054 | ||
4055 | if(inta & ISR_TLPDOK){ //Low priority tx ok | |
c8d86be3 | 4056 | priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828 |
c8d86be3 GKH |
4057 | priv->stats.txlpokint++; |
4058 | rtl8180_tx_isr(dev,LOW_PRIORITY,0); | |
4059 | rtl8180_try_wake_queue(dev, LOW_PRIORITY); | |
4060 | } | |
4061 | ||
c8d86be3 GKH |
4062 | if(inta & ISR_TBKDOK){ //corresponding to BK_PRIORITY |
4063 | priv->stats.txbkpokint++; | |
c8d86be3 GKH |
4064 | priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828 |
4065 | rtl8180_tx_isr(dev,BK_PRIORITY,0); | |
4066 | rtl8180_try_wake_queue(dev, BE_PRIORITY); | |
4067 | } | |
4068 | ||
4069 | if(inta & ISR_TBEDOK){ //corresponding to BE_PRIORITY | |
4070 | priv->stats.txbeperr++; | |
c8d86be3 GKH |
4071 | priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828 |
4072 | rtl8180_tx_isr(dev,BE_PRIORITY,0); | |
4073 | rtl8180_try_wake_queue(dev, BE_PRIORITY); | |
4074 | } | |
c8d86be3 GKH |
4075 | force_pci_posting(dev); |
4076 | spin_unlock_irqrestore(&priv->irq_th_lock,flags); | |
4077 | ||
4078 | return IRQ_HANDLED; | |
4079 | } | |
4080 | ||
c8d86be3 GKH |
4081 | void rtl8180_irq_rx_tasklet(struct r8180_priv* priv) |
4082 | { | |
c8d86be3 | 4083 | rtl8180_rx(priv->dev); |
c8d86be3 GKH |
4084 | } |
4085 | ||
c8d86be3 GKH |
4086 | void GPIOChangeRFWorkItemCallBack(struct work_struct *work) |
4087 | { | |
c8d86be3 GKH |
4088 | struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work); |
4089 | struct net_device *dev = ieee->dev; | |
4090 | struct r8180_priv *priv = ieee80211_priv(dev); | |
c8d86be3 GKH |
4091 | u8 btPSR; |
4092 | u8 btConfig0; | |
4093 | RT_RF_POWER_STATE eRfPowerStateToSet; | |
4094 | bool bActuallySet=false; | |
4095 | ||
4096 | char *argv[3]; | |
4097 | static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh"; | |
4098 | static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL}; | |
4099 | static int readf_count = 0; | |
c8d86be3 | 4100 | |
c8d86be3 GKH |
4101 | if(readf_count % 10 == 0) |
4102 | priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state"); | |
4103 | ||
4104 | readf_count = (readf_count+1)%0xffff; | |
1994130e | 4105 | /* We should turn off LED before polling FF51[4]. */ |
c8d86be3 | 4106 | |
1994130e LF |
4107 | /* Turn off LED. */ |
4108 | btPSR = read_nic_byte(dev, PSR); | |
4109 | write_nic_byte(dev, PSR, (btPSR & ~BIT3)); | |
c8d86be3 | 4110 | |
1994130e LF |
4111 | /* It need to delay 4us suggested by Jong, 2008-01-16 */ |
4112 | udelay(4); | |
c8d86be3 | 4113 | |
1994130e LF |
4114 | /* HW radio On/Off according to the value of FF51[4](config0) */ |
4115 | btConfig0 = btPSR = read_nic_byte(dev, CONFIG0); | |
c8d86be3 | 4116 | |
1994130e | 4117 | eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff; |
c8d86be3 | 4118 | |
6de92dd6 LF |
4119 | /* Turn LED back on when radio enabled */ |
4120 | if (eRfPowerStateToSet == eRfOn) | |
4121 | write_nic_byte(dev, PSR, btPSR | BIT3); | |
c8d86be3 | 4122 | |
1994130e LF |
4123 | if ((priv->ieee80211->bHwRadioOff == true) && |
4124 | (eRfPowerStateToSet == eRfOn)) { | |
4125 | priv->ieee80211->bHwRadioOff = false; | |
4126 | bActuallySet = true; | |
4127 | } else if ((priv->ieee80211->bHwRadioOff == false) && | |
4128 | (eRfPowerStateToSet == eRfOff)) { | |
4129 | priv->ieee80211->bHwRadioOff = true; | |
4130 | bActuallySet = true; | |
4131 | } | |
c8d86be3 | 4132 | |
1994130e LF |
4133 | if (bActuallySet) { |
4134 | MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); | |
4135 | ||
4136 | /* To update the UI status for Power status changed */ | |
4137 | if (priv->ieee80211->bHwRadioOff == true) | |
4138 | argv[1] = "RFOFF"; | |
4139 | else | |
4140 | argv[1] = "RFON"; | |
4141 | argv[0] = RadioPowerPath; | |
4142 | argv[2] = NULL; | |
4143 | ||
4144 | call_usermodehelper(RadioPowerPath, argv, envp, 1); | |
4145 | } | |
c8d86be3 GKH |
4146 | } |
4147 | ||
4148 | static u8 read_acadapter_file(char *filename) | |
4149 | { | |
c8d86be3 GKH |
4150 | return 0; |
4151 | } | |
4152 | ||
c8d86be3 GKH |
4153 | module_init(rtl8180_pci_module_init); |
4154 | module_exit(rtl8180_pci_module_exit); |