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Staging: rtl8187se: Remove card_type
[net-next-2.6.git] / drivers / staging / rtl8187se / r8180_core.c
CommitLineData
c8d86be3
GKH		 1/*
2 This is part of rtl818x pci OpenSource driver - v 0.1
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public License)
5
6 Parts of this driver are based on the GPL part of the official
7 Realtek driver.
8
9 Parts of this driver are based on the rtl8180 driver skeleton
10 from Patric Schenke & Andres Salomon.
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
13
14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
15
16 RSSI calc function from 'The Deuce'
17
18 Some ideas borrowed from the 8139too.c driver included in linux kernel.
19
20 We (I?) want to thanks the Authors of those projecs and also the
21 Ndiswrapper's project Authors.
22
23 A big big thanks goes also to Realtek corp. for their help in my attempt to
24 add RTL8185 and RTL8225 support, and to David Young also.
b6d11c07
BZ		 25
26 Power management interface routines.
27 Written by Mariusz Matuszek.
c8d86be3
GKH		 28*/
29
c8d86be3 30#undef RX_DONT_PASS_UL
c8d86be3 31#undef DUMMY_RX
c8d86be3 32
c8d86be3 33#include <linux/syscalls.h>
fd882783 34
c8d86be3
GKH		 35#include "r8180_hw.h"
36#include "r8180.h"
c8d86be3 37#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
c8d86be3
GKH		 38#include "r8180_93cx6.h" /* Card EEPROM */
39#include "r8180_wx.h"
40#include "r8180_dm.h"
41
fd9b8d6e 42#include "ieee80211/dot11d.h"
c8d86be3 43
c8d86be3
GKH		 44#ifndef PCI_VENDOR_ID_BELKIN
45 #define PCI_VENDOR_ID_BELKIN 0x1799
46#endif
47#ifndef PCI_VENDOR_ID_DLINK
48 #define PCI_VENDOR_ID_DLINK 0x1186
49#endif
50
51static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = {
52 {
53 .vendor = PCI_VENDOR_ID_REALTEK,
c8d86be3
GKH		 54 .device = 0x8199,
55 .subvendor = PCI_ANY_ID,
56 .subdevice = PCI_ANY_ID,
57 .driver_data = 0,
58 },
c8d86be3
GKH		 59 {
60 .vendor = 0,
61 .device = 0,
62 .subvendor = 0,
63 .subdevice = 0,
64 .driver_data = 0,
65 }
66};
67
68
69static char* ifname = "wlan%d";
70static int hwseqnum = 0;
c8d86be3
GKH		 71static int hwwep = 0;
72static int channels = 0x3fff;
73
74#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
75#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
76MODULE_LICENSE("GPL");
77MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
78MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
79MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards");
80
81
c8d86be3
GKH		 82module_param(ifname, charp, S_IRUGO|S_IWUSR );
83module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
84module_param(hwwep,int, S_IRUGO|S_IWUSR);
85module_param(channels,int, S_IRUGO|S_IWUSR);
c8d86be3
GKH		 86
87MODULE_PARM_DESC(devname," Net interface name, wlan%d=default");
c8d86be3
GKH		 88MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
89MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
90MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
91
92
93static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
94 const struct pci_device_id *id);
95
96static void __devexit rtl8180_pci_remove(struct pci_dev *pdev);
97
98static void rtl8180_shutdown (struct pci_dev *pdev)
99{
100 struct net_device *dev = pci_get_drvdata(pdev);
727ae303
AB		 101 if (dev->netdev_ops->ndo_stop)
102 dev->netdev_ops->ndo_stop(dev);
c8d86be3
GKH		 103 pci_disable_device(pdev);
104}
105
b6d11c07
BZ		 106static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
107{
108 struct net_device *dev = pci_get_drvdata(pdev);
109
110 if (!netif_running(dev))
111 goto out_pci_suspend;
112
113 if (dev->netdev_ops->ndo_stop)
114 dev->netdev_ops->ndo_stop(dev);
115
116 netif_device_detach(dev);
117
118out_pci_suspend:
119 pci_save_state(pdev);
120 pci_disable_device(pdev);
121 pci_set_power_state(pdev, pci_choose_state(pdev, state));
122 return 0;
123}
124
125static int rtl8180_resume(struct pci_dev *pdev)
126{
127 struct net_device *dev = pci_get_drvdata(pdev);
128 int err;
129 u32 val;
130
131 pci_set_power_state(pdev, PCI_D0);
132
133 err = pci_enable_device(pdev);
134 if (err) {
135 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
136 dev->name);
137
138 return err;
139 }
140
141 pci_restore_state(pdev);
142
143 /*
144 * Suspend/Resume resets the PCI configuration space, so we have to
145 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
146 * from interfering with C3 CPU state. pci_restore_state won't help
147 * here since it only restores the first 64 bytes pci config header.
148 */
149 pci_read_config_dword(pdev, 0x40, &val);
150 if ((val & 0x0000ff00) != 0)
151 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
152
153 if (!netif_running(dev))
154 goto out;
155
156 if (dev->netdev_ops->ndo_open)
157 dev->netdev_ops->ndo_open(dev);
158
159 netif_device_attach(dev);
160out:
161 return 0;
162}
163
c8d86be3 164static struct pci_driver rtl8180_pci_driver = {
fd882783
BZ		 165 .name = RTL8180_MODULE_NAME,
166 .id_table = rtl8180_pci_id_tbl,
167 .probe = rtl8180_pci_probe,
168 .remove = __devexit_p(rtl8180_pci_remove),
169 .suspend = rtl8180_suspend,
170 .resume = rtl8180_resume,
c8d86be3
GKH		 171 .shutdown = rtl8180_shutdown,
172};
173
c8d86be3
GKH		 174u8 read_nic_byte(struct net_device *dev, int x)
175{
176 return 0xff&readb((u8*)dev->mem_start +x);
177}
178
179u32 read_nic_dword(struct net_device *dev, int x)
180{
181 return readl((u8*)dev->mem_start +x);
182}
183
184u16 read_nic_word(struct net_device *dev, int x)
185{
186 return readw((u8*)dev->mem_start +x);
187}
188
189void write_nic_byte(struct net_device *dev, int x,u8 y)
190{
191 writeb(y,(u8*)dev->mem_start +x);
192 udelay(20);
193}
194
195void write_nic_dword(struct net_device *dev, int x,u32 y)
196{
197 writel(y,(u8*)dev->mem_start +x);
198 udelay(20);
199}
200
201void write_nic_word(struct net_device *dev, int x,u16 y)
202{
203 writew(y,(u8*)dev->mem_start +x);
204 udelay(20);
205}
206
c8d86be3
GKH		 207inline void force_pci_posting(struct net_device *dev)
208{
209 read_nic_byte(dev,EPROM_CMD);
c8d86be3 210 mb();
c8d86be3
GKH		 211}
212
c8d86be3
GKH		 213irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs);
214void set_nic_rxring(struct net_device *dev);
215void set_nic_txring(struct net_device *dev);
216static struct net_device_stats *rtl8180_stats(struct net_device *dev);
217void rtl8180_commit(struct net_device *dev);
218void rtl8180_start_tx_beacon(struct net_device *dev);
219
c8d86be3
GKH		 220static struct proc_dir_entry *rtl8180_proc = NULL;
221
222static int proc_get_registers(char *page, char **start,
223 off_t offset, int count,
224 int *eof, void *data)
225{
226 struct net_device *dev = data;
c8d86be3
GKH		 227 int len = 0;
228 int i,n;
fd882783 229 int max = 0xff;
c8d86be3
GKH		 230
231 /* This dump the current register page */
fd882783
BZ		 232 for (n = 0; n <= max;) {
233 len += snprintf(page + len, count - len, "\nD: %2x > ", n);
c8d86be3 234
fd882783
BZ		 235 for (i = 0; i < 16 && n <= max; i++, n++)
236 len += snprintf(page + len, count - len, "%2x ",
237 read_nic_byte(dev, n));
c8d86be3
GKH		 238 }
239 len += snprintf(page + len, count - len,"\n");
240
c8d86be3
GKH		 241 *eof = 1;
242 return len;
c8d86be3
GKH		 243}
244
245int get_curr_tx_free_desc(struct net_device *dev, int priority);
246
247static int proc_get_stats_hw(char *page, char **start,
248 off_t offset, int count,
249 int *eof, void *data)
250{
c8d86be3 251 int len = 0;
c8d86be3 252
c8d86be3
GKH		 253 *eof = 1;
254 return len;
255}
256
c8d86be3
GKH		 257static int proc_get_stats_rx(char *page, char **start,
258 off_t offset, int count,
259 int *eof, void *data)
260{
261 struct net_device *dev = data;
262 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
263
264 int len = 0;
265
266 len += snprintf(page + len, count - len,
c8d86be3
GKH		 267 "RX OK: %lu\n"
268 "RX Retry: %lu\n"
269 "RX CRC Error(0-500): %lu\n"
270 "RX CRC Error(500-1000): %lu\n"
271 "RX CRC Error(>1000): %lu\n"
272 "RX ICV Error: %lu\n",
273 priv->stats.rxint,
274 priv->stats.rxerr,
275 priv->stats.rxcrcerrmin,
276 priv->stats.rxcrcerrmid,
277 priv->stats.rxcrcerrmax,
278 priv->stats.rxicverr
279 );
280
281 *eof = 1;
282 return len;
283}
284
c8d86be3
GKH		 285static int proc_get_stats_tx(char *page, char **start,
286 off_t offset, int count,
287 int *eof, void *data)
288{
289 struct net_device *dev = data;
290 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
291
292 int len = 0;
293 unsigned long totalOK;
294
295 totalOK=priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
296 len += snprintf(page + len, count - len,
c8d86be3
GKH		 297 "TX OK: %lu\n"
298 "TX Error: %lu\n"
299 "TX Retry: %lu\n"
300 "TX beacon OK: %lu\n"
301 "TX beacon error: %lu\n",
302 totalOK,
303 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
304 priv->stats.txretry,
305 priv->stats.txbeacon,
306 priv->stats.txbeaconerr
307 );
308
309 *eof = 1;
310 return len;
311}
312
c8d86be3
GKH		 313void rtl8180_proc_module_init(void)
314{
315 DMESG("Initializing proc filesystem");
c8d86be3 316 rtl8180_proc=create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net);
c8d86be3
GKH		 317}
318
c8d86be3
GKH		 319void rtl8180_proc_module_remove(void)
320{
c8d86be3 321 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
c8d86be3
GKH		 322}
323
c8d86be3
GKH		 324void rtl8180_proc_remove_one(struct net_device *dev)
325{
326 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
327 if (priv->dir_dev) {
328 remove_proc_entry("stats-hw", priv->dir_dev);
329 remove_proc_entry("stats-tx", priv->dir_dev);
330 remove_proc_entry("stats-rx", priv->dir_dev);
c8d86be3
GKH		 331 remove_proc_entry("registers", priv->dir_dev);
332 remove_proc_entry(dev->name, rtl8180_proc);
333 priv->dir_dev = NULL;
334 }
335}
336
c8d86be3
GKH		 337void rtl8180_proc_init_one(struct net_device *dev)
338{
339 struct proc_dir_entry *e;
340 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 341
be286fd2 342 priv->dir_dev = rtl8180_proc;
c8d86be3 343 if (!priv->dir_dev) {
be286fd2 344 DMESGE("Unable to initialize /proc/net/r8180/%s\n",
c8d86be3
GKH		 345 dev->name);
346 return;
347 }
348
349 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
350 priv->dir_dev, proc_get_stats_hw, dev);
c8d86be3
GKH		 351 if (!e) {
352 DMESGE("Unable to initialize "
be286fd2 353 "/proc/net/r8180/%s/stats-hw\n",
c8d86be3
GKH		 354 dev->name);
355 }
356
357 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
358 priv->dir_dev, proc_get_stats_rx, dev);
c8d86be3
GKH		 359 if (!e) {
360 DMESGE("Unable to initialize "
be286fd2 361 "/proc/net/r8180/%s/stats-rx\n",
c8d86be3
GKH		 362 dev->name);
363 }
364
365
366 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
367 priv->dir_dev, proc_get_stats_tx, dev);
c8d86be3
GKH		 368 if (!e) {
369 DMESGE("Unable to initialize "
be286fd2 370 "/proc/net/r8180/%s/stats-tx\n",
c8d86be3
GKH		 371 dev->name);
372 }
c8d86be3
GKH		 373
374 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
375 priv->dir_dev, proc_get_registers, dev);
c8d86be3
GKH		 376 if (!e) {
377 DMESGE("Unable to initialize "
be286fd2 378 "/proc/net/r8180/%s/registers\n",
c8d86be3
GKH		 379 dev->name);
380 }
381}
fd882783 382
c8d86be3
GKH		 383/*
384 FIXME: check if we can use some standard already-existent
385 data type+functions in kernel
386*/
387
388short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
389 struct buffer **bufferhead)
390{
c8d86be3
GKH		 391 struct buffer *tmp;
392
393 if(! *buffer){
394
395 *buffer = kmalloc(sizeof(struct buffer),GFP_KERNEL);
396
397 if (*buffer == NULL) {
398 DMESGE("Failed to kmalloc head of TX/RX struct");
399 return -1;
400 }
401 (*buffer)->next=*buffer;
402 (*buffer)->buf=buf;
403 (*buffer)->dma=dma;
404 if(bufferhead !=NULL)
405 (*bufferhead) = (*buffer);
406 return 0;
407 }
408 tmp=*buffer;
409
410 while(tmp->next!=(*buffer)) tmp=tmp->next;
411 if ((tmp->next= kmalloc(sizeof(struct buffer),GFP_KERNEL)) == NULL){
412 DMESGE("Failed to kmalloc TX/RX struct");
413 return -1;
414 }
415 tmp->next->buf=buf;
416 tmp->next->dma=dma;
417 tmp->next->next=*buffer;
418
419 return 0;
420}
421
c8d86be3
GKH		 422void buffer_free(struct net_device *dev,struct buffer **buffer,int len,short
423consistent)
424{
425
426 struct buffer *tmp,*next;
427 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
428 struct pci_dev *pdev=priv->pdev;
c8d86be3 429
fd882783
BZ		 430 if (!*buffer)
431 return;
c8d86be3 432
fd882783 433 tmp = *buffer;
c8d86be3 434
c8d86be3
GKH		 435 do{
436 next=tmp->next;
437 if(consistent){
438 pci_free_consistent(pdev,len,
439 tmp->buf,tmp->dma);
440 }else{
441 pci_unmap_single(pdev, tmp->dma,
442 len,PCI_DMA_FROMDEVICE);
443 kfree(tmp->buf);
444 }
445 kfree(tmp);
446 tmp = next;
447 }
448 while(next != *buffer);
449
450 *buffer=NULL;
451}
452
c8d86be3
GKH		 453void print_buffer(u32 *buffer, int len)
454{
455 int i;
456 u8 *buf =(u8*)buffer;
457
458 printk("ASCII BUFFER DUMP (len: %x):\n",len);
459
460 for(i=0;i<len;i++)
461 printk("%c",buf[i]);
462
463 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
464
465 for(i=0;i<len;i++)
466 printk("%02x",buf[i]);
467
468 printk("\n");
469}
470
c8d86be3
GKH		 471int get_curr_tx_free_desc(struct net_device *dev, int priority)
472{
473 struct r8180_priv *priv = ieee80211_priv(dev);
474 u32* tail;
475 u32* head;
476 int ret;
477
478 switch (priority){
479 case MANAGE_PRIORITY:
480 head = priv->txmapringhead;
481 tail = priv->txmapringtail;
482 break;
483 case BK_PRIORITY:
484 head = priv->txbkpringhead;
485 tail = priv->txbkpringtail;
486 break;
487 case BE_PRIORITY:
488 head = priv->txbepringhead;
489 tail = priv->txbepringtail;
490 break;
491 case VI_PRIORITY:
492 head = priv->txvipringhead;
493 tail = priv->txvipringtail;
494 break;
495 case VO_PRIORITY:
496 head = priv->txvopringhead;
497 tail = priv->txvopringtail;
498 break;
499 case HI_PRIORITY:
500 head = priv->txhpringhead;
501 tail = priv->txhpringtail;
502 break;
503 default:
504 return -1;
505 }
506
fd882783 507 if (head <= tail)
c8d86be3
GKH		 508 ret = priv->txringcount - (tail - head)/8;
509 else
510 ret = (head - tail)/8;
511
fd882783
BZ		 512 if (ret > priv->txringcount)
513 DMESG("BUG");
514
c8d86be3 515 return ret;
c8d86be3
GKH		 516}
517
c8d86be3
GKH		 518short check_nic_enought_desc(struct net_device *dev, int priority)
519{
520 struct r8180_priv *priv = ieee80211_priv(dev);
521 struct ieee80211_device *ieee = netdev_priv(dev);
c8d86be3 522 int requiredbyte, required;
fd882783 523
c8d86be3
GKH		 524 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
525
fd882783 526 if (ieee->current_network.QoS_Enable)
c8d86be3 527 requiredbyte += 2;
c8d86be3
GKH		 528
529 required = requiredbyte / (priv->txbuffsize-4);
fd882783
BZ		 530
531 if (requiredbyte % priv->txbuffsize)
532 required++;
533
c8d86be3
GKH		 534 /* for now we keep two free descriptor as a safety boundary
535 * between the tail and the head
536 */
537
538 return (required+2 < get_curr_tx_free_desc(dev,priority));
539}
540
c8d86be3
GKH		 541void fix_tx_fifo(struct net_device *dev)
542{
543 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
544 u32 *tmp;
545 int i;
ff954853 546
c8d86be3
GKH		 547 for (tmp=priv->txmapring, i=0;
548 i < priv->txringcount;
549 tmp+=8, i++){
550 *tmp = *tmp &~ (1<<31);
551 }
552
553 for (tmp=priv->txbkpring, i=0;
554 i < priv->txringcount;
555 tmp+=8, i++) {
556 *tmp = *tmp &~ (1<<31);
557 }
558
559 for (tmp=priv->txbepring, i=0;
560 i < priv->txringcount;
561 tmp+=8, i++){
562 *tmp = *tmp &~ (1<<31);
563 }
564 for (tmp=priv->txvipring, i=0;
565 i < priv->txringcount;
566 tmp+=8, i++) {
567 *tmp = *tmp &~ (1<<31);
568 }
569
570 for (tmp=priv->txvopring, i=0;
571 i < priv->txringcount;
572 tmp+=8, i++){
573 *tmp = *tmp &~ (1<<31);
574 }
575
576 for (tmp=priv->txhpring, i=0;
577 i < priv->txringcount;
578 tmp+=8,i++){
579 *tmp = *tmp &~ (1<<31);
580 }
581
582 for (tmp=priv->txbeaconring, i=0;
583 i < priv->txbeaconcount;
584 tmp+=8, i++){
585 *tmp = *tmp &~ (1<<31);
586 }
ff954853 587
c8d86be3
GKH		 588 priv->txmapringtail = priv->txmapring;
589 priv->txmapringhead = priv->txmapring;
590 priv->txmapbufstail = priv->txmapbufs;
591
592 priv->txbkpringtail = priv->txbkpring;
593 priv->txbkpringhead = priv->txbkpring;
594 priv->txbkpbufstail = priv->txbkpbufs;
595
596 priv->txbepringtail = priv->txbepring;
597 priv->txbepringhead = priv->txbepring;
598 priv->txbepbufstail = priv->txbepbufs;
599
600 priv->txvipringtail = priv->txvipring;
601 priv->txvipringhead = priv->txvipring;
602 priv->txvipbufstail = priv->txvipbufs;
603
604 priv->txvopringtail = priv->txvopring;
605 priv->txvopringhead = priv->txvopring;
606 priv->txvopbufstail = priv->txvopbufs;
607
608 priv->txhpringtail = priv->txhpring;
609 priv->txhpringhead = priv->txhpring;
610 priv->txhpbufstail = priv->txhpbufs;
611
612 priv->txbeaconringtail = priv->txbeaconring;
613 priv->txbeaconbufstail = priv->txbeaconbufs;
614 set_nic_txring(dev);
615
616 ieee80211_reset_queue(priv->ieee80211);
617 priv->ack_tx_to_ieee = 0;
618}
619
c8d86be3
GKH		 620void fix_rx_fifo(struct net_device *dev)
621{
622 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
623 u32 *tmp;
624 struct buffer *rxbuf;
625 u8 rx_desc_size;
626
c8d86be3 627 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 628
c8d86be3
GKH		 629 for (tmp=priv->rxring, rxbuf=priv->rxbufferhead;
630 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
631 tmp+=rx_desc_size,rxbuf=rxbuf->next){
632 *(tmp+2) = rxbuf->dma;
633 *tmp=*tmp &~ 0xfff;
634 *tmp=*tmp | priv->rxbuffersize;
635 *tmp |= (1<<31);
636 }
637
c8d86be3
GKH		 638 priv->rxringtail=priv->rxring;
639 priv->rxbuffer=priv->rxbufferhead;
640 priv->rx_skb_complete=1;
641 set_nic_rxring(dev);
642}
643
c8d86be3 644unsigned char QUALITY_MAP[] = {
fd882783
BZ		 645 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61,
646 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c,
647 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f,
648 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29,
649 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
650 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20,
651 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e,
652 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19,
653 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f,
654 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00
c8d86be3
GKH		 655};
656
657unsigned char STRENGTH_MAP[] = {
fd882783
BZ		 658 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
659 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
660 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
661 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
662 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
663 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
664 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
665 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
666 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
667 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
c8d86be3
GKH		 668};
669
fd882783
BZ		 670void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual)
671{
c8d86be3
GKH		 672 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
673 u32 temp;
674 u32 temp2;
675 u32 temp3;
676 u32 lsb;
677 u32 q;
678 u32 orig_qual;
679 u8 _rssi;
680
681 q = *qual;
682 orig_qual = *qual;
683 _rssi = 0; // avoid gcc complains..
684
685 if (q <= 0x4e) {
686 temp = QUALITY_MAP[q];
687 } else {
688 if( q & 0x80 ) {
689 temp = 0x32;
690 } else {
691 temp = 1;
692 }
693 }
694
695 *qual = temp;
696 temp2 = *rssi;
697
698 switch(priv->rf_chip){
699 case RFCHIPID_RFMD:
700 lsb = temp2 & 1;
701 temp2 &= 0x7e;
702 if ( !lsb || !(temp2 <= 0x3c) ) {
703 temp2 = 0x64;
704 } else {
705 temp2 = 100 * temp2 / 0x3c;
706 }
707 *rssi = temp2 & 0xff;
708 _rssi = temp2 & 0xff;
709 break;
710 case RFCHIPID_INTERSIL:
711 lsb = temp2;
712 temp2 &= 0xfffffffe;
713 temp2 *= 251;
714 temp3 = temp2;
715 temp2 <<= 6;
716 temp3 += temp2;
717 temp3 <<= 1;
718 temp2 = 0x4950df;
719 temp2 -= temp3;
720 lsb &= 1;
721 if ( temp2 <= 0x3e0000 ) {
722 if ( temp2 < 0xffef0000 )
723 temp2 = 0xffef0000;
724 } else {
725 temp2 = 0x3e0000;
726 }
727 if ( !lsb ) {
728 temp2 -= 0xf0000;
729 } else {
730 temp2 += 0xf0000;
731 }
732
733 temp3 = 0x4d0000;
734 temp3 -= temp2;
735 temp3 *= 100;
736 temp3 = temp3 / 0x6d;
737 temp3 >>= 0x10;
738 _rssi = temp3 & 0xff;
739 *rssi = temp3 & 0xff;
740 break;
741 case RFCHIPID_GCT:
742 lsb = temp2 & 1;
743 temp2 &= 0x7e;
744 if ( ! lsb || !(temp2 <= 0x3c) ){
745 temp2 = 0x64;
746 } else {
747 temp2 = (100 * temp2) / 0x3c;
748 }
749 *rssi = temp2 & 0xff;
750 _rssi = temp2 & 0xff;
751 break;
752 case RFCHIPID_PHILIPS:
753 if( orig_qual <= 0x4e ){
754 _rssi = STRENGTH_MAP[orig_qual];
755 *rssi = _rssi;
756 } else {
757 orig_qual -= 0x80;
758 if ( !orig_qual ){
759 _rssi = 1;
760 *rssi = 1;
761 } else {
762 _rssi = 0x32;
763 *rssi = 0x32;
764 }
765 }
766 break;
c8d86be3
GKH		 767 case RFCHIPID_MAXIM:
768 lsb = temp2 & 1;
769 temp2 &= 0x7e;
770 temp2 >>= 1;
771 temp2 += 0x42;
772 if( lsb != 0 ){
773 temp2 += 0xa;
774 }
775 *rssi = temp2 & 0xff;
776 _rssi = temp2 & 0xff;
777 break;
778 }
779
780 if ( _rssi < 0x64 ){
781 if ( _rssi == 0 ) {
782 *rssi = 1;
783 }
784 } else {
785 *rssi = 0x64;
786 }
787
788 return;
789}
790
c8d86be3
GKH		 791void rtl8180_irq_enable(struct net_device *dev)
792{
793 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 794
c8d86be3 795 priv->irq_enabled = 1;
c8d86be3
GKH		 796 write_nic_word(dev,INTA_MASK, priv->irq_mask);
797}
798
c8d86be3
GKH		 799void rtl8180_irq_disable(struct net_device *dev)
800{
801 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
802
c8d86be3 803 write_nic_dword(dev,IMR,0);
c8d86be3
GKH		 804 force_pci_posting(dev);
805 priv->irq_enabled = 0;
806}
807
c8d86be3
GKH		 808void rtl8180_set_mode(struct net_device *dev,int mode)
809{
810 u8 ecmd;
fd882783 811
c8d86be3
GKH		 812 ecmd=read_nic_byte(dev, EPROM_CMD);
813 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
814 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
815 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
816 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
817 write_nic_byte(dev, EPROM_CMD, ecmd);
818}
819
820void rtl8180_adapter_start(struct net_device *dev);
821void rtl8180_beacon_tx_enable(struct net_device *dev);
822
823void rtl8180_update_msr(struct net_device *dev)
824{
825 struct r8180_priv *priv = ieee80211_priv(dev);
826 u8 msr;
827 u32 rxconf;
828
829 msr = read_nic_byte(dev, MSR);
830 msr &= ~ MSR_LINK_MASK;
831
832 rxconf=read_nic_dword(dev,RX_CONF);
833
834 if(priv->ieee80211->state == IEEE80211_LINKED)
835 {
836 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
837 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
838 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
839 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
840 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
841 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
842 else
843 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
844 rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
845
846 }else {
847 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
848 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
849 }
850
851 write_nic_byte(dev, MSR, msr);
852 write_nic_dword(dev, RX_CONF, rxconf);
c8d86be3
GKH		 853}
854
c8d86be3
GKH		 855void rtl8180_set_chan(struct net_device *dev,short ch)
856{
857 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
858
fd882783 859 if ((ch > 14) || (ch < 1)) {
d599edca 860 printk("In %s: Invalid chnanel %d\n", __func__, ch);
c8d86be3
GKH		 861 return;
862 }
863
864 priv->chan=ch;
c8d86be3 865 priv->rf_set_chan(dev,priv->chan);
c8d86be3
GKH		 866}
867
c8d86be3
GKH		 868void rtl8180_rx_enable(struct net_device *dev)
869{
870 u8 cmd;
871 u32 rxconf;
872 /* for now we accept data, management & ctl frame*/
873 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
874
875 rxconf=read_nic_dword(dev,RX_CONF);
876 rxconf = rxconf &~ MAC_FILTER_MASK;
877 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
878 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
879 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
880 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
fd882783
BZ		 881 if (dev->flags & IFF_PROMISC)
882 DMESG("NIC in promisc mode");
c8d86be3
GKH		 883
884 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
885 dev->flags & IFF_PROMISC){
886 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
887 }else{
888 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
c8d86be3
GKH		 889 }
890
c8d86be3
GKH		 891 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
892 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
893 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
894 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
895 }
896
897 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
898 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
899
fd882783
BZ		 900 rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK;
901 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT);
c8d86be3
GKH		 902
903 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
904 rxconf = rxconf &~ MAX_RX_DMA_MASK;
905 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
906
fd882783 907 rxconf = rxconf | RCR_ONLYERLPKT;
c8d86be3
GKH		 908
909 rxconf = rxconf &~ RCR_CS_MASK;
fd882783 910
c8d86be3
GKH		 911 write_nic_dword(dev, RX_CONF, rxconf);
912
913 fix_rx_fifo(dev);
914
c8d86be3
GKH		 915 cmd=read_nic_byte(dev,CMD);
916 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
c8d86be3
GKH		 917}
918
c8d86be3
GKH		 919void set_nic_txring(struct net_device *dev)
920{
921 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 922
923 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
c8d86be3 924 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
c8d86be3 925 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
c8d86be3 926 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
c8d86be3 927 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
c8d86be3 928 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
c8d86be3
GKH		 929 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
930}
931
c8d86be3
GKH		 932void rtl8180_conttx_enable(struct net_device *dev)
933{
934 u32 txconf;
fd882783 935
c8d86be3
GKH		 936 txconf = read_nic_dword(dev,TX_CONF);
937 txconf = txconf &~ TX_LOOPBACK_MASK;
938 txconf = txconf | (TX_LOOPBACK_CONTINUE <<TX_LOOPBACK_SHIFT);
939 write_nic_dword(dev,TX_CONF,txconf);
940}
941
c8d86be3
GKH		 942void rtl8180_conttx_disable(struct net_device *dev)
943{
944 u32 txconf;
fd882783 945
c8d86be3
GKH		 946 txconf = read_nic_dword(dev,TX_CONF);
947 txconf = txconf &~ TX_LOOPBACK_MASK;
948 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
949 write_nic_dword(dev,TX_CONF,txconf);
950}
951
c8d86be3
GKH		 952void rtl8180_tx_enable(struct net_device *dev)
953{
954 u8 cmd;
955 u8 tx_agc_ctl;
956 u8 byte;
957 u32 txconf;
958 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 959
fd882783 960 txconf = read_nic_dword(dev, TX_CONF);
c8d86be3 961
d44eb889
LF		 962 byte = read_nic_byte(dev, CW_CONF);
963 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
964 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
965 write_nic_byte(dev, CW_CONF, byte);
c8d86be3 966
d44eb889
LF		 967 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
968 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
969 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
970 tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT);
971 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
972 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
973
974 txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
c8d86be3
GKH		 975
976 txconf = txconf &~ TX_LOOPBACK_MASK;
977 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
978 txconf = txconf &~ TCR_DPRETRY_MASK;
979 txconf = txconf &~ TCR_RTSRETRY_MASK;
980 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
981 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
982 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
983
d44eb889
LF		 984 if (priv->hw_plcp_len)
985 txconf = txconf & ~TCR_PLCP_LEN;
986 else
987 txconf = txconf | TCR_PLCP_LEN;
fd882783 988
c8d86be3
GKH		 989 txconf = txconf &~ TCR_MXDMA_MASK;
990 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
991 txconf = txconf | TCR_CWMIN;
992 txconf = txconf | TCR_DISCW;
993
fd882783 994 txconf = txconf | (1 << TX_NOICV_SHIFT);
c8d86be3
GKH		 995
996 write_nic_dword(dev,TX_CONF,txconf);
997
c8d86be3
GKH		 998 fix_tx_fifo(dev);
999
c8d86be3
GKH		 1000 cmd=read_nic_byte(dev,CMD);
1001 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1002
c8d86be3 1003 write_nic_dword(dev,TX_CONF,txconf);
c8d86be3
GKH		 1004}
1005
c8d86be3
GKH		 1006void rtl8180_beacon_tx_enable(struct net_device *dev)
1007{
1008 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1009
1010 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1011 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
1012 write_nic_byte(dev,TPPollStop, priv->dma_poll_mask);
c8d86be3
GKH		 1013 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1014}
1015
c8d86be3
GKH		 1016void rtl8180_beacon_tx_disable(struct net_device *dev)
1017{
1018 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1019
1020 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1021 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
1022 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1023 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1024
1025}
1026
c8d86be3
GKH		 1027void rtl8180_rtx_disable(struct net_device *dev)
1028{
1029 u8 cmd;
1030 struct r8180_priv *priv = ieee80211_priv(dev);
1031
1032 cmd=read_nic_byte(dev,CMD);
1033 write_nic_byte(dev, CMD, cmd &~ \
1034 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
1035 force_pci_posting(dev);
1036 mdelay(10);
c8d86be3
GKH		 1037
1038 if(!priv->rx_skb_complete)
1039 dev_kfree_skb_any(priv->rx_skb);
1040}
1041
c8d86be3
GKH		 1042short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
1043 int addr)
1044{
1045 int i;
1046 u32 *desc;
1047 u32 *tmp;
1048 dma_addr_t dma_desc, dma_tmp;
1049 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1050 struct pci_dev *pdev = priv->pdev;
1051 void *buf;
1052
1053 if((bufsize & 0xfff) != bufsize) {
1054 DMESGE ("TX buffer allocation too large");
1055 return 0;
1056 }
1057 desc = (u32*)pci_alloc_consistent(pdev,
1058 sizeof(u32)*8*count+256, &dma_desc);
fd882783
BZ		 1059 if (desc == NULL)
1060 return -1;
c8d86be3 1061
fd882783 1062 if (dma_desc & 0xff)
c8d86be3
GKH		 1063 /*
1064 * descriptor's buffer must be 256 byte aligned
1065 * we shouldn't be here, since we set DMA mask !
1066 */
be286fd2 1067 WARN(1, "DMA buffer is not aligned\n");
fd882783
BZ		 1068
1069 tmp = desc;
1070
1071 for (i = 0; i < count; i++) {
1072 buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp);
1073 if (buf == NULL)
1074 return -ENOMEM;
c8d86be3
GKH		 1075
1076 switch(addr) {
c8d86be3
GKH		 1077 case TX_MANAGEPRIORITY_RING_ADDR:
1078 if(-1 == buffer_add(&(priv->txmapbufs),buf,dma_tmp,NULL)){
1079 DMESGE("Unable to allocate mem for buffer NP");
1080 return -ENOMEM;
1081 }
1082 break;
c8d86be3
GKH		 1083 case TX_BKPRIORITY_RING_ADDR:
1084 if(-1 == buffer_add(&(priv->txbkpbufs),buf,dma_tmp,NULL)){
1085 DMESGE("Unable to allocate mem for buffer LP");
1086 return -ENOMEM;
1087 }
1088 break;
1089 case TX_BEPRIORITY_RING_ADDR:
1090 if(-1 == buffer_add(&(priv->txbepbufs),buf,dma_tmp,NULL)){
1091 DMESGE("Unable to allocate mem for buffer NP");
1092 return -ENOMEM;
1093 }
1094 break;
c8d86be3
GKH		 1095 case TX_VIPRIORITY_RING_ADDR:
1096 if(-1 == buffer_add(&(priv->txvipbufs),buf,dma_tmp,NULL)){
1097 DMESGE("Unable to allocate mem for buffer LP");
1098 return -ENOMEM;
1099 }
1100 break;
1101 case TX_VOPRIORITY_RING_ADDR:
1102 if(-1 == buffer_add(&(priv->txvopbufs),buf,dma_tmp,NULL)){
1103 DMESGE("Unable to allocate mem for buffer NP");
1104 return -ENOMEM;
1105 }
1106 break;
c8d86be3
GKH		 1107 case TX_HIGHPRIORITY_RING_ADDR:
1108 if(-1 == buffer_add(&(priv->txhpbufs),buf,dma_tmp,NULL)){
1109 DMESGE("Unable to allocate mem for buffer HP");
1110 return -ENOMEM;
1111 }
1112 break;
1113 case TX_BEACON_RING_ADDR:
1114 if(-1 == buffer_add(&(priv->txbeaconbufs),buf,dma_tmp,NULL)){
1115 DMESGE("Unable to allocate mem for buffer BP");
1116 return -ENOMEM;
1117 }
1118 break;
1119 }
1120 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1121 *(tmp+2) = (u32)dma_tmp;
1122 *(tmp+3) = bufsize;
1123
1124 if(i+1<count)
1125 *(tmp+4) = (u32)dma_desc+((i+1)*8*4);
1126 else
1127 *(tmp+4) = (u32)dma_desc;
1128
1129 tmp=tmp+8;
1130 }
1131
1132 switch(addr) {
1133 case TX_MANAGEPRIORITY_RING_ADDR:
1134 priv->txmapringdma=dma_desc;
1135 priv->txmapring=desc;
1136 break;
c8d86be3
GKH		 1137 case TX_BKPRIORITY_RING_ADDR:
1138 priv->txbkpringdma=dma_desc;
1139 priv->txbkpring=desc;
1140 break;
c8d86be3
GKH		 1141 case TX_BEPRIORITY_RING_ADDR:
1142 priv->txbepringdma=dma_desc;
1143 priv->txbepring=desc;
1144 break;
c8d86be3
GKH		 1145 case TX_VIPRIORITY_RING_ADDR:
1146 priv->txvipringdma=dma_desc;
1147 priv->txvipring=desc;
1148 break;
c8d86be3
GKH		 1149 case TX_VOPRIORITY_RING_ADDR:
1150 priv->txvopringdma=dma_desc;
1151 priv->txvopring=desc;
1152 break;
c8d86be3
GKH		 1153 case TX_HIGHPRIORITY_RING_ADDR:
1154 priv->txhpringdma=dma_desc;
1155 priv->txhpring=desc;
1156 break;
c8d86be3
GKH		 1157 case TX_BEACON_RING_ADDR:
1158 priv->txbeaconringdma=dma_desc;
1159 priv->txbeaconring=desc;
1160 break;
1161
1162 }
1163
c8d86be3
GKH		 1164 return 0;
1165}
1166
c8d86be3
GKH		 1167void free_tx_desc_rings(struct net_device *dev)
1168{
c8d86be3
GKH		 1169 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1170 struct pci_dev *pdev=priv->pdev;
1171 int count = priv->txringcount;
1172
1173 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1174 priv->txmapring, priv->txmapringdma);
1175 buffer_free(dev,&(priv->txmapbufs),priv->txbuffsize,1);
1176
1177 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1178 priv->txbkpring, priv->txbkpringdma);
1179 buffer_free(dev,&(priv->txbkpbufs),priv->txbuffsize,1);
1180
1181 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1182 priv->txbepring, priv->txbepringdma);
1183 buffer_free(dev,&(priv->txbepbufs),priv->txbuffsize,1);
1184
1185 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1186 priv->txvipring, priv->txvipringdma);
1187 buffer_free(dev,&(priv->txvipbufs),priv->txbuffsize,1);
1188
1189 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1190 priv->txvopring, priv->txvopringdma);
1191 buffer_free(dev,&(priv->txvopbufs),priv->txbuffsize,1);
1192
1193 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1194 priv->txhpring, priv->txhpringdma);
1195 buffer_free(dev,&(priv->txhpbufs),priv->txbuffsize,1);
1196
1197 count = priv->txbeaconcount;
1198 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1199 priv->txbeaconring, priv->txbeaconringdma);
1200 buffer_free(dev,&(priv->txbeaconbufs),priv->txbuffsize,1);
1201}
1202
c8d86be3
GKH		 1203void free_rx_desc_ring(struct net_device *dev)
1204{
1205 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1206 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH		 1207 int count = priv->rxringcount;
1208
c8d86be3
GKH		 1209 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1210 priv->rxring, priv->rxringdma);
c8d86be3
GKH		 1211
1212 buffer_free(dev,&(priv->rxbuffer),priv->rxbuffersize,0);
1213}
1214
c8d86be3
GKH		 1215short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
1216{
1217 int i;
1218 u32 *desc;
1219 u32 *tmp;
1220 dma_addr_t dma_desc,dma_tmp;
1221 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1222 struct pci_dev *pdev=priv->pdev;
1223 void *buf;
1224 u8 rx_desc_size;
1225
c8d86be3 1226 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3
GKH		 1227
1228 if((bufsize & 0xfff) != bufsize){
1229 DMESGE ("RX buffer allocation too large");
1230 return -1;
1231 }
1232
1233 desc = (u32*)pci_alloc_consistent(pdev,sizeof(u32)*rx_desc_size*count+256,
1234 &dma_desc);
1235
fd882783 1236 if (dma_desc & 0xff)
c8d86be3
GKH		 1237 /*
1238 * descriptor's buffer must be 256 byte aligned
1239 * should never happen since we specify the DMA mask
1240 */
be286fd2 1241 WARN(1, "DMA buffer is not aligned\n");
c8d86be3
GKH		 1242
1243 priv->rxring=desc;
1244 priv->rxringdma=dma_desc;
1245 tmp=desc;
1246
fd882783 1247 for (i = 0; i < count; i++) {
c8d86be3
GKH		 1248 if ((buf= kmalloc(bufsize * sizeof(u8),GFP_ATOMIC)) == NULL){
1249 DMESGE("Failed to kmalloc RX buffer");
1250 return -1;
1251 }
1252
1253 dma_tmp = pci_map_single(pdev,buf,bufsize * sizeof(u8),
1254 PCI_DMA_FROMDEVICE);
1255
c8d86be3
GKH		 1256 if(-1 == buffer_add(&(priv->rxbuffer), buf,dma_tmp,
1257 &(priv->rxbufferhead))){
1258 DMESGE("Unable to allocate mem RX buf");
1259 return -1;
1260 }
1261 *tmp = 0; //zero pads the header of the descriptor
1262 *tmp = *tmp |( bufsize&0xfff);
1263 *(tmp+2) = (u32)dma_tmp;
1264 *tmp = *tmp |(1<<31); // descriptor void, owned by the NIC
1265
c8d86be3
GKH		 1266 tmp=tmp+rx_desc_size;
1267 }
1268
1269 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor
1270
c8d86be3
GKH		 1271 return 0;
1272}
1273
1274
1275void set_nic_rxring(struct net_device *dev)
1276{
1277 u8 pgreg;
1278 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1279
c8d86be3
GKH		 1280 pgreg=read_nic_byte(dev, PGSELECT);
1281 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
1282
c8d86be3
GKH		 1283 write_nic_dword(dev, RXRING_ADDR,priv->rxringdma);
1284}
1285
c8d86be3
GKH		 1286void rtl8180_reset(struct net_device *dev)
1287{
c8d86be3
GKH		 1288 u8 cr;
1289
c8d86be3
GKH		 1290 rtl8180_irq_disable(dev);
1291
1292 cr=read_nic_byte(dev,CMD);
1293 cr = cr & 2;
1294 cr = cr | (1<<CMD_RST_SHIFT);
1295 write_nic_byte(dev,CMD,cr);
1296
1297 force_pci_posting(dev);
1298
1299 mdelay(200);
1300
1301 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1302 DMESGW("Card reset timeout!");
1303 else
1304 DMESG("Card successfully reset");
1305
c8d86be3
GKH		 1306 rtl8180_set_mode(dev,EPROM_CMD_LOAD);
1307 force_pci_posting(dev);
1308 mdelay(200);
c8d86be3
GKH		 1309}
1310
1311inline u16 ieeerate2rtlrate(int rate)
1312{
1313 switch(rate){
1314 case 10:
fd882783 1315 return 0;
c8d86be3 1316 case 20:
fd882783 1317 return 1;
c8d86be3 1318 case 55:
fd882783 1319 return 2;
c8d86be3 1320 case 110:
fd882783 1321 return 3;
c8d86be3 1322 case 60:
fd882783 1323 return 4;
c8d86be3 1324 case 90:
fd882783 1325 return 5;
c8d86be3 1326 case 120:
fd882783 1327 return 6;
c8d86be3 1328 case 180:
fd882783 1329 return 7;
c8d86be3 1330 case 240:
fd882783 1331 return 8;
c8d86be3 1332 case 360:
fd882783 1333 return 9;
c8d86be3 1334 case 480:
fd882783 1335 return 10;
c8d86be3 1336 case 540:
fd882783 1337 return 11;
c8d86be3 1338 default:
fd882783 1339 return 3;
c8d86be3
GKH		 1340 }
1341}
1342
1343static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540,720};
fd882783 1344
c8d86be3
GKH		 1345inline u16 rtl8180_rate2rate(short rate)
1346{
fd882783
BZ		 1347 if (rate > 12)
1348 return 10;
c8d86be3
GKH		 1349 return rtl_rate[rate];
1350}
fd882783 1351
c8d86be3
GKH		 1352inline u8 rtl8180_IsWirelessBMode(u16 rate)
1353{
1354 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
1355 return 1;
fd882783
BZ		 1356 else
1357 return 0;
c8d86be3 1358}
fd882783 1359
c8d86be3 1360u16 N_DBPSOfRate(u16 DataRate);
fd882783
BZ		 1361
1362u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame,
1363 u8 bShortPreamble)
c8d86be3
GKH		 1364{
1365 u16 FrameTime;
1366 u16 N_DBPS;
1367 u16 Ceiling;
1368
fd882783
BZ		 1369 if (rtl8180_IsWirelessBMode(DataRate)) {
1370 if (bManagementFrame || !bShortPreamble || DataRate == 10)
1371 /* long preamble */
c8d86be3 1372 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
c8d86be3 1373 else
fd882783 1374 /* short preamble */
c8d86be3 1375 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
fd882783
BZ		 1376
1377 if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */
1378 FrameTime++;
1379 } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */
c8d86be3
GKH		 1380 N_DBPS = N_DBPSOfRate(DataRate);
1381 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
1382 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
1383 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
1384 }
1385 return FrameTime;
1386}
fd882783 1387
c8d86be3
GKH		 1388u16 N_DBPSOfRate(u16 DataRate)
1389{
1390 u16 N_DBPS = 24;
1391
fd882783
BZ		 1392 switch (DataRate) {
1393 case 60:
1394 N_DBPS = 24;
1395 break;
1396 case 90:
1397 N_DBPS = 36;
1398 break;
1399 case 120:
1400 N_DBPS = 48;
1401 break;
1402 case 180:
1403 N_DBPS = 72;
1404 break;
1405 case 240:
1406 N_DBPS = 96;
1407 break;
1408 case 360:
1409 N_DBPS = 144;
1410 break;
1411 case 480:
1412 N_DBPS = 192;
1413 break;
1414 case 540:
1415 N_DBPS = 216;
1416 break;
1417 default:
1418 break;
1419 }
c8d86be3 1420
fd882783 1421 return N_DBPS;
c8d86be3
GKH		 1422}
1423
1424//{by amy 080312
1425//
1426// Description:
1427// For Netgear case, they want good-looking singal strength.
1428// 2004.12.05, by rcnjko.
1429//
fd882783 1430long NetgearSignalStrengthTranslate(long LastSS, long CurrSS)
c8d86be3
GKH		 1431{
1432 long RetSS;
1433
1434 // Step 1. Scale mapping.
fd882783 1435 if (CurrSS >= 71 && CurrSS <= 100)
c8d86be3 1436 RetSS = 90 + ((CurrSS - 70) / 3);
fd882783 1437 else if (CurrSS >= 41 && CurrSS <= 70)
c8d86be3 1438 RetSS = 78 + ((CurrSS - 40) / 3);
fd882783 1439 else if (CurrSS >= 31 && CurrSS <= 40)
c8d86be3 1440 RetSS = 66 + (CurrSS - 30);
fd882783 1441 else if (CurrSS >= 21 && CurrSS <= 30)
c8d86be3 1442 RetSS = 54 + (CurrSS - 20);
fd882783 1443 else if (CurrSS >= 5 && CurrSS <= 20)
c8d86be3 1444 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
fd882783 1445 else if (CurrSS == 4)
c8d86be3 1446 RetSS = 36;
fd882783 1447 else if (CurrSS == 3)
c8d86be3 1448 RetSS = 27;
fd882783 1449 else if (CurrSS == 2)
c8d86be3 1450 RetSS = 18;
fd882783 1451 else if (CurrSS == 1)
c8d86be3 1452 RetSS = 9;
c8d86be3 1453 else
c8d86be3 1454 RetSS = CurrSS;
c8d86be3
GKH		 1455
1456 // Step 2. Smoothing.
1457 if(LastSS > 0)
c8d86be3 1458 RetSS = ((LastSS * 5) + (RetSS)+ 5) / 6;
c8d86be3
GKH		 1459
1460 return RetSS;
1461}
fd882783 1462
c8d86be3
GKH		 1463//
1464// Description:
1465// Translate 0-100 signal strength index into dBm.
1466//
fd882783 1467long TranslateToDbm8185(u8 SignalStrengthIndex)
c8d86be3 1468{
fd882783 1469 long SignalPower;
c8d86be3
GKH		 1470
1471 // Translate to dBm (x=0.5y-95).
1472 SignalPower = (long)((SignalStrengthIndex + 1) >> 1);
1473 SignalPower -= 95;
1474
1475 return SignalPower;
1476}
fd882783 1477
c8d86be3
GKH		 1478//
1479// Description:
1480// Perform signal smoothing for dynamic mechanism.
1481// This is different with PerformSignalSmoothing8185 in smoothing fomula.
1482// No dramatic adjustion is apply because dynamic mechanism need some degree
1483// of correctness. Ported from 8187B.
1484// 2007-02-26, by Bruce.
1485//
fd882783
BZ		 1486void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv,
1487 bool bCckRate)
c8d86be3 1488{
c8d86be3
GKH		 1489 // Determin the current packet is CCK rate.
1490 priv->bCurCCKPkt = bCckRate;
1491
fd882783 1492 if (priv->UndecoratedSmoothedSS >= 0)
c8d86be3 1493 priv->UndecoratedSmoothedSS = ( (priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10) ) / 6;
c8d86be3 1494 else
c8d86be3 1495 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10;
c8d86be3
GKH		 1496
1497 priv->UndercorateSmoothedRxPower = ( (priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower* 11)) / 60;
1498
fd882783 1499 if (bCckRate)
c8d86be3 1500 priv->CurCCKRSSI = priv->RSSI;
c8d86be3 1501 else
c8d86be3 1502 priv->CurCCKRSSI = 0;
c8d86be3
GKH		 1503}
1504
1505//by amy 080312}
1506
1507/* This is rough RX isr handling routine*/
1508void rtl8180_rx(struct net_device *dev)
1509{
1510 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1511 struct sk_buff *tmp_skb;
c8d86be3
GKH		 1512 short first,last;
1513 u32 len;
1514 int lastlen;
1515 unsigned char quality, signal;
1516 u8 rate;
c8d86be3
GKH		 1517 u32 *tmp,*tmp2;
1518 u8 rx_desc_size;
1519 u8 padding;
c8d86be3
GKH		 1520 char rxpower = 0;
1521 u32 RXAGC = 0;
1522 long RxAGC_dBm = 0;
1523 u8 LNA=0, BB=0;
1524 u8 LNA_gain[4]={02, 17, 29, 39};
1525 u8 Antenna = 0;
0604384d 1526 struct ieee80211_hdr_4addr *hdr;
c8d86be3
GKH		 1527 u16 fc,type;
1528 u8 bHwError = 0,bCRC = 0,bICV = 0;
c8d86be3
GKH		 1529 bool bCckRate = false;
1530 u8 RSSI = 0;
fd882783 1531 long SignalStrengthIndex = 0;
c8d86be3
GKH		 1532 struct ieee80211_rx_stats stats = {
1533 .signal = 0,
1534 .noise = -98,
1535 .rate = 0,
c8d86be3
GKH		 1536 .freq = IEEE80211_24GHZ_BAND,
1537 };
1538
c8d86be3
GKH		 1539 stats.nic_type = NIC_8185B;
1540 rx_desc_size = 8;
1541
c8d86be3 1542 if ((*(priv->rxringtail)) & (1<<31)) {
c8d86be3
GKH		 1543 /* we have got an RX int, but the descriptor
1544 * we are pointing is empty*/
1545
1546 priv->stats.rxnodata++;
1547 priv->ieee80211->stats.rx_errors++;
1548
c8d86be3
GKH		 1549 tmp2 = NULL;
1550 tmp = priv->rxringtail;
1551 do{
1552 if(tmp == priv->rxring)
c8d86be3
GKH		 1553 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size;
1554 else
1555 tmp -= rx_desc_size;
1556
1557 if(! (*tmp & (1<<31)))
1558 tmp2 = tmp;
1559 }while(tmp != priv->rxring);
1560
1561 if(tmp2) priv->rxringtail = tmp2;
c8d86be3
GKH		 1562 }
1563
1564 /* while there are filled descriptors */
1565 while(!(*(priv->rxringtail) & (1<<31))){
1566 if(*(priv->rxringtail) & (1<<26))
1567 DMESGW("RX buffer overflow");
1568 if(*(priv->rxringtail) & (1<<12))
1569 priv->stats.rxicverr++;
1570
1571 if(*(priv->rxringtail) & (1<<27)){
1572 priv->stats.rxdmafail++;
1573 //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail);
1574 goto drop;
1575 }
1576
1577 pci_dma_sync_single_for_cpu(priv->pdev,
1578 priv->rxbuffer->dma,
1579 priv->rxbuffersize * \
1580 sizeof(u8),
1581 PCI_DMA_FROMDEVICE);
1582
1583 first = *(priv->rxringtail) & (1<<29) ? 1:0;
1584 if(first) priv->rx_prevlen=0;
1585
1586 last = *(priv->rxringtail) & (1<<28) ? 1:0;
1587 if(last){
1588 lastlen=((*priv->rxringtail) &0xfff);
1589
1590 /* if the last descriptor (that should
1591 * tell us the total packet len) tell
1592 * us something less than the descriptors
1593 * len we had until now, then there is some
1594 * problem..
1595 * workaround to prevent kernel panic
1596 */
1597 if(lastlen < priv->rx_prevlen)
1598 len=0;
1599 else
1600 len=lastlen-priv->rx_prevlen;
1601
1602 if(*(priv->rxringtail) & (1<<13)) {
c8d86be3
GKH		 1603 if ((*(priv->rxringtail) & 0xfff) <500)
1604 priv->stats.rxcrcerrmin++;
1605 else if ((*(priv->rxringtail) & 0x0fff) >1000)
1606 priv->stats.rxcrcerrmax++;
1607 else
1608 priv->stats.rxcrcerrmid++;
1609
1610 }
1611
1612 }else{
1613 len = priv->rxbuffersize;
1614 }
1615
c8d86be3
GKH		 1616 if(first && last) {
1617 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1618 }else if(first) {
1619 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1620 if(padding) {
1621 len -= 2;
1622 }
1623 }else {
1624 padding = 0;
1625 }
c8d86be3 1626 padding = 0;
c8d86be3
GKH		 1627 priv->rx_prevlen+=len;
1628
1629 if(priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100){
1630 /* HW is probably passing several buggy frames
1631 * without FD or LD flag set.
1632 * Throw this garbage away to prevent skb
1633 * memory exausting
1634 */
1635 if(!priv->rx_skb_complete)
1636 dev_kfree_skb_any(priv->rx_skb);
1637 priv->rx_skb_complete = 1;
1638 }
1639
c8d86be3
GKH		 1640 signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16);
1641 signal=(signal&0xfe)>>1; // Modify by hikaru 6.6
1642
1643 quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff));
1644
1645 stats.mac_time[0] = *(priv->rxringtail+1);
1646 stats.mac_time[1] = *(priv->rxringtail+2);
1647 rxpower =((char)(((*(priv->rxringtail+4))& (0x00ff0000))>>16))/2 - 42;
1648 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>> 8)) & (0x7f);
1649
c8d86be3
GKH		 1650 rate=((*(priv->rxringtail)) &
1651 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20;
1652
1653 stats.rate = rtl8180_rate2rate(rate);
c8d86be3 1654 Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ;
c8d86be3
GKH		 1655//by amy for antenna
1656 if(!rtl8180_IsWirelessBMode(stats.rate))
1657 { // OFDM rate.
1658
1659 RxAGC_dBm = rxpower+1; //bias
1660 }
1661 else
1662 { // CCK rate.
1663 RxAGC_dBm = signal;//bit 0 discard
1664
1665 LNA = (u8) (RxAGC_dBm & 0x60 ) >> 5 ; //bit 6~ bit 5
1666 BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0
1667
1668 RxAGC_dBm = -( LNA_gain[LNA] + (BB *2) ); //Pin_11b=-(LNA_gain+BB_gain) (dBm)
1669
1670 RxAGC_dBm +=4; //bias
1671 }
1672
1673 if(RxAGC_dBm & 0x80) //absolute value
1674 RXAGC= ~(RxAGC_dBm)+1;
1675 bCckRate = rtl8180_IsWirelessBMode(stats.rate);
1676 // Translate RXAGC into 1-100.
1677 if(!rtl8180_IsWirelessBMode(stats.rate))
1678 { // OFDM rate.
1679 if(RXAGC>90)
1680 RXAGC=90;
1681 else if(RXAGC<25)
1682 RXAGC=25;
1683 RXAGC=(90-RXAGC)*100/65;
1684 }
1685 else
1686 { // CCK rate.
1687 if(RXAGC>95)
1688 RXAGC=95;
1689 else if(RXAGC<30)
1690 RXAGC=30;
1691 RXAGC=(95-RXAGC)*100/65;
1692 }
1693 priv->SignalStrength = (u8)RXAGC;
1694 priv->RecvSignalPower = RxAGC_dBm ; // It can use directly by SD3 CMLin
1695 priv->RxPower = rxpower;
1696 priv->RSSI = RSSI;
1697//{by amy 080312
1698 // SQ translation formular is provided by SD3 DZ. 2006.06.27, by rcnjko.
1699 if(quality >= 127)
1700 quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now;
1701 else if(quality < 27)
1702 quality = 100;
1703 else
1704 quality = 127 - quality;
1705 priv->SignalQuality = quality;
c8d86be3
GKH		 1706
1707 stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength;
1708 stats.signalstrength = RXAGC;
1709 if(stats.signalstrength > 100)
1710 stats.signalstrength = 100;
1711 stats.signalstrength = (stats.signalstrength * 70)/100 + 30;
1712 // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength);
1713 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality;
1714 stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual;
1715//by amy 080312}
1716 bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 )
1717 | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 );
1718 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13;
1719 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12;
0604384d 1720 hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf;
c8d86be3
GKH		 1721 fc = le16_to_cpu(hdr->frame_ctl);
1722 type = WLAN_FC_GET_TYPE(fc);
1723
1724 if((IEEE80211_FTYPE_CTL != type) &&
1725 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
1726 && (!bHwError) && (!bCRC)&& (!bICV))
1727 {
1728//by amy 080312
1729 // Perform signal smoothing for dynamic mechanism on demand.
1730 // This is different with PerformSignalSmoothing8185 in smoothing fomula.
1731 // No dramatic adjustion is apply because dynamic mechanism need some degree
1732 // of correctness. 2007.01.23, by shien chang.
1733 PerformUndecoratedSignalSmoothing8185(priv,bCckRate);
1734 //
1735 // For good-looking singal strength.
1736 //
1737 SignalStrengthIndex = NetgearSignalStrengthTranslate(
1738 priv->LastSignalStrengthInPercent,
1739 priv->SignalStrength);
1740
1741 priv->LastSignalStrengthInPercent = SignalStrengthIndex;
1742 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex);
1743 //
1744 // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified,
1745 // so we record the correct power here.
1746 //
1747 priv->Stats_SignalQuality =(long) (priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6;
1748 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower -1) / 6;
1749
1750 // Figure out which antenna that received the lasted packet.
1751 priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main.
1752//by amy 080312
1753 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength);
1754 }
1755
1756//by amy for antenna
c8d86be3
GKH		 1757#ifndef DUMMY_RX
1758 if(first){
1759 if(!priv->rx_skb_complete){
1760 /* seems that HW sometimes fails to reiceve and
1761 doesn't provide the last descriptor */
c8d86be3
GKH		 1762 dev_kfree_skb_any(priv->rx_skb);
1763 priv->stats.rxnolast++;
c8d86be3
GKH		 1764 }
1765 /* support for prism header has been originally added by Christian */
1766 if(priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1767
c8d86be3
GKH		 1768 }else{
1769 priv->rx_skb = dev_alloc_skb(len+2);
1770 if( !priv->rx_skb) goto drop;
c8d86be3
GKH		 1771 }
1772
1773 priv->rx_skb_complete=0;
1774 priv->rx_skb->dev=dev;
1775 }else{
1776 /* if we are here we should have already RXed
1777 * the first frame.
1778 * If we get here and the skb is not allocated then
1779 * we have just throw out garbage (skb not allocated)
1780 * and we are still rxing garbage....
1781 */
1782 if(!priv->rx_skb_complete){
1783
1784 tmp_skb= dev_alloc_skb(priv->rx_skb->len +len+2);
1785
1786 if(!tmp_skb) goto drop;
1787
1788 tmp_skb->dev=dev;
c8d86be3 1789
c8d86be3
GKH		 1790 memcpy(skb_put(tmp_skb,priv->rx_skb->len),
1791 priv->rx_skb->data,
1792 priv->rx_skb->len);
c8d86be3
GKH		 1793
1794 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH		 1795
1796 priv->rx_skb=tmp_skb;
1797 }
1798 }
ff954853 1799
c8d86be3 1800 if(!priv->rx_skb_complete) {
c8d86be3
GKH		 1801 if(padding) {
1802 memcpy(skb_put(priv->rx_skb,len),
1803 (((unsigned char *)priv->rxbuffer->buf) + 2),len);
1804 } else {
c8d86be3
GKH		 1805 memcpy(skb_put(priv->rx_skb,len),
1806 priv->rxbuffer->buf,len);
c8d86be3 1807 }
c8d86be3 1808 }
c8d86be3
GKH		 1809
1810 if(last && !priv->rx_skb_complete){
c8d86be3
GKH		 1811 if(priv->rx_skb->len > 4)
1812 skb_trim(priv->rx_skb,priv->rx_skb->len-4);
c8d86be3
GKH		 1813#ifndef RX_DONT_PASS_UL
1814 if(!ieee80211_rx(priv->ieee80211,
1815 priv->rx_skb, &stats)){
c8d86be3
GKH		 1816#endif // RX_DONT_PASS_UL
1817
1818 dev_kfree_skb_any(priv->rx_skb);
1819#ifndef RX_DONT_PASS_UL
1820 }
c8d86be3
GKH		 1821#endif
1822 priv->rx_skb_complete=1;
1823 }
1824
1825#endif //DUMMY_RX
c8d86be3
GKH		 1826 pci_dma_sync_single_for_device(priv->pdev,
1827 priv->rxbuffer->dma,
1828 priv->rxbuffersize * \
1829 sizeof(u8),
1830 PCI_DMA_FROMDEVICE);
1831
bbc9a991 1832drop: // this is used when we have not enough mem
c8d86be3
GKH		 1833 /* restore the descriptor */
1834 *(priv->rxringtail+2)=priv->rxbuffer->dma;
1835 *(priv->rxringtail)=*(priv->rxringtail) &~ 0xfff;
1836 *(priv->rxringtail)=
1837 *(priv->rxringtail) | priv->rxbuffersize;
1838
1839 *(priv->rxringtail)=
1840 *(priv->rxringtail) | (1<<31);
c8d86be3
GKH		 1841
1842 priv->rxringtail+=rx_desc_size;
1843 if(priv->rxringtail >=
1844 (priv->rxring)+(priv->rxringcount )*rx_desc_size)
1845 priv->rxringtail=priv->rxring;
1846
c8d86be3 1847 priv->rxbuffer=(priv->rxbuffer->next);
c8d86be3 1848 }
c8d86be3
GKH		 1849}
1850
1851
1852void rtl8180_dma_kick(struct net_device *dev, int priority)
1853{
1854 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1855
1856 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1857 write_nic_byte(dev, TX_DMA_POLLING,
1858 (1 << (priority + 1)) | priv->dma_poll_mask);
1859 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1860
1861 force_pci_posting(dev);
1862}
1863
c8d86be3
GKH		 1864void rtl8180_data_hard_stop(struct net_device *dev)
1865{
1866 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1867
1868 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1869 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ;
1870 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1871 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1872}
1873
c8d86be3
GKH		 1874void rtl8180_data_hard_resume(struct net_device *dev)
1875{
1876 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1877
1878 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1879 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ);
1880 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1881 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1882}
1883
c8d86be3
GKH		 1884/* this function TX data frames when the ieee80211 stack requires this.
1885 * It checks also if we need to stop the ieee tx queue, eventually do it
1886 */
1887void rtl8180_hard_data_xmit(struct sk_buff *skb,struct net_device *dev, int
1888rate)
1889{
1890 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1891 int mode;
1892 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data;
1893 short morefrag = (h->frame_ctl) & IEEE80211_FCTL_MOREFRAGS;
1894 unsigned long flags;
1895 int priority;
c8d86be3
GKH		 1896
1897 mode = priv->ieee80211->iw_mode;
1898
1899 rate = ieeerate2rtlrate(rate);
1900 /*
1901 * This function doesn't require lock because we make
1902 * sure it's called with the tx_lock already acquired.
bbc9a991
AGR		 1903 * this come from the kernel's hard_xmit callback (through
1904 * the ieee stack, or from the try_wake_queue (again through
c8d86be3
GKH		 1905 * the ieee stack.
1906 */
c8d86be3 1907 priority = AC2Q(skb->priority);
c8d86be3
GKH		 1908 spin_lock_irqsave(&priv->tx_lock,flags);
1909
1910 if(priv->ieee80211->bHwRadioOff)
1911 {
1912 spin_unlock_irqrestore(&priv->tx_lock,flags);
1913
1914 return;
1915 }
1916
c8d86be3 1917 if (!check_nic_enought_desc(dev, priority)){
c8d86be3
GKH		 1918 DMESGW("Error: no descriptor left by previous TX (avail %d) ",
1919 get_curr_tx_free_desc(dev, priority));
c8d86be3
GKH		 1920 ieee80211_stop_queue(priv->ieee80211);
1921 }
1922 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag,0,rate);
1923 if (!check_nic_enought_desc(dev, priority))
1924 ieee80211_stop_queue(priv->ieee80211);
1925
c8d86be3 1926 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3
GKH		 1927}
1928
1929/* This is a rough attempt to TX a frame
1930 * This is called by the ieee 80211 stack to TX management frames.
1931 * If the ring is full packet are dropped (for data frame the queue
1932 * is stopped before this can happen). For this reason it is better
1933 * if the descriptors are larger than the largest management frame
1934 * we intend to TX: i'm unsure what the HW does if it will not found
1935 * the last fragment of a frame because it has been dropped...
1936 * Since queues for Management and Data frames are different we
1937 * might use a different lock than tx_lock (for example mgmt_tx_lock)
1938 */
1939/* these function may loops if invoked with 0 descriptors or 0 len buffer*/
1940int rtl8180_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
1941{
1942 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 1943 unsigned long flags;
c8d86be3
GKH		 1944 int priority;
1945
c8d86be3 1946 priority = MANAGE_PRIORITY;
c8d86be3
GKH		 1947
1948 spin_lock_irqsave(&priv->tx_lock,flags);
1949
fd882783 1950 if (priv->ieee80211->bHwRadioOff) {
c8d86be3 1951 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3 1952 dev_kfree_skb_any(skb);
ec634fe3 1953 return NETDEV_TX_OK;
c8d86be3
GKH		 1954 }
1955
1956 rtl8180_tx(dev, skb->data, skb->len, priority,
1957 0, 0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
1958
1959 priv->ieee80211->stats.tx_bytes+=skb->len;
1960 priv->ieee80211->stats.tx_packets++;
1961 spin_unlock_irqrestore(&priv->tx_lock,flags);
1962
1963 dev_kfree_skb_any(skb);
ec634fe3 1964 return NETDEV_TX_OK;
c8d86be3
GKH		 1965}
1966
1967// longpre 144+48 shortpre 72+24
1968u16 rtl8180_len2duration(u32 len, short rate,short* ext)
1969{
1970 u16 duration;
1971 u16 drift;
1972 *ext=0;
1973
1974 switch(rate){
1975 case 0://1mbps
1976 *ext=0;
1977 duration = ((len+4)<<4) /0x2;
1978 drift = ((len+4)<<4) % 0x2;
1979 if(drift ==0 ) break;
1980 duration++;
1981 break;
c8d86be3
GKH		 1982 case 1://2mbps
1983 *ext=0;
1984 duration = ((len+4)<<4) /0x4;
1985 drift = ((len+4)<<4) % 0x4;
1986 if(drift ==0 ) break;
1987 duration++;
1988 break;
c8d86be3
GKH		 1989 case 2: //5.5mbps
1990 *ext=0;
1991 duration = ((len+4)<<4) /0xb;
1992 drift = ((len+4)<<4) % 0xb;
1993 if(drift ==0 )
1994 break;
1995 duration++;
1996 break;
c8d86be3
GKH		 1997 default:
1998 case 3://11mbps
1999 *ext=0;
2000 duration = ((len+4)<<4) /0x16;
2001 drift = ((len+4)<<4) % 0x16;
2002 if(drift ==0 )
2003 break;
2004 duration++;
2005 if(drift > 6)
2006 break;
2007 *ext=1;
2008 break;
2009 }
2010
2011 return duration;
2012}
2013
c8d86be3
GKH		 2014void rtl8180_prepare_beacon(struct net_device *dev)
2015{
c8d86be3 2016 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 2017 struct sk_buff *skb;
2018
2019 u16 word = read_nic_word(dev, BcnItv);
2020 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
2021 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval);//0x64;
2022 write_nic_word(dev, BcnItv, word);
2023
c8d86be3
GKH		 2024 skb = ieee80211_get_beacon(priv->ieee80211);
2025 if(skb){
2026 rtl8180_tx(dev,skb->data,skb->len,BEACON_PRIORITY,
2027 0,0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
2028 dev_kfree_skb_any(skb);
2029 }
c8d86be3
GKH		 2030}
2031
2032/* This function do the real dirty work: it enqueues a TX command
2033 * descriptor in the ring buffer, copyes the frame in a TX buffer
2034 * and kicks the NIC to ensure it does the DMA transfer.
2035 */
2036short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority,
2037 short morefrag, short descfrag, int rate)
2038{
2039 struct r8180_priv *priv = ieee80211_priv(dev);
2040 u32 *tail,*temp_tail;
2041 u32 *begin;
2042 u32 *buf;
2043 int i;
2044 int remain;
2045 int buflen;
2046 int count;
c8d86be3
GKH		 2047 u16 duration;
2048 short ext;
2049 struct buffer* buflist;
c8d86be3
GKH		 2050 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf;
2051 u8 dest[ETH_ALEN];
2052 u8 bUseShortPreamble = 0;
2053 u8 bCTSEnable = 0;
2054 u8 bRTSEnable = 0;
c8d86be3
GKH		 2055 u16 Duration = 0;
2056 u16 RtsDur = 0;
2057 u16 ThisFrameTime = 0;
2058 u16 TxDescDuration = 0;
2059 u8 ownbit_flag = false; //added by david woo for sync Tx, 2007.12.14
c8d86be3
GKH		 2060
2061 switch(priority) {
2062 case MANAGE_PRIORITY:
2063 tail=priv->txmapringtail;
2064 begin=priv->txmapring;
2065 buflist = priv->txmapbufstail;
2066 count = priv->txringcount;
2067 break;
c8d86be3
GKH		 2068 case BK_PRIORITY:
2069 tail=priv->txbkpringtail;
2070 begin=priv->txbkpring;
2071 buflist = priv->txbkpbufstail;
2072 count = priv->txringcount;
2073 break;
c8d86be3
GKH		 2074 case BE_PRIORITY:
2075 tail=priv->txbepringtail;
2076 begin=priv->txbepring;
2077 buflist = priv->txbepbufstail;
2078 count = priv->txringcount;
2079 break;
c8d86be3
GKH		 2080 case VI_PRIORITY:
2081 tail=priv->txvipringtail;
2082 begin=priv->txvipring;
2083 buflist = priv->txvipbufstail;
2084 count = priv->txringcount;
2085 break;
c8d86be3
GKH		 2086 case VO_PRIORITY:
2087 tail=priv->txvopringtail;
2088 begin=priv->txvopring;
2089 buflist = priv->txvopbufstail;
2090 count = priv->txringcount;
2091 break;
c8d86be3
GKH		 2092 case HI_PRIORITY:
2093 tail=priv->txhpringtail;
2094 begin=priv->txhpring;
2095 buflist = priv->txhpbufstail;
2096 count = priv->txringcount;
2097 break;
c8d86be3
GKH		 2098 case BEACON_PRIORITY:
2099 tail=priv->txbeaconringtail;
2100 begin=priv->txbeaconring;
2101 buflist = priv->txbeaconbufstail;
2102 count = priv->txbeaconcount;
2103 break;
c8d86be3
GKH		 2104 default:
2105 return -1;
2106 break;
2107 }
2108
c8d86be3
GKH		 2109 memcpy(&dest, frag_hdr->addr1, ETH_ALEN);
2110 if (is_multicast_ether_addr(dest) ||
2111 is_broadcast_ether_addr(dest))
2112 {
2113 Duration = 0;
2114 RtsDur = 0;
2115 bRTSEnable = 0;
2116 bCTSEnable = 0;
2117
2118 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2119 TxDescDuration = ThisFrameTime;
2120 } else {// Unicast packet
c8d86be3
GKH		 2121 u16 AckTime;
2122
2123 //YJ,add,080828,for Keep alive
2124 priv->NumTxUnicast++;
2125
2126 // Figure out ACK rate according to BSS basic rate and Tx rate, 2006.03.08 by rcnjko.
c8d86be3 2127 AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
c8d86be3
GKH		 2128
2129 if ( ((len + sCrcLng) > priv->rts) && priv->rts )
2130 { // RTS/CTS.
2131 u16 RtsTime, CtsTime;
2132 //u16 CtsRate;
2133 bRTSEnable = 1;
2134 bCTSEnable = 0;
2135
2136 // Rate and time required for RTS.
2137 RtsTime = ComputeTxTime( sAckCtsLng/8,priv->ieee80211->basic_rate, 0, 0);
2138 // Rate and time required for CTS.
2139 CtsTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
2140
2141 // Figure out time required to transmit this frame.
2142 ThisFrameTime = ComputeTxTime(len + sCrcLng,
2143 rtl8180_rate2rate(rate),
2144 0,
2145 bUseShortPreamble);
2146
2147 // RTS-CTS-ThisFrame-ACK.
2148 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime;
2149
2150 TxDescDuration = RtsTime + RtsDur;
2151 }
2152 else {// Normal case.
2153 bCTSEnable = 0;
2154 bRTSEnable = 0;
2155 RtsDur = 0;
2156
2157 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2158 TxDescDuration = ThisFrameTime + aSifsTime + AckTime;
2159 }
2160
2161 if(!(frag_hdr->frame_ctl & IEEE80211_FCTL_MOREFRAGS)) { //no more fragment
2162 // ThisFrame-ACK.
2163 Duration = aSifsTime + AckTime;
2164 } else { // One or more fragments remained.
2165 u16 NextFragTime;
2166 NextFragTime = ComputeTxTime( len + sCrcLng, //pretend following packet length equal current packet
2167 rtl8180_rate2rate(rate),
2168 0,
2169 bUseShortPreamble );
2170
2171 //ThisFrag-ACk-NextFrag-ACK.
2172 Duration = NextFragTime + 3*aSifsTime + 2*AckTime;
2173 }
2174
2175 } // End of Unicast packet
2176
2177 frag_hdr->duration_id = Duration;
c8d86be3
GKH		 2178
2179 buflen=priv->txbuffsize;
2180 remain=len;
2181 temp_tail = tail;
fd882783 2182
c8d86be3 2183 while(remain!=0){
c8d86be3
GKH		 2184 mb();
2185 if(!buflist){
2186 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority);
c8d86be3
GKH		 2187 return -1;
2188 }
2189 buf=buflist->buf;
2190
fd882783
BZ		 2191 if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) {
2192 DMESGW("No more TX desc, returning %x of %x",
2193 remain, len);
2194 priv->stats.txrdu++;
c8d86be3 2195 return remain;
c8d86be3
GKH		 2196 }
2197
2198 *tail= 0; // zeroes header
2199 *(tail+1) = 0;
2200 *(tail+3) = 0;
2201 *(tail+5) = 0;
2202 *(tail+6) = 0;
2203 *(tail+7) = 0;
2204
d44eb889
LF		 2205 /*FIXME: this should be triggered by HW encryption parameters.*/
2206 *tail |= (1<<15); /* no encrypt */
fd882783 2207
c8d86be3
GKH		 2208 if(remain==len && !descfrag) {
2209 ownbit_flag = false; //added by david woo,2007.12.14
c8d86be3
GKH		 2210 *tail = *tail| (1<<29) ; //fist segment of the packet
2211 *tail = *tail |(len);
2212 } else {
2213 ownbit_flag = true;
2214 }
2215
2216 for(i=0;i<buflen&& remain >0;i++,remain--){
2217 ((u8*)buf)[i]=txbuf[i]; //copy data into descriptor pointed DMAble buffer
2218 if(remain == 4 && i+4 >= buflen) break;
2219 /* ensure the last desc has at least 4 bytes payload */
2220
2221 }
2222 txbuf = txbuf + i;
2223 *(tail+3)=*(tail+3) &~ 0xfff;
2224 *(tail+3)=*(tail+3) | i; // buffer lenght
2225 // Use short preamble or not
2226 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE)
2227 if (priv->plcp_preamble_mode==1 && rate!=0) // short mode now, not long!
b3184e1e 2228 ;// *tail |= (1<<16); // enable short preamble mode.
c8d86be3 2229
c8d86be3
GKH		 2230 if(bCTSEnable) {
2231 *tail |= (1<<18);
2232 }
2233
2234 if(bRTSEnable) //rts enable
2235 {
2236 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE
2237 *tail |= (1<<23);//rts enable
2238 *(tail+1) |=(RtsDur&0xffff);//RTS Duration
2239 }
2240 *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION
2241// *(tail+3) |= (0xe6<<16);
2242 *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ;
c8d86be3
GKH		 2243
2244 *tail = *tail | ((rate&0xf) << 24);
c8d86be3
GKH		 2245
2246 /* hw_plcp_len is not used for rtl8180 chip */
2247 /* FIXME */
d44eb889 2248 if (!priv->hw_plcp_len) {
fd882783 2249 duration = rtl8180_len2duration(len, rate, &ext);
c8d86be3
GKH		 2250 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16);
2251 if(ext) *(tail+1) = *(tail+1) |(1<<31); //plcp length extension
2252 }
2253
2254 if(morefrag) *tail = (*tail) | (1<<17); // more fragment
2255 if(!remain) *tail = (*tail) | (1<<28); // last segment of frame
2256
c8d86be3
GKH		 2257 *(tail+5) = *(tail+5)|(2<<27);
2258 *(tail+7) = *(tail+7)|(1<<4);
2259
2260 wmb();
2261 if(ownbit_flag)
2262 {
2263 *tail = *tail | (1<<31); // descriptor ready to be txed
2264 }
2265
c8d86be3
GKH		 2266 if((tail - begin)/8 == count-1)
2267 tail=begin;
c8d86be3
GKH		 2268 else
2269 tail=tail+8;
2270
2271 buflist=buflist->next;
2272
2273 mb();
2274
2275 switch(priority) {
2276 case MANAGE_PRIORITY:
2277 priv->txmapringtail=tail;
2278 priv->txmapbufstail=buflist;
2279 break;
c8d86be3
GKH		 2280 case BK_PRIORITY:
2281 priv->txbkpringtail=tail;
2282 priv->txbkpbufstail=buflist;
2283 break;
c8d86be3
GKH		 2284 case BE_PRIORITY:
2285 priv->txbepringtail=tail;
2286 priv->txbepbufstail=buflist;
2287 break;
c8d86be3
GKH		 2288 case VI_PRIORITY:
2289 priv->txvipringtail=tail;
2290 priv->txvipbufstail=buflist;
2291 break;
c8d86be3
GKH		 2292 case VO_PRIORITY:
2293 priv->txvopringtail=tail;
2294 priv->txvopbufstail=buflist;
2295 break;
c8d86be3
GKH		 2296 case HI_PRIORITY:
2297 priv->txhpringtail=tail;
2298 priv->txhpbufstail = buflist;
2299 break;
c8d86be3
GKH		 2300 case BEACON_PRIORITY:
2301 /* the HW seems to be happy with the 1st
2302 * descriptor filled and the 2nd empty...
2303 * So always update descriptor 1 and never
2304 * touch 2nd
2305 */
c8d86be3 2306 break;
c8d86be3 2307 }
c8d86be3
GKH		 2308 }
2309 *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed
2310 rtl8180_dma_kick(dev,priority);
c8d86be3
GKH		 2311
2312 return 0;
c8d86be3
GKH		 2313}
2314
c8d86be3
GKH		 2315void rtl8180_irq_rx_tasklet(struct r8180_priv * priv);
2316
c8d86be3
GKH		 2317void rtl8180_link_change(struct net_device *dev)
2318{
2319 struct r8180_priv *priv = ieee80211_priv(dev);
2320 u16 beacon_interval;
c8d86be3 2321 struct ieee80211_network *net = &priv->ieee80211->current_network;
c8d86be3 2322
fd882783 2323 rtl8180_update_msr(dev);
c8d86be3
GKH		 2324
2325 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2326
2327 write_nic_dword(dev,BSSID,((u32*)net->bssid)[0]);
2328 write_nic_word(dev,BSSID+4,((u16*)net->bssid)[2]);
2329
c8d86be3
GKH		 2330 beacon_interval = read_nic_dword(dev,BEACON_INTERVAL);
2331 beacon_interval &= ~ BEACON_INTERVAL_MASK;
2332 beacon_interval |= net->beacon_interval;
2333 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval);
2334
2335 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
2336
d44eb889 2337 rtl8180_set_chan(dev, priv->chan);
c8d86be3
GKH		 2338}
2339
2340void rtl8180_rq_tx_ack(struct net_device *dev){
2341
2342 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 2343
c8d86be3
GKH		 2344 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)|CONFIG4_PWRMGT);
2345 priv->ack_tx_to_ieee = 1;
2346}
2347
2348short rtl8180_is_tx_queue_empty(struct net_device *dev){
2349
2350 struct r8180_priv *priv = ieee80211_priv(dev);
2351 u32* d;
2352
2353 for (d = priv->txmapring;
2354 d < priv->txmapring + priv->txringcount;d+=8)
2355 if(*d & (1<<31)) return 0;
2356
2357 for (d = priv->txbkpring;
2358 d < priv->txbkpring + priv->txringcount;d+=8)
2359 if(*d & (1<<31)) return 0;
2360
2361 for (d = priv->txbepring;
2362 d < priv->txbepring + priv->txringcount;d+=8)
2363 if(*d & (1<<31)) return 0;
2364
2365 for (d = priv->txvipring;
2366 d < priv->txvipring + priv->txringcount;d+=8)
2367 if(*d & (1<<31)) return 0;
2368
2369 for (d = priv->txvopring;
2370 d < priv->txvopring + priv->txringcount;d+=8)
2371 if(*d & (1<<31)) return 0;
2372
2373 for (d = priv->txhpring;
2374 d < priv->txhpring + priv->txringcount;d+=8)
2375 if(*d & (1<<31)) return 0;
2376 return 1;
2377}
2378/* FIXME FIXME 5msecs is random */
2379#define HW_WAKE_DELAY 5
2380
2381void rtl8180_hw_wakeup(struct net_device *dev)
2382{
2383 unsigned long flags;
c8d86be3
GKH		 2384 struct r8180_priv *priv = ieee80211_priv(dev);
2385
2386 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3 2387 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)&~CONFIG4_PWRMGT);
fd882783 2388 if (priv->rf_wakeup)
c8d86be3 2389 priv->rf_wakeup(dev);
c8d86be3
GKH		 2390 spin_unlock_irqrestore(&priv->ps_lock,flags);
2391}
2392
2393void rtl8180_hw_sleep_down(struct net_device *dev)
2394{
2395 unsigned long flags;
c8d86be3
GKH		 2396 struct r8180_priv *priv = ieee80211_priv(dev);
2397
2398 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3
GKH		 2399 if(priv->rf_sleep)
2400 priv->rf_sleep(dev);
2401 spin_unlock_irqrestore(&priv->ps_lock,flags);
2402}
2403
c8d86be3
GKH		 2404void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl)
2405{
c8d86be3 2406 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 2407 u32 rb = jiffies;
2408 unsigned long flags;
2409
2410 spin_lock_irqsave(&priv->ps_lock,flags);
2411
2412 /* Writing HW register with 0 equals to disable
2413 * the timer, that is not really what we want
2414 */
2415 tl -= MSECS(4+16+7);
2416
c8d86be3
GKH		 2417 /* If the interval in witch we are requested to sleep is too
2418 * short then give up and remain awake
2419 */
2420 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
2421 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
2422 spin_unlock_irqrestore(&priv->ps_lock,flags);
2423 printk("too short to sleep\n");
2424 return;
2425 }
2426
c8d86be3
GKH		 2427 {
2428 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
c8d86be3 2429
c8d86be3
GKH		 2430 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp);
2431
2432 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
2433 }
2434 /* if we suspect the TimerInt is gone beyond tl
2435 * while setting it, then give up
2436 */
fd882783 2437
c8d86be3
GKH		 2438 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
2439 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
2440 spin_unlock_irqrestore(&priv->ps_lock,flags);
2441 return;
2442 }
c8d86be3
GKH		 2443
2444 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq);
2445 spin_unlock_irqrestore(&priv->ps_lock,flags);
2446}
2447
c8d86be3
GKH		 2448void rtl8180_wmm_param_update(struct work_struct * work)
2449{
2450 struct ieee80211_device * ieee = container_of(work, struct ieee80211_device,wmm_param_update_wq);
c8d86be3 2451 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 2452 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param);
2453 u8 mode = ieee->current_network.mode;
2454 AC_CODING eACI;
2455 AC_PARAM AcParam;
2456 PAC_PARAM pAcParam;
2457 u8 i;
2458
c8d86be3
GKH		 2459 if(!ieee->current_network.QoS_Enable){
2460 //legacy ac_xx_param update
2461 AcParam.longData = 0;
2462 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2463 AcParam.f.AciAifsn.f.ACM = 0;
2464 AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin.
2465 AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax.
2466 AcParam.f.TXOPLimit = 0;
2467 for(eACI = 0; eACI < AC_MAX; eACI++){
2468 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2469 {
2470 u8 u1bAIFS;
2471 u32 u4bAcParam;
2472 pAcParam = (PAC_PARAM)(&AcParam);
2473 // Retrive paramters to udpate.
2474 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN *(((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2475 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)|
2476 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)|
2477 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)|
2478 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2479 switch(eACI){
2480 case AC1_BK:
2481 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2482 break;
c8d86be3
GKH		 2483 case AC0_BE:
2484 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2485 break;
c8d86be3
GKH		 2486 case AC2_VI:
2487 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2488 break;
c8d86be3
GKH		 2489 case AC3_VO:
2490 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2491 break;
c8d86be3
GKH		 2492 default:
2493 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI);
2494 break;
2495 }
2496 }
2497 }
2498 return;
2499 }
2500
2501 for(i = 0; i < AC_MAX; i++){
2502 //AcParam.longData = 0;
2503 pAcParam = (AC_PARAM * )ac_param;
2504 {
2505 AC_CODING eACI;
2506 u8 u1bAIFS;
2507 u32 u4bAcParam;
2508
2509 // Retrive paramters to udpate.
2510 eACI = pAcParam->f.AciAifsn.f.ACI;
2511 //Mode G/A: slotTimeTimer = 9; Mode B: 20
2512 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2513 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2514 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2515 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2516 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2517
2518 switch(eACI){
2519 case AC1_BK:
2520 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2521 break;
c8d86be3
GKH		 2522 case AC0_BE:
2523 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2524 break;
c8d86be3
GKH		 2525 case AC2_VI:
2526 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2527 break;
c8d86be3
GKH		 2528 case AC3_VO:
2529 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2530 break;
c8d86be3
GKH		 2531 default:
2532 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2533 break;
2534 }
2535 }
2536 ac_param += (sizeof(AC_PARAM));
2537 }
c8d86be3
GKH		 2538}
2539
c8d86be3 2540void rtl8180_tx_irq_wq(struct work_struct *work);
c8d86be3
GKH		 2541void rtl8180_restart_wq(struct work_struct *work);
2542//void rtl8180_rq_tx_ack(struct work_struct *work);
c8d86be3 2543void rtl8180_watch_dog_wq(struct work_struct *work);
c8d86be3 2544void rtl8180_hw_wakeup_wq(struct work_struct *work);
c8d86be3 2545void rtl8180_hw_sleep_wq(struct work_struct *work);
c8d86be3 2546void rtl8180_sw_antenna_wq(struct work_struct *work);
0370453f
BZ		 2547void rtl8180_watch_dog(struct net_device *dev);
2548
c8d86be3
GKH		 2549void watch_dog_adaptive(unsigned long data)
2550{
fd882783
BZ		 2551 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data);
2552
2553 if (!priv->up) {
c8d86be3
GKH		 2554 DMESG("<----watch_dog_adaptive():driver is not up!\n");
2555 return;
2556 }
2557
c8d86be3
GKH		 2558 // Tx High Power Mechanism.
2559#ifdef HIGH_POWER
2560 if(CheckHighPower((struct net_device *)data))
2561 {
2562 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq);
2563 }
2564#endif
2565
c8d86be3
GKH		 2566 // Tx Power Tracking on 87SE.
2567#ifdef TX_TRACK
2568 //if( priv->bTxPowerTrack ) //lzm mod 080826
2569 if( CheckTxPwrTracking((struct net_device *)data));
2570 TxPwrTracking87SE((struct net_device *)data);
c8d86be3
GKH		 2571#endif
2572
2573 // Perform DIG immediately.
2574#ifdef SW_DIG
2575 if(CheckDig((struct net_device *)data) == true)
2576 {
2577 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq);
2578 }
2579#endif
c8d86be3
GKH		 2580 rtl8180_watch_dog((struct net_device *)data);
2581
c8d86be3
GKH		 2582 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem);
2583
2584 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
2585 add_timer(&priv->watch_dog_timer);
c8d86be3
GKH		 2586}
2587
c8d86be3
GKH		 2588static CHANNEL_LIST ChannelPlan[] = {
2589 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC
2590 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
2591 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
2592 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI.
2593 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI.
2594 {{14,36,40,44,48,52,56,60,64},9}, //MKK
2595 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1
2596 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel.
2597 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC
2598 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
2599 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826
2600};
2601
2602static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee)
2603{
2604 int i;
2605
2606 //lzm add 080826
2607 ieee->MinPassiveChnlNum=MAX_CHANNEL_NUMBER+1;
2608 ieee->IbssStartChnl=0;
2609
2610 switch (channel_plan)
2611 {
2612 case COUNTRY_CODE_FCC:
2613 case COUNTRY_CODE_IC:
2614 case COUNTRY_CODE_ETSI:
2615 case COUNTRY_CODE_SPAIN:
2616 case COUNTRY_CODE_FRANCE:
2617 case COUNTRY_CODE_MKK:
2618 case COUNTRY_CODE_MKK1:
2619 case COUNTRY_CODE_ISRAEL:
2620 case COUNTRY_CODE_TELEC:
2621 {
2622 Dot11d_Init(ieee);
2623 ieee->bGlobalDomain = false;
2624 if (ChannelPlan[channel_plan].Len != 0){
2625 // Clear old channel map
2626 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2627 // Set new channel map
2628 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
2629 {
2630 if(ChannelPlan[channel_plan].Channel[i] <= 14)
2631 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
2632 }
2633 }
2634 break;
2635 }
2636 case COUNTRY_CODE_GLOBAL_DOMAIN:
2637 {
2638 GET_DOT11D_INFO(ieee)->bEnabled = 0;
2639 Dot11d_Reset(ieee);
2640 ieee->bGlobalDomain = true;
2641 break;
2642 }
2643 case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826
2644 {
2645 ieee->MinPassiveChnlNum=12;
2646 ieee->IbssStartChnl= 10;
2647 break;
2648 }
2649 default:
2650 {
2651 Dot11d_Init(ieee);
2652 ieee->bGlobalDomain = false;
2653 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2654 for (i=1;i<=14;i++)
2655 {
2656 GET_DOT11D_INFO(ieee)->channel_map[i] = 1;
2657 }
2658 break;
2659 }
2660 }
2661}
c8d86be3 2662
c8d86be3 2663void GPIOChangeRFWorkItemCallBack(struct work_struct *work);
c8d86be3
GKH		 2664
2665//YJ,add,080828
2666static void rtl8180_statistics_init(struct Stats *pstats)
2667{
2668 memset(pstats, 0, sizeof(struct Stats));
2669}
fd882783 2670
c8d86be3
GKH		 2671static void rtl8180_link_detect_init(plink_detect_t plink_detect)
2672{
2673 memset(plink_detect, 0, sizeof(link_detect_t));
2674 plink_detect->SlotNum = DEFAULT_SLOT_NUM;
2675}
2676//YJ,add,080828,end
2677
2678short rtl8180_init(struct net_device *dev)
2679{
2680 struct r8180_priv *priv = ieee80211_priv(dev);
2681 u16 word;
2682 u16 version;
c8d86be3
GKH		 2683 u32 usValue;
2684 u16 tmpu16;
2685 int i, j;
2686
c8d86be3
GKH		 2687 priv->channel_plan = eprom_read(dev, EEPROM_COUNTRY_CODE>>1) & 0xFF;
2688 if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){
2689 printk("rtl8180_init:Error channel plan! Set to default.\n");
2690 priv->channel_plan = 0;
2691 }
c8d86be3
GKH		 2692
2693 DMESG("Channel plan is %d\n",priv->channel_plan);
2694 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211);
c8d86be3 2695
c8d86be3
GKH		 2696 //FIXME: these constants are placed in a bad pleace.
2697 priv->txbuffsize = 2048;//1024;
2698 priv->txringcount = 32;//32;
2699 priv->rxbuffersize = 2048;//1024;
2700 priv->rxringcount = 64;//32;
2701 priv->txbeaconcount = 2;
2702 priv->rx_skb_complete = 1;
c8d86be3 2703
c8d86be3 2704 priv->RegThreeWireMode = HW_THREE_WIRE_SI;
c8d86be3 2705
c8d86be3
GKH		 2706 priv->RFChangeInProgress = false;
2707 priv->SetRFPowerStateInProgress = false;
2708 priv->RFProgType = 0;
2709 priv->bInHctTest = false;
2710
2711 priv->irq_enabled=0;
2712
c8d86be3
GKH		 2713 rtl8180_statistics_init(&priv->stats);
2714 rtl8180_link_detect_init(&priv->link_detect);
c8d86be3
GKH		 2715
2716 priv->ack_tx_to_ieee = 0;
2717 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
2718 priv->ieee80211->iw_mode = IW_MODE_INFRA;
2719 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
2720 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2721 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2722 priv->ieee80211->active_scan = 1;
2723 priv->ieee80211->rate = 110; //11 mbps
2724 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION;
2725 priv->ieee80211->host_encrypt = 1;
2726 priv->ieee80211->host_decrypt = 1;
2727 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup;
2728 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack;
2729 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep;
2730 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty;
2731
2732 priv->hw_wep = hwwep;
2733 priv->prism_hdr=0;
2734 priv->dev=dev;
2735 priv->retry_rts = DEFAULT_RETRY_RTS;
2736 priv->retry_data = DEFAULT_RETRY_DATA;
2737 priv->RFChangeInProgress = false;
2738 priv->SetRFPowerStateInProgress = false;
2739 priv->RFProgType = 0;
2740 priv->bInHctTest = false;
2741 priv->bInactivePs = true;//false;
2742 priv->ieee80211->bInactivePs = priv->bInactivePs;
2743 priv->bSwRfProcessing = false;
2744 priv->eRFPowerState = eRfOff;
2745 priv->RfOffReason = 0;
2746 priv->LedStrategy = SW_LED_MODE0;
c8d86be3
GKH		 2747 priv->TxPollingTimes = 0;//lzm add 080826
2748 priv->bLeisurePs = true;
2749 priv->dot11PowerSaveMode = eActive;
2750//by amy for antenna
2751 priv->AdMinCheckPeriod = 5;
2752 priv->AdMaxCheckPeriod = 10;
2753// Lower signal strength threshold to fit the HW participation in antenna diversity. +by amy 080312
2754 priv->AdMaxRxSsThreshold = 30;//60->30
2755 priv->AdRxSsThreshold = 20;//50->20
2756 priv->AdCheckPeriod = priv->AdMinCheckPeriod;
2757 priv->AdTickCount = 0;
2758 priv->AdRxSignalStrength = -1;
2759 priv->RegSwAntennaDiversityMechanism = 0;
2760 priv->RegDefaultAntenna = 0;
2761 priv->SignalStrength = 0;
2762 priv->AdRxOkCnt = 0;
2763 priv->CurrAntennaIndex = 0;
2764 priv->AdRxSsBeforeSwitched = 0;
2765 init_timer(&priv->SwAntennaDiversityTimer);
2766 priv->SwAntennaDiversityTimer.data = (unsigned long)dev;
2767 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback;
2768//by amy for antenna
2769//{by amy 080312
2770 priv->bDigMechanism = 1;
2771 priv->InitialGain = 6;
2772 priv->bXtalCalibration = false;
2773 priv->XtalCal_Xin = 0;
2774 priv->XtalCal_Xout = 0;
2775 priv->bTxPowerTrack = false;
2776 priv->ThermalMeter = 0;
2777 priv->FalseAlarmRegValue = 0;
2778 priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG.
2779 priv->DIG_NumberFallbackVote = 0;
2780 priv->DIG_NumberUpgradeVote = 0;
2781 priv->LastSignalStrengthInPercent = 0;
2782 priv->Stats_SignalStrength = 0;
2783 priv->LastRxPktAntenna = 0;
2784 priv->SignalQuality = 0; // in 0-100 index.
2785 priv->Stats_SignalQuality = 0;
2786 priv->RecvSignalPower = 0; // in dBm.
2787 priv->Stats_RecvSignalPower = 0;
2788 priv->AdMainAntennaRxOkCnt = 0;
2789 priv->AdAuxAntennaRxOkCnt = 0;
2790 priv->bHWAdSwitched = false;
2791 priv->bRegHighPowerMechanism = true;
2792 priv->RegHiPwrUpperTh = 77;
2793 priv->RegHiPwrLowerTh = 75;
2794 priv->RegRSSIHiPwrUpperTh = 70;
2795 priv->RegRSSIHiPwrLowerTh = 20;
2796 priv->bCurCCKPkt = false;
2797 priv->UndecoratedSmoothedSS = -1;
2798 priv->bToUpdateTxPwr = false;
2799 priv->CurCCKRSSI = 0;
2800 priv->RxPower = 0;
2801 priv->RSSI = 0;
c8d86be3
GKH		 2802 priv->NumTxOkTotal = 0;
2803 priv->NumTxUnicast = 0;
2804 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL;
2805 priv->PowerProfile = POWER_PROFILE_AC;
c8d86be3
GKH		 2806 priv->CurrRetryCnt=0;
2807 priv->LastRetryCnt=0;
2808 priv->LastTxokCnt=0;
2809 priv->LastRxokCnt=0;
2810 priv->LastRetryRate=0;
2811 priv->bTryuping=0;
2812 priv->CurrTxRate=0;
2813 priv->CurrRetryRate=0;
2814 priv->TryupingCount=0;
2815 priv->TryupingCountNoData=0;
2816 priv->TryDownCountLowData=0;
2817 priv->LastTxOKBytes=0;
2818 priv->LastFailTxRate=0;
2819 priv->LastFailTxRateSS=0;
2820 priv->FailTxRateCount=0;
2821 priv->LastTxThroughput=0;
2822 priv->NumTxOkBytesTotal=0;
2823 priv->ForcedDataRate = 0;
2824 priv->RegBModeGainStage = 1;
2825
c8d86be3
GKH		 2826 priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
2827 spin_lock_init(&priv->irq_lock);
2828 spin_lock_init(&priv->irq_th_lock);
2829 spin_lock_init(&priv->tx_lock);
2830 spin_lock_init(&priv->ps_lock);
2831 spin_lock_init(&priv->rf_ps_lock);
2832 sema_init(&priv->wx_sem,1);
2833 sema_init(&priv->rf_state,1);
c8d86be3
GKH		 2834 INIT_WORK(&priv->reset_wq,(void*) rtl8180_restart_wq);
2835 INIT_WORK(&priv->tx_irq_wq,(void*) rtl8180_tx_irq_wq);
2836 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8180_hw_wakeup_wq);
2837 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8180_hw_sleep_wq);
c8d86be3
GKH		 2838 INIT_WORK(&priv->ieee80211->wmm_param_update_wq,(void*) rtl8180_wmm_param_update);
2839 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,(void*)rtl8180_rate_adapter);//+by amy 080312
2840 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,(void*)rtl8180_hw_dig_wq);//+by amy 080312
2841 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,(void*)rtl8180_tx_pw_wq);//+by amy 080312
2842
c8d86be3 2843 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,(void*) GPIOChangeRFWorkItemCallBack);
c8d86be3
GKH		 2844
2845 tasklet_init(&priv->irq_rx_tasklet,
2846 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet,
2847 (unsigned long)priv);
fd882783 2848
c8d86be3
GKH		 2849 init_timer(&priv->watch_dog_timer);
2850 priv->watch_dog_timer.data = (unsigned long)dev;
2851 priv->watch_dog_timer.function = watch_dog_adaptive;
c8d86be3 2852
c8d86be3
GKH		 2853 init_timer(&priv->rateadapter_timer);
2854 priv->rateadapter_timer.data = (unsigned long)dev;
2855 priv->rateadapter_timer.function = timer_rate_adaptive;
2856 priv->RateAdaptivePeriod= RATE_ADAPTIVE_TIMER_PERIOD;
2857 priv->bEnhanceTxPwr=false;
c8d86be3
GKH		 2858
2859 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit;
2860 priv->ieee80211->set_chan = rtl8180_set_chan;
2861 priv->ieee80211->link_change = rtl8180_link_change;
2862 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit;
2863 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop;
2864 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume;
2865
2866 priv->ieee80211->init_wmmparam_flag = 0;
2867
2868 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon;
2869 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable;
2870 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
2871
c8d86be3
GKH		 2872 priv->MWIEnable = 0;
2873
2874 priv->ShortRetryLimit = 7;
2875 priv->LongRetryLimit = 7;
2876 priv->EarlyRxThreshold = 7;
2877
2878 priv->CSMethod = (0x01 << 29);
2879
2880 priv->TransmitConfig =
2881 1<<TCR_DurProcMode_OFFSET | //for RTL8185B, duration setting by HW
2882 (7<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
2883 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit
2884 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
2885 (0 ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
2886
2887 priv->ReceiveConfig =
c8d86be3
GKH		 2888 RCR_AMF | RCR_ADF | //accept management/data
2889 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
2890 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
c8d86be3
GKH		 2891 (7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
2892 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
2893 (priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0);
2894
2895 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER |
2896 IMR_THPDER | IMR_THPDOK |
2897 IMR_TVODER | IMR_TVODOK |
2898 IMR_TVIDER | IMR_TVIDOK |
2899 IMR_TBEDER | IMR_TBEDOK |
2900 IMR_TBKDER | IMR_TBKDOK |
2901 IMR_RDU | // To handle the defragmentation not enough Rx descriptors case. Annie, 2006-03-27.
2902 IMR_RER | IMR_ROK |
2903 IMR_RQoSOK; // <NOTE> ROK and RQoSOK are mutually exclusive, so, we must handle RQoSOK interrupt to receive QoS frames, 2005.12.09, by rcnjko.
2904
2905 priv->InitialGain = 6;
c8d86be3 2906
d44eb889
LF		 2907 DMESG("MAC controller is a RTL8187SE b/g");
2908 priv->phy_ver = 2;
c8d86be3 2909
d44eb889
LF		 2910 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION;
2911 priv->ieee80211->short_slot = 1;
c8d86be3 2912
c8d86be3 2913 // just for sync 85
c8d86be3
GKH		 2914 priv->enable_gpio0 = 0;
2915
c8d86be3
GKH		 2916 usValue = eprom_read(dev, EEPROM_SW_REVD_OFFSET);
2917 DMESG("usValue is 0x%x\n",usValue);
c8d86be3 2918 //3Read AntennaDiversity
fd882783 2919
c8d86be3 2920 // SW Antenna Diversity.
fd882783 2921 if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE)
c8d86be3 2922 priv->EEPROMSwAntennaDiversity = false;
c8d86be3 2923 else
c8d86be3 2924 priv->EEPROMSwAntennaDiversity = true;
fd882783 2925
c8d86be3 2926 // Default Antenna to use.
fd882783 2927 if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1)
c8d86be3 2928 priv->EEPROMDefaultAntenna1 = false;
c8d86be3 2929 else
c8d86be3 2930 priv->EEPROMDefaultAntenna1 = true;
c8d86be3 2931
c8d86be3 2932 if( priv->RegSwAntennaDiversityMechanism == 0 ) // Auto
fd882783 2933 /* 0: default from EEPROM. */
c8d86be3 2934 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity;
c8d86be3 2935 else
fd882783 2936 /* 1:disable antenna diversity, 2: enable antenna diversity. */
c8d86be3 2937 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1)? false : true);
c8d86be3 2938
fd882783
BZ		 2939 if (priv->RegDefaultAntenna == 0)
2940 /* 0: default from EEPROM. */
c8d86be3 2941 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1;
c8d86be3 2942 else
fd882783 2943 /* 1: main, 2: aux. */
c8d86be3 2944 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna== 2) ? true : false);
fd882783 2945
c8d86be3
GKH		 2946 /* rtl8185 can calc plcp len in HW.*/
2947 priv->hw_plcp_len = 1;
2948
2949 priv->plcp_preamble_mode = 2;
2950 /*the eeprom type is stored in RCR register bit #6 */
fd882783 2951 if (RCR_9356SEL & read_nic_dword(dev, RCR))
c8d86be3 2952 priv->epromtype=EPROM_93c56;
fd882783 2953 else
c8d86be3 2954 priv->epromtype=EPROM_93c46;
c8d86be3 2955
c8d86be3
GKH		 2956 dev->dev_addr[0]=eprom_read(dev,MAC_ADR) & 0xff;
2957 dev->dev_addr[1]=(eprom_read(dev,MAC_ADR) & 0xff00)>>8;
2958 dev->dev_addr[2]=eprom_read(dev,MAC_ADR+1) & 0xff;
2959 dev->dev_addr[3]=(eprom_read(dev,MAC_ADR+1) & 0xff00)>>8;
2960 dev->dev_addr[4]=eprom_read(dev,MAC_ADR+2) & 0xff;
2961 dev->dev_addr[5]=(eprom_read(dev,MAC_ADR+2) & 0xff00)>>8;
c8d86be3
GKH		 2962
2963 for(i=1,j=0; i<14; i+=2,j++){
c8d86be3
GKH		 2964 word = eprom_read(dev,EPROM_TXPW_CH1_2 + j);
2965 priv->chtxpwr[i]=word & 0xff;
2966 priv->chtxpwr[i+1]=(word & 0xff00)>>8;
c8d86be3 2967 }
d44eb889
LF		 2968 for (i = 1, j = 0; i < 14; i += 2, j++) {
2969 word = eprom_read(dev, EPROM_TXPW_OFDM_CH1_2 + j);
2970 priv->chtxpwr_ofdm[i] = word & 0xff;
2971 priv->chtxpwr_ofdm[i+1] = (word & 0xff00)>>8;
c8d86be3 2972 }
fd882783 2973
c8d86be3
GKH		 2974 //3Read crystal calibtration and thermal meter indication on 87SE.
2975
2976 // By SD3 SY's request. Added by Roger, 2007.12.11.
2977
2978 tmpu16 = eprom_read(dev, EEPROM_RSV>>1);
2979
c8d86be3
GKH		 2980 // Crystal calibration for Xin and Xout resp.
2981 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; // 0~7.5pF
2982 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK)>>4; // 0~7.5pF
2983 if((tmpu16 & EEPROM_XTAL_CAL_ENABLE)>>12)
2984 priv->bXtalCalibration = true;
2985
2986 // Thermal meter reference indication.
2987 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK)>>8);
2988 if((tmpu16 & EEPROM_THERMAL_METER_ENABLE)>>13)
2989 priv->bTxPowerTrack = true;
2990
c8d86be3
GKH		 2991 word = eprom_read(dev,EPROM_TXPW_BASE);
2992 priv->cck_txpwr_base = word & 0xf;
2993 priv->ofdm_txpwr_base = (word>>4) & 0xf;
c8d86be3
GKH		 2994
2995 version = eprom_read(dev,EPROM_VERSION);
2996 DMESG("EEPROM version %x",version);
d44eb889 2997 priv->rcr_csense = 3;
c8d86be3 2998
d44eb889 2999 priv->cs_treshold = (eprom_read(dev, ENERGY_TRESHOLD) & 0xff00) >> 8;
c8d86be3 3000
d44eb889 3001 priv->rf_chip = 0xff & eprom_read(dev, RFCHIPID);
c8d86be3 3002
c8d86be3
GKH		 3003 priv->rf_chip = RF_ZEBRA4;
3004 priv->rf_sleep = rtl8225z4_rf_sleep;
3005 priv->rf_wakeup = rtl8225z4_rf_wakeup;
c8d86be3
GKH		 3006 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!");
3007
3008 priv->rf_close = rtl8225z2_rf_close;
3009 priv->rf_init = rtl8225z2_rf_init;
3010 priv->rf_set_chan = rtl8225z2_rf_set_chan;
3011 priv->rf_set_sens = NULL;
c8d86be3 3012
c8d86be3
GKH		 3013
3014 if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount))
3015 return -ENOMEM;
3016
3017 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3018 TX_MANAGEPRIORITY_RING_ADDR))
3019 return -ENOMEM;
3020
3021 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3022 TX_BKPRIORITY_RING_ADDR))
3023 return -ENOMEM;
3024
3025 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3026 TX_BEPRIORITY_RING_ADDR))
3027 return -ENOMEM;
3028
3029 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3030 TX_VIPRIORITY_RING_ADDR))
3031 return -ENOMEM;
3032
3033 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3034 TX_VOPRIORITY_RING_ADDR))
3035 return -ENOMEM;
3036
3037 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3038 TX_HIGHPRIORITY_RING_ADDR))
3039 return -ENOMEM;
3040
3041 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount,
3042 TX_BEACON_RING_ADDR))
3043 return -ENOMEM;
3044
c8d86be3
GKH		 3045#if !defined(SA_SHIRQ)
3046 if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){
3047#else
3048 if(request_irq(dev->irq, (void *)rtl8180_interrupt, SA_SHIRQ, dev->name, dev)){
3049#endif
3050 DMESGE("Error allocating IRQ %d",dev->irq);
3051 return -1;
3052 }else{
3053 priv->irq=dev->irq;
3054 DMESG("IRQ %d",dev->irq);
3055 }
3056
c8d86be3 3057 return 0;
c8d86be3
GKH		 3058}
3059
c8d86be3
GKH		 3060void rtl8180_no_hw_wep(struct net_device *dev)
3061{
c8d86be3
GKH		 3062}
3063
c8d86be3
GKH		 3064void rtl8180_set_hw_wep(struct net_device *dev)
3065{
3066 struct r8180_priv *priv = ieee80211_priv(dev);
3067 u8 pgreg;
3068 u8 security;
3069 u32 key0_word4;
3070
3071 pgreg=read_nic_byte(dev, PGSELECT);
3072 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
3073
3074 key0_word4 = read_nic_dword(dev, KEY0+4+4+4);
3075 key0_word4 &= ~ 0xff;
3076 key0_word4 |= priv->key0[3]& 0xff;
3077 write_nic_dword(dev,KEY0,(priv->key0[0]));
3078 write_nic_dword(dev,KEY0+4,(priv->key0[1]));
3079 write_nic_dword(dev,KEY0+4+4,(priv->key0[2]));
3080 write_nic_dword(dev,KEY0+4+4+4,(key0_word4));
3081
c8d86be3
GKH		 3082 security = read_nic_byte(dev,SECURITY);
3083 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT);
3084 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT);
3085 security &= ~ SECURITY_ENCRYP_MASK;
3086 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT);
3087
3088 write_nic_byte(dev, SECURITY, security);
3089
3090 DMESG("key %x %x %x %x",read_nic_dword(dev,KEY0+4+4+4),
3091 read_nic_dword(dev,KEY0+4+4),read_nic_dword(dev,KEY0+4),
3092 read_nic_dword(dev,KEY0));
c8d86be3
GKH		 3093}
3094
3095
3096void rtl8185_rf_pins_enable(struct net_device *dev)
3097{
3098// u16 tmp;
3099// tmp = read_nic_word(dev, RFPinsEnable);
3100 write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp);
c8d86be3
GKH		 3101}
3102
c8d86be3
GKH		 3103void rtl8185_set_anaparam2(struct net_device *dev, u32 a)
3104{
3105 u8 conf3;
3106
3107 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3108
3109 conf3 = read_nic_byte(dev, CONFIG3);
3110 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3111 write_nic_dword(dev, ANAPARAM2, a);
3112
3113 conf3 = read_nic_byte(dev, CONFIG3);
3114 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3115 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH		 3116}
3117
c8d86be3
GKH		 3118void rtl8180_set_anaparam(struct net_device *dev, u32 a)
3119{
3120 u8 conf3;
3121
3122 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3123
3124 conf3 = read_nic_byte(dev, CONFIG3);
3125 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3126 write_nic_dword(dev, ANAPARAM, a);
3127
3128 conf3 = read_nic_byte(dev, CONFIG3);
3129 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3130 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3131}
3132
c8d86be3
GKH		 3133void rtl8185_tx_antenna(struct net_device *dev, u8 ant)
3134{
3135 write_nic_byte(dev, TX_ANTENNA, ant);
3136 force_pci_posting(dev);
3137 mdelay(1);
3138}
3139
c8d86be3
GKH		 3140void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data)
3141{
c8d86be3 3142 u32 phyw;
c8d86be3
GKH		 3143
3144 adr |= 0x80;
3145
3146 phyw= ((data<<8) | adr);
c8d86be3 3147
c8d86be3
GKH		 3148 // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register.
3149 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24));
3150 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16));
3151 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8));
3152 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff) ));
5521a513 3153
c8d86be3
GKH		 3154 /* this is ok to fail when we write AGC table. check for AGC table might be
3155 * done by masking with 0x7f instead of 0xff
3156 */
3157 //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr);
3158}
3159
c8d86be3
GKH		 3160inline void write_phy_ofdm (struct net_device *dev, u8 adr, u32 data)
3161{
3162 data = data & 0xff;
3163 rtl8185_write_phy(dev, adr, data);
3164}
3165
c8d86be3
GKH		 3166void write_phy_cck (struct net_device *dev, u8 adr, u32 data)
3167{
3168 data = data & 0xff;
3169 rtl8185_write_phy(dev, adr, data | 0x10000);
3170}
3171
c8d86be3
GKH		 3172/* 70*3 = 210 ms
3173 * I hope this is enougth
3174 */
3175#define MAX_PHY 70
3176void write_phy(struct net_device *dev, u8 adr, u8 data)
3177{
3178 u32 phy;
3179 int i;
3180
3181 phy = 0xff0000;
3182 phy |= adr;
3183 phy |= 0x80; /* this should enable writing */
3184 phy |= (data<<8);
3185
3186 //PHY_ADR, PHY_R and PHY_W are contig and treated as one dword
3187 write_nic_dword(dev,PHY_ADR, phy);
3188
3189 phy= 0xffff00;
3190 phy |= adr;
3191
3192 write_nic_dword(dev,PHY_ADR, phy);
3193 for(i=0;i<MAX_PHY;i++){
3194 phy=read_nic_dword(dev,PHY_ADR);
3195 phy= phy & 0xff0000;
3196 phy= phy >> 16;
3197 if(phy == data){ //SUCCESS!
3198 force_pci_posting(dev);
3199 mdelay(3); //random value
c8d86be3
GKH		 3200 return;
3201 }else{
3202 force_pci_posting(dev);
3203 mdelay(3); //random value
3204 }
3205 }
3206 DMESGW ("Phy writing %x %x failed!", adr,data);
3207}
3208
3209void rtl8185_set_rate(struct net_device *dev)
3210{
3211 int i;
3212 u16 word;
3213 int basic_rate,min_rr_rate,max_rr_rate;
3214
c8d86be3
GKH		 3215 basic_rate = ieeerate2rtlrate(240);
3216 min_rr_rate = ieeerate2rtlrate(60);
3217 max_rr_rate = ieeerate2rtlrate(240);
3218
c8d86be3
GKH		 3219 write_nic_byte(dev, RESP_RATE,
3220 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3221
3222 word = read_nic_word(dev, BRSR);
3223 word &= ~BRSR_MBR_8185;
3224
c8d86be3
GKH		 3225 for(i=0;i<=basic_rate;i++)
3226 word |= (1<<i);
3227
3228 write_nic_word(dev, BRSR, word);
c8d86be3
GKH		 3229}
3230
c8d86be3
GKH		 3231void rtl8180_adapter_start(struct net_device *dev)
3232{
3233 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 3234
3235 rtl8180_rtx_disable(dev);
3236 rtl8180_reset(dev);
3237
c8d86be3
GKH		 3238 /* enable beacon timeout, beacon TX ok and err
3239 * LP tx ok and err, HP TX ok and err, NP TX ok and err,
3240 * RX ok and ERR, and GP timer */
3241 priv->irq_mask = 0x6fcf;
3242
3243 priv->dma_poll_mask = 0;
3244
3245 rtl8180_beacon_tx_disable(dev);
3246
c8d86be3
GKH		 3247 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3248 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
3249 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
3250 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3251
3252 rtl8180_update_msr(dev);
3253
c8d86be3
GKH		 3254 /* These might be unnecessary since we do in rx_enable / tx_enable */
3255 fix_rx_fifo(dev);
3256 fix_tx_fifo(dev);
c8d86be3
GKH		 3257
3258 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3259
3260 /*
3261 The following is very strange. seems to be that 1 means test mode,
3262 but we need to acknolwledges the nic when a packet is ready
bbc9a991 3263 although we set it to 0
c8d86be3
GKH		 3264 */
3265
3266 write_nic_byte(dev,
3267 CONFIG2, read_nic_byte(dev,CONFIG2) &~\
3268 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT));
3269 //^the nic isn't in test mode
d44eb889 3270 write_nic_byte(dev,
c8d86be3
GKH		 3271 CONFIG2, read_nic_byte(dev,CONFIG2)|(1<<4));
3272
3273 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3274
3275 write_nic_dword(dev,INT_TIMEOUT,0);
c8d86be3 3276
d44eb889 3277 write_nic_byte(dev, WPA_CONFIG, 0);
c8d86be3
GKH		 3278
3279 rtl8180_no_hw_wep(dev);
3280
d44eb889
LF		 3281 rtl8185_set_rate(dev);
3282 write_nic_byte(dev, RATE_FALLBACK, 0x81);
c8d86be3 3283
d44eb889 3284 write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6));
c8d86be3 3285
d44eb889
LF		 3286 /*FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */
3287 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3288 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3)
3289 | (1 << CONFIG3_CLKRUN_SHIFT));
3290 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH		 3291
3292 priv->rf_init(dev);
3293
3294 if(priv->rf_set_sens != NULL)
3295 priv->rf_set_sens(dev,priv->sens);
3296 rtl8180_irq_enable(dev);
3297
3298 netif_start_queue(dev);
c8d86be3
GKH		 3299}
3300
c8d86be3
GKH		 3301/* this configures registers for beacon tx and enables it via
3302 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might
3303 * be used to stop beacon transmission
3304 */
3305void rtl8180_start_tx_beacon(struct net_device *dev)
3306{
c8d86be3 3307 u16 word;
c8d86be3
GKH		 3308
3309 DMESG("Enabling beacon TX");
c8d86be3
GKH		 3310 rtl8180_prepare_beacon(dev);
3311 rtl8180_irq_disable(dev);
3312 rtl8180_beacon_tx_enable(dev);
c8d86be3 3313
c8d86be3
GKH		 3314 word = read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd;
3315 write_nic_word(dev, AtimWnd,word);// word |=
c8d86be3
GKH		 3316
3317 word = read_nic_word(dev, BintrItv);
3318 word &= ~BintrItv_BintrItv;
3319 word |= 1000;/*priv->ieee80211->current_network.beacon_interval *
3320 ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
3321 // FIXME: check if correct ^^ worked with 0x3e8;
3322 */
3323 write_nic_word(dev, BintrItv, word);
3324
c8d86be3
GKH		 3325 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3326
c8d86be3 3327 rtl8185b_irq_enable(dev);
c8d86be3
GKH		 3328}
3329
c8d86be3
GKH		 3330static struct net_device_stats *rtl8180_stats(struct net_device *dev)
3331{
3332 struct r8180_priv *priv = ieee80211_priv(dev);
3333
3334 return &priv->ieee80211->stats;
3335}
3336//
3337// Change current and default preamble mode.
3338// 2005.01.06, by rcnjko.
3339//
3340bool
3341MgntActSet_802_11_PowerSaveMode(
3342 struct r8180_priv *priv,
3343 RT_PS_MODE rtPsMode
3344)
3345{
c8d86be3
GKH		 3346 // Currently, we do not change power save mode on IBSS mode.
3347 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3 3348 return false;
c8d86be3 3349
c8d86be3 3350 priv->ieee80211->ps = rtPsMode;
5521a513 3351
c8d86be3
GKH		 3352 return true;
3353}
3354
fd882783 3355void LeisurePSEnter(struct r8180_priv *priv)
c8d86be3 3356{
fd882783 3357 if (priv->bLeisurePs) {
c8d86be3 3358 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED)
c8d86be3 3359 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE
c8d86be3
GKH		 3360 }
3361}
3362
fd882783 3363void LeisurePSLeave(struct r8180_priv *priv)
c8d86be3 3364{
fd882783 3365 if (priv->bLeisurePs) {
c8d86be3 3366 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED)
c8d86be3 3367 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
c8d86be3
GKH		 3368 }
3369}
0370453f 3370
c8d86be3
GKH		 3371void rtl8180_hw_wakeup_wq (struct work_struct *work)
3372{
bf6aede7 3373 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 3374 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
3375 struct net_device *dev = ieee->dev;
c8d86be3 3376
c8d86be3 3377 rtl8180_hw_wakeup(dev);
c8d86be3
GKH		 3378}
3379
c8d86be3
GKH		 3380void rtl8180_hw_sleep_wq (struct work_struct *work)
3381{
bf6aede7 3382 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 3383 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
3384 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 3385
3386 rtl8180_hw_sleep_down(dev);
3387}
3388
c8d86be3
GKH		 3389static void MgntLinkKeepAlive(struct r8180_priv *priv )
3390{
3391 if (priv->keepAliveLevel == 0)
3392 return;
3393
3394 if(priv->ieee80211->state == IEEE80211_LINKED)
3395 {
3396 //
3397 // Keep-Alive.
3398 //
c8d86be3
GKH		 3399
3400 if ( (priv->keepAliveLevel== 2) ||
3401 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast &&
3402 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast )
3403 )
3404 {
3405 priv->link_detect.IdleCount++;
3406
3407 //
3408 // Send a Keep-Alive packet packet to AP if we had been idle for a while.
3409 //
3410 if(priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1) )
3411 {
3412 priv->link_detect.IdleCount = 0;
3413 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false);
3414 }
3415 }
3416 else
3417 {
3418 priv->link_detect.IdleCount = 0;
3419 }
3420 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast;
3421 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast;
3422 }
3423}
c8d86be3
GKH		 3424
3425static u8 read_acadapter_file(char *filename);
fd882783 3426
c8d86be3
GKH		 3427void rtl8180_watch_dog(struct net_device *dev)
3428{
3429 struct r8180_priv *priv = ieee80211_priv(dev);
3430 bool bEnterPS = false;
3431 bool bBusyTraffic = false;
3432 u32 TotalRxNum = 0;
3433 u16 SlotIndex = 0;
3434 u16 i = 0;
c8d86be3
GKH		 3435 if(priv->ieee80211->actscanning == false){
3436 if((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)){
3437 IPSEnter(dev);
3438 }
3439 }
c8d86be3
GKH		 3440 //YJ,add,080828,for link state check
3441 if((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)){
3442 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum;
3443 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod;
3444 for( i=0; i<priv->link_detect.SlotNum; i++ )
3445 TotalRxNum+= priv->link_detect.RxFrameNum[i];
fd882783 3446
c8d86be3
GKH		 3447 if(TotalRxNum == 0){
3448 priv->ieee80211->state = IEEE80211_ASSOCIATING;
3449 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
3450 }
3451 }
3452
3453 //YJ,add,080828,for KeepAlive
3454 MgntLinkKeepAlive(priv);
3455
3456 //YJ,add,080828,for LPS
3457#ifdef ENABLE_LPS
fd882783 3458 if (priv->PowerProfile == POWER_PROFILE_BATTERY)
c8d86be3 3459 priv->bLeisurePs = true;
fd882783 3460 else if (priv->PowerProfile == POWER_PROFILE_AC) {
c8d86be3
GKH		 3461 LeisurePSLeave(priv);
3462 priv->bLeisurePs= false;
3463 }
c8d86be3 3464
c8d86be3
GKH		 3465 if(priv->ieee80211->state == IEEE80211_LINKED){
3466 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod;
3467 //printk("TxOk=%d RxOk=%d\n", priv->link_detect.NumTxOkInPeriod, priv->link_detect.NumRxOkInPeriod);
3468 if( priv->link_detect.NumRxOkInPeriod> 666 ||
3469 priv->link_detect.NumTxOkInPeriod> 666 ) {
3470 bBusyTraffic = true;
3471 }
3472 if(((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8)
3473 || (priv->link_detect.NumRxOkInPeriod > 2)) {
3474 bEnterPS= false;
fd882783 3475 } else
c8d86be3 3476 bEnterPS= true;
c8d86be3 3477
fd882783 3478 if (bEnterPS)
c8d86be3 3479 LeisurePSEnter(priv);
fd882783 3480 else
c8d86be3 3481 LeisurePSLeave(priv);
fd882783 3482 } else
c8d86be3 3483 LeisurePSLeave(priv);
c8d86be3
GKH		 3484#endif
3485 priv->link_detect.bBusyTraffic = bBusyTraffic;
3486 priv->link_detect.NumRxOkInPeriod = 0;
3487 priv->link_detect.NumTxOkInPeriod = 0;
3488 priv->ieee80211->NumRxDataInPeriod = 0;
3489 priv->ieee80211->NumRxBcnInPeriod = 0;
c8d86be3 3490}
fd882783 3491
c8d86be3
GKH		 3492int _rtl8180_up(struct net_device *dev)
3493{
3494 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 3495
3496 priv->up=1;
3497
3498 DMESG("Bringing up iface");
c8d86be3
GKH		 3499 rtl8185b_adapter_start(dev);
3500 rtl8185b_rx_enable(dev);
3501 rtl8185b_tx_enable(dev);
c8d86be3
GKH		 3502 if(priv->bInactivePs){
3503 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
3504 IPSLeave(dev);
3505 }
c8d86be3
GKH		 3506#ifdef RATE_ADAPT
3507 timer_rate_adaptive((unsigned long)dev);
3508#endif
c8d86be3
GKH		 3509 watch_dog_adaptive((unsigned long)dev);
3510#ifdef SW_ANTE
3511 if(priv->bSwAntennaDiverity)
3512 SwAntennaDiversityTimerCallback(dev);
3513#endif
c8d86be3
GKH		 3514 ieee80211_softmac_start_protocol(priv->ieee80211);
3515
c8d86be3
GKH		 3516 return 0;
3517}
3518
c8d86be3
GKH		 3519int rtl8180_open(struct net_device *dev)
3520{
3521 struct r8180_priv *priv = ieee80211_priv(dev);
3522 int ret;
3523
3524 down(&priv->wx_sem);
3525 ret = rtl8180_up(dev);
3526 up(&priv->wx_sem);
3527 return ret;
c8d86be3
GKH		 3528}
3529
c8d86be3
GKH		 3530int rtl8180_up(struct net_device *dev)
3531{
3532 struct r8180_priv *priv = ieee80211_priv(dev);
3533
3534 if (priv->up == 1) return -1;
3535
3536 return _rtl8180_up(dev);
3537}
3538
c8d86be3
GKH		 3539int rtl8180_close(struct net_device *dev)
3540{
3541 struct r8180_priv *priv = ieee80211_priv(dev);
3542 int ret;
3543
3544 down(&priv->wx_sem);
3545 ret = rtl8180_down(dev);
3546 up(&priv->wx_sem);
3547
3548 return ret;
c8d86be3
GKH		 3549}
3550
3551int rtl8180_down(struct net_device *dev)
3552{
3553 struct r8180_priv *priv = ieee80211_priv(dev);
3554
fd882783
BZ		 3555 if (priv->up == 0)
3556 return -1;
c8d86be3
GKH		 3557
3558 priv->up=0;
3559
3560 ieee80211_softmac_stop_protocol(priv->ieee80211);
3561 /* FIXME */
3562 if (!netif_queue_stopped(dev))
3563 netif_stop_queue(dev);
3564 rtl8180_rtx_disable(dev);
3565 rtl8180_irq_disable(dev);
3566 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ		 3567 del_timer_sync(&priv->rateadapter_timer);
3568 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH		 3569 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3570 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3571 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3572 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3573 del_timer_sync(&priv->SwAntennaDiversityTimer);
3574 SetZebraRFPowerState8185(dev,eRfOff);
c8d86be3
GKH		 3575 memset(&(priv->ieee80211->current_network),0,sizeof(struct ieee80211_network));
3576 priv->ieee80211->state = IEEE80211_NOLINK;
3577 return 0;
3578}
3579
c8d86be3
GKH		 3580void rtl8180_restart_wq(struct work_struct *work)
3581{
3582 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
3583 struct net_device *dev = priv->dev;
0370453f 3584
c8d86be3
GKH		 3585 down(&priv->wx_sem);
3586
3587 rtl8180_commit(dev);
3588
3589 up(&priv->wx_sem);
3590}
3591
3592void rtl8180_restart(struct net_device *dev)
3593{
3594 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 3595
c8d86be3 3596 schedule_work(&priv->reset_wq);
c8d86be3
GKH		 3597}
3598
c8d86be3
GKH		 3599void rtl8180_commit(struct net_device *dev)
3600{
3601 struct r8180_priv *priv = ieee80211_priv(dev);
3602
fd882783
BZ		 3603 if (priv->up == 0)
3604 return ;
3605
c8d86be3 3606 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ		 3607 del_timer_sync(&priv->rateadapter_timer);
3608 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH		 3609 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3610 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3611 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3612 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3613 del_timer_sync(&priv->SwAntennaDiversityTimer);
3614 ieee80211_softmac_stop_protocol(priv->ieee80211);
3615 rtl8180_irq_disable(dev);
3616 rtl8180_rtx_disable(dev);
3617 _rtl8180_up(dev);
3618}
3619
c8d86be3
GKH		 3620static void r8180_set_multicast(struct net_device *dev)
3621{
3622 struct r8180_priv *priv = ieee80211_priv(dev);
3623 short promisc;
3624
c8d86be3
GKH		 3625 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
3626
3627 if (promisc != priv->promisc)
3628 rtl8180_restart(dev);
3629
3630 priv->promisc = promisc;
c8d86be3
GKH		 3631}
3632
c8d86be3
GKH		 3633int r8180_set_mac_adr(struct net_device *dev, void *mac)
3634{
3635 struct r8180_priv *priv = ieee80211_priv(dev);
3636 struct sockaddr *addr = mac;
3637
3638 down(&priv->wx_sem);
3639
3640 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3641
3642 if(priv->ieee80211->iw_mode == IW_MODE_MASTER)
3643 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN);
3644
3645 if (priv->up) {
3646 rtl8180_down(dev);
3647 rtl8180_up(dev);
3648 }
3649
3650 up(&priv->wx_sem);
3651
3652 return 0;
3653}
3654
3655/* based on ipw2200 driver */
3656int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3657{
3658 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 3659 struct iwreq *wrq = (struct iwreq *) rq;
3660 int ret=-1;
fd882783 3661
c8d86be3 3662 switch (cmd) {
fd882783 3663 case RTL_IOCTL_WPA_SUPPLICANT:
c8d86be3
GKH		 3664 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
3665 return ret;
fd882783 3666 default:
c8d86be3
GKH		 3667 return -EOPNOTSUPP;
3668 }
3669
3670 return -EOPNOTSUPP;
3671}
3672
727ae303
AB		 3673static const struct net_device_ops rtl8180_netdev_ops = {
3674 .ndo_open = rtl8180_open,
3675 .ndo_stop = rtl8180_close,
3676 .ndo_get_stats = rtl8180_stats,
3677 .ndo_tx_timeout = rtl8180_restart,
3678 .ndo_do_ioctl = rtl8180_ioctl,
3679 .ndo_set_multicast_list = r8180_set_multicast,
3680 .ndo_set_mac_address = r8180_set_mac_adr,
3681 .ndo_validate_addr = eth_validate_addr,
3682 .ndo_change_mtu = eth_change_mtu,
3683 .ndo_start_xmit = ieee80211_xmit,
3684};
c8d86be3
GKH		 3685
3686static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
3687 const struct pci_device_id *id)
3688{
3689 unsigned long ioaddr = 0;
3690 struct net_device *dev = NULL;
3691 struct r8180_priv *priv= NULL;
c8d86be3
GKH		 3692 u8 unit = 0;
3693
c8d86be3 3694 unsigned long pmem_start, pmem_len, pmem_flags;
c8d86be3
GKH		 3695
3696 DMESG("Configuring chip resources");
3697
3698 if( pci_enable_device (pdev) ){
3699 DMESG("Failed to enable PCI device");
3700 return -EIO;
3701 }
3702
3703 pci_set_master(pdev);
c8d86be3
GKH		 3704 pci_set_dma_mask(pdev, 0xffffff00ULL);
3705 pci_set_consistent_dma_mask(pdev,0xffffff00ULL);
3706 dev = alloc_ieee80211(sizeof(struct r8180_priv));
3707 if (!dev)
3708 return -ENOMEM;
3709 priv = ieee80211_priv(dev);
3710 priv->ieee80211 = netdev_priv(dev);
3711
c8d86be3
GKH		 3712 pci_set_drvdata(pdev, dev);
3713 SET_NETDEV_DEV(dev, &pdev->dev);
3714
3715 priv = ieee80211_priv(dev);
fd882783 3716 priv->pdev = pdev;
c8d86be3
GKH		 3717
3718 pmem_start = pci_resource_start(pdev, 1);
3719 pmem_len = pci_resource_len(pdev, 1);
3720 pmem_flags = pci_resource_flags (pdev, 1);
3721
3722 if (!(pmem_flags & IORESOURCE_MEM)) {
3723 DMESG("region #1 not a MMIO resource, aborting");
3724 goto fail;
3725 }
3726
c8d86be3
GKH		 3727 if( ! request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) {
3728 DMESG("request_mem_region failed!");
3729 goto fail;
3730 }
3731
c8d86be3
GKH		 3732 ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len);
3733 if( ioaddr == (unsigned long)NULL ){
3734 DMESG("ioremap failed!");
c8d86be3
GKH		 3735 goto fail1;
3736 }
3737
3738 dev->mem_start = ioaddr; // shared mem start
3739 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
3740
c8d86be3
GKH		 3741 pci_read_config_byte(pdev, 0x05, &unit);
3742 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
c8d86be3
GKH		 3743
3744 dev->irq = pdev->irq;
3745 priv->irq = 0;
3746
727ae303 3747 dev->netdev_ops = &rtl8180_netdev_ops;
c8d86be3 3748 dev->wireless_handlers = &r8180_wx_handlers_def;
c8d86be3 3749
c8d86be3
GKH		 3750 dev->type=ARPHRD_ETHER;
3751 dev->watchdog_timeo = HZ*3; //added by david woo, 2007.12.13
3752
3753 if (dev_alloc_name(dev, ifname) < 0){
3754 DMESG("Oops: devname already taken! Trying wlan%%d...\n");
3755 ifname = "wlan%d";
c8d86be3
GKH		 3756 dev_alloc_name(dev, ifname);
3757 }
3758
c8d86be3
GKH		 3759 if(rtl8180_init(dev)!=0){
3760 DMESG("Initialization failed");
3761 goto fail1;
3762 }
3763
3764 netif_carrier_off(dev);
3765
3766 register_netdev(dev);
3767
3768 rtl8180_proc_init_one(dev);
3769
3770 DMESG("Driver probe completed\n");
3771 return 0;
c8d86be3 3772fail1:
c8d86be3
GKH		 3773 if( dev->mem_start != (unsigned long)NULL ){
3774 iounmap( (void *)dev->mem_start );
3775 release_mem_region( pci_resource_start(pdev, 1),
3776 pci_resource_len(pdev, 1) );
3777 }
c8d86be3
GKH		 3778fail:
3779 if(dev){
c8d86be3
GKH		 3780 if (priv->irq) {
3781 free_irq(dev->irq, dev);
3782 dev->irq=0;
3783 }
3784 free_ieee80211(dev);
3785 }
3786
3787 pci_disable_device(pdev);
3788
3789 DMESG("wlan driver load failed\n");
3790 pci_set_drvdata(pdev, NULL);
3791 return -ENODEV;
c8d86be3
GKH		 3792}
3793
c8d86be3
GKH		 3794static void __devexit rtl8180_pci_remove(struct pci_dev *pdev)
3795{
3796 struct r8180_priv *priv;
3797 struct net_device *dev = pci_get_drvdata(pdev);
c8d86be3 3798
fd882783 3799 if (dev) {
c8d86be3
GKH		 3800 unregister_netdev(dev);
3801
fd882783 3802 priv = ieee80211_priv(dev);
c8d86be3
GKH		 3803
3804 rtl8180_proc_remove_one(dev);
3805 rtl8180_down(dev);
3806 priv->rf_close(dev);
3807 rtl8180_reset(dev);
c8d86be3 3808 mdelay(10);
c8d86be3
GKH		 3809
3810 if(priv->irq){
c8d86be3
GKH		 3811 DMESG("Freeing irq %d",dev->irq);
3812 free_irq(dev->irq, dev);
3813 priv->irq=0;
c8d86be3
GKH		 3814 }
3815
3816 free_rx_desc_ring(dev);
3817 free_tx_desc_rings(dev);
c8d86be3 3818
c8d86be3
GKH		 3819 if( dev->mem_start != (unsigned long)NULL ){
3820 iounmap( (void *)dev->mem_start );
3821 release_mem_region( pci_resource_start(pdev, 1),
3822 pci_resource_len(pdev, 1) );
3823 }
c8d86be3
GKH		 3824
3825 free_ieee80211(dev);
3826 }
3827 pci_disable_device(pdev);
3828
3829 DMESG("wlan driver removed\n");
3830}
3831
c8d86be3
GKH		 3832/* fun with the built-in ieee80211 stack... */
3833extern int ieee80211_crypto_init(void);
3834extern void ieee80211_crypto_deinit(void);
3835extern int ieee80211_crypto_tkip_init(void);
3836extern void ieee80211_crypto_tkip_exit(void);
3837extern int ieee80211_crypto_ccmp_init(void);
3838extern void ieee80211_crypto_ccmp_exit(void);
3839extern int ieee80211_crypto_wep_init(void);
3840extern void ieee80211_crypto_wep_exit(void);
3841
3842static int __init rtl8180_pci_module_init(void)
3843{
3844 int ret;
3845
3846 ret = ieee80211_crypto_init();
3847 if (ret) {
3848 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret);
3849 return ret;
3850 }
3851 ret = ieee80211_crypto_tkip_init();
3852 if (ret) {
3853 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret);
3854 return ret;
3855 }
3856 ret = ieee80211_crypto_ccmp_init();
3857 if (ret) {
3858 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret);
3859 return ret;
3860 }
3861 ret = ieee80211_crypto_wep_init();
3862 if (ret) {
3863 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret);
3864 return ret;
3865 }
3866
3867 printk(KERN_INFO "\nLinux kernel driver for RTL8180 \
3868/ RTL8185 based WLAN cards\n");
3869 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n");
3870 DMESG("Initializing module");
3871 DMESG("Wireless extensions version %d", WIRELESS_EXT);
3872 rtl8180_proc_module_init();
3873
fd882783 3874 if (pci_register_driver(&rtl8180_pci_driver)) {
c8d86be3 3875 DMESG("No device found");
c8d86be3
GKH		 3876 return -ENODEV;
3877 }
3878 return 0;
3879}
3880
c8d86be3
GKH		 3881static void __exit rtl8180_pci_module_exit(void)
3882{
3883 pci_unregister_driver (&rtl8180_pci_driver);
3884 rtl8180_proc_module_remove();
c8d86be3
GKH		 3885 ieee80211_crypto_tkip_exit();
3886 ieee80211_crypto_ccmp_exit();
3887 ieee80211_crypto_wep_exit();
096c55d1 3888 ieee80211_crypto_deinit();
c8d86be3
GKH		 3889 DMESG("Exiting");
3890}
3891
c8d86be3
GKH		 3892void rtl8180_try_wake_queue(struct net_device *dev, int pri)
3893{
3894 unsigned long flags;
3895 short enough_desc;
3896 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3897
3898 spin_lock_irqsave(&priv->tx_lock,flags);
3899 enough_desc = check_nic_enought_desc(dev,pri);
3900 spin_unlock_irqrestore(&priv->tx_lock,flags);
3901
3902 if(enough_desc)
3903 ieee80211_wake_queue(priv->ieee80211);
3904}
3905
c8d86be3
GKH		 3906void rtl8180_tx_isr(struct net_device *dev, int pri,short error)
3907{
3908 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 3909 u32 *tail; //tail virtual addr
3910 u32 *head; //head virtual addr
3911 u32 *begin;//start of ring virtual addr
3912 u32 *nicv; //nic pointer virtual addr
c8d86be3
GKH		 3913 u32 nic; //nic pointer physical addr
3914 u32 nicbegin;// start of ring physical addr
c8d86be3
GKH		 3915 unsigned long flag;
3916 /* physical addr are ok on 32 bits since we set DMA mask*/
c8d86be3
GKH		 3917 int offs;
3918 int j,i;
3919 int hd;
3920 if (error) priv->stats.txretry++; //tony 20060601
3921 spin_lock_irqsave(&priv->tx_lock,flag);
3922 switch(pri) {
3923 case MANAGE_PRIORITY:
3924 tail = priv->txmapringtail;
3925 begin = priv->txmapring;
3926 head = priv->txmapringhead;
3927 nic = read_nic_dword(dev,TX_MANAGEPRIORITY_RING_ADDR);
3928 nicbegin = priv->txmapringdma;
3929 break;
c8d86be3
GKH		 3930 case BK_PRIORITY:
3931 tail = priv->txbkpringtail;
3932 begin = priv->txbkpring;
3933 head = priv->txbkpringhead;
3934 nic = read_nic_dword(dev,TX_BKPRIORITY_RING_ADDR);
3935 nicbegin = priv->txbkpringdma;
3936 break;
c8d86be3
GKH		 3937 case BE_PRIORITY:
3938 tail = priv->txbepringtail;
3939 begin = priv->txbepring;
3940 head = priv->txbepringhead;
3941 nic = read_nic_dword(dev,TX_BEPRIORITY_RING_ADDR);
3942 nicbegin = priv->txbepringdma;
3943 break;
c8d86be3
GKH		 3944 case VI_PRIORITY:
3945 tail = priv->txvipringtail;
3946 begin = priv->txvipring;
3947 head = priv->txvipringhead;
3948 nic = read_nic_dword(dev,TX_VIPRIORITY_RING_ADDR);
3949 nicbegin = priv->txvipringdma;
3950 break;
c8d86be3
GKH		 3951 case VO_PRIORITY:
3952 tail = priv->txvopringtail;
3953 begin = priv->txvopring;
3954 head = priv->txvopringhead;
3955 nic = read_nic_dword(dev,TX_VOPRIORITY_RING_ADDR);
3956 nicbegin = priv->txvopringdma;
3957 break;
c8d86be3
GKH		 3958 case HI_PRIORITY:
3959 tail = priv->txhpringtail;
3960 begin = priv->txhpring;
3961 head = priv->txhpringhead;
3962 nic = read_nic_dword(dev,TX_HIGHPRIORITY_RING_ADDR);
3963 nicbegin = priv->txhpringdma;
3964 break;
3965
3966 default:
3967 spin_unlock_irqrestore(&priv->tx_lock,flag);
3968 return ;
3969 }
fd882783 3970
c8d86be3
GKH		 3971 nicv = (u32*) ((nic - nicbegin) + (u8*)begin);
3972 if((head <= tail && (nicv > tail || nicv < head)) ||
3973 (head > tail && (nicv > tail && nicv < head))){
c8d86be3 3974 DMESGW("nic has lost pointer");
c8d86be3
GKH		 3975 spin_unlock_irqrestore(&priv->tx_lock,flag);
3976 rtl8180_restart(dev);
3977 return;
3978 }
3979
3980 /* we check all the descriptors between the head and the nic,
bbc9a991 3981 * but not the currently pointed by the nic (the next to be txed)
c8d86be3
GKH		 3982 * and the previous of the pointed (might be in process ??)
3983 */
c8d86be3 3984 offs = (nic - nicbegin);
c8d86be3 3985 offs = offs / 8 /4;
c8d86be3
GKH		 3986 hd = (head - begin) /8;
3987
3988 if(offs >= hd)
3989 j = offs - hd;
3990 else
3991 j = offs + (priv->txringcount -1 -hd);
c8d86be3
GKH		 3992
3993 j-=2;
3994 if(j<0) j=0;
3995
c8d86be3
GKH		 3996 for(i=0;i<j;i++)
3997 {
c8d86be3
GKH		 3998 if((*head) & (1<<31))
3999 break;
4000 if(((*head)&(0x10000000)) != 0){
c8d86be3 4001 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff));
fd882783 4002 if (!error)
c8d86be3 4003 priv->NumTxOkTotal++;
c8d86be3 4004 }
fd882783
BZ		 4005
4006 if (!error)
c8d86be3 4007 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff);
fd882783 4008
c8d86be3
GKH		 4009 *head = *head &~ (1<<31);
4010
4011 if((head - begin)/8 == priv->txringcount-1)
4012 head=begin;
c8d86be3
GKH		 4013 else
4014 head+=8;
4015 }
c8d86be3 4016
c8d86be3
GKH		 4017 /* the head has been moved to the last certainly TXed
4018 * (or at least processed by the nic) packet.
4019 * The driver take forcefully owning of all these packets
4020 * If the packet previous of the nic pointer has been
4021 * processed this doesn't matter: it will be checked
4022 * here at the next round. Anyway if no more packet are
4023 * TXed no memory leak occour at all.
4024 */
4025
4026 switch(pri) {
4027 case MANAGE_PRIORITY:
4028 priv->txmapringhead = head;
fd882783 4029
c8d86be3 4030 if(priv->ack_tx_to_ieee){
c8d86be3 4031 if(rtl8180_is_tx_queue_empty(dev)){
c8d86be3
GKH		 4032 priv->ack_tx_to_ieee = 0;
4033 ieee80211_ps_tx_ack(priv->ieee80211,!error);
4034 }
c8d86be3
GKH		 4035 }
4036 break;
c8d86be3
GKH		 4037 case BK_PRIORITY:
4038 priv->txbkpringhead = head;
4039 break;
c8d86be3
GKH		 4040 case BE_PRIORITY:
4041 priv->txbepringhead = head;
4042 break;
c8d86be3
GKH		 4043 case VI_PRIORITY:
4044 priv->txvipringhead = head;
4045 break;
c8d86be3
GKH		 4046 case VO_PRIORITY:
4047 priv->txvopringhead = head;
4048 break;
c8d86be3
GKH		 4049 case HI_PRIORITY:
4050 priv->txhpringhead = head;
4051 break;
4052 }
4053
c8d86be3 4054 spin_unlock_irqrestore(&priv->tx_lock,flag);
c8d86be3
GKH		 4055}
4056
c8d86be3
GKH		 4057void rtl8180_tx_irq_wq(struct work_struct *work)
4058{
bf6aede7 4059 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 4060 struct ieee80211_device * ieee = (struct ieee80211_device*)
4061 container_of(dwork, struct ieee80211_device, watch_dog_wq);
4062 struct net_device *dev = ieee->dev;
0370453f 4063
c8d86be3
GKH		 4064 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
4065}
4066irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs)
4067{
4068 struct net_device *dev = (struct net_device *) netdev;
4069 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
4070 unsigned long flags;
4071 u32 inta;
4072
4073 /* We should return IRQ_NONE, but for now let me keep this */
4074 if(priv->irq_enabled == 0) return IRQ_HANDLED;
4075
4076 spin_lock_irqsave(&priv->irq_th_lock,flags);
4077
c8d86be3
GKH		 4078 //ISR: 4bytes
4079 inta = read_nic_dword(dev, ISR);// & priv->IntrMask;
4080 write_nic_dword(dev,ISR,inta); // reset int situation
c8d86be3
GKH		 4081
4082 priv->stats.shints++;
4083
c8d86be3
GKH		 4084 if(!inta){
4085 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4086 return IRQ_HANDLED;
4087 /*
4088 most probably we can safely return IRQ_NONE,
4089 but for now is better to avoid problems
4090 */
4091 }
4092
fd882783
BZ		 4093 if (inta == 0xffff) {
4094 /* HW disappared */
4095 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
4096 return IRQ_HANDLED;
c8d86be3
GKH		 4097 }
4098
4099 priv->stats.ints++;
c8d86be3
GKH		 4100
4101 if(!netif_running(dev)) {
4102 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4103 return IRQ_HANDLED;
4104 }
4105
fd882783 4106 if (inta & ISR_TimeOut)
c8d86be3 4107 write_nic_dword(dev, TimerInt, 0);
c8d86be3 4108
fd882783 4109 if (inta & ISR_TBDOK)
c8d86be3 4110 priv->stats.txbeacon++;
c8d86be3 4111
fd882783 4112 if (inta & ISR_TBDER)
c8d86be3 4113 priv->stats.txbeaconerr++;
c8d86be3 4114
fd882783 4115 if (inta & IMR_TMGDOK)
c8d86be3 4116 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
c8d86be3
GKH		 4117
4118 if(inta & ISR_THPDER){
c8d86be3
GKH		 4119 priv->stats.txhperr++;
4120 rtl8180_tx_isr(dev,HI_PRIORITY,1);
4121 priv->ieee80211->stats.tx_errors++;
4122 }
4123
4124 if(inta & ISR_THPDOK){ //High priority tx ok
c8d86be3
GKH		 4125 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4126 priv->stats.txhpokint++;
4127 rtl8180_tx_isr(dev,HI_PRIORITY,0);
4128 }
4129
4130 if(inta & ISR_RER) {
4131 priv->stats.rxerr++;
c8d86be3 4132 }
c8d86be3
GKH		 4133 if(inta & ISR_TBKDER){ //corresponding to BK_PRIORITY
4134 priv->stats.txbkperr++;
4135 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH		 4136 rtl8180_tx_isr(dev,BK_PRIORITY,1);
4137 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4138 }
4139
4140 if(inta & ISR_TBEDER){ //corresponding to BE_PRIORITY
4141 priv->stats.txbeperr++;
4142 priv->ieee80211->stats.tx_errors++;
c8d86be3 4143 rtl8180_tx_isr(dev,BE_PRIORITY,1);
c8d86be3
GKH		 4144 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4145 }
c8d86be3
GKH		 4146 if(inta & ISR_TNPDER){ //corresponding to VO_PRIORITY
4147 priv->stats.txnperr++;
4148 priv->ieee80211->stats.tx_errors++;
c8d86be3 4149 rtl8180_tx_isr(dev,NORM_PRIORITY,1);
c8d86be3 4150 rtl8180_try_wake_queue(dev, NORM_PRIORITY);
c8d86be3
GKH		 4151 }
4152
4153 if(inta & ISR_TLPDER){ //corresponding to VI_PRIORITY
4154 priv->stats.txlperr++;
4155 priv->ieee80211->stats.tx_errors++;
c8d86be3 4156 rtl8180_tx_isr(dev,LOW_PRIORITY,1);
c8d86be3
GKH		 4157 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4158 }
4159
4160 if(inta & ISR_ROK){
c8d86be3
GKH		 4161 priv->stats.rxint++;
4162 tasklet_schedule(&priv->irq_rx_tasklet);
4163 }
4164
4165 if(inta & ISR_RQoSOK ){
c8d86be3
GKH		 4166 priv->stats.rxint++;
4167 tasklet_schedule(&priv->irq_rx_tasklet);
4168 }
4169 if(inta & ISR_BcnInt) {
c8d86be3
GKH		 4170 rtl8180_prepare_beacon(dev);
4171 }
4172
4173 if(inta & ISR_RDU){
c8d86be3
GKH		 4174 DMESGW("No RX descriptor available");
4175 priv->stats.rxrdu++;
c8d86be3 4176 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3 4177 }
fd882783 4178
c8d86be3 4179 if(inta & ISR_RXFOVW){
c8d86be3
GKH		 4180 priv->stats.rxoverflow++;
4181 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3
GKH		 4182 }
4183
fd882783
BZ		 4184 if (inta & ISR_TXFOVW)
4185 priv->stats.txoverflow++;
c8d86be3
GKH		 4186
4187 if(inta & ISR_TNPDOK){ //Normal priority tx ok
c8d86be3 4188 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH		 4189 priv->stats.txnpokint++;
4190 rtl8180_tx_isr(dev,NORM_PRIORITY,0);
4191 }
4192
4193 if(inta & ISR_TLPDOK){ //Low priority tx ok
c8d86be3 4194 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH		 4195 priv->stats.txlpokint++;
4196 rtl8180_tx_isr(dev,LOW_PRIORITY,0);
4197 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4198 }
4199
c8d86be3
GKH		 4200 if(inta & ISR_TBKDOK){ //corresponding to BK_PRIORITY
4201 priv->stats.txbkpokint++;
c8d86be3
GKH		 4202 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4203 rtl8180_tx_isr(dev,BK_PRIORITY,0);
4204 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4205 }
4206
4207 if(inta & ISR_TBEDOK){ //corresponding to BE_PRIORITY
4208 priv->stats.txbeperr++;
c8d86be3
GKH		 4209 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4210 rtl8180_tx_isr(dev,BE_PRIORITY,0);
4211 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4212 }
c8d86be3
GKH		 4213 force_pci_posting(dev);
4214 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4215
4216 return IRQ_HANDLED;
4217}
4218
c8d86be3
GKH		 4219void rtl8180_irq_rx_tasklet(struct r8180_priv* priv)
4220{
c8d86be3 4221 rtl8180_rx(priv->dev);
c8d86be3
GKH		 4222}
4223
c8d86be3
GKH		 4224void GPIOChangeRFWorkItemCallBack(struct work_struct *work)
4225{
c8d86be3
GKH		 4226 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work);
4227 struct net_device *dev = ieee->dev;
4228 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 4229 u8 btPSR;
4230 u8 btConfig0;
4231 RT_RF_POWER_STATE eRfPowerStateToSet;
4232 bool bActuallySet=false;
4233
4234 char *argv[3];
4235 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh";
4236 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL};
4237 static int readf_count = 0;
c8d86be3
GKH		 4238
4239#ifdef ENABLE_LPS
4240 if(readf_count % 10 == 0)
4241 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state");
4242
4243 readf_count = (readf_count+1)%0xffff;
c8d86be3
GKH		 4244#endif
4245 {
4246 // We should turn off LED before polling FF51[4].
4247
4248 //Turn off LED.
4249 btPSR = read_nic_byte(dev, PSR);
4250 write_nic_byte(dev, PSR, (btPSR & ~BIT3));
4251
4252 //It need to delay 4us suggested by Jong, 2008-01-16
4253 udelay(4);
4254
4255 //HW radio On/Off according to the value of FF51[4](config0)
4256 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0);
4257
4258 //Turn on LED.
4259 write_nic_byte(dev, PSR, btPSR| BIT3);
4260
4261 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;
4262
4263 if((priv->ieee80211->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
4264 {
4265 priv->ieee80211->bHwRadioOff = false;
4266 bActuallySet = true;
4267 }
4268 else if((priv->ieee80211->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
4269 {
4270 priv->ieee80211->bHwRadioOff = true;
4271 bActuallySet = true;
4272 }
4273
4274 if(bActuallySet)
4275 {
4276 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
4277
4278 /* To update the UI status for Power status changed */
4279 if(priv->ieee80211->bHwRadioOff == true)
4280 argv[1] = "RFOFF";
4281 else{
4282 //if(!priv->RfOffReason)
4283 argv[1] = "RFON";
4284 //else
4285 // argv[1] = "RFOFF";
4286 }
4287 argv[0] = RadioPowerPath;
4288 argv[2] = NULL;
4289
4290 call_usermodehelper(RadioPowerPath,argv,envp,1);
4291 }
c8d86be3 4292 }
c8d86be3
GKH		 4293}
4294
4295static u8 read_acadapter_file(char *filename)
4296{
c8d86be3
GKH		 4297 return 0;
4298}
4299
c8d86be3
GKH		 4300module_init(rtl8180_pci_module_init);
4301module_exit(rtl8180_pci_module_exit);
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