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Staging: rt28x0: run *.h files through Lindent
[net-next-2.6.git] / drivers / staging / rt2860 / chip / rtmp_mac.h
CommitLineData
91980990
GKH		 1/*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
ca97b838 28 rtmp_mac.h
91980990
GKH		 29
30 Abstract:
ca97b838 31 Ralink Wireless Chip MAC related definition & structures
91980990
GKH		 32
33 Revision History:
34 Who When What
35 -------- ---------- ----------------------------------------------
91980990
GKH		 36*/
37
ca97b838
BZ		 38#ifndef __RTMP_MAC_H__
39#define __RTMP_MAC_H__
40
ca97b838
BZ		 41// =================================================================================
42// TX / RX ring descriptor format
43// =================================================================================
44
45// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
46// MAC block use this TXINFO to control the transmission behavior of this frame.
47#define FIFO_MGMT 0
48#define FIFO_HCCA 1
49#define FIFO_EDCA 2
91980990 50
91980990 51//
ca97b838 52// TXD Wireless Information format for Tx ring and Mgmt Ring
91980990 53//
ca97b838
BZ		 54//txop : for txop mode
55// 0:txop for the MPDU frame will be handles by ASIC by register
56// 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
52b81c89
BZ		 57typedef struct PACKED _TXWI_STRUC {
58 // Word 0
ca97b838 59 // ex: 00 03 00 40 means txop = 3, PHYMODE = 1
52b81c89
BZ		 60 UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment.
61 UINT32 MIMOps:1; // the remote peer is in dynamic MIMO-PS mode
62 UINT32 CFACK:1;
63 UINT32 TS:1;
64
65 UINT32 AMPDU:1;
66 UINT32 MpduDensity:3;
67 UINT32 txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
68 UINT32 rsv:6;
69
70 UINT32 MCS:7;
71 UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz
72 UINT32 ShortGI:1;
73 UINT32 STBC:2; // 1: STBC support MCS =0-7, 2,3 : RESERVE
74 UINT32 Ifs:1; //
75// UINT32 rsv2:2; //channel bandwidth 20MHz or 40 MHz
76 UINT32 rsv2:1;
77 UINT32 TxBF:1; // 3*3
78 UINT32 PHYMODE:2;
ca97b838
BZ		 79 // Word1
80 // ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38
52b81c89
BZ		 81 UINT32 ACK:1;
82 UINT32 NSEQ:1;
83 UINT32 BAWinSize:6;
84 UINT32 WirelessCliID:8;
85 UINT32 MPDUtotalByteCount:12;
86 UINT32 PacketId:4;
ca97b838 87 //Word2
52b81c89 88 UINT32 IV;
ca97b838 89 //Word3
52b81c89
BZ		 90 UINT32 EIV;
91} TXWI_STRUC, *PTXWI_STRUC;
ca97b838
BZ		 92
93//
94// RXWI wireless information format, in PBF. invisible in driver.
95//
52b81c89
BZ		 96typedef struct PACKED _RXWI_STRUC {
97 // Word 0
98 UINT32 WirelessCliID:8;
99 UINT32 KeyIndex:2;
100 UINT32 BSSID:3;
101 UINT32 UDF:3;
102 UINT32 MPDUtotalByteCount:12;
103 UINT32 TID:4;
104 // Word 1
105 UINT32 FRAG:4;
106 UINT32 SEQUENCE:12;
107 UINT32 MCS:7;
108 UINT32 BW:1;
109 UINT32 ShortGI:1;
110 UINT32 STBC:2;
111 UINT32 rsv:3;
112 UINT32 PHYMODE:2; // 1: this RX frame is unicast to me
ca97b838 113 //Word2
52b81c89
BZ		 114 UINT32 RSSI0:8;
115 UINT32 RSSI1:8;
116 UINT32 RSSI2:8;
117 UINT32 rsv1:8;
ca97b838 118 //Word3
52b81c89
BZ		 119 UINT32 SNR0:8;
120 UINT32 SNR1:8;
121 UINT32 FOFFSET:8; // RT35xx
122 UINT32 rsv2:8;
123 /*UINT32 rsv2:16; */
124} RXWI_STRUC, *PRXWI_STRUC;
ca97b838
BZ		 125
126// =================================================================================
127// Register format
128// =================================================================================
bf5f6ca4 129
91980990
GKH		 130//
131// SCH/DMA registers - base address 0x0200
132//
133// INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
134//
ca97b838
BZ		 135#define DMA_CSR0 0x200
136#define INT_SOURCE_CSR 0x200
52b81c89
BZ		 137typedef union _INT_SOURCE_CSR_STRUC {
138 struct {
139 UINT32 RxDelayINT:1;
140 UINT32 TxDelayINT:1;
141 UINT32 RxDone:1;
142 UINT32 Ac0DmaDone:1; //4
143 UINT32 Ac1DmaDone:1;
144 UINT32 Ac2DmaDone:1;
145 UINT32 Ac3DmaDone:1;
146 UINT32 HccaDmaDone:1; // bit7
147 UINT32 MgmtDmaDone:1;
148 UINT32 MCUCommandINT:1; //bit 9
149 UINT32 RxTxCoherent:1;
150 UINT32 TBTTInt:1;
151 UINT32 PreTBTT:1;
152 UINT32 TXFifoStatusInt:1; //FIFO Statistics is full, sw should read 0x171c
153 UINT32 AutoWakeup:1; //bit14
154 UINT32 GPTimer:1;
155 UINT32 RxCoherent:1; //bit16
156 UINT32 TxCoherent:1;
157 UINT32:14;
158 } field;
159 UINT32 word;
91980990 160} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
91980990
GKH		 161
162//
163// INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF
164//
165#define INT_MASK_CSR 0x204
52b81c89
BZ		 166typedef union _INT_MASK_CSR_STRUC {
167 struct {
168 UINT32 RXDelay_INT_MSK:1;
169 UINT32 TxDelay:1;
170 UINT32 RxDone:1;
171 UINT32 Ac0DmaDone:1;
172 UINT32 Ac1DmaDone:1;
173 UINT32 Ac2DmaDone:1;
174 UINT32 Ac3DmaDone:1;
175 UINT32 HccaDmaDone:1;
176 UINT32 MgmtDmaDone:1;
177 UINT32 MCUCommandINT:1;
178 UINT32:20;
179 UINT32 RxCoherent:1;
180 UINT32 TxCoherent:1;
181 } field;
182 UINT32 word;
91980990 183} INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
51f94a7b 184
ca97b838 185#define WPDMA_GLO_CFG 0x208
52b81c89
BZ		 186typedef union _WPDMA_GLO_CFG_STRUC {
187 struct {
188 UINT32 EnableTxDMA:1;
189 UINT32 TxDMABusy:1;
190 UINT32 EnableRxDMA:1;
191 UINT32 RxDMABusy:1;
192 UINT32 WPDMABurstSIZE:2;
193 UINT32 EnTXWriteBackDDONE:1;
194 UINT32 BigEndian:1;
195 UINT32 RXHdrScater:8;
196 UINT32 HDR_SEG_LEN:16;
197 } field;
198 UINT32 word;
91980990 199} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
51f94a7b 200
ca97b838 201#define WPDMA_RST_IDX 0x20c
52b81c89
BZ		 202typedef union _WPDMA_RST_IDX_STRUC {
203 struct {
204 UINT32 RST_DTX_IDX0:1;
205 UINT32 RST_DTX_IDX1:1;
206 UINT32 RST_DTX_IDX2:1;
207 UINT32 RST_DTX_IDX3:1;
208 UINT32 RST_DTX_IDX4:1;
209 UINT32 RST_DTX_IDX5:1;
210 UINT32 rsv:10;
211 UINT32 RST_DRX_IDX0:1;
212 UINT32:15;
213 } field;
214 UINT32 word;
91980990 215} WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
91980990 216#define DELAY_INT_CFG 0x0210
52b81c89
BZ		 217typedef union _DELAY_INT_CFG_STRUC {
218 struct {
219 UINT32 RXMAX_PTIME:8;
220 UINT32 RXMAX_PINT:7;
221 UINT32 RXDLY_INT_EN:1;
222 UINT32 TXMAX_PTIME:8;
223 UINT32 TXMAX_PINT:7;
224 UINT32 TXDLY_INT_EN:1;
225 } field;
226 UINT32 word;
91980990 227} DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
91980990 228#define WMM_AIFSN_CFG 0x0214
52b81c89
BZ		 229typedef union _AIFSN_CSR_STRUC {
230 struct {
231 UINT32 Aifsn0:4; // for AC_BE
232 UINT32 Aifsn1:4; // for AC_BK
233 UINT32 Aifsn2:4; // for AC_VI
234 UINT32 Aifsn3:4; // for AC_VO
235 UINT32 Rsv:16;
236 } field;
237 UINT32 word;
238} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
91980990
GKH		 239//
240// CWMIN_CSR: CWmin for each EDCA AC
241//
242#define WMM_CWMIN_CFG 0x0218
52b81c89
BZ		 243typedef union _CWMIN_CSR_STRUC {
244 struct {
245 UINT32 Cwmin0:4; // for AC_BE
246 UINT32 Cwmin1:4; // for AC_BK
247 UINT32 Cwmin2:4; // for AC_VI
248 UINT32 Cwmin3:4; // for AC_VO
249 UINT32 Rsv:16;
250 } field;
251 UINT32 word;
252} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
91980990
GKH		 253
254//
255// CWMAX_CSR: CWmin for each EDCA AC
256//
257#define WMM_CWMAX_CFG 0x021c
52b81c89
BZ		 258typedef union _CWMAX_CSR_STRUC {
259 struct {
260 UINT32 Cwmax0:4; // for AC_BE
261 UINT32 Cwmax1:4; // for AC_BK
262 UINT32 Cwmax2:4; // for AC_VI
263 UINT32 Cwmax3:4; // for AC_VO
264 UINT32 Rsv:16;
265 } field;
266 UINT32 word;
267} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
ca97b838 268
91980990
GKH		 269//
270// AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
271//
272#define WMM_TXOP0_CFG 0x0220
52b81c89
BZ		 273typedef union _AC_TXOP_CSR0_STRUC {
274 struct {
275 USHORT Ac0Txop; // for AC_BK, in unit of 32us
276 USHORT Ac1Txop; // for AC_BE, in unit of 32us
277 } field;
278 UINT32 word;
279} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
91980990
GKH		 280
281//
282// AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
283//
284#define WMM_TXOP1_CFG 0x0224
52b81c89
BZ		 285typedef union _AC_TXOP_CSR1_STRUC {
286 struct {
287 USHORT Ac2Txop; // for AC_VI, in unit of 32us
288 USHORT Ac3Txop; // for AC_VO, in unit of 32us
289 } field;
290 UINT32 word;
291} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
ca97b838 292
91980990
GKH		 293#define RINGREG_DIFF 0x10
294#define GPIO_CTRL_CFG 0x0228 //MAC_CSR13
295#define MCU_CMD_CFG 0x022c
296#define TX_BASE_PTR0 0x0230 //AC_BK base address
297#define TX_MAX_CNT0 0x0234
298#define TX_CTX_IDX0 0x0238
299#define TX_DTX_IDX0 0x023c
52b81c89 300#define TX_BASE_PTR1 0x0240 //AC_BE base address
91980990
GKH		 301#define TX_MAX_CNT1 0x0244
302#define TX_CTX_IDX1 0x0248
303#define TX_DTX_IDX1 0x024c
52b81c89 304#define TX_BASE_PTR2 0x0250 //AC_VI base address
91980990
GKH		 305#define TX_MAX_CNT2 0x0254
306#define TX_CTX_IDX2 0x0258
307#define TX_DTX_IDX2 0x025c
52b81c89 308#define TX_BASE_PTR3 0x0260 //AC_VO base address
91980990
GKH		 309#define TX_MAX_CNT3 0x0264
310#define TX_CTX_IDX3 0x0268
311#define TX_DTX_IDX3 0x026c
52b81c89 312#define TX_BASE_PTR4 0x0270 //HCCA base address
91980990
GKH		 313#define TX_MAX_CNT4 0x0274
314#define TX_CTX_IDX4 0x0278
315#define TX_DTX_IDX4 0x027c
52b81c89 316#define TX_BASE_PTR5 0x0280 //MGMT base address
91980990
GKH		 317#define TX_MAX_CNT5 0x0284
318#define TX_CTX_IDX5 0x0288
319#define TX_DTX_IDX5 0x028c
320#define TX_MGMTMAX_CNT TX_MAX_CNT5
321#define TX_MGMTCTX_IDX TX_CTX_IDX5
322#define TX_MGMTDTX_IDX TX_DTX_IDX5
ca97b838 323#define RX_BASE_PTR 0x0290 //RX base address
91980990
GKH		 324#define RX_MAX_CNT 0x0294
325#define RX_CRX_IDX 0x0298
326#define RX_DRX_IDX 0x029c
51f94a7b 327
ca97b838 328#define USB_DMA_CFG 0x02a0
52b81c89
BZ		 329typedef union _USB_DMA_CFG_STRUC {
330 struct {
331 UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns
332 UINT32 RxBulkAggLmt:8; //Rx Bulk Aggregation Limit in unit of 256 bytes
333 UINT32 phyclear:1; //phy watch dog enable. write 1
334 UINT32 rsv:2;
335 UINT32 TxClear:1; //Clear USB DMA TX path
336 UINT32 TxopHalt:1; //Halt TXOP count down when TX buffer is full.
337 UINT32 RxBulkAggEn:1; //Enable Rx Bulk Aggregation
338 UINT32 RxBulkEn:1; //Enable USB DMA Rx
339 UINT32 TxBulkEn:1; //Enable USB DMA Tx
340 UINT32 EpoutValid:6; //OUT endpoint data valid
341 UINT32 RxBusy:1; //USB DMA RX FSM busy
342 UINT32 TxBusy:1; //USB DMA TX FSM busy
343 } field;
344 UINT32 word;
345} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
ca97b838 346
91980990
GKH		 347//
348// 3 PBF registers
349//
350//
351// Most are for debug. Driver doesn't touch PBF register.
ca97b838
BZ		 352#define PBF_SYS_CTRL 0x0400
353#define PBF_CFG 0x0408
354#define PBF_MAX_PCNT 0x040C
355#define PBF_CTRL 0x0410
356#define PBF_INT_STA 0x0414
357#define PBF_INT_ENA 0x0418
358#define TXRXQ_PCNT 0x0438
359#define PBF_DBG 0x043c
360#define PBF_CAP_CTRL 0x0440
361
362#ifdef RT30xx
363#ifdef RTMP_EFUSE_SUPPORT
3a32ed12 364// eFuse registers
ca97b838
BZ		 365#define EFUSE_CTRL 0x0580
366#define EFUSE_DATA0 0x0590
367#define EFUSE_DATA1 0x0594
368#define EFUSE_DATA2 0x0598
369#define EFUSE_DATA3 0x059c
370#endif // RTMP_EFUSE_SUPPORT //
371#endif // RT30xx //
372
373#define OSC_CTRL 0x5a4
374#define PCIE_PHY_TX_ATTENUATION_CTRL 0x05C8
375#define LDO_CFG0 0x05d4
3a32ed12 376#define GPIO_SWITCH 0x05dc
3a32ed12 377
91980990
GKH		 378//
379// 4 MAC registers
380//
381//
382// 4.1 MAC SYSTEM configuration registers (offset:0x1000)
383//
384#define MAC_CSR0 0x1000
52b81c89
BZ		 385typedef union _ASIC_VER_ID_STRUC {
386 struct {
387 USHORT ASICRev; // reversion : 0
388 USHORT ASICVer; // version : 2860
389 } field;
390 UINT32 word;
391} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
392#define MAC_SYS_CTRL 0x1004 //MAC_CSR1
393#define MAC_ADDR_DW0 0x1008 // MAC ADDR DW0
394#define MAC_ADDR_DW1 0x100c // MAC ADDR DW1
91980990
GKH		 395//
396// MAC_CSR2: STA MAC register 0
397//
52b81c89
BZ		 398typedef union _MAC_DW0_STRUC {
399 struct {
400 UCHAR Byte0; // MAC address byte 0
401 UCHAR Byte1; // MAC address byte 1
402 UCHAR Byte2; // MAC address byte 2
403 UCHAR Byte3; // MAC address byte 3
404 } field;
405 UINT32 word;
406} MAC_DW0_STRUC, *PMAC_DW0_STRUC;
91980990
GKH		 407
408//
409// MAC_CSR3: STA MAC register 1
410//
52b81c89
BZ		 411typedef union _MAC_DW1_STRUC {
412 struct {
413 UCHAR Byte4; // MAC address byte 4
414 UCHAR Byte5; // MAC address byte 5
415 UCHAR U2MeMask;
416 UCHAR Rsvd1;
417 } field;
418 UINT32 word;
419} MAC_DW1_STRUC, *PMAC_DW1_STRUC;
91980990 420
52b81c89
BZ		 421#define MAC_BSSID_DW0 0x1010 // MAC BSSID DW0
422#define MAC_BSSID_DW1 0x1014 // MAC BSSID DW1
91980990
GKH		 423
424//
425// MAC_CSR5: BSSID register 1
426//
52b81c89
BZ		 427typedef union _MAC_CSR5_STRUC {
428 struct {
429 UCHAR Byte4; // BSSID byte 4
430 UCHAR Byte5; // BSSID byte 5
431 USHORT BssIdMask:2; // 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID
432 USHORT MBssBcnNum:3;
433 USHORT Rsvd:11;
434 } field;
435 UINT32 word;
436} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
91980990 437
52b81c89
BZ		 438#define MAX_LEN_CFG 0x1018 // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
439#define BBP_CSR_CFG 0x101c //
91980990
GKH		 440//
441// BBP_CSR_CFG: BBP serial control register
442//
52b81c89
BZ		 443typedef union _BBP_CSR_CFG_STRUC {
444 struct {
445 UINT32 Value:8; // Register value to program into BBP
446 UINT32 RegNum:8; // Selected BBP register
447 UINT32 fRead:1; // 0: Write BBP, 1: Read BBP
448 UINT32 Busy:1; // 1: ASIC is busy execute BBP programming.
449 UINT32 BBP_PAR_DUR:1; // 0: 4 MAC clock cycles 1: 8 MAC clock cycles
450 UINT32 BBP_RW_MODE:1; // 0: use serial mode 1:parallel
451 UINT32:12;
452 } field;
453 UINT32 word;
454} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
ca97b838 455#define RF_CSR_CFG0 0x1020
91980990
GKH		 456//
457// RF_CSR_CFG: RF control register
458//
52b81c89
BZ		 459typedef union _RF_CSR_CFG0_STRUC {
460 struct {
461 UINT32 RegIdAndContent:24; // Register value to program into BBP
462 UINT32 bitwidth:5; // Selected BBP register
463 UINT32 StandbyMode:1; // 0: high when stand by 1: low when standby
464 UINT32 Sel:1; // 0:RF_LE0 activate 1:RF_LE1 activate
465 UINT32 Busy:1; // 0: idle 1: 8busy
466 } field;
467 UINT32 word;
468} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
ca97b838 469#define RF_CSR_CFG1 0x1024
52b81c89
BZ		 470typedef union _RF_CSR_CFG1_STRUC {
471 struct {
472 UINT32 RegIdAndContent:24; // Register value to program into BBP
473 UINT32 RFGap:5; // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
474 UINT32 rsv:7; // 0: idle 1: 8busy
475 } field;
476 UINT32 word;
477} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
478#define RF_CSR_CFG2 0x1028 //
479typedef union _RF_CSR_CFG2_STRUC {
480 struct {
481 UINT32 RegIdAndContent:24; // Register value to program into BBP
482 UINT32 rsv:8; // 0: idle 1: 8busy
483 } field;
484 UINT32 word;
485} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
486#define LED_CFG 0x102c // MAC_CSR14
487typedef union _LED_CFG_STRUC {
488 struct {
489 UINT32 OnPeriod:8; // blinking on period unit 1ms
490 UINT32 OffPeriod:8; // blinking off period unit 1ms
491 UINT32 SlowBlinkPeriod:6; // slow blinking period. unit:1ms
492 UINT32 rsv:2;
493 UINT32 RLedMode:2; // red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on
494 UINT32 GLedMode:2; // green Led Mode
495 UINT32 YLedMode:2; // yellow Led Mode
496 UINT32 LedPolar:1; // Led Polarity. 0: active low1: active high
497 UINT32:1;
498 } field;
499 UINT32 word;
500} LED_CFG_STRUC, *PLED_CFG_STRUC;
91980990
GKH		 501//
502// 4.2 MAC TIMING configuration registers (offset:0x1100)
503//
52b81c89
BZ		 504#define XIFS_TIME_CFG 0x1100 // MAC_CSR8 MAC_CSR9
505typedef union _IFS_SLOT_CFG_STRUC {
506 struct {
507 UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX
508 UINT32 OfdmSifsTime:8; // unit 1us. Applied after OFDM RX/TX
509 UINT32 OfdmXifsTime:4; //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
510 UINT32 EIFS:9; // unit 1us
511 UINT32 BBRxendEnable:1; // reference RXEND signal to begin XIFS defer
512 UINT32 rsv:2;
513 } field;
514 UINT32 word;
515} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
516
517#define BKOFF_SLOT_CFG 0x1104 // mac_csr9 last 8 bits
518#define NAV_TIME_CFG 0x1108 // NAV (MAC_CSR15)
519#define CH_TIME_CFG 0x110C // Count as channel busy
520#define PBF_LIFE_TIMER 0x1110 //TX/RX MPDU timestamp timer (free run)Unit: 1us
521#define BCN_TIME_CFG 0x1114 // TXRX_CSR9
91980990
GKH		 522
523#define BCN_OFFSET0 0x042C
524#define BCN_OFFSET1 0x0430
525
526//
527// BCN_TIME_CFG : Synchronization control register
528//
52b81c89
BZ		 529typedef union _BCN_TIME_CFG_STRUC {
530 struct {
531 UINT32 BeaconInterval:16; // in unit of 1/16 TU
532 UINT32 bTsfTicking:1; // Enable TSF auto counting
533 UINT32 TsfSyncMode:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
534 UINT32 bTBTTEnable:1;
535 UINT32 bBeaconGen:1; // Enable beacon generator
536 UINT32:3;
537 UINT32 TxTimestampCompensate:8;
538 } field;
539 UINT32 word;
540} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
541#define TBTT_SYNC_CFG 0x1118 // txrx_csr10
542#define TSF_TIMER_DW0 0x111C // Local TSF timer lsb 32 bits. Read-only
543#define TSF_TIMER_DW1 0x1120 // msb 32 bits. Read-only.
544#define TBTT_TIMER 0x1124 // TImer remains till next TBTT. Read-only. TXRX_CSR14
545#define INT_TIMER_CFG 0x1128 //
546#define INT_TIMER_EN 0x112c // GP-timer and pre-tbtt Int enable
547#define CH_IDLE_STA 0x1130 // channel idle time
548#define CH_BUSY_STA 0x1134 // channle busy time
91980990
GKH		 549//
550// 4.2 MAC POWER configuration registers (offset:0x1200)
551//
52b81c89
BZ		 552#define MAC_STATUS_CFG 0x1200 // old MAC_CSR12
553#define PWR_PIN_CFG 0x1204 // old MAC_CSR12
554#define AUTO_WAKEUP_CFG 0x1208 // old MAC_CSR10
91980990
GKH		 555//
556// AUTO_WAKEUP_CFG: Manual power control / status register
557//
52b81c89
BZ		 558typedef union _AUTO_WAKEUP_STRUC {
559 struct {
560 UINT32 AutoLeadTime:8;
561 UINT32 NumofSleepingTbtt:7; // ForceWake has high privilege than PutToSleep when both set
562 UINT32 EnableAutoWakeup:1; // 0:sleep, 1:awake
563 UINT32:16;
564 } field;
565 UINT32 word;
566} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
91980990
GKH		 567//
568// 4.3 MAC TX configuration registers (offset:0x1300)
569//
570
52b81c89 571#define EDCA_AC0_CFG 0x1300 //AC_TXOP_CSR0 0x3474
91980990
GKH		 572#define EDCA_AC1_CFG 0x1304
573#define EDCA_AC2_CFG 0x1308
574#define EDCA_AC3_CFG 0x130c
52b81c89
BZ		 575typedef union _EDCA_AC_CFG_STRUC {
576 struct {
577 UINT32 AcTxop:8; // in unit of 32us
578 UINT32 Aifsn:4; // # of slot time
579 UINT32 Cwmin:4; //
580 UINT32 Cwmax:4; //unit power of 2
581 UINT32:12; //
582 } field;
583 UINT32 word;
584} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
91980990
GKH		 585
586#define EDCA_TID_AC_MAP 0x1310
587#define TX_PWR_CFG_0 0x1314
588#define TX_PWR_CFG_1 0x1318
589#define TX_PWR_CFG_2 0x131C
590#define TX_PWR_CFG_3 0x1320
591#define TX_PWR_CFG_4 0x1324
592#define TX_PIN_CFG 0x1328
52b81c89 593#define TX_BAND_CFG 0x132c // 0x1 use upper 20MHz. 0 juse lower 20MHz
91980990
GKH		 594#define TX_SW_CFG0 0x1330
595#define TX_SW_CFG1 0x1334
596#define TX_SW_CFG2 0x1338
597#define TXOP_THRES_CFG 0x133c
598#define TXOP_CTRL_CFG 0x1340
599#define TX_RTS_CFG 0x1344
600
52b81c89
BZ		 601typedef union _TX_RTS_CFG_STRUC {
602 struct {
603 UINT32 AutoRtsRetryLimit:8;
604 UINT32 RtsThres:16; // unit:byte
605 UINT32 RtsFbkEn:1; // enable rts rate fallback
606 UINT32 rsv:7; // 1: HT non-STBC control frame enable
607 } field;
608 UINT32 word;
609} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
91980990 610#define TX_TIMEOUT_CFG 0x1348
52b81c89
BZ		 611typedef union _TX_TIMEOUT_CFG_STRUC {
612 struct {
613 UINT32 rsv:4;
614 UINT32 MpduLifeTime:4; // expiration time = 2^(9+MPDU LIFE TIME) us
615 UINT32 RxAckTimeout:8; // unit:slot. Used for TX precedure
616 UINT32 TxopTimeout:8; //TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
617 UINT32 rsv2:8; // 1: HT non-STBC control frame enable
618 } field;
619 UINT32 word;
620} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
51f94a7b 621#define TX_RTY_CFG 0x134c
52b81c89
BZ		 622typedef union PACKED _TX_RTY_CFG_STRUC {
623 struct {
624 UINT32 ShortRtyLimit:8; // short retry limit
625 UINT32 LongRtyLimit:8; //long retry limit
626 UINT32 LongRtyThre:12; // Long retry threshoold
627 UINT32 NonAggRtyMode:1; // Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
628 UINT32 AggRtyMode:1; // Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
629 UINT32 TxautoFBEnable:1; // Tx retry PHY rate auto fallback enable
630 UINT32 rsv:1; // 1: HT non-STBC control frame enable
631 } field;
632 UINT32 word;
633} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
91980990 634#define TX_LINK_CFG 0x1350
52b81c89 635typedef union PACKED _TX_LINK_CFG_STRUC {
91980990 636 struct PACKED {
52b81c89
BZ		 637 UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us
638 UINT32 MFBEnable:1; // TX apply remote MFB 1:enable
639 UINT32 RemoteUMFSEnable:1; // remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7)
640 UINT32 TxMRQEn:1; // MCS request TX enable
641 UINT32 TxRDGEn:1; // RDG TX enable
642 UINT32 TxCFAckEn:1; // Piggyback CF-ACK enable
643 UINT32 rsv:3; //
644 UINT32 RemotMFB:8; // remote MCS feedback
645 UINT32 RemotMFS:8; //remote MCS feedback sequence number
646 } field;
647 UINT32 word;
648} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
91980990 649#define HT_FBK_CFG0 0x1354
52b81c89
BZ		 650typedef union PACKED _HT_FBK_CFG0_STRUC {
651 struct {
652 UINT32 HTMCS0FBK:4;
653 UINT32 HTMCS1FBK:4;
654 UINT32 HTMCS2FBK:4;
655 UINT32 HTMCS3FBK:4;
656 UINT32 HTMCS4FBK:4;
657 UINT32 HTMCS5FBK:4;
658 UINT32 HTMCS6FBK:4;
659 UINT32 HTMCS7FBK:4;
660 } field;
661 UINT32 word;
662} HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
91980990 663#define HT_FBK_CFG1 0x1358
52b81c89
BZ		 664typedef union _HT_FBK_CFG1_STRUC {
665 struct {
666 UINT32 HTMCS8FBK:4;
667 UINT32 HTMCS9FBK:4;
668 UINT32 HTMCS10FBK:4;
669 UINT32 HTMCS11FBK:4;
670 UINT32 HTMCS12FBK:4;
671 UINT32 HTMCS13FBK:4;
672 UINT32 HTMCS14FBK:4;
673 UINT32 HTMCS15FBK:4;
674 } field;
675 UINT32 word;
676} HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
91980990 677#define LG_FBK_CFG0 0x135c
52b81c89
BZ		 678typedef union _LG_FBK_CFG0_STRUC {
679 struct {
680 UINT32 OFDMMCS0FBK:4; //initial value is 0
681 UINT32 OFDMMCS1FBK:4; //initial value is 0
682 UINT32 OFDMMCS2FBK:4; //initial value is 1
683 UINT32 OFDMMCS3FBK:4; //initial value is 2
684 UINT32 OFDMMCS4FBK:4; //initial value is 3
685 UINT32 OFDMMCS5FBK:4; //initial value is 4
686 UINT32 OFDMMCS6FBK:4; //initial value is 5
687 UINT32 OFDMMCS7FBK:4; //initial value is 6
688 } field;
689 UINT32 word;
690} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
91980990 691#define LG_FBK_CFG1 0x1360
52b81c89
BZ		 692typedef union _LG_FBK_CFG1_STRUC {
693 struct {
694 UINT32 CCKMCS0FBK:4; //initial value is 0
695 UINT32 CCKMCS1FBK:4; //initial value is 0
696 UINT32 CCKMCS2FBK:4; //initial value is 1
697 UINT32 CCKMCS3FBK:4; //initial value is 2
698 UINT32 rsv:16;
699 } field;
700 UINT32 word;
701} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
ca97b838 702
91980990
GKH		 703//=======================================================
704//================ Protection Paramater================================
705//=======================================================
52b81c89 706#define CCK_PROT_CFG 0x1364 //CCK Protection
91980990
GKH		 707#define ASIC_SHORTNAV 1
708#define ASIC_LONGNAV 2
709#define ASIC_RTS 1
710#define ASIC_CTS 2
52b81c89
BZ		 711typedef union _PROT_CFG_STRUC {
712 struct {
713 UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
714 UINT32 ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
715 UINT32 ProtectNav:2; //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv
716 UINT32 TxopAllowCck:1; //CCK TXOP allowance.0:disallow.
717 UINT32 TxopAllowOfdm:1; //CCK TXOP allowance.0:disallow.
718 UINT32 TxopAllowMM20:1; //CCK TXOP allowance. 0:disallow.
719 UINT32 TxopAllowMM40:1; //CCK TXOP allowance.0:disallow.
720 UINT32 TxopAllowGF20:1; //CCK TXOP allowance.0:disallow.
721 UINT32 TxopAllowGF40:1; //CCK TXOP allowance.0:disallow.
722 UINT32 RTSThEn:1; //RTS threshold enable on CCK TX
723 UINT32 rsv:5;
724 } field;
725 UINT32 word;
726} PROT_CFG_STRUC, *PPROT_CFG_STRUC;
727
728#define OFDM_PROT_CFG 0x1368 //OFDM Protection
729#define MM20_PROT_CFG 0x136C //MM20 Protection
730#define MM40_PROT_CFG 0x1370 //MM40 Protection
731#define GF20_PROT_CFG 0x1374 //GF20 Protection
732#define GF40_PROT_CFG 0x1378 //GR40 Protection
733#define EXP_CTS_TIME 0x137C //
734#define EXP_ACK_TIME 0x1380 //
91980990
GKH		 735
736//
737// 4.4 MAC RX configuration registers (offset:0x1400)
738//
52b81c89
BZ		 739#define RX_FILTR_CFG 0x1400 //TXRX_CSR0
740#define AUTO_RSP_CFG 0x1404 //TXRX_CSR4
91980990
GKH		 741//
742// TXRX_CSR4: Auto-Responder/
743//
91980990 744typedef union _AUTO_RSP_CFG_STRUC {
52b81c89
BZ		 745 struct {
746 UINT32 AutoResponderEnable:1;
747 UINT32 BACAckPolicyEnable:1; // 0:long, 1:short preamble
748 UINT32 CTS40MMode:1; // Response CTS 40MHz duplicate mode
749 UINT32 CTS40MRef:1; // Response CTS 40MHz duplicate mode
750 UINT32 AutoResponderPreamble:1; // 0:long, 1:short preamble
751 UINT32 rsv:1; // Power bit value in conrtrol frame
752 UINT32 DualCTSEn:1; // Power bit value in conrtrol frame
753 UINT32 AckCtsPsmBit:1; // Power bit value in conrtrol frame
754 UINT32:24;
755 } field;
756 UINT32 word;
91980990 757} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
91980990
GKH		 758
759#define LEGACY_BASIC_RATE 0x1408 // TXRX_CSR5 0x3054
760#define HT_BASIC_RATE 0x140c
761#define HT_CTRL_CFG 0x1410
762#define SIFS_COST_CFG 0x1414
763#define RX_PARSER_CFG 0x1418 //Set NAV for all received frames
764
765//
766// 4.5 MAC Security configuration (offset:0x1500)
767//
52b81c89
BZ		 768#define TX_SEC_CNT0 0x1500 //
769#define RX_SEC_CNT0 0x1504 //
770#define CCMP_FC_MUTE 0x1508 //
91980990
GKH		 771//
772// 4.6 HCCA/PSMP (offset:0x1600)
773//
774#define TXOP_HLDR_ADDR0 0x1600
775#define TXOP_HLDR_ADDR1 0x1604
776#define TXOP_HLDR_ET 0x1608
777#define QOS_CFPOLL_RA_DW0 0x160c
778#define QOS_CFPOLL_A1_DW1 0x1610
779#define QOS_CFPOLL_QC 0x1614
780//
781// 4.7 MAC Statistis registers (offset:0x1700)
782//
52b81c89
BZ		 783#define RX_STA_CNT0 0x1700 //
784#define RX_STA_CNT1 0x1704 //
785#define RX_STA_CNT2 0x1708 //
91980990
GKH		 786
787//
788// RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
789//
52b81c89
BZ		 790typedef union _RX_STA_CNT0_STRUC {
791 struct {
792 USHORT CrcErr;
793 USHORT PhyErr;
794 } field;
795 UINT32 word;
796} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
91980990
GKH		 797
798//
799// RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
800//
52b81c89
BZ		 801typedef union _RX_STA_CNT1_STRUC {
802 struct {
803 USHORT FalseCca;
804 USHORT PlcpErr;
805 } field;
806 UINT32 word;
807} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
91980990
GKH		 808
809//
810// RX_STA_CNT2_STRUC:
811//
52b81c89
BZ		 812typedef union _RX_STA_CNT2_STRUC {
813 struct {
814 USHORT RxDupliCount;
815 USHORT RxFifoOverflowCount;
816 } field;
817 UINT32 word;
818} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
819#define TX_STA_CNT0 0x170C //
91980990
GKH		 820//
821// STA_CSR3: TX Beacon count
822//
52b81c89
BZ		 823typedef union _TX_STA_CNT0_STRUC {
824 struct {
825 USHORT TxFailCount;
826 USHORT TxBeaconCount;
827 } field;
828 UINT32 word;
829} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
830#define TX_STA_CNT1 0x1710 //
91980990
GKH		 831//
832// TX_STA_CNT1: TX tx count
833//
52b81c89
BZ		 834typedef union _TX_STA_CNT1_STRUC {
835 struct {
836 USHORT TxSuccess;
837 USHORT TxRetransmit;
838 } field;
839 UINT32 word;
840} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
841#define TX_STA_CNT2 0x1714 //
91980990
GKH		 842//
843// TX_STA_CNT2: TX tx count
844//
52b81c89
BZ		 845typedef union _TX_STA_CNT2_STRUC {
846 struct {
847 USHORT TxZeroLenCount;
848 USHORT TxUnderFlowCount;
849 } field;
850 UINT32 word;
851} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
852#define TX_STA_FIFO 0x1718 //
91980990
GKH		 853//
854// TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
855//
52b81c89
BZ		 856typedef union PACKED _TX_STA_FIFO_STRUC {
857 struct {
858 UINT32 bValid:1; // 1:This register contains a valid TX result
859 UINT32 PidType:4;
860 UINT32 TxSuccess:1; // Tx No retry success
861 UINT32 TxAggre:1; // Tx Retry Success
862 UINT32 TxAckRequired:1; // Tx fail
863 UINT32 wcid:8; //wireless client index
864// UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
865 UINT32 SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
866 UINT32 TxBF:1;
867 UINT32 Reserve:2;
868 } field;
869 UINT32 word;
870} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
91980990
GKH		 871// Debug counter
872#define TX_AGG_CNT 0x171c
52b81c89
BZ		 873typedef union _TX_AGG_CNT_STRUC {
874 struct {
875 USHORT NonAggTxCount;
876 USHORT AggTxCount;
877 } field;
878 UINT32 word;
879} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
91980990
GKH		 880// Debug counter
881#define TX_AGG_CNT0 0x1720
52b81c89
BZ		 882typedef union _TX_AGG_CNT0_STRUC {
883 struct {
884 USHORT AggSize1Count;
885 USHORT AggSize2Count;
886 } field;
887 UINT32 word;
888} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
91980990
GKH		 889// Debug counter
890#define TX_AGG_CNT1 0x1724
52b81c89
BZ		 891typedef union _TX_AGG_CNT1_STRUC {
892 struct {
893 USHORT AggSize3Count;
894 USHORT AggSize4Count;
895 } field;
896 UINT32 word;
897} TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
91980990 898#define TX_AGG_CNT2 0x1728
52b81c89
BZ		 899typedef union _TX_AGG_CNT2_STRUC {
900 struct {
901 USHORT AggSize5Count;
902 USHORT AggSize6Count;
903 } field;
904 UINT32 word;
905} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
91980990
GKH		 906// Debug counter
907#define TX_AGG_CNT3 0x172c
52b81c89
BZ		 908typedef union _TX_AGG_CNT3_STRUC {
909 struct {
910 USHORT AggSize7Count;
911 USHORT AggSize8Count;
912 } field;
913 UINT32 word;
914} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
91980990
GKH		 915// Debug counter
916#define TX_AGG_CNT4 0x1730
52b81c89
BZ		 917typedef union _TX_AGG_CNT4_STRUC {
918 struct {
919 USHORT AggSize9Count;
920 USHORT AggSize10Count;
921 } field;
922 UINT32 word;
923} TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
91980990 924#define TX_AGG_CNT5 0x1734
52b81c89
BZ		 925typedef union _TX_AGG_CNT5_STRUC {
926 struct {
927 USHORT AggSize11Count;
928 USHORT AggSize12Count;
929 } field;
930 UINT32 word;
931} TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
91980990 932#define TX_AGG_CNT6 0x1738
52b81c89
BZ		 933typedef union _TX_AGG_CNT6_STRUC {
934 struct {
935 USHORT AggSize13Count;
936 USHORT AggSize14Count;
937 } field;
938 UINT32 word;
939} TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
91980990 940#define TX_AGG_CNT7 0x173c
52b81c89
BZ		 941typedef union _TX_AGG_CNT7_STRUC {
942 struct {
943 USHORT AggSize15Count;
944 USHORT AggSize16Count;
945 } field;
946 UINT32 word;
947} TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
91980990 948#define MPDU_DENSITY_CNT 0x1740
52b81c89
BZ		 949typedef union _MPDU_DEN_CNT_STRUC {
950 struct {
951 USHORT TXZeroDelCount; //TX zero length delimiter count
952 USHORT RXZeroDelCount; //RX zero length delimiter count
953 } field;
954 UINT32 word;
955} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
91980990
GKH		 956//
957// TXRX control registers - base address 0x3000
958//
959// rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
960#define TXRX_CSR1 0x77d0
961
962//
963// Security key table memory, base address = 0x1000
964//
52b81c89 965#define MAC_WCID_BASE 0x1800 //8-bytes(use only 6-bytes) * 256 entry =
91980990 966#define HW_WCID_ENTRY_SIZE 8
52b81c89 967#define PAIRWISE_KEY_TABLE_BASE 0x4000 // 32-byte * 256-entry = -byte
91980990 968#define HW_KEY_ENTRY_SIZE 0x20
52b81c89
BZ		 969#define PAIRWISE_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
970#define MAC_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
91980990 971#define HW_IVEIV_ENTRY_SIZE 8
52b81c89 972#define MAC_WCID_ATTRIBUTE_BASE 0x6800 // 4-byte * 256-entry = -byte
91980990 973#define HW_WCID_ATTRI_SIZE 4
ca97b838 974#define WCID_RESERVED 0x6bfc
52b81c89
BZ		 975#define SHARED_KEY_TABLE_BASE 0x6c00 // 32-byte * 16-entry = 512-byte
976#define SHARED_KEY_MODE_BASE 0x7000 // 32-byte * 16-entry = 512-byte
91980990
GKH		 977#define HW_SHARED_KEY_MODE_SIZE 4
978#define SHAREDKEYTABLE 0
979#define PAIRWISEKEYTABLE 1
980
52b81c89
BZ		 981typedef union _SHAREDKEY_MODE_STRUC {
982 struct {
983 UINT32 Bss0Key0CipherAlg:3;
984 UINT32:1;
985 UINT32 Bss0Key1CipherAlg:3;
986 UINT32:1;
987 UINT32 Bss0Key2CipherAlg:3;
988 UINT32:1;
989 UINT32 Bss0Key3CipherAlg:3;
990 UINT32:1;
991 UINT32 Bss1Key0CipherAlg:3;
992 UINT32:1;
993 UINT32 Bss1Key1CipherAlg:3;
994 UINT32:1;
995 UINT32 Bss1Key2CipherAlg:3;
996 UINT32:1;
997 UINT32 Bss1Key3CipherAlg:3;
998 UINT32:1;
999 } field;
1000 UINT32 word;
1001} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
91980990 1002// 64-entry for pairwise key table
52b81c89
BZ		 1003typedef struct _HW_WCID_ENTRY { // 8-byte per entry
1004 UCHAR Address[6];
1005 UCHAR Rsv[2];
91980990
GKH		 1006} HW_WCID_ENTRY, PHW_WCID_ENTRY;
1007
91980990
GKH		 1008// =================================================================================
1009// WCID format
1010// =================================================================================
52b81c89
BZ		 1011//7.1 WCID ENTRY format : 8bytes
1012typedef struct _WCID_ENTRY_STRUC {
1013 UCHAR RXBABitmap7; // bit0 for TID8, bit7 for TID 15
1014 UCHAR RXBABitmap0; // bit0 for TID0, bit7 for TID 7
1015 UCHAR MAC[6]; // 0 for shared key table. 1 for pairwise key table
1016} WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1017
1018//8.1.1 SECURITY KEY format : 8DW
91980990 1019// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
52b81c89
BZ		 1020typedef struct _HW_KEY_ENTRY { // 32-byte per entry
1021 UCHAR Key[16];
1022 UCHAR TxMic[8];
1023 UCHAR RxMic[8];
91980990
GKH		 1024} HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1025
52b81c89 1026//8.1.2 IV/EIV format : 2DW
91980990 1027
52b81c89
BZ		 1028//8.1.3 RX attribute entry format : 1DW
1029typedef struct _MAC_ATTRIBUTE_STRUC {
1030 UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table
1031 UINT32 PairKeyMode:3;
1032 UINT32 BSSIDIdx:3; //multipleBSS index for the WCID
1033 UINT32 RXWIUDF:3;
1034 UINT32 rsv:22;
1035} MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
91980990
GKH		 1036
1037// =================================================================================
1038// HOST-MCU communication data structure
1039// =================================================================================
1040
1041//
1042// H2M_MAILBOX_CSR: Host-to-MCU Mailbox
1043//
52b81c89
BZ		 1044typedef union _H2M_MAILBOX_STRUC {
1045 struct {
1046 UINT32 LowByte:8;
1047 UINT32 HighByte:8;
1048 UINT32 CmdToken:8;
1049 UINT32 Owner:8;
1050 } field;
1051 UINT32 word;
91980990 1052} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
91980990
GKH		 1053
1054//
1055// M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
1056//
91980990 1057typedef union _M2H_CMD_DONE_STRUC {
52b81c89
BZ		 1058 struct {
1059 UINT32 CmdToken0;
1060 UINT32 CmdToken1;
1061 UINT32 CmdToken2;
1062 UINT32 CmdToken3;
1063 } field;
1064 UINT32 word;
91980990 1065} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
91980990 1066
91980990 1067//NAV_TIME_CFG :NAV
52b81c89
BZ		 1068typedef union _NAV_TIME_CFG_STRUC {
1069 struct {
1070 UCHAR Sifs; // in unit of 1-us
1071 UCHAR SlotTime; // in unit of 1-us
1072 USHORT Eifs:9; // in unit of 1-us
1073 USHORT ZeroSifs:1; // Applied zero SIFS timer after OFDM RX 0: disable
1074 USHORT rsv:6;
1075 } field;
1076 UINT32 word;
1077} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
ca97b838 1078
91980990
GKH		 1079//
1080// RX_FILTR_CFG: /RX configuration register
1081//
52b81c89
BZ		 1082typedef union _RX_FILTR_CFG_STRUC {
1083 struct {
1084 UINT32 DropCRCErr:1; // Drop CRC error
1085 UINT32 DropPhyErr:1; // Drop physical error
1086 UINT32 DropNotToMe:1; // Drop not to me unicast frame
1087 UINT32 DropNotMyBSSID:1; // Drop fram ToDs bit is true
91980990 1088
52b81c89
BZ		 1089 UINT32 DropVerErr:1; // Drop version error frame
1090 UINT32 DropMcast:1; // Drop multicast frames
1091 UINT32 DropBcast:1; // Drop broadcast frames
1092 UINT32 DropDuplicate:1; // Drop duplicate frame
91980990 1093
52b81c89
BZ		 1094 UINT32 DropCFEndAck:1; // Drop Ps-Poll
1095 UINT32 DropCFEnd:1; // Drop Ps-Poll
1096 UINT32 DropAck:1; // Drop Ps-Poll
1097 UINT32 DropCts:1; // Drop Ps-Poll
ca97b838 1098
52b81c89
BZ		 1099 UINT32 DropRts:1; // Drop Ps-Poll
1100 UINT32 DropPsPoll:1; // Drop Ps-Poll
1101 UINT32 DropBA:1; //
1102 UINT32 DropBAR:1; //
ca97b838 1103
52b81c89
BZ		 1104 UINT32 DropRsvCntlType:1;
1105 UINT32:15;
1106 } field;
1107 UINT32 word;
1108} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
ca97b838 1109
91980990
GKH		 1110//
1111// PHY_CSR4: RF serial control register
1112//
52b81c89
BZ		 1113typedef union _PHY_CSR4_STRUC {
1114 struct {
1115 UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1116 UINT32 NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1117 UINT32 IFSelect:1; // 1: select IF to program, 0: select RF to program
1118 UINT32 PLL_LD:1; // RF PLL_LD status
1119 UINT32 Busy:1; // 1: ASIC is busy execute RF programming.
1120 } field;
1121 UINT32 word;
1122} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
ca97b838 1123
91980990
GKH		 1124//
1125// SEC_CSR5: shared key table security mode register
1126//
52b81c89
BZ		 1127typedef union _SEC_CSR5_STRUC {
1128 struct {
1129 UINT32 Bss2Key0CipherAlg:3;
1130 UINT32:1;
1131 UINT32 Bss2Key1CipherAlg:3;
1132 UINT32:1;
1133 UINT32 Bss2Key2CipherAlg:3;
1134 UINT32:1;
1135 UINT32 Bss2Key3CipherAlg:3;
1136 UINT32:1;
1137 UINT32 Bss3Key0CipherAlg:3;
1138 UINT32:1;
1139 UINT32 Bss3Key1CipherAlg:3;
1140 UINT32:1;
1141 UINT32 Bss3Key2CipherAlg:3;
1142 UINT32:1;
1143 UINT32 Bss3Key3CipherAlg:3;
1144 UINT32:1;
1145 } field;
1146 UINT32 word;
1147} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
ca97b838 1148
91980990
GKH		 1149//
1150// HOST_CMD_CSR: For HOST to interrupt embedded processor
1151//
52b81c89
BZ		 1152typedef union _HOST_CMD_CSR_STRUC {
1153 struct {
1154 UINT32 HostCommand:8;
1155 UINT32 Rsv:24;
1156 } field;
1157 UINT32 word;
1158} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
ca97b838 1159
91980990
GKH		 1160//
1161// AIFSN_CSR: AIFSN for each EDCA AC
1162//
1163
91980990
GKH		 1164//
1165// E2PROM_CSR: EEPROM control register
1166//
52b81c89
BZ		 1167typedef union _E2PROM_CSR_STRUC {
1168 struct {
1169 UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
1170 UINT32 EepromSK:1;
1171 UINT32 EepromCS:1;
1172 UINT32 EepromDI:1;
1173 UINT32 EepromDO:1;
1174 UINT32 Type:1; // 1: 93C46, 0:93C66
1175 UINT32 LoadStatus:1; // 1:loading, 0:done
1176 UINT32 Rsvd:25;
1177 } field;
1178 UINT32 word;
1179} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
91980990 1180
91980990
GKH		 1181//
1182// QOS_CSR0: TXOP holder address0 register
1183//
52b81c89
BZ		 1184typedef union _QOS_CSR0_STRUC {
1185 struct {
1186 UCHAR Byte0; // MAC address byte 0
1187 UCHAR Byte1; // MAC address byte 1
1188 UCHAR Byte2; // MAC address byte 2
1189 UCHAR Byte3; // MAC address byte 3
1190 } field;
1191 UINT32 word;
1192} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
91980990
GKH		 1193
1194//
1195// QOS_CSR1: TXOP holder address1 register
1196//
52b81c89
BZ		 1197typedef union _QOS_CSR1_STRUC {
1198 struct {
1199 UCHAR Byte4; // MAC address byte 4
1200 UCHAR Byte5; // MAC address byte 5
1201 UCHAR Rsvd0;
1202 UCHAR Rsvd1;
1203 } field;
1204 UINT32 word;
1205} QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
91980990
GKH		 1206
1207#define RF_CSR_CFG 0x500
52b81c89
BZ		 1208typedef union _RF_CSR_CFG_STRUC {
1209 struct {
1210 UINT RF_CSR_DATA:8; // DATA
1211 UINT TESTCSR_RFACC_REGNUM:5; // RF register ID
1212 UINT Rsvd2:3; // Reserved
1213 UINT RF_CSR_WR:1; // 0: read 1: write
1214 UINT RF_CSR_KICK:1; // kick RF register read/write
1215 UINT Rsvd1:14; // Reserved
1216 } field;
1217 UINT word;
1218} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
ca97b838
BZ		 1219
1220//
1221// Other on-chip shared memory space, base = 0x2000
1222//
1223
1224// CIS space - base address = 0x2000
1225#define HW_CIS_BASE 0x2000
1226
1227// Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
1228#define HW_CS_CTS_BASE 0x7700
1229// DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1230#define HW_DFS_CTS_BASE 0x7780
1231#define HW_CTS_FRAME_SIZE 0x80
1232
1233// 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
1234// to save debugging settings
52b81c89
BZ		 1235#define HW_DEBUG_SETTING_BASE 0x77f0 // 0x77f0~0x77ff total 16 bytes
1236#define HW_DEBUG_SETTING_BASE2 0x7770 // 0x77f0~0x77ff total 16 bytes
ca97b838
BZ		 1237
1238// In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
1239// Three section discontinue memory segments will be used.
1240// 1. The original region for BCN 0~3
1241// 2. Extract memory from FCE table for BCN 4~5
1242// 3. Extract memory from Pair-wise key table for BCN 6~7
52b81c89
BZ		 1243// It occupied those memory of wcid 238~253 for BCN 6
1244// and wcid 222~237 for BCN 7
1245#define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
ca97b838
BZ		 1246#define HW_BEACON_BASE0 0x7800
1247#define HW_BEACON_BASE1 0x7A00
1248#define HW_BEACON_BASE2 0x7C00
1249#define HW_BEACON_BASE3 0x7E00
1250#define HW_BEACON_BASE4 0x7200
1251#define HW_BEACON_BASE5 0x7400
1252#define HW_BEACON_BASE6 0x5DC0
1253#define HW_BEACON_BASE7 0x5BC0
1254
1255#define HW_BEACON_MAX_COUNT 8
1256#define HW_BEACON_OFFSET 0x0200
1257#define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
1258
1259// HOST-MCU shared memory - base address = 0x2100
1260#define HOST_CMD_CSR 0x404
1261#define H2M_MAILBOX_CSR 0x7010
1262#define H2M_MAILBOX_CID 0x7014
1263#define H2M_MAILBOX_STATUS 0x701c
1264#define H2M_INT_SRC 0x7024
1265#define H2M_BBP_AGENT 0x7028
1266#define M2H_CMD_DONE_CSR 0x000c
52b81c89
BZ		 1267#define MCU_TXOP_ARRAY_BASE 0x000c // TODO: to be provided by Albert
1268#define MCU_TXOP_ENTRY_SIZE 32 // TODO: to be provided by Albert
1269#define MAX_NUM_OF_TXOP_ENTRY 16 // TODO: must be same with 8051 firmware
1270#define MCU_MBOX_VERSION 0x01 // TODO: to be confirmed by Albert
1271#define MCU_MBOX_VERSION_OFFSET 5 // TODO: to be provided by Albert
ca97b838
BZ		 1272
1273//
1274// Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
1275//
1276//
1277// DMA RING DESCRIPTOR
1278//
1279#define E2PROM_CSR 0x0004
1280#define IO_CNTL_CSR 0x77d0
1281
ca97b838 1282// ================================================================
52b81c89 1283// Tx / Rx / Mgmt ring descriptor definition
ca97b838
BZ		 1284// ================================================================
1285
1286// the following PID values are used to mark outgoing frame type in TXD->PID so that
1287// proper TX statistics can be collected based on these categories
1288// b3-2 of PID field -
1289#define PID_MGMT 0x05
1290#define PID_BEACON 0x0c
1291#define PID_DATA_NORMALUCAST 0x02
1292#define PID_DATA_AMPDU 0x04
1293#define PID_DATA_NO_ACK 0x08
1294#define PID_DATA_NOT_NORM_ACK 0x03
1295// value domain of pTxD->HostQId (4-bit: 0~15)
52b81c89
BZ		 1296#define QID_AC_BK 1 // meet ACI definition in 802.11e
1297#define QID_AC_BE 0 // meet ACI definition in 802.11e
ca97b838
BZ		 1298#define QID_AC_VI 2
1299#define QID_AC_VO 3
1300#define QID_HCCA 4
1301#define NUM_OF_TX_RING 4
1302#define QID_MGMT 13
1303#define QID_RX 14
1304#define QID_OTHER 15
1305
1306#endif // __RTMP_MAC_H__ //
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