[net-next-2.6.git] / drivers / staging / et131x / et131x_isr.c

/*
 * Agere Systems Inc.
 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
 *
 * Copyright © 2005 Agere Systems Inc.
 * All rights reserved.
 *   http://www.agere.com
 *
 *------------------------------------------------------------------------------
 *
 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
 *                for processing interrupts from the device.
 *
 *------------------------------------------------------------------------------
 *
 * SOFTWARE LICENSE
 *
 * This software is provided subject to the following terms and conditions,
 * which you should read carefully before using the software.  Using this
 * software indicates your acceptance of these terms and conditions.  If you do
 * not agree with these terms and conditions, do not use the software.
 *
 * Copyright © 2005 Agere Systems Inc.
 * All rights reserved.
 *
 * Redistribution and use in source or binary forms, with or without
 * modifications, are permitted provided that the following conditions are met:
 *
 * . Redistributions of source code must retain the above copyright notice, this
 *    list of conditions and the following Disclaimer as comments in the code as
 *    well as in the documentation and/or other materials provided with the
 *    distribution.
 *
 * . Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following Disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * . Neither the name of Agere Systems Inc. nor the names of the contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * Disclaimer
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGE.
 *
 */

#include "et131x_version.h"
#include "et131x_defs.h"

#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>

#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/pci.h>
#include <asm/system.h>

#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>

#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et1310_mac.h"

#include "et131x_adapter.h"

/**
 *	et131x_enable_interrupts	-	enable interrupt
 *	@adapter: et131x device
 *
 *	Enable the appropriate interrupts on the ET131x according to our
 *	configuration
 */

void et131x_enable_interrupts(struct et131x_adapter *adapter)
{
	u32 mask;

	/* Enable all global interrupts */
	if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both)
		mask = INT_MASK_ENABLE;
	else
		mask = INT_MASK_ENABLE_NO_FLOW;

	adapter->CachedMaskValue = mask;
	writel(mask, &adapter->regs->global.int_mask);
}

/**
 *	et131x_disable_interrupts	-	interrupt disable
 *	@adapter: et131x device
 *
 *	Block all interrupts from the et131x device at the device itself
 */

void et131x_disable_interrupts(struct et131x_adapter *adapter)
{
	/* Disable all global interrupts */
	adapter->CachedMaskValue = INT_MASK_DISABLE;
	writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
}


/**
 * et131x_isr - The Interrupt Service Routine for the driver.
 * @irq: the IRQ on which the interrupt was received.
 * @dev_id: device-specific info (here a pointer to a net_device struct)
 *
 * Returns a value indicating if the interrupt was handled.
 */

irqreturn_t et131x_isr(int irq, void *dev_id)
{
	bool handled = true;
	struct net_device *netdev = (struct net_device *)dev_id;
	struct et131x_adapter *adapter = NULL;
	u32 status;

	if (!netif_device_present(netdev)) {
		handled = false;
		goto out;
	}

	adapter = netdev_priv(netdev);

	/* If the adapter is in low power state, then it should not
	 * recognize any interrupt
	 */

	/* Disable Device Interrupts */
	et131x_disable_interrupts(adapter);

	/* Get a copy of the value in the interrupt status register
	 * so we can process the interrupting section
	 */
	status = readl(&adapter->regs->global.int_status);

	if (adapter->FlowControl == TxOnly ||
	    adapter->FlowControl == Both) {
		status &= ~INT_MASK_ENABLE;
	} else {
		status &= ~INT_MASK_ENABLE_NO_FLOW;
	}

	/* Make sure this is our interrupt */
	if (!status) {
		handled = false;
		et131x_enable_interrupts(adapter);
		goto out;
	}

	/* This is our interrupt, so process accordingly */

	if (status & ET_INTR_WATCHDOG) {
		struct tcb *tcb = adapter->tx_ring.send_head;

		if (tcb)
			if (++tcb->stale > 1)
				status |= ET_INTR_TXDMA_ISR;

		if (adapter->RxRing.UnfinishedReceives)
			status |= ET_INTR_RXDMA_XFR_DONE;
		else if (tcb == NULL)
			writel(0, &adapter->regs->global.watchdog_timer);

		status &= ~ET_INTR_WATCHDOG;
	}

	if (status == 0) {
		/* This interrupt has in some way been "handled" by
		 * the ISR. Either it was a spurious Rx interrupt, or
		 * it was a Tx interrupt that has been filtered by
		 * the ISR.
		 */
		et131x_enable_interrupts(adapter);
		goto out;
	}

	/* We need to save the interrupt status value for use in our
	 * DPC. We will clear the software copy of that in that
	 * routine.
	 */
	adapter->Stats.InterruptStatus = status;

	/* Schedule the ISR handler as a bottom-half task in the
	 * kernel's tq_immediate queue, and mark the queue for
	 * execution
	 */
	schedule_work(&adapter->task);
out:
	return IRQ_RETVAL(handled);
}

/**
 * et131x_isr_handler - The ISR handler
 * @p_adapter, a pointer to the device's private adapter structure
 *
 * scheduled to run in a deferred context by the ISR. This is where the ISR's
 * work actually gets done.
 */
void et131x_isr_handler(struct work_struct *work)
{
	struct et131x_adapter *etdev =
		container_of(work, struct et131x_adapter, task);
	u32 status = etdev->Stats.InterruptStatus;
	ADDRESS_MAP_t __iomem *iomem = etdev->regs;

	/*
	 * These first two are by far the most common.  Once handled, we clear
	 * their two bits in the status word.  If the word is now zero, we
	 * exit.
	 */
	/* Handle all the completed Transmit interrupts */
	if (status & ET_INTR_TXDMA_ISR) {
		et131x_handle_send_interrupt(etdev);
	}

	/* Handle all the completed Receives interrupts */
	if (status & ET_INTR_RXDMA_XFR_DONE) {
		et131x_handle_recv_interrupt(etdev);
	}

	status &= 0xffffffd7;

	if (status) {
		/* Handle the TXDMA Error interrupt */
		if (status & ET_INTR_TXDMA_ERR) {
			u32 txdma_err;

			/* Following read also clears the register (COR) */
			txdma_err = readl(&iomem->txdma.TxDmaError);

			dev_warn(&etdev->pdev->dev,
				    "TXDMA_ERR interrupt, error = %d\n",
				    txdma_err);
		}

		/* Handle Free Buffer Ring 0 and 1 Low interrupt */
		if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
			/*
			 * This indicates the number of unused buffers in
			 * RXDMA free buffer ring 0 is <= the limit you
			 * programmed. Free buffer resources need to be
			 * returned.  Free buffers are consumed as packets
			 * are passed from the network to the host. The host
			 * becomes aware of the packets from the contents of
			 * the packet status ring. This ring is queried when
			 * the packet done interrupt occurs. Packets are then
			 * passed to the OS. When the OS is done with the
			 * packets the resources can be returned to the
			 * ET1310 for re-use. This interrupt is one method of
			 * returning resources.
			 */

			/* If the user has flow control on, then we will
			 * send a pause packet, otherwise just exit
			 */
			if (etdev->FlowControl == TxOnly ||
			    etdev->FlowControl == Both) {
				u32 pm_csr;

				/* Tell the device to send a pause packet via
				 * the back pressure register
				 */
				pm_csr = readl(&iomem->global.pm_csr);
				if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
					TXMAC_BP_CTRL_t bp_ctrl = { 0 };

					bp_ctrl.bits.bp_req = 1;
					bp_ctrl.bits.bp_xonxoff = 1;
					writel(bp_ctrl.value,
					       &iomem->txmac.bp_ctrl.value);
				}
			}
		}

		/* Handle Packet Status Ring Low Interrupt */
		if (status & ET_INTR_RXDMA_STAT_LOW) {

			/*
			 * Same idea as with the two Free Buffer Rings.
			 * Packets going from the network to the host each
			 * consume a free buffer resource and a packet status
			 * resource.  These resoures are passed to the OS.
			 * When the OS is done with the resources, they need
			 * to be returned to the ET1310. This is one method
			 * of returning the resources.
			 */
		}

		/* Handle RXDMA Error Interrupt */
		if (status & ET_INTR_RXDMA_ERR) {
			/*
			 * The rxdma_error interrupt is sent when a time-out
			 * on a request issued by the JAGCore has occurred or
			 * a completion is returned with an un-successful
			 * status.  In both cases the request is considered
			 * complete. The JAGCore will automatically re-try the
			 * request in question. Normally information on events
			 * like these are sent to the host using the "Advanced
			 * Error Reporting" capability. This interrupt is
			 * another way of getting similar information. The
			 * only thing required is to clear the interrupt by
			 * reading the ISR in the global resources. The
			 * JAGCore will do a re-try on the request.  Normally
			 * you should never see this interrupt. If you start
			 * to see this interrupt occurring frequently then
			 * something bad has occurred. A reset might be the
			 * thing to do.
			 */
			/* TRAP();*/

			etdev->TxMacTest = readl(&iomem->txmac.tx_test);
			dev_warn(&etdev->pdev->dev,
				    "RxDMA_ERR interrupt, error %x\n",
				    etdev->TxMacTest);
		}

		/* Handle the Wake on LAN Event */
		if (status & ET_INTR_WOL) {
			/*
			 * This is a secondary interrupt for wake on LAN.
			 * The driver should never see this, if it does,
			 * something serious is wrong. We will TRAP the
			 * message when we are in DBG mode, otherwise we
			 * will ignore it.
			 */
			dev_err(&etdev->pdev->dev, "WAKE_ON_LAN interrupt\n");
		}

		/* Handle the PHY interrupt */
		if (status & ET_INTR_PHY) {
			u32 pm_csr;
			MI_BMSR_t BmsrInts, BmsrData;
			MI_ISR_t myIsr;

			/* If we are in coma mode when we get this interrupt,
			 * we need to disable it.
			 */
			pm_csr = readl(&iomem->global.pm_csr);
			if (pm_csr & ET_PM_PHY_SW_COMA) {
				/*
				 * Check to see if we are in coma mode and if
				 * so, disable it because we will not be able
				 * to read PHY values until we are out.
				 */
				DisablePhyComa(etdev);
			}

			/* Read the PHY ISR to clear the reason for the
			 * interrupt.
			 */
			MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr),
			       &myIsr.value);

			if (!etdev->ReplicaPhyLoopbk) {
				MiRead(etdev,
				       (uint8_t) offsetof(MI_REGS_t, bmsr),
				       &BmsrData.value);

				BmsrInts.value =
				    etdev->Bmsr.value ^ BmsrData.value;
				etdev->Bmsr.value = BmsrData.value;

				/* Do all the cable in / cable out stuff */
				et131x_Mii_check(etdev, BmsrData, BmsrInts);
			}
		}

		/* Let's move on to the TxMac */
		if (status & ET_INTR_TXMAC) {
			u32 err = readl(&iomem->txmac.err.value);

			/*
			 * When any of the errors occur and TXMAC generates
			 * an interrupt to report these errors, it usually
			 * means that TXMAC has detected an error in the data
			 * stream retrieved from the on-chip Tx Q. All of
			 * these errors are catastrophic and TXMAC won't be
			 * able to recover data when these errors occur.  In
			 * a nutshell, the whole Tx path will have to be reset
			 * and re-configured afterwards.
			 */
			dev_warn(&etdev->pdev->dev,
				    "TXMAC interrupt, error 0x%08x\n",
				    err);

			/* If we are debugging, we want to see this error,
			 * otherwise we just want the device to be reset and
			 * continue
			 */
		}

		/* Handle RXMAC Interrupt */
		if (status & ET_INTR_RXMAC) {
			/*
			 * These interrupts are catastrophic to the device,
			 * what we need to do is disable the interrupts and
			 * set the flag to cause us to reset so we can solve
			 * this issue.
			 */
			/* MP_SET_FLAG( etdev,
						fMP_ADAPTER_HARDWARE_ERROR); */

			dev_warn(&etdev->pdev->dev,
			  "RXMAC interrupt, error 0x%08x.  Requesting reset\n",
				    readl(&iomem->rxmac.err_reg.value));

			dev_warn(&etdev->pdev->dev,
				    "Enable 0x%08x, Diag 0x%08x\n",
				    readl(&iomem->rxmac.ctrl.value),
				    readl(&iomem->rxmac.rxq_diag.value));

			/*
			 * If we are debugging, we want to see this error,
			 * otherwise we just want the device to be reset and
			 * continue
			 */
		}

		/* Handle MAC_STAT Interrupt */
		if (status & ET_INTR_MAC_STAT) {
			/*
			 * This means at least one of the un-masked counters
			 * in the MAC_STAT block has rolled over.  Use this
			 * to maintain the top, software managed bits of the
			 * counter(s).
			 */
			HandleMacStatInterrupt(etdev);
		}

		/* Handle SLV Timeout Interrupt */
		if (status & ET_INTR_SLV_TIMEOUT) {
			/*
			 * This means a timeout has occured on a read or
			 * write request to one of the JAGCore registers. The
			 * Global Resources block has terminated the request
			 * and on a read request, returned a "fake" value.
			 * The most likely reasons are: Bad Address or the
			 * addressed module is in a power-down state and
			 * can't respond.
			 */
		}
	}
	et131x_enable_interrupts(etdev);
}
Commit	Line	Data
cfb739b4 GKH	1	/*
	2	* Agere Systems Inc.
	3	* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
	4	*
64f93036	5	* Copyright © 2005 Agere Systems Inc.
cfb739b4 GKH	6	* All rights reserved.
	7	* http://www.agere.com
	8	*
	9	*------------------------------------------------------------------------------
	10	*
	11	* et131x_isr.c - File which contains the ISR, ISR handler, and related routines
	12	* for processing interrupts from the device.
	13	*
	14	*------------------------------------------------------------------------------
	15	*
	16	* SOFTWARE LICENSE
	17	*
	18	* This software is provided subject to the following terms and conditions,
	19	* which you should read carefully before using the software. Using this
	20	* software indicates your acceptance of these terms and conditions. If you do
	21	* not agree with these terms and conditions, do not use the software.
	22	*
64f93036	23	* Copyright © 2005 Agere Systems Inc.
cfb739b4 GKH	24	* All rights reserved.
	25	*
	26	* Redistribution and use in source or binary forms, with or without
	27	* modifications, are permitted provided that the following conditions are met:
	28	*
	29	* . Redistributions of source code must retain the above copyright notice, this
	30	* list of conditions and the following Disclaimer as comments in the code as
	31	* well as in the documentation and/or other materials provided with the
	32	* distribution.
	33	*
	34	* . Redistributions in binary form must reproduce the above copyright notice,
	35	* this list of conditions and the following Disclaimer in the documentation
	36	* and/or other materials provided with the distribution.
	37	*
	38	* . Neither the name of Agere Systems Inc. nor the names of the contributors
	39	* may be used to endorse or promote products derived from this software
	40	* without specific prior written permission.
	41	*
	42	* Disclaimer
	43	*
64f93036	44	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
cfb739b4 GKH	45	* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
	46	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
	47	* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
	48	* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
	49	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	50	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	51	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	52	* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
	53	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
	54	* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
	55	* DAMAGE.
	56	*
	57	*/
	58
	59	#include "et131x_version.h"
cfb739b4 GKH	60	#include "et131x_defs.h"
	61
	62	#include <linux/init.h>
	63	#include <linux/module.h>
	64	#include <linux/types.h>
	65	#include <linux/kernel.h>
	66
	67	#include <linux/sched.h>
	68	#include <linux/ptrace.h>
	69	#include <linux/slab.h>
	70	#include <linux/ctype.h>
	71	#include <linux/string.h>
	72	#include <linux/timer.h>
	73	#include <linux/interrupt.h>
	74	#include <linux/in.h>
	75	#include <linux/delay.h>
64f93036 AC	76	#include <linux/io.h>
64f93036 AC	77	#include <linux/bitops.h>
15700039	78	#include <linux/pci.h>
cfb739b4	79	#include <asm/system.h>
cfb739b4 GKH	80
	81	#include <linux/netdevice.h>
	82	#include <linux/etherdevice.h>
	83	#include <linux/skbuff.h>
	84	#include <linux/if_arp.h>
	85	#include <linux/ioport.h>
	86
	87	#include "et1310_phy.h"
	88	#include "et1310_pm.h"
	89	#include "et1310_jagcore.h"
	90	#include "et1310_mac.h"
	91
	92	#include "et131x_adapter.h"
	93
b8c4cc46 AC	94	/**
	95	* et131x_enable_interrupts - enable interrupt
	96	* @adapter: et131x device
	97	*
	98	* Enable the appropriate interrupts on the ET131x according to our
	99	* configuration
	100	*/
	101
	102	void et131x_enable_interrupts(struct et131x_adapter *adapter)
	103	{
	104	u32 mask;
	105
	106	/* Enable all global interrupts */
	107	if (adapter->FlowControl == TxOnly \|\| adapter->FlowControl == Both)
	108	mask = INT_MASK_ENABLE;
	109	else
	110	mask = INT_MASK_ENABLE_NO_FLOW;
	111
b8c4cc46 AC	112	adapter->CachedMaskValue = mask;
	113	writel(mask, &adapter->regs->global.int_mask);
	114	}
	115
	116	/**
	117	* et131x_disable_interrupts - interrupt disable
	118	* @adapter: et131x device
	119	*
	120	* Block all interrupts from the et131x device at the device itself
	121	*/
	122
	123	void et131x_disable_interrupts(struct et131x_adapter *adapter)
	124	{
	125	/* Disable all global interrupts */
	126	adapter->CachedMaskValue = INT_MASK_DISABLE;
	127	writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
	128	}
	129
	130
cfb739b4 GKH	131	/**
	132	* et131x_isr - The Interrupt Service Routine for the driver.
	133	* @irq: the IRQ on which the interrupt was received.
	134	* @dev_id: device-specific info (here a pointer to a net_device struct)
	135	*
	136	* Returns a value indicating if the interrupt was handled.
	137	*/
b8c4cc46	138
cfb739b4 GKH	139	irqreturn_t et131x_isr(int irq, void *dev_id)
	140	{
	141	bool handled = true;
	142	struct net_device netdev = (struct net_device )dev_id;
	143	struct et131x_adapter *adapter = NULL;
2211b732	144	u32 status;
cfb739b4	145
15700039	146	if (!netif_device_present(netdev)) {
cfb739b4 GKH	147	handled = false;
	148	goto out;
	149	}
	150
	151	adapter = netdev_priv(netdev);
	152
	153	/* If the adapter is in low power state, then it should not
	154	* recognize any interrupt
	155	*/
	156
	157	/* Disable Device Interrupts */
	158	et131x_disable_interrupts(adapter);
	159
	160	/* Get a copy of the value in the interrupt status register
	161	* so we can process the interrupting section
	162	*/
2211b732	163	status = readl(&adapter->regs->global.int_status);
cfb739b4 GKH	164
	165	if (adapter->FlowControl == TxOnly \|\|
	166	adapter->FlowControl == Both) {
2211b732	167	status &= ~INT_MASK_ENABLE;
cfb739b4	168	} else {
2211b732	169	status &= ~INT_MASK_ENABLE_NO_FLOW;
cfb739b4 GKH	170	}
	171
	172	/* Make sure this is our interrupt */
2211b732	173	if (!status) {
cfb739b4	174	handled = false;
cfb739b4 GKH	175	et131x_enable_interrupts(adapter);
	176	goto out;
	177	}
	178
	179	/* This is our interrupt, so process accordingly */
cfb739b4	180
2211b732	181	if (status & ET_INTR_WATCHDOG) {
c78732ad	182	struct tcb *tcb = adapter->tx_ring.send_head;
cfb739b4	183
b711b2e0	184	if (tcb)
c78732ad	185	if (++tcb->stale > 1)
2211b732	186	status \|= ET_INTR_TXDMA_ISR;
cfb739b4	187
64f93036	188	if (adapter->RxRing.UnfinishedReceives)
2211b732	189	status \|= ET_INTR_RXDMA_XFR_DONE;
b711b2e0	190	else if (tcb == NULL)
f3f415a3	191	writel(0, &adapter->regs->global.watchdog_timer);
cfb739b4	192
2211b732	193	status &= ~ET_INTR_WATCHDOG;
cfb739b4 GKH	194	}
cfb739b4 GKH	195
2211b732	196	if (status == 0) {
cfb739b4 GKH	197	/* This interrupt has in some way been "handled" by
	198	* the ISR. Either it was a spurious Rx interrupt, or
	199	* it was a Tx interrupt that has been filtered by
	200	* the ISR.
	201	*/
	202	et131x_enable_interrupts(adapter);
	203	goto out;
	204	}
	205
	206	/* We need to save the interrupt status value for use in our
	207	* DPC. We will clear the software copy of that in that
	208	* routine.
	209	*/
	210	adapter->Stats.InterruptStatus = status;
	211
	212	/* Schedule the ISR handler as a bottom-half task in the
	213	* kernel's tq_immediate queue, and mark the queue for
	214	* execution
	215	*/
	216	schedule_work(&adapter->task);
cfb739b4 GKH	217	out:
	218	return IRQ_RETVAL(handled);
	219	}
	220
	221	/**
	222	* et131x_isr_handler - The ISR handler
	223	* @p_adapter, a pointer to the device's private adapter structure
	224	*
	225	* scheduled to run in a deferred context by the ISR. This is where the ISR's
	226	* work actually gets done.
	227	*/
	228	void et131x_isr_handler(struct work_struct *work)
	229	{
25ad00bb	230	struct et131x_adapter *etdev =
cfb739b4	231	container_of(work, struct et131x_adapter, task);
2211b732	232	u32 status = etdev->Stats.InterruptStatus;
f3f415a3	233	ADDRESS_MAP_t __iomem *iomem = etdev->regs;
cfb739b4 GKH	234
	235	/*
	236	* These first two are by far the most common. Once handled, we clear
	237	* their two bits in the status word. If the word is now zero, we
	238	* exit.
	239	*/
	240	/* Handle all the completed Transmit interrupts */
2211b732	241	if (status & ET_INTR_TXDMA_ISR) {
25ad00bb	242	et131x_handle_send_interrupt(etdev);
cfb739b4 GKH	243	}
	244
	245	/* Handle all the completed Receives interrupts */
2211b732	246	if (status & ET_INTR_RXDMA_XFR_DONE) {
25ad00bb	247	et131x_handle_recv_interrupt(etdev);
cfb739b4 GKH	248	}
cfb739b4 GKH	249
2211b732	250	status &= 0xffffffd7;
cfb739b4	251
2211b732	252	if (status) {
cfb739b4	253	/* Handle the TXDMA Error interrupt */
2211b732	254	if (status & ET_INTR_TXDMA_ERR) {
fba84166	255	u32 txdma_err;
cfb739b4 GKH	256
cfb739b4 GKH	257	/* Following read also clears the register (COR) */
fba84166	258	txdma_err = readl(&iomem->txdma.TxDmaError);
cfb739b4	259
15700039	260	dev_warn(&etdev->pdev->dev,
cfb739b4	261	"TXDMA_ERR interrupt, error = %d\n",
fba84166	262	txdma_err);
cfb739b4 GKH	263	}
	264
	265	/* Handle Free Buffer Ring 0 and 1 Low interrupt */
2211b732	266	if (status & (ET_INTR_RXDMA_FB_R0_LOW \| ET_INTR_RXDMA_FB_R1_LOW)) {
cfb739b4 GKH	267	/*
	268	* This indicates the number of unused buffers in
	269	* RXDMA free buffer ring 0 is <= the limit you
	270	* programmed. Free buffer resources need to be
	271	* returned. Free buffers are consumed as packets
	272	* are passed from the network to the host. The host
	273	* becomes aware of the packets from the contents of
	274	* the packet status ring. This ring is queried when
	275	* the packet done interrupt occurs. Packets are then
	276	* passed to the OS. When the OS is done with the
	277	* packets the resources can be returned to the
	278	* ET1310 for re-use. This interrupt is one method of
	279	* returning resources.
	280	*/
cfb739b4 GKH	281
	282	/* If the user has flow control on, then we will
	283	* send a pause packet, otherwise just exit
	284	*/
25ad00bb AC	285	if (etdev->FlowControl == TxOnly \|\|
25ad00bb AC	286	etdev->FlowControl == Both) {
f2c98d27	287	u32 pm_csr;
cfb739b4 GKH	288
	289	/* Tell the device to send a pause packet via
	290	* the back pressure register
	291	*/
f2c98d27 AC	292	pm_csr = readl(&iomem->global.pm_csr);
f2c98d27 AC	293	if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
cfb739b4 GKH	294	TXMAC_BP_CTRL_t bp_ctrl = { 0 };
	295
	296	bp_ctrl.bits.bp_req = 1;
	297	bp_ctrl.bits.bp_xonxoff = 1;
	298	writel(bp_ctrl.value,
	299	&iomem->txmac.bp_ctrl.value);
	300	}
	301	}
	302	}
	303
	304	/* Handle Packet Status Ring Low Interrupt */
2211b732	305	if (status & ET_INTR_RXDMA_STAT_LOW) {
cfb739b4 GKH	306
	307	/*
	308	* Same idea as with the two Free Buffer Rings.
	309	* Packets going from the network to the host each
	310	* consume a free buffer resource and a packet status
	311	* resource. These resoures are passed to the OS.
	312	* When the OS is done with the resources, they need
	313	* to be returned to the ET1310. This is one method
	314	* of returning the resources.
	315	*/
	316	}
	317
	318	/* Handle RXDMA Error Interrupt */
2211b732	319	if (status & ET_INTR_RXDMA_ERR) {
cfb739b4 GKH	320	/*
	321	* The rxdma_error interrupt is sent when a time-out
	322	* on a request issued by the JAGCore has occurred or
	323	* a completion is returned with an un-successful
	324	* status. In both cases the request is considered
	325	* complete. The JAGCore will automatically re-try the
	326	* request in question. Normally information on events
	327	* like these are sent to the host using the "Advanced
	328	* Error Reporting" capability. This interrupt is
	329	* another way of getting similar information. The
	330	* only thing required is to clear the interrupt by
	331	* reading the ISR in the global resources. The
	332	* JAGCore will do a re-try on the request. Normally
	333	* you should never see this interrupt. If you start
	334	* to see this interrupt occurring frequently then
	335	* something bad has occurred. A reset might be the
	336	* thing to do.
	337	*/
64f93036	338	/* TRAP();*/
cfb739b4	339
f838cabd	340	etdev->TxMacTest = readl(&iomem->txmac.tx_test);
15700039	341	dev_warn(&etdev->pdev->dev,
cfb739b4	342	"RxDMA_ERR interrupt, error %x\n",
f838cabd	343	etdev->TxMacTest);
cfb739b4 GKH	344	}
	345
	346	/* Handle the Wake on LAN Event */
2211b732	347	if (status & ET_INTR_WOL) {
cfb739b4 GKH	348	/*
	349	* This is a secondary interrupt for wake on LAN.
	350	* The driver should never see this, if it does,
	351	* something serious is wrong. We will TRAP the
	352	* message when we are in DBG mode, otherwise we
	353	* will ignore it.
	354	*/
15700039	355	dev_err(&etdev->pdev->dev, "WAKE_ON_LAN interrupt\n");
cfb739b4 GKH	356	}
	357
	358	/* Handle the PHY interrupt */
2211b732	359	if (status & ET_INTR_PHY) {
f2c98d27	360	u32 pm_csr;
cfb739b4 GKH	361	MI_BMSR_t BmsrInts, BmsrData;
	362	MI_ISR_t myIsr;
	363
cfb739b4 GKH	364	/* If we are in coma mode when we get this interrupt,
	365	* we need to disable it.
	366	*/
f2c98d27 AC	367	pm_csr = readl(&iomem->global.pm_csr);
f2c98d27 AC	368	if (pm_csr & ET_PM_PHY_SW_COMA) {
cfb739b4 GKH	369	/*
	370	* Check to see if we are in coma mode and if
	371	* so, disable it because we will not be able
	372	* to read PHY values until we are out.
	373	*/
25ad00bb	374	DisablePhyComa(etdev);
cfb739b4 GKH	375	}
	376
	377	/* Read the PHY ISR to clear the reason for the
	378	* interrupt.
	379	*/
25ad00bb	380	MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr),
cfb739b4 GKH	381	&myIsr.value);
cfb739b4 GKH	382
25ad00bb AC	383	if (!etdev->ReplicaPhyLoopbk) {
25ad00bb AC	384	MiRead(etdev,
cfb739b4 GKH	385	(uint8_t) offsetof(MI_REGS_t, bmsr),
	386	&BmsrData.value);
	387
	388	BmsrInts.value =
25ad00bb AC	389	etdev->Bmsr.value ^ BmsrData.value;
25ad00bb AC	390	etdev->Bmsr.value = BmsrData.value;
cfb739b4	391
cfb739b4	392	/* Do all the cable in / cable out stuff */
25ad00bb	393	et131x_Mii_check(etdev, BmsrData, BmsrInts);
cfb739b4 GKH	394	}
	395	}
	396
	397	/* Let's move on to the TxMac */
2211b732	398	if (status & ET_INTR_TXMAC) {
ceef1a5e	399	u32 err = readl(&iomem->txmac.err.value);
cfb739b4 GKH	400
	401	/*
	402	* When any of the errors occur and TXMAC generates
	403	* an interrupt to report these errors, it usually
	404	* means that TXMAC has detected an error in the data
	405	* stream retrieved from the on-chip Tx Q. All of
	406	* these errors are catastrophic and TXMAC won't be
	407	* able to recover data when these errors occur. In
	408	* a nutshell, the whole Tx path will have to be reset
	409	* and re-configured afterwards.
	410	*/
15700039	411	dev_warn(&etdev->pdev->dev,
cfb739b4	412	"TXMAC interrupt, error 0x%08x\n",
ceef1a5e	413	err);
cfb739b4 GKH	414
	415	/* If we are debugging, we want to see this error,
	416	* otherwise we just want the device to be reset and
	417	* continue
	418	*/
cfb739b4 GKH	419	}
	420
	421	/* Handle RXMAC Interrupt */
2211b732	422	if (status & ET_INTR_RXMAC) {
cfb739b4 GKH	423	/*
	424	* These interrupts are catastrophic to the device,
	425	* what we need to do is disable the interrupts and
	426	* set the flag to cause us to reset so we can solve
	427	* this issue.
	428	*/
25ad00bb	429	/* MP_SET_FLAG( etdev,
64f93036	430	fMP_ADAPTER_HARDWARE_ERROR); */
cfb739b4	431
15700039	432	dev_warn(&etdev->pdev->dev,
64f93036	433	"RXMAC interrupt, error 0x%08x. Requesting reset\n",
cfb739b4 GKH	434	readl(&iomem->rxmac.err_reg.value));
cfb739b4 GKH	435
15700039	436	dev_warn(&etdev->pdev->dev,
cfb739b4 GKH	437	"Enable 0x%08x, Diag 0x%08x\n",
	438	readl(&iomem->rxmac.ctrl.value),
	439	readl(&iomem->rxmac.rxq_diag.value));
	440
	441	/*
	442	* If we are debugging, we want to see this error,
	443	* otherwise we just want the device to be reset and
	444	* continue
	445	*/
cfb739b4 GKH	446	}
	447
	448	/* Handle MAC_STAT Interrupt */
2211b732	449	if (status & ET_INTR_MAC_STAT) {
cfb739b4 GKH	450	/*
	451	* This means at least one of the un-masked counters
	452	* in the MAC_STAT block has rolled over. Use this
	453	* to maintain the top, software managed bits of the
	454	* counter(s).
	455	*/
25ad00bb	456	HandleMacStatInterrupt(etdev);
cfb739b4 GKH	457	}
	458
	459	/* Handle SLV Timeout Interrupt */
2211b732	460	if (status & ET_INTR_SLV_TIMEOUT) {
cfb739b4 GKH	461	/*
	462	* This means a timeout has occured on a read or
	463	* write request to one of the JAGCore registers. The
	464	* Global Resources block has terminated the request
	465	* and on a read request, returned a "fake" value.
	466	* The most likely reasons are: Bad Address or the
	467	* addressed module is in a power-down state and
	468	* can't respond.
	469	*/
cfb739b4 GKH	470	}
cfb739b4 GKH	471	}
20dedd3f	472	et131x_enable_interrupts(etdev);
cfb739b4	473	}